1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_CORE_H__ 7 #define __INTEL_DISPLAY_CORE_H__ 8 9 #include <linux/list.h> 10 #include <linux/llist.h> 11 #include <linux/mutex.h> 12 #include <linux/types.h> 13 #include <linux/wait.h> 14 #include <linux/workqueue.h> 15 16 #include <drm/drm_connector.h> 17 18 #include "intel_cdclk.h" 19 #include "intel_display.h" 20 #include "intel_display_power.h" 21 #include "intel_dmc.h" 22 #include "intel_dpll_mgr.h" 23 #include "intel_fbc.h" 24 #include "intel_global_state.h" 25 #include "intel_gmbus.h" 26 #include "intel_opregion.h" 27 #include "intel_pm_types.h" 28 29 struct drm_i915_private; 30 struct drm_property; 31 struct i915_audio_component; 32 struct i915_hdcp_comp_master; 33 struct intel_atomic_state; 34 struct intel_audio_funcs; 35 struct intel_bios_encoder_data; 36 struct intel_cdclk_funcs; 37 struct intel_cdclk_vals; 38 struct intel_color_funcs; 39 struct intel_crtc; 40 struct intel_crtc_state; 41 struct intel_dpll_funcs; 42 struct intel_dpll_mgr; 43 struct intel_fbdev; 44 struct intel_fdi_funcs; 45 struct intel_hotplug_funcs; 46 struct intel_initial_plane_config; 47 struct intel_overlay; 48 49 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 50 #define I915_NUM_QGV_POINTS 8 51 52 /* Amount of PSF GV points, BSpec precisely defines this */ 53 #define I915_NUM_PSF_GV_POINTS 3 54 55 struct intel_display_funcs { 56 /* 57 * Returns the active state of the crtc, and if the crtc is active, 58 * fills out the pipe-config with the hw state. 59 */ 60 bool (*get_pipe_config)(struct intel_crtc *, 61 struct intel_crtc_state *); 62 void (*get_initial_plane_config)(struct intel_crtc *, 63 struct intel_initial_plane_config *); 64 void (*crtc_enable)(struct intel_atomic_state *state, 65 struct intel_crtc *crtc); 66 void (*crtc_disable)(struct intel_atomic_state *state, 67 struct intel_crtc *crtc); 68 void (*commit_modeset_enables)(struct intel_atomic_state *state); 69 }; 70 71 /* functions used for watermark calcs for display. */ 72 struct intel_wm_funcs { 73 /* update_wm is for legacy wm management */ 74 void (*update_wm)(struct drm_i915_private *dev_priv); 75 int (*compute_pipe_wm)(struct intel_atomic_state *state, 76 struct intel_crtc *crtc); 77 int (*compute_intermediate_wm)(struct intel_atomic_state *state, 78 struct intel_crtc *crtc); 79 void (*initial_watermarks)(struct intel_atomic_state *state, 80 struct intel_crtc *crtc); 81 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 82 struct intel_crtc *crtc); 83 void (*optimize_watermarks)(struct intel_atomic_state *state, 84 struct intel_crtc *crtc); 85 int (*compute_global_watermarks)(struct intel_atomic_state *state); 86 }; 87 88 struct intel_audio { 89 /* hda/i915 audio component */ 90 struct i915_audio_component *component; 91 bool component_registered; 92 /* mutex for audio/video sync */ 93 struct mutex mutex; 94 int power_refcount; 95 u32 freq_cntrl; 96 97 /* Used to save the pipe-to-encoder mapping for audio */ 98 struct intel_encoder *encoder_map[I915_MAX_PIPES]; 99 100 /* necessary resource sharing with HDMI LPE audio driver. */ 101 struct { 102 struct platform_device *platdev; 103 int irq; 104 } lpe; 105 }; 106 107 /* 108 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes 109 * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per 110 * dpll, because on some platforms plls share registers. 111 */ 112 struct intel_dpll { 113 struct mutex lock; 114 115 int num_shared_dpll; 116 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 117 const struct intel_dpll_mgr *mgr; 118 119 struct { 120 int nssc; 121 int ssc; 122 } ref_clks; 123 }; 124 125 struct intel_frontbuffer_tracking { 126 spinlock_t lock; 127 128 /* 129 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 130 * scheduled flips. 131 */ 132 unsigned busy_bits; 133 unsigned flip_bits; 134 }; 135 136 struct intel_hotplug { 137 struct delayed_work hotplug_work; 138 139 const u32 *hpd, *pch_hpd; 140 141 struct { 142 unsigned long last_jiffies; 143 int count; 144 enum { 145 HPD_ENABLED = 0, 146 HPD_DISABLED = 1, 147 HPD_MARK_DISABLED = 2 148 } state; 149 } stats[HPD_NUM_PINS]; 150 u32 event_bits; 151 u32 retry_bits; 152 struct delayed_work reenable_work; 153 154 u32 long_port_mask; 155 u32 short_port_mask; 156 struct work_struct dig_port_work; 157 158 struct work_struct poll_init_work; 159 bool poll_enabled; 160 161 unsigned int hpd_storm_threshold; 162 /* Whether or not to count short HPD IRQs in HPD storms */ 163 u8 hpd_short_storm_enabled; 164 165 /* 166 * if we get a HPD irq from DP and a HPD irq from non-DP 167 * the non-DP HPD could block the workqueue on a mode config 168 * mutex getting, that userspace may have taken. However 169 * userspace is waiting on the DP workqueue to run which is 170 * blocked behind the non-DP one. 171 */ 172 struct workqueue_struct *dp_wq; 173 }; 174 175 struct intel_vbt_data { 176 /* bdb version */ 177 u16 version; 178 179 /* Feature bits */ 180 unsigned int int_tv_support:1; 181 unsigned int int_crt_support:1; 182 unsigned int lvds_use_ssc:1; 183 unsigned int int_lvds_support:1; 184 unsigned int display_clock_mode:1; 185 unsigned int fdi_rx_polarity_inverted:1; 186 int lvds_ssc_freq; 187 enum drm_panel_orientation orientation; 188 189 bool override_afc_startup; 190 u8 override_afc_startup_val; 191 192 int crt_ddc_pin; 193 194 struct list_head display_devices; 195 struct list_head bdb_blocks; 196 197 struct intel_bios_encoder_data *ports[I915_MAX_PORTS]; /* Non-NULL if port present. */ 198 struct sdvo_device_mapping { 199 u8 initialized; 200 u8 dvo_port; 201 u8 slave_addr; 202 u8 dvo_wiring; 203 u8 i2c_pin; 204 u8 ddc_pin; 205 } sdvo_mappings[2]; 206 }; 207 208 struct intel_wm { 209 /* 210 * Raw watermark latency values: 211 * in 0.1us units for WM0, 212 * in 0.5us units for WM1+. 213 */ 214 /* primary */ 215 u16 pri_latency[5]; 216 /* sprite */ 217 u16 spr_latency[5]; 218 /* cursor */ 219 u16 cur_latency[5]; 220 /* 221 * Raw watermark memory latency values 222 * for SKL for all 8 levels 223 * in 1us units. 224 */ 225 u16 skl_latency[8]; 226 227 /* current hardware state */ 228 union { 229 struct ilk_wm_values hw; 230 struct vlv_wm_values vlv; 231 struct g4x_wm_values g4x; 232 }; 233 234 u8 max_level; 235 236 /* 237 * Should be held around atomic WM register writing; also 238 * protects * intel_crtc->wm.active and 239 * crtc_state->wm.need_postvbl_update. 240 */ 241 struct mutex wm_mutex; 242 243 bool ipc_enabled; 244 }; 245 246 struct intel_display { 247 /* Display functions */ 248 struct { 249 /* Top level crtc-ish functions */ 250 const struct intel_display_funcs *display; 251 252 /* Display CDCLK functions */ 253 const struct intel_cdclk_funcs *cdclk; 254 255 /* Display pll funcs */ 256 const struct intel_dpll_funcs *dpll; 257 258 /* irq display functions */ 259 const struct intel_hotplug_funcs *hotplug; 260 261 /* pm display functions */ 262 const struct intel_wm_funcs *wm; 263 264 /* fdi display functions */ 265 const struct intel_fdi_funcs *fdi; 266 267 /* Display internal color functions */ 268 const struct intel_color_funcs *color; 269 270 /* Display internal audio functions */ 271 const struct intel_audio_funcs *audio; 272 } funcs; 273 274 /* Grouping using anonymous structs. Keep sorted. */ 275 struct intel_atomic_helper { 276 struct llist_head free_list; 277 struct work_struct free_work; 278 } atomic_helper; 279 280 struct { 281 /* backlight registers and fields in struct intel_panel */ 282 struct mutex lock; 283 } backlight; 284 285 struct { 286 struct intel_global_obj obj; 287 288 struct intel_bw_info { 289 /* for each QGV point */ 290 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 291 /* for each PSF GV point */ 292 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS]; 293 u8 num_qgv_points; 294 u8 num_psf_gv_points; 295 u8 num_planes; 296 } max[6]; 297 } bw; 298 299 struct { 300 /* The current hardware cdclk configuration */ 301 struct intel_cdclk_config hw; 302 303 /* cdclk, divider, and ratio table from bspec */ 304 const struct intel_cdclk_vals *table; 305 306 struct intel_global_obj obj; 307 308 unsigned int max_cdclk_freq; 309 } cdclk; 310 311 struct { 312 /* The current hardware dbuf configuration */ 313 u8 enabled_slices; 314 315 struct intel_global_obj obj; 316 } dbuf; 317 318 struct { 319 /* 320 * dkl.phy_lock protects against concurrent access of the 321 * Dekel TypeC PHYs. 322 */ 323 spinlock_t phy_lock; 324 } dkl; 325 326 struct { 327 /* VLV/CHV/BXT/GLK DSI MMIO register base address */ 328 u32 mmio_base; 329 } dsi; 330 331 struct { 332 /* list of fbdev register on this device */ 333 struct intel_fbdev *fbdev; 334 struct work_struct suspend_work; 335 } fbdev; 336 337 struct { 338 unsigned int pll_freq; 339 u32 rx_config; 340 } fdi; 341 342 struct { 343 /* 344 * Base address of where the gmbus and gpio blocks are located 345 * (either on PCH or on SoC for platforms without PCH). 346 */ 347 u32 mmio_base; 348 349 /* 350 * gmbus.mutex protects against concurrent usage of the single 351 * hw gmbus controller on different i2c buses. 352 */ 353 struct mutex mutex; 354 355 struct intel_gmbus *bus[GMBUS_NUM_PINS]; 356 357 wait_queue_head_t wait_queue; 358 } gmbus; 359 360 struct { 361 struct i915_hdcp_comp_master *master; 362 bool comp_added; 363 364 /* Mutex to protect the above hdcp component related values. */ 365 struct mutex comp_mutex; 366 } hdcp; 367 368 struct { 369 struct i915_power_domains domains; 370 371 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 372 u32 chv_phy_control; 373 374 /* perform PHY state sanity checks? */ 375 bool chv_phy_assert[2]; 376 } power; 377 378 struct { 379 u32 mmio_base; 380 381 /* protects panel power sequencer state */ 382 struct mutex mutex; 383 } pps; 384 385 struct { 386 struct drm_property *broadcast_rgb; 387 struct drm_property *force_audio; 388 } properties; 389 390 struct { 391 unsigned long mask; 392 } quirks; 393 394 struct { 395 enum { 396 I915_SAGV_UNKNOWN = 0, 397 I915_SAGV_DISABLED, 398 I915_SAGV_ENABLED, 399 I915_SAGV_NOT_CONTROLLED 400 } status; 401 402 u32 block_time_us; 403 } sagv; 404 405 struct { 406 /* ordered wq for modesets */ 407 struct workqueue_struct *modeset; 408 409 /* unbound hipri wq for page flips/plane updates */ 410 struct workqueue_struct *flip; 411 } wq; 412 413 /* Grouping using named structs. Keep sorted. */ 414 struct intel_audio audio; 415 struct intel_dmc dmc; 416 struct intel_dpll dpll; 417 struct intel_fbc *fbc[I915_MAX_FBCS]; 418 struct intel_frontbuffer_tracking fb_tracking; 419 struct intel_hotplug hotplug; 420 struct intel_opregion opregion; 421 struct intel_overlay *overlay; 422 struct intel_vbt_data vbt; 423 struct intel_wm wm; 424 }; 425 426 #endif /* __INTEL_DISPLAY_CORE_H__ */ 427