1 /* $Id: fore200e.h,v 1.4 2000/04/14 10:10:34 davem Exp $ */ 2 #ifndef _FORE200E_H 3 #define _FORE200E_H 4 5 #ifdef __KERNEL__ 6 #include <linux/config.h> 7 8 /* rx buffer sizes */ 9 10 #define SMALL_BUFFER_SIZE 384 /* size of small buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */ 11 #define LARGE_BUFFER_SIZE 4032 /* size of large buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */ 12 13 14 #define RBD_BLK_SIZE 32 /* nbr of supplied rx buffers per rbd */ 15 16 17 #define MAX_PDU_SIZE 65535 /* maximum PDU size supported by AALs */ 18 19 20 #define BUFFER_S1_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 1 */ 21 #define BUFFER_L1_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 1 */ 22 23 #define BUFFER_S2_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 2 */ 24 #define BUFFER_L2_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 2 */ 25 26 #define BUFFER_S1_NBR (RBD_BLK_SIZE * 6) 27 #define BUFFER_L1_NBR (RBD_BLK_SIZE * 4) 28 29 #define BUFFER_S2_NBR (RBD_BLK_SIZE * 6) 30 #define BUFFER_L2_NBR (RBD_BLK_SIZE * 4) 31 32 33 #define QUEUE_SIZE_CMD 16 /* command queue capacity */ 34 #define QUEUE_SIZE_RX 64 /* receive queue capacity */ 35 #define QUEUE_SIZE_TX 256 /* transmit queue capacity */ 36 #define QUEUE_SIZE_BS 32 /* buffer supply queue capacity */ 37 38 #define FORE200E_VPI_BITS 0 39 #define FORE200E_VCI_BITS 10 40 #define NBR_CONNECT (1 << (FORE200E_VPI_BITS + FORE200E_VCI_BITS)) /* number of connections */ 41 42 43 #define TSD_FIXED 2 44 #define TSD_EXTENSION 0 45 #define TSD_NBR (TSD_FIXED + TSD_EXTENSION) 46 47 48 /* the cp starts putting a received PDU into one *small* buffer, 49 then it uses a number of *large* buffers for the trailing data. 50 we compute here the total number of receive segment descriptors 51 required to hold the largest possible PDU */ 52 53 #define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE) + 1) 54 55 #define RSD_FIXED 3 56 57 /* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU, 58 but we have to keep the size of the receive PDU descriptor multiple of 32 bytes, 59 so we add one extra RSD to RSD_EXTENSION 60 (WARNING: THIS MAY CHANGE IF BUFFER SIZES ARE MODIFIED) */ 61 62 #define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1) 63 #define RSD_NBR (RSD_FIXED + RSD_EXTENSION) 64 65 66 #define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data)) 67 #define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data)) 68 69 /* bitfields endian games */ 70 71 #if defined(__LITTLE_ENDIAN_BITFIELD) 72 #define BITFIELD2(b1, b2) b1; b2; 73 #define BITFIELD3(b1, b2, b3) b1; b2; b3; 74 #define BITFIELD4(b1, b2, b3, b4) b1; b2; b3; b4; 75 #define BITFIELD5(b1, b2, b3, b4, b5) b1; b2; b3; b4; b5; 76 #define BITFIELD6(b1, b2, b3, b4, b5, b6) b1; b2; b3; b4; b5; b6; 77 #elif defined(__BIG_ENDIAN_BITFIELD) 78 #define BITFIELD2(b1, b2) b2; b1; 79 #define BITFIELD3(b1, b2, b3) b3; b2; b1; 80 #define BITFIELD4(b1, b2, b3, b4) b4; b3; b2; b1; 81 #define BITFIELD5(b1, b2, b3, b4, b5) b5; b4; b3; b2; b1; 82 #define BITFIELD6(b1, b2, b3, b4, b5, b6) b6; b5; b4; b3; b2; b1; 83 #else 84 #error unknown bitfield endianess 85 #endif 86 87 88 /* ATM cell header (minus HEC byte) */ 89 90 typedef struct atm_header { 91 BITFIELD5( 92 u32 clp : 1, /* cell loss priority */ 93 u32 plt : 3, /* payload type */ 94 u32 vci : 16, /* virtual channel identifier */ 95 u32 vpi : 8, /* virtual path identifier */ 96 u32 gfc : 4 /* generic flow control */ 97 ) 98 } atm_header_t; 99 100 101 /* ATM adaptation layer id */ 102 103 typedef enum fore200e_aal { 104 FORE200E_AAL0 = 0, 105 FORE200E_AAL34 = 4, 106 FORE200E_AAL5 = 5, 107 } fore200e_aal_t; 108 109 110 /* transmit PDU descriptor specification */ 111 112 typedef struct tpd_spec { 113 BITFIELD4( 114 u32 length : 16, /* total PDU length */ 115 u32 nseg : 8, /* number of transmit segments */ 116 enum fore200e_aal aal : 4, /* adaptation layer */ 117 u32 intr : 4 /* interrupt requested */ 118 ) 119 } tpd_spec_t; 120 121 122 /* transmit PDU rate control */ 123 124 typedef struct tpd_rate 125 { 126 BITFIELD2( 127 u32 idle_cells : 16, /* number of idle cells to insert */ 128 u32 data_cells : 16 /* number of data cells to transmit */ 129 ) 130 } tpd_rate_t; 131 132 133 /* transmit segment descriptor */ 134 135 typedef struct tsd { 136 u32 buffer; /* transmit buffer DMA address */ 137 u32 length; /* number of bytes in buffer */ 138 } tsd_t; 139 140 141 /* transmit PDU descriptor */ 142 143 typedef struct tpd { 144 struct atm_header atm_header; /* ATM header minus HEC byte */ 145 struct tpd_spec spec; /* tpd specification */ 146 struct tpd_rate rate; /* tpd rate control */ 147 u32 pad; /* reserved */ 148 struct tsd tsd[ TSD_NBR ]; /* transmit segment descriptors */ 149 } tpd_t; 150 151 152 /* receive segment descriptor */ 153 154 typedef struct rsd { 155 u32 handle; /* host supplied receive buffer handle */ 156 u32 length; /* number of bytes in buffer */ 157 } rsd_t; 158 159 160 /* receive PDU descriptor */ 161 162 typedef struct rpd { 163 struct atm_header atm_header; /* ATM header minus HEC byte */ 164 u32 nseg; /* number of receive segments */ 165 struct rsd rsd[ RSD_NBR ]; /* receive segment descriptors */ 166 } rpd_t; 167 168 169 /* buffer scheme */ 170 171 typedef enum buffer_scheme { 172 BUFFER_SCHEME_ONE, 173 BUFFER_SCHEME_TWO, 174 BUFFER_SCHEME_NBR /* always last */ 175 } buffer_scheme_t; 176 177 178 /* buffer magnitude */ 179 180 typedef enum buffer_magn { 181 BUFFER_MAGN_SMALL, 182 BUFFER_MAGN_LARGE, 183 BUFFER_MAGN_NBR /* always last */ 184 } buffer_magn_t; 185 186 187 /* receive buffer descriptor */ 188 189 typedef struct rbd { 190 u32 handle; /* host supplied handle */ 191 u32 buffer_haddr; /* host DMA address of host buffer */ 192 } rbd_t; 193 194 195 /* receive buffer descriptor block */ 196 197 typedef struct rbd_block { 198 struct rbd rbd[ RBD_BLK_SIZE ]; /* receive buffer descriptor */ 199 } rbd_block_t; 200 201 202 /* tpd DMA address */ 203 204 typedef struct tpd_haddr { 205 BITFIELD3( 206 u32 size : 4, /* tpd size expressed in 32 byte blocks */ 207 u32 pad : 1, /* reserved */ 208 u32 haddr : 27 /* tpd DMA addr aligned on 32 byte boundary */ 209 ) 210 } tpd_haddr_t; 211 212 #define TPD_HADDR_SHIFT 5 /* addr aligned on 32 byte boundary */ 213 214 /* cp resident transmit queue entry */ 215 216 typedef struct cp_txq_entry { 217 struct tpd_haddr tpd_haddr; /* host DMA address of tpd */ 218 u32 status_haddr; /* host DMA address of completion status */ 219 } cp_txq_entry_t; 220 221 222 /* cp resident receive queue entry */ 223 224 typedef struct cp_rxq_entry { 225 u32 rpd_haddr; /* host DMA address of rpd */ 226 u32 status_haddr; /* host DMA address of completion status */ 227 } cp_rxq_entry_t; 228 229 230 /* cp resident buffer supply queue entry */ 231 232 typedef struct cp_bsq_entry { 233 u32 rbd_block_haddr; /* host DMA address of rbd block */ 234 u32 status_haddr; /* host DMA address of completion status */ 235 } cp_bsq_entry_t; 236 237 238 /* completion status */ 239 240 typedef volatile enum status { 241 STATUS_PENDING = (1<<0), /* initial status (written by host) */ 242 STATUS_COMPLETE = (1<<1), /* completion status (written by cp) */ 243 STATUS_FREE = (1<<2), /* initial status (written by host) */ 244 STATUS_ERROR = (1<<3) /* completion status (written by cp) */ 245 } status_t; 246 247 248 /* cp operation code */ 249 250 typedef enum opcode { 251 OPCODE_INITIALIZE = 1, /* initialize board */ 252 OPCODE_ACTIVATE_VCIN, /* activate incoming VCI */ 253 OPCODE_ACTIVATE_VCOUT, /* activate outgoing VCI */ 254 OPCODE_DEACTIVATE_VCIN, /* deactivate incoming VCI */ 255 OPCODE_DEACTIVATE_VCOUT, /* deactivate incoing VCI */ 256 OPCODE_GET_STATS, /* get board statistics */ 257 OPCODE_SET_OC3, /* set OC-3 registers */ 258 OPCODE_GET_OC3, /* get OC-3 registers */ 259 OPCODE_RESET_STATS, /* reset board statistics */ 260 OPCODE_GET_PROM, /* get expansion PROM data (PCI specific) */ 261 OPCODE_SET_VPI_BITS, /* set x bits of those decoded by the 262 firmware to be low order bits from 263 the VPI field of the ATM cell header */ 264 OPCODE_REQUEST_INTR = (1<<7) /* request interrupt */ 265 } opcode_t; 266 267 268 /* virtual path / virtual channel identifers */ 269 270 typedef struct vpvc { 271 BITFIELD3( 272 u32 vci : 16, /* virtual channel identifier */ 273 u32 vpi : 8, /* virtual path identifier */ 274 u32 pad : 8 /* reserved */ 275 ) 276 } vpvc_t; 277 278 279 /* activate VC command opcode */ 280 281 typedef struct activate_opcode { 282 BITFIELD4( 283 enum opcode opcode : 8, /* cp opcode */ 284 enum fore200e_aal aal : 8, /* adaptation layer */ 285 enum buffer_scheme scheme : 8, /* buffer scheme */ 286 u32 pad : 8 /* reserved */ 287 ) 288 } activate_opcode_t; 289 290 291 /* activate VC command block */ 292 293 typedef struct activate_block { 294 struct activate_opcode opcode; /* activate VC command opcode */ 295 struct vpvc vpvc; /* VPI/VCI */ 296 u32 mtu; /* for AAL0 only */ 297 298 } activate_block_t; 299 300 301 /* deactivate VC command opcode */ 302 303 typedef struct deactivate_opcode { 304 BITFIELD2( 305 enum opcode opcode : 8, /* cp opcode */ 306 u32 pad : 24 /* reserved */ 307 ) 308 } deactivate_opcode_t; 309 310 311 /* deactivate VC command block */ 312 313 typedef struct deactivate_block { 314 struct deactivate_opcode opcode; /* deactivate VC command opcode */ 315 struct vpvc vpvc; /* VPI/VCI */ 316 } deactivate_block_t; 317 318 319 /* OC-3 registers */ 320 321 typedef struct oc3_regs { 322 u32 reg[ 128 ]; /* see the PMC Sierra PC5346 S/UNI-155-Lite 323 Saturn User Network Interface documentation 324 for a description of the OC-3 chip registers */ 325 } oc3_regs_t; 326 327 328 /* set/get OC-3 regs command opcode */ 329 330 typedef struct oc3_opcode { 331 BITFIELD4( 332 enum opcode opcode : 8, /* cp opcode */ 333 u32 reg : 8, /* register index */ 334 u32 value : 8, /* register value */ 335 u32 mask : 8 /* register mask that specifies which 336 bits of the register value field 337 are significant */ 338 ) 339 } oc3_opcode_t; 340 341 342 /* set/get OC-3 regs command block */ 343 344 typedef struct oc3_block { 345 struct oc3_opcode opcode; /* set/get OC-3 regs command opcode */ 346 u32 regs_haddr; /* host DMA address of OC-3 regs buffer */ 347 } oc3_block_t; 348 349 350 /* physical encoding statistics */ 351 352 typedef struct stats_phy { 353 u32 crc_header_errors; /* cells received with bad header CRC */ 354 u32 framing_errors; /* cells received with bad framing */ 355 u32 pad[ 2 ]; /* i960 padding */ 356 } stats_phy_t; 357 358 359 /* OC-3 statistics */ 360 361 typedef struct stats_oc3 { 362 u32 section_bip8_errors; /* section 8 bit interleaved parity */ 363 u32 path_bip8_errors; /* path 8 bit interleaved parity */ 364 u32 line_bip24_errors; /* line 24 bit interleaved parity */ 365 u32 line_febe_errors; /* line far end block errors */ 366 u32 path_febe_errors; /* path far end block errors */ 367 u32 corr_hcs_errors; /* correctable header check sequence */ 368 u32 ucorr_hcs_errors; /* uncorrectable header check sequence */ 369 u32 pad[ 1 ]; /* i960 padding */ 370 } stats_oc3_t; 371 372 373 /* ATM statistics */ 374 375 typedef struct stats_atm { 376 u32 cells_transmitted; /* cells transmitted */ 377 u32 cells_received; /* cells received */ 378 u32 vpi_bad_range; /* cell drops: VPI out of range */ 379 u32 vpi_no_conn; /* cell drops: no connection for VPI */ 380 u32 vci_bad_range; /* cell drops: VCI out of range */ 381 u32 vci_no_conn; /* cell drops: no connection for VCI */ 382 u32 pad[ 2 ]; /* i960 padding */ 383 } stats_atm_t; 384 385 /* AAL0 statistics */ 386 387 typedef struct stats_aal0 { 388 u32 cells_transmitted; /* cells transmitted */ 389 u32 cells_received; /* cells received */ 390 u32 cells_dropped; /* cells dropped */ 391 u32 pad[ 1 ]; /* i960 padding */ 392 } stats_aal0_t; 393 394 395 /* AAL3/4 statistics */ 396 397 typedef struct stats_aal34 { 398 u32 cells_transmitted; /* cells transmitted from segmented PDUs */ 399 u32 cells_received; /* cells reassembled into PDUs */ 400 u32 cells_crc_errors; /* payload CRC error count */ 401 u32 cells_protocol_errors; /* SAR or CS layer protocol errors */ 402 u32 cells_dropped; /* cells dropped: partial reassembly */ 403 u32 cspdus_transmitted; /* CS PDUs transmitted */ 404 u32 cspdus_received; /* CS PDUs received */ 405 u32 cspdus_protocol_errors; /* CS layer protocol errors */ 406 u32 cspdus_dropped; /* reassembled PDUs drop'd (in cells) */ 407 u32 pad[ 3 ]; /* i960 padding */ 408 } stats_aal34_t; 409 410 411 /* AAL5 statistics */ 412 413 typedef struct stats_aal5 { 414 u32 cells_transmitted; /* cells transmitted from segmented SDUs */ 415 u32 cells_received; /* cells reassembled into SDUs */ 416 u32 cells_dropped; /* reassembled PDUs dropped (in cells) */ 417 u32 congestion_experienced; /* CRC error and length wrong */ 418 u32 cspdus_transmitted; /* CS PDUs transmitted */ 419 u32 cspdus_received; /* CS PDUs received */ 420 u32 cspdus_crc_errors; /* CS PDUs CRC errors */ 421 u32 cspdus_protocol_errors; /* CS layer protocol errors */ 422 u32 cspdus_dropped; /* reassembled PDUs dropped */ 423 u32 pad[ 3 ]; /* i960 padding */ 424 } stats_aal5_t; 425 426 427 /* auxiliary statistics */ 428 429 typedef struct stats_aux { 430 u32 small_b1_failed; /* receive BD allocation failures */ 431 u32 large_b1_failed; /* receive BD allocation failures */ 432 u32 small_b2_failed; /* receive BD allocation failures */ 433 u32 large_b2_failed; /* receive BD allocation failures */ 434 u32 rpd_alloc_failed; /* receive PDU allocation failures */ 435 u32 receive_carrier; /* no carrier = 0, carrier = 1 */ 436 u32 pad[ 2 ]; /* i960 padding */ 437 } stats_aux_t; 438 439 440 /* whole statistics buffer */ 441 442 typedef struct stats { 443 struct stats_phy phy; /* physical encoding statistics */ 444 struct stats_oc3 oc3; /* OC-3 statistics */ 445 struct stats_atm atm; /* ATM statistics */ 446 struct stats_aal0 aal0; /* AAL0 statistics */ 447 struct stats_aal34 aal34; /* AAL3/4 statistics */ 448 struct stats_aal5 aal5; /* AAL5 statistics */ 449 struct stats_aux aux; /* auxiliary statistics */ 450 } stats_t; 451 452 453 /* get statistics command opcode */ 454 455 typedef struct stats_opcode { 456 BITFIELD2( 457 enum opcode opcode : 8, /* cp opcode */ 458 u32 pad : 24 /* reserved */ 459 ) 460 } stats_opcode_t; 461 462 463 /* get statistics command block */ 464 465 typedef struct stats_block { 466 struct stats_opcode opcode; /* get statistics command opcode */ 467 u32 stats_haddr; /* host DMA address of stats buffer */ 468 } stats_block_t; 469 470 471 /* expansion PROM data (PCI specific) */ 472 473 typedef struct prom_data { 474 u32 hw_revision; /* hardware revision */ 475 u32 serial_number; /* board serial number */ 476 u8 mac_addr[ 8 ]; /* board MAC address */ 477 } prom_data_t; 478 479 480 /* get expansion PROM data command opcode */ 481 482 typedef struct prom_opcode { 483 BITFIELD2( 484 enum opcode opcode : 8, /* cp opcode */ 485 u32 pad : 24 /* reserved */ 486 ) 487 } prom_opcode_t; 488 489 490 /* get expansion PROM data command block */ 491 492 typedef struct prom_block { 493 struct prom_opcode opcode; /* get PROM data command opcode */ 494 u32 prom_haddr; /* host DMA address of PROM buffer */ 495 } prom_block_t; 496 497 498 /* cp command */ 499 500 typedef union cmd { 501 enum opcode opcode; /* operation code */ 502 struct activate_block activate_block; /* activate VC */ 503 struct deactivate_block deactivate_block; /* deactivate VC */ 504 struct stats_block stats_block; /* get statistics */ 505 struct prom_block prom_block; /* get expansion PROM data */ 506 struct oc3_block oc3_block; /* get/set OC-3 registers */ 507 u32 pad[ 4 ]; /* i960 padding */ 508 } cmd_t; 509 510 511 /* cp resident command queue */ 512 513 typedef struct cp_cmdq_entry { 514 union cmd cmd; /* command */ 515 u32 status_haddr; /* host DMA address of completion status */ 516 u32 pad[ 3 ]; /* i960 padding */ 517 } cp_cmdq_entry_t; 518 519 520 /* host resident transmit queue entry */ 521 522 typedef struct host_txq_entry { 523 struct cp_txq_entry* cp_entry; /* addr of cp resident tx queue entry */ 524 enum status* status; /* addr of host resident status */ 525 struct tpd* tpd; /* addr of transmit PDU descriptor */ 526 u32 tpd_dma; /* DMA address of tpd */ 527 struct sk_buff* skb; /* related skb */ 528 void* data; /* copy of misaligned data */ 529 unsigned long incarn; /* vc_map incarnation when submitted for tx */ 530 struct fore200e_vc_map* vc_map; 531 532 } host_txq_entry_t; 533 534 535 /* host resident receive queue entry */ 536 537 typedef struct host_rxq_entry { 538 struct cp_rxq_entry* cp_entry; /* addr of cp resident rx queue entry */ 539 enum status* status; /* addr of host resident status */ 540 struct rpd* rpd; /* addr of receive PDU descriptor */ 541 u32 rpd_dma; /* DMA address of rpd */ 542 } host_rxq_entry_t; 543 544 545 /* host resident buffer supply queue entry */ 546 547 typedef struct host_bsq_entry { 548 struct cp_bsq_entry* cp_entry; /* addr of cp resident buffer supply queue entry */ 549 enum status* status; /* addr of host resident status */ 550 struct rbd_block* rbd_block; /* addr of receive buffer descriptor block */ 551 u32 rbd_block_dma; /* DMA address od rdb */ 552 } host_bsq_entry_t; 553 554 555 /* host resident command queue entry */ 556 557 typedef struct host_cmdq_entry { 558 struct cp_cmdq_entry* cp_entry; /* addr of cp resident cmd queue entry */ 559 enum status* status; /* addr of host resident status */ 560 } host_cmdq_entry_t; 561 562 563 /* chunk of memory */ 564 565 typedef struct chunk { 566 void* alloc_addr; /* base address of allocated chunk */ 567 void* align_addr; /* base address of aligned chunk */ 568 u32 dma_addr; /* DMA address of aligned chunk */ 569 int direction; /* direction of DMA mapping */ 570 u32 alloc_size; /* length of allocated chunk */ 571 u32 align_size; /* length of aligned chunk */ 572 } chunk_t; 573 574 #define dma_size align_size /* DMA useable size */ 575 576 577 /* host resident receive buffer */ 578 579 typedef struct buffer { 580 struct buffer* next; /* next receive buffer */ 581 enum buffer_scheme scheme; /* buffer scheme */ 582 enum buffer_magn magn; /* buffer magnitude */ 583 struct chunk data; /* data buffer */ 584 #ifdef FORE200E_BSQ_DEBUG 585 unsigned long index; /* buffer # in queue */ 586 int supplied; /* 'buffer supplied' flag */ 587 #endif 588 } buffer_t; 589 590 591 #if (BITS_PER_LONG == 32) 592 #define FORE200E_BUF2HDL(buffer) ((u32)(buffer)) 593 #define FORE200E_HDL2BUF(handle) ((struct buffer*)(handle)) 594 #else /* deal with 64 bit pointers */ 595 #define FORE200E_BUF2HDL(buffer) ((u32)((u64)(buffer))) 596 #define FORE200E_HDL2BUF(handle) ((struct buffer*)(((u64)(handle)) | PAGE_OFFSET)) 597 #endif 598 599 600 /* host resident command queue */ 601 602 typedef struct host_cmdq { 603 struct host_cmdq_entry host_entry[ QUEUE_SIZE_CMD ]; /* host resident cmd queue entries */ 604 int head; /* head of cmd queue */ 605 struct chunk status; /* array of completion status */ 606 } host_cmdq_t; 607 608 609 /* host resident transmit queue */ 610 611 typedef struct host_txq { 612 struct host_txq_entry host_entry[ QUEUE_SIZE_TX ]; /* host resident tx queue entries */ 613 int head; /* head of tx queue */ 614 int tail; /* tail of tx queue */ 615 struct chunk tpd; /* array of tpds */ 616 struct chunk status; /* arry of completion status */ 617 int txing; /* number of pending PDUs in tx queue */ 618 } host_txq_t; 619 620 621 /* host resident receive queue */ 622 623 typedef struct host_rxq { 624 struct host_rxq_entry host_entry[ QUEUE_SIZE_RX ]; /* host resident rx queue entries */ 625 int head; /* head of rx queue */ 626 struct chunk rpd; /* array of rpds */ 627 struct chunk status; /* array of completion status */ 628 } host_rxq_t; 629 630 631 /* host resident buffer supply queues */ 632 633 typedef struct host_bsq { 634 struct host_bsq_entry host_entry[ QUEUE_SIZE_BS ]; /* host resident buffer supply queue entries */ 635 int head; /* head of buffer supply queue */ 636 struct chunk rbd_block; /* array of rbds */ 637 struct chunk status; /* array of completion status */ 638 struct buffer* buffer; /* array of rx buffers */ 639 struct buffer* freebuf; /* list of free rx buffers */ 640 volatile int freebuf_count; /* count of free rx buffers */ 641 } host_bsq_t; 642 643 644 /* header of the firmware image */ 645 646 typedef struct fw_header { 647 u32 magic; /* magic number */ 648 u32 version; /* firware version id */ 649 u32 load_offset; /* fw load offset in board memory */ 650 u32 start_offset; /* fw execution start address in board memory */ 651 } fw_header_t; 652 653 #define FW_HEADER_MAGIC 0x65726f66 /* 'fore' */ 654 655 656 /* receive buffer supply queues scheme specification */ 657 658 typedef struct bs_spec { 659 u32 queue_length; /* queue capacity */ 660 u32 buffer_size; /* host buffer size */ 661 u32 pool_size; /* number of rbds */ 662 u32 supply_blksize; /* num of rbds in I/O block (multiple 663 of 4 between 4 and 124 inclusive) */ 664 } bs_spec_t; 665 666 667 /* initialization command block (one-time command, not in cmd queue) */ 668 669 typedef struct init_block { 670 enum opcode opcode; /* initialize command */ 671 enum status status; /* related status word */ 672 u32 receive_threshold; /* not used */ 673 u32 num_connect; /* ATM connections */ 674 u32 cmd_queue_len; /* length of command queue */ 675 u32 tx_queue_len; /* length of transmit queue */ 676 u32 rx_queue_len; /* length of receive queue */ 677 u32 rsd_extension; /* number of extra 32 byte blocks */ 678 u32 tsd_extension; /* number of extra 32 byte blocks */ 679 u32 conless_vpvc; /* not used */ 680 u32 pad[ 2 ]; /* force quad alignment */ 681 struct bs_spec bs_spec[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues spec */ 682 } init_block_t; 683 684 685 typedef enum media_type { 686 MEDIA_TYPE_CAT5_UTP = 0x06, /* unshielded twisted pair */ 687 MEDIA_TYPE_MM_OC3_ST = 0x16, /* multimode fiber ST */ 688 MEDIA_TYPE_MM_OC3_SC = 0x26, /* multimode fiber SC */ 689 MEDIA_TYPE_SM_OC3_ST = 0x36, /* single-mode fiber ST */ 690 MEDIA_TYPE_SM_OC3_SC = 0x46 /* single-mode fiber SC */ 691 } media_type_t; 692 693 #define FORE200E_MEDIA_INDEX(media_type) ((media_type)>>4) 694 695 696 /* cp resident queues */ 697 698 typedef struct cp_queues { 699 u32 cp_cmdq; /* command queue */ 700 u32 cp_txq; /* transmit queue */ 701 u32 cp_rxq; /* receive queue */ 702 u32 cp_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues */ 703 u32 imask; /* 1 enables cp to host interrupts */ 704 u32 istat; /* 1 for interrupt posted */ 705 u32 heap_base; /* offset form beginning of ram */ 706 u32 heap_size; /* space available for queues */ 707 u32 hlogger; /* non zero for host logging */ 708 u32 heartbeat; /* cp heartbeat */ 709 u32 fw_release; /* firmware version */ 710 u32 mon960_release; /* i960 monitor version */ 711 u32 tq_plen; /* transmit throughput measurements */ 712 /* make sure the init block remains on a quad word boundary */ 713 struct init_block init; /* one time cmd, not in cmd queue */ 714 enum media_type media_type; /* media type id */ 715 u32 oc3_revision; /* OC-3 revision number */ 716 } cp_queues_t; 717 718 719 /* boot status */ 720 721 typedef enum boot_status { 722 BSTAT_COLD_START = (u32) 0xc01dc01d, /* cold start */ 723 BSTAT_SELFTEST_OK = (u32) 0x02201958, /* self-test ok */ 724 BSTAT_SELFTEST_FAIL = (u32) 0xadbadbad, /* self-test failed */ 725 BSTAT_CP_RUNNING = (u32) 0xce11feed, /* cp is running */ 726 BSTAT_MON_TOO_BIG = (u32) 0x10aded00 /* i960 monitor is too big */ 727 } boot_status_t; 728 729 730 /* software UART */ 731 732 typedef struct soft_uart { 733 u32 send; /* write register */ 734 u32 recv; /* read register */ 735 } soft_uart_t; 736 737 #define FORE200E_CP_MONITOR_UART_FREE 0x00000000 738 #define FORE200E_CP_MONITOR_UART_AVAIL 0x01000000 739 740 741 /* i960 monitor */ 742 743 typedef struct cp_monitor { 744 struct soft_uart soft_uart; /* software UART */ 745 enum boot_status bstat; /* boot status */ 746 u32 app_base; /* application base offset */ 747 u32 mon_version; /* i960 monitor version */ 748 } cp_monitor_t; 749 750 751 /* device state */ 752 753 typedef enum fore200e_state { 754 FORE200E_STATE_BLANK, /* initial state */ 755 FORE200E_STATE_REGISTER, /* device registered */ 756 FORE200E_STATE_CONFIGURE, /* bus interface configured */ 757 FORE200E_STATE_MAP, /* board space mapped in host memory */ 758 FORE200E_STATE_RESET, /* board resetted */ 759 FORE200E_STATE_LOAD_FW, /* firmware loaded */ 760 FORE200E_STATE_START_FW, /* firmware started */ 761 FORE200E_STATE_INITIALIZE, /* initialize command successful */ 762 FORE200E_STATE_INIT_CMDQ, /* command queue initialized */ 763 FORE200E_STATE_INIT_TXQ, /* transmit queue initialized */ 764 FORE200E_STATE_INIT_RXQ, /* receive queue initialized */ 765 FORE200E_STATE_INIT_BSQ, /* buffer supply queue initialized */ 766 FORE200E_STATE_ALLOC_BUF, /* receive buffers allocated */ 767 FORE200E_STATE_IRQ, /* host interrupt requested */ 768 FORE200E_STATE_COMPLETE /* initialization completed */ 769 } fore200e_state; 770 771 772 /* PCA-200E registers */ 773 774 typedef struct fore200e_pca_regs { 775 volatile u32* hcr; /* address of host control register */ 776 volatile u32* imr; /* address of host interrupt mask register */ 777 volatile u32* psr; /* address of PCI specific register */ 778 } fore200e_pca_regs_t; 779 780 781 /* SBA-200E registers */ 782 783 typedef struct fore200e_sba_regs { 784 volatile u32* hcr; /* address of host control register */ 785 volatile u32* bsr; /* address of burst transfer size register */ 786 volatile u32* isr; /* address of interrupt level selection register */ 787 } fore200e_sba_regs_t; 788 789 790 /* model-specific registers */ 791 792 typedef union fore200e_regs { 793 struct fore200e_pca_regs pca; /* PCA-200E registers */ 794 struct fore200e_sba_regs sba; /* SBA-200E registers */ 795 } fore200e_regs; 796 797 798 struct fore200e; 799 800 /* bus-dependent data */ 801 802 typedef struct fore200e_bus { 803 char* model_name; /* board model name */ 804 char* proc_name; /* board name under /proc/atm */ 805 int descr_alignment; /* tpd/rpd/rbd DMA alignment requirement */ 806 int buffer_alignment; /* rx buffers DMA alignment requirement */ 807 int status_alignment; /* status words DMA alignment requirement */ 808 const unsigned char* fw_data; /* address of firmware data start */ 809 const unsigned int* fw_size; /* address of firmware data size */ 810 u32 (*read)(volatile u32*); 811 void (*write)(u32, volatile u32*); 812 u32 (*dma_map)(struct fore200e*, void*, int, int); 813 void (*dma_unmap)(struct fore200e*, u32, int, int); 814 void (*dma_sync)(struct fore200e*, u32, int, int); 815 int (*dma_chunk_alloc)(struct fore200e*, struct chunk*, int, int, int); 816 void (*dma_chunk_free)(struct fore200e*, struct chunk*); 817 struct fore200e* (*detect)(const struct fore200e_bus*, int); 818 int (*configure)(struct fore200e*); 819 int (*map)(struct fore200e*); 820 void (*reset)(struct fore200e*); 821 int (*prom_read)(struct fore200e*, struct prom_data*); 822 void (*unmap)(struct fore200e*); 823 void (*irq_enable)(struct fore200e*); 824 int (*irq_check)(struct fore200e*); 825 void (*irq_ack)(struct fore200e*); 826 int (*proc_read)(struct fore200e*, char*); 827 } fore200e_bus_t; 828 829 830 #if defined(CONFIG_ATM_FORE200E_SBA) 831 # if defined(CONFIG_ATM_FORE200E_PCA) 832 # if (PCI_DMA_BIDIRECTIONAL == SBUS_DMA_BIDIRECTIONAL) && \ 833 (PCI_DMA_TODEVICE == SBUS_DMA_TODEVICE) && \ 834 (PCI_DMA_FROMDEVICE == SBUS_DMA_FROMDEVICE) 835 # define FORE200E_DMA_BIDIRECTIONAL PCI_DMA_BIDIRECTIONAL 836 # define FORE200E_DMA_TODEVICE PCI_DMA_TODEVICE 837 # define FORE200E_DMA_FROMDEVICE PCI_DMA_FROMDEVICE 838 # else 839 /* in that case, we'll need to add an extra indirection, e.g. 840 fore200e->bus->dma_direction[ fore200e_dma_direction ] */ 841 # error PCI and SBUS DMA direction flags have different values! 842 # endif 843 # else 844 # define FORE200E_DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL 845 # define FORE200E_DMA_TODEVICE SBUS_DMA_TODEVICE 846 # define FORE200E_DMA_FROMDEVICE SBUS_DMA_FROMDEVICE 847 # endif 848 #else 849 # ifndef CONFIG_ATM_FORE200E_PCA 850 # warning compiling the fore200e driver without any hardware support enabled! 851 # include <linux/pci.h> 852 # endif 853 # define FORE200E_DMA_BIDIRECTIONAL PCI_DMA_BIDIRECTIONAL 854 # define FORE200E_DMA_TODEVICE PCI_DMA_TODEVICE 855 # define FORE200E_DMA_FROMDEVICE PCI_DMA_FROMDEVICE 856 #endif 857 858 859 /* vc mapping */ 860 861 typedef struct fore200e_vc_map { 862 struct atm_vcc* vcc; /* vcc entry */ 863 unsigned long incarn; /* vcc incarnation number */ 864 } fore200e_vc_map_t; 865 866 #define FORE200E_VC_MAP(fore200e, vpi, vci) \ 867 (& (fore200e)->vc_map[ ((vpi) << FORE200E_VCI_BITS) | (vci) ]) 868 869 870 /* per-device data */ 871 872 typedef struct fore200e { 873 struct fore200e* next; /* next device */ 874 const struct fore200e_bus* bus; /* bus-dependent code and data */ 875 union fore200e_regs regs; /* bus-dependent registers */ 876 struct atm_dev* atm_dev; /* ATM device */ 877 878 enum fore200e_state state; /* device state */ 879 880 char name[16]; /* device name */ 881 void* bus_dev; /* bus-specific kernel data */ 882 int irq; /* irq number */ 883 unsigned long phys_base; /* physical base address */ 884 void* virt_base; /* virtual base address */ 885 886 unsigned char esi[ ESI_LEN ]; /* end system identifier */ 887 888 struct cp_monitor* cp_monitor; /* i960 monitor address */ 889 struct cp_queues* cp_queues; /* cp resident queues */ 890 struct host_cmdq host_cmdq; /* host resident cmd queue */ 891 struct host_txq host_txq; /* host resident tx queue */ 892 struct host_rxq host_rxq; /* host resident rx queue */ 893 /* host resident buffer supply queues */ 894 struct host_bsq host_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; 895 896 u32 available_cell_rate; /* remaining pseudo-CBR bw on link */ 897 898 int loop_mode; /* S/UNI loopback mode */ 899 900 struct stats* stats; /* last snapshot of the stats */ 901 902 struct semaphore rate_sf; /* protects rate reservation ops */ 903 spinlock_t q_lock; /* protects queue ops */ 904 #ifdef FORE200E_USE_TASKLET 905 struct tasklet_struct tx_tasklet; /* performs tx interrupt work */ 906 struct tasklet_struct rx_tasklet; /* performs rx interrupt work */ 907 #endif 908 unsigned long tx_sat; /* tx queue saturation count */ 909 910 unsigned long incarn_count; 911 struct fore200e_vc_map vc_map[ NBR_CONNECT ]; /* vc mapping */ 912 } fore200e_t; 913 914 915 /* per-vcc data */ 916 917 typedef struct fore200e_vcc { 918 enum buffer_scheme scheme; /* rx buffer scheme */ 919 struct tpd_rate rate; /* tx rate control data */ 920 int rx_min_pdu; /* size of smallest PDU received */ 921 int rx_max_pdu; /* size of largest PDU received */ 922 int tx_min_pdu; /* size of smallest PDU transmitted */ 923 int tx_max_pdu; /* size of largest PDU transmitted */ 924 unsigned long tx_pdu; /* nbr of tx pdus */ 925 unsigned long rx_pdu; /* nbr of rx pdus */ 926 } fore200e_vcc_t; 927 928 929 930 /* 200E-series common memory layout */ 931 932 #define FORE200E_CP_MONITOR_OFFSET 0x00000400 /* i960 monitor interface */ 933 #define FORE200E_CP_QUEUES_OFFSET 0x00004d40 /* cp resident queues */ 934 935 936 /* PCA-200E memory layout */ 937 938 #define PCA200E_IOSPACE_LENGTH 0x00200000 939 940 #define PCA200E_HCR_OFFSET 0x00100000 /* board control register */ 941 #define PCA200E_IMR_OFFSET 0x00100004 /* host IRQ mask register */ 942 #define PCA200E_PSR_OFFSET 0x00100008 /* PCI specific register */ 943 944 945 /* PCA-200E host control register */ 946 947 #define PCA200E_HCR_RESET (1<<0) /* read / write */ 948 #define PCA200E_HCR_HOLD_LOCK (1<<1) /* read / write */ 949 #define PCA200E_HCR_I960FAIL (1<<2) /* read */ 950 #define PCA200E_HCR_INTRB (1<<2) /* write */ 951 #define PCA200E_HCR_HOLD_ACK (1<<3) /* read */ 952 #define PCA200E_HCR_INTRA (1<<3) /* write */ 953 #define PCA200E_HCR_OUTFULL (1<<4) /* read */ 954 #define PCA200E_HCR_CLRINTR (1<<4) /* write */ 955 #define PCA200E_HCR_ESPHOLD (1<<5) /* read */ 956 #define PCA200E_HCR_INFULL (1<<6) /* read */ 957 #define PCA200E_HCR_TESTMODE (1<<7) /* read */ 958 959 960 /* PCA-200E PCI bus interface regs (offsets in PCI config space) */ 961 962 #define PCA200E_PCI_LATENCY 0x40 /* maximum slave latenty */ 963 #define PCA200E_PCI_MASTER_CTRL 0x41 /* master control */ 964 #define PCA200E_PCI_THRESHOLD 0x42 /* burst / continous req threshold */ 965 966 /* PBI master control register */ 967 968 #define PCA200E_CTRL_DIS_CACHE_RD (1<<0) /* disable cache-line reads */ 969 #define PCA200E_CTRL_DIS_WRT_INVAL (1<<1) /* disable writes and invalidates */ 970 #define PCA200E_CTRL_2_CACHE_WRT_INVAL (1<<2) /* require 2 cache-lines for writes and invalidates */ 971 #define PCA200E_CTRL_IGN_LAT_TIMER (1<<3) /* ignore the latency timer */ 972 #define PCA200E_CTRL_ENA_CONT_REQ_MODE (1<<4) /* enable continuous request mode */ 973 #define PCA200E_CTRL_LARGE_PCI_BURSTS (1<<5) /* force large PCI bus bursts */ 974 #define PCA200E_CTRL_CONVERT_ENDIAN (1<<6) /* convert endianess of slave RAM accesses */ 975 976 977 978 #define SBA200E_PROM_NAME "FORE,sba-200e" /* device name in openprom tree */ 979 980 981 /* size of SBA-200E registers */ 982 983 #define SBA200E_HCR_LENGTH 4 984 #define SBA200E_BSR_LENGTH 4 985 #define SBA200E_ISR_LENGTH 4 986 #define SBA200E_RAM_LENGTH 0x40000 987 988 989 /* SBA-200E SBUS burst transfer size register */ 990 991 #define SBA200E_BSR_BURST4 0x04 992 #define SBA200E_BSR_BURST8 0x08 993 #define SBA200E_BSR_BURST16 0x10 994 995 996 /* SBA-200E host control register */ 997 998 #define SBA200E_HCR_RESET (1<<0) /* read / write (sticky) */ 999 #define SBA200E_HCR_HOLD_LOCK (1<<1) /* read / write (sticky) */ 1000 #define SBA200E_HCR_I960FAIL (1<<2) /* read */ 1001 #define SBA200E_HCR_I960SETINTR (1<<2) /* write */ 1002 #define SBA200E_HCR_OUTFULL (1<<3) /* read */ 1003 #define SBA200E_HCR_INTR_CLR (1<<3) /* write */ 1004 #define SBA200E_HCR_INTR_ENA (1<<4) /* read / write (sticky) */ 1005 #define SBA200E_HCR_ESPHOLD (1<<5) /* read */ 1006 #define SBA200E_HCR_INFULL (1<<6) /* read */ 1007 #define SBA200E_HCR_TESTMODE (1<<7) /* read */ 1008 #define SBA200E_HCR_INTR_REQ (1<<8) /* read */ 1009 1010 #define SBA200E_HCR_STICKY (SBA200E_HCR_RESET | SBA200E_HCR_HOLD_LOCK | SBA200E_HCR_INTR_ENA) 1011 1012 1013 #endif /* __KERNEL__ */ 1014 #endif /* _FORE200E_H */ 1015