1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Physical Function ethernet driver
3  *
4  * Copyright (C) 2020 Marvell.
5  *
6  */
7 
8 #include <linux/module.h>
9 #include <linux/interrupt.h>
10 #include <linux/pci.h>
11 #include <linux/etherdevice.h>
12 #include <linux/of.h>
13 #include <linux/if_vlan.h>
14 #include <linux/iommu.h>
15 #include <net/ip.h>
16 #include <linux/bpf.h>
17 #include <linux/bpf_trace.h>
18 #include <linux/bitfield.h>
19 
20 #include "otx2_reg.h"
21 #include "otx2_common.h"
22 #include "otx2_txrx.h"
23 #include "otx2_struct.h"
24 #include "otx2_ptp.h"
25 #include "cn10k.h"
26 #include <rvu_trace.h>
27 
28 #define DRV_NAME	"rvu_nicpf"
29 #define DRV_STRING	"Marvell RVU NIC Physical Function Driver"
30 
31 /* Supported devices */
32 static const struct pci_device_id otx2_pf_id_table[] = {
33 	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) },
34 	{ 0, }  /* end of table */
35 };
36 
37 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
38 MODULE_DESCRIPTION(DRV_STRING);
39 MODULE_LICENSE("GPL v2");
40 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table);
41 
42 static void otx2_vf_link_event_task(struct work_struct *work);
43 
44 enum {
45 	TYPE_PFAF,
46 	TYPE_PFVF,
47 };
48 
49 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable);
50 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable);
51 
otx2_change_mtu(struct net_device * netdev,int new_mtu)52 static int otx2_change_mtu(struct net_device *netdev, int new_mtu)
53 {
54 	struct otx2_nic *pf = netdev_priv(netdev);
55 	bool if_up = netif_running(netdev);
56 	int err = 0;
57 
58 	if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) {
59 		netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n",
60 			    netdev->mtu);
61 		return -EINVAL;
62 	}
63 	if (if_up)
64 		otx2_stop(netdev);
65 
66 	netdev_info(netdev, "Changing MTU from %d to %d\n",
67 		    netdev->mtu, new_mtu);
68 	netdev->mtu = new_mtu;
69 
70 	if (if_up)
71 		err = otx2_open(netdev);
72 
73 	return err;
74 }
75 
otx2_disable_flr_me_intr(struct otx2_nic * pf)76 static void otx2_disable_flr_me_intr(struct otx2_nic *pf)
77 {
78 	int irq, vfs = pf->total_vfs;
79 
80 	/* Disable VFs ME interrupts */
81 	otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
82 	irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0);
83 	free_irq(irq, pf);
84 
85 	/* Disable VFs FLR interrupts */
86 	otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
87 	irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0);
88 	free_irq(irq, pf);
89 
90 	if (vfs <= 64)
91 		return;
92 
93 	otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
94 	irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1);
95 	free_irq(irq, pf);
96 
97 	otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
98 	irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1);
99 	free_irq(irq, pf);
100 }
101 
otx2_flr_wq_destroy(struct otx2_nic * pf)102 static void otx2_flr_wq_destroy(struct otx2_nic *pf)
103 {
104 	if (!pf->flr_wq)
105 		return;
106 	destroy_workqueue(pf->flr_wq);
107 	pf->flr_wq = NULL;
108 	devm_kfree(pf->dev, pf->flr_wrk);
109 }
110 
otx2_flr_handler(struct work_struct * work)111 static void otx2_flr_handler(struct work_struct *work)
112 {
113 	struct flr_work *flrwork = container_of(work, struct flr_work, work);
114 	struct otx2_nic *pf = flrwork->pf;
115 	struct mbox *mbox = &pf->mbox;
116 	struct msg_req *req;
117 	int vf, reg = 0;
118 
119 	vf = flrwork - pf->flr_wrk;
120 
121 	mutex_lock(&mbox->lock);
122 	req = otx2_mbox_alloc_msg_vf_flr(mbox);
123 	if (!req) {
124 		mutex_unlock(&mbox->lock);
125 		return;
126 	}
127 	req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK;
128 	req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK;
129 
130 	if (!otx2_sync_mbox_msg(&pf->mbox)) {
131 		if (vf >= 64) {
132 			reg = 1;
133 			vf = vf - 64;
134 		}
135 		/* clear transcation pending bit */
136 		otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
137 		otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
138 	}
139 
140 	mutex_unlock(&mbox->lock);
141 }
142 
otx2_pf_flr_intr_handler(int irq,void * pf_irq)143 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq)
144 {
145 	struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
146 	int reg, dev, vf, start_vf, num_reg = 1;
147 	u64 intr;
148 
149 	if (pf->total_vfs > 64)
150 		num_reg = 2;
151 
152 	for (reg = 0; reg < num_reg; reg++) {
153 		intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg));
154 		if (!intr)
155 			continue;
156 		start_vf = 64 * reg;
157 		for (vf = 0; vf < 64; vf++) {
158 			if (!(intr & BIT_ULL(vf)))
159 				continue;
160 			dev = vf + start_vf;
161 			queue_work(pf->flr_wq, &pf->flr_wrk[dev].work);
162 			/* Clear interrupt */
163 			otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
164 			/* Disable the interrupt */
165 			otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg),
166 				     BIT_ULL(vf));
167 		}
168 	}
169 	return IRQ_HANDLED;
170 }
171 
otx2_pf_me_intr_handler(int irq,void * pf_irq)172 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq)
173 {
174 	struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
175 	int vf, reg, num_reg = 1;
176 	u64 intr;
177 
178 	if (pf->total_vfs > 64)
179 		num_reg = 2;
180 
181 	for (reg = 0; reg < num_reg; reg++) {
182 		intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg));
183 		if (!intr)
184 			continue;
185 		for (vf = 0; vf < 64; vf++) {
186 			if (!(intr & BIT_ULL(vf)))
187 				continue;
188 			/* clear trpend bit */
189 			otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
190 			/* clear interrupt */
191 			otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf));
192 		}
193 	}
194 	return IRQ_HANDLED;
195 }
196 
otx2_register_flr_me_intr(struct otx2_nic * pf,int numvfs)197 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs)
198 {
199 	struct otx2_hw *hw = &pf->hw;
200 	char *irq_name;
201 	int ret;
202 
203 	/* Register ME interrupt handler*/
204 	irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE];
205 	snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc));
206 	ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0),
207 			  otx2_pf_me_intr_handler, 0, irq_name, pf);
208 	if (ret) {
209 		dev_err(pf->dev,
210 			"RVUPF: IRQ registration failed for ME0\n");
211 	}
212 
213 	/* Register FLR interrupt handler */
214 	irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE];
215 	snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc));
216 	ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0),
217 			  otx2_pf_flr_intr_handler, 0, irq_name, pf);
218 	if (ret) {
219 		dev_err(pf->dev,
220 			"RVUPF: IRQ registration failed for FLR0\n");
221 		return ret;
222 	}
223 
224 	if (numvfs > 64) {
225 		irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE];
226 		snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1",
227 			 rvu_get_pf(pf->pcifunc));
228 		ret = request_irq(pci_irq_vector
229 				  (pf->pdev, RVU_PF_INT_VEC_VFME1),
230 				  otx2_pf_me_intr_handler, 0, irq_name, pf);
231 		if (ret) {
232 			dev_err(pf->dev,
233 				"RVUPF: IRQ registration failed for ME1\n");
234 		}
235 		irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE];
236 		snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1",
237 			 rvu_get_pf(pf->pcifunc));
238 		ret = request_irq(pci_irq_vector
239 				  (pf->pdev, RVU_PF_INT_VEC_VFFLR1),
240 				  otx2_pf_flr_intr_handler, 0, irq_name, pf);
241 		if (ret) {
242 			dev_err(pf->dev,
243 				"RVUPF: IRQ registration failed for FLR1\n");
244 			return ret;
245 		}
246 	}
247 
248 	/* Enable ME interrupt for all VFs*/
249 	otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs));
250 	otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs));
251 
252 	/* Enable FLR interrupt for all VFs*/
253 	otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs));
254 	otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs));
255 
256 	if (numvfs > 64) {
257 		numvfs -= 64;
258 
259 		otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs));
260 		otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1),
261 			     INTR_MASK(numvfs));
262 
263 		otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs));
264 		otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1),
265 			     INTR_MASK(numvfs));
266 	}
267 	return 0;
268 }
269 
otx2_pf_flr_init(struct otx2_nic * pf,int num_vfs)270 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs)
271 {
272 	int vf;
273 
274 	pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq",
275 				     WQ_UNBOUND | WQ_HIGHPRI, 1);
276 	if (!pf->flr_wq)
277 		return -ENOMEM;
278 
279 	pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs,
280 				   sizeof(struct flr_work), GFP_KERNEL);
281 	if (!pf->flr_wrk) {
282 		destroy_workqueue(pf->flr_wq);
283 		return -ENOMEM;
284 	}
285 
286 	for (vf = 0; vf < num_vfs; vf++) {
287 		pf->flr_wrk[vf].pf = pf;
288 		INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler);
289 	}
290 
291 	return 0;
292 }
293 
otx2_queue_work(struct mbox * mw,struct workqueue_struct * mbox_wq,int first,int mdevs,u64 intr,int type)294 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq,
295 			    int first, int mdevs, u64 intr, int type)
296 {
297 	struct otx2_mbox_dev *mdev;
298 	struct otx2_mbox *mbox;
299 	struct mbox_hdr *hdr;
300 	int i;
301 
302 	for (i = first; i < mdevs; i++) {
303 		/* start from 0 */
304 		if (!(intr & BIT_ULL(i - first)))
305 			continue;
306 
307 		mbox = &mw->mbox;
308 		mdev = &mbox->dev[i];
309 		if (type == TYPE_PFAF)
310 			otx2_sync_mbox_bbuf(mbox, i);
311 		hdr = mdev->mbase + mbox->rx_start;
312 		/* The hdr->num_msgs is set to zero immediately in the interrupt
313 		 * handler to  ensure that it holds a correct value next time
314 		 * when the interrupt handler is called.
315 		 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler
316 		 * pf>mbox.up_num_msgs holds the data for use in
317 		 * pfaf_mbox_up_handler.
318 		 */
319 		if (hdr->num_msgs) {
320 			mw[i].num_msgs = hdr->num_msgs;
321 			hdr->num_msgs = 0;
322 			if (type == TYPE_PFAF)
323 				memset(mbox->hwbase + mbox->rx_start, 0,
324 				       ALIGN(sizeof(struct mbox_hdr),
325 					     sizeof(u64)));
326 
327 			queue_work(mbox_wq, &mw[i].mbox_wrk);
328 		}
329 
330 		mbox = &mw->mbox_up;
331 		mdev = &mbox->dev[i];
332 		if (type == TYPE_PFAF)
333 			otx2_sync_mbox_bbuf(mbox, i);
334 		hdr = mdev->mbase + mbox->rx_start;
335 		if (hdr->num_msgs) {
336 			mw[i].up_num_msgs = hdr->num_msgs;
337 			hdr->num_msgs = 0;
338 			if (type == TYPE_PFAF)
339 				memset(mbox->hwbase + mbox->rx_start, 0,
340 				       ALIGN(sizeof(struct mbox_hdr),
341 					     sizeof(u64)));
342 
343 			queue_work(mbox_wq, &mw[i].mbox_up_wrk);
344 		}
345 	}
346 }
347 
otx2_forward_msg_pfvf(struct otx2_mbox_dev * mdev,struct otx2_mbox * pfvf_mbox,void * bbuf_base,int devid)348 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev,
349 				  struct otx2_mbox *pfvf_mbox, void *bbuf_base,
350 				  int devid)
351 {
352 	struct otx2_mbox_dev *src_mdev = mdev;
353 	int offset;
354 
355 	/* Msgs are already copied, trigger VF's mbox irq */
356 	smp_wmb();
357 
358 	offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift);
359 	writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset);
360 
361 	/* Restore VF's mbox bounce buffer region address */
362 	src_mdev->mbase = bbuf_base;
363 }
364 
otx2_forward_vf_mbox_msgs(struct otx2_nic * pf,struct otx2_mbox * src_mbox,int dir,int vf,int num_msgs)365 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf,
366 				     struct otx2_mbox *src_mbox,
367 				     int dir, int vf, int num_msgs)
368 {
369 	struct otx2_mbox_dev *src_mdev, *dst_mdev;
370 	struct mbox_hdr *mbox_hdr;
371 	struct mbox_hdr *req_hdr;
372 	struct mbox *dst_mbox;
373 	int dst_size, err;
374 
375 	if (dir == MBOX_DIR_PFAF) {
376 		/* Set VF's mailbox memory as PF's bounce buffer memory, so
377 		 * that explicit copying of VF's msgs to PF=>AF mbox region
378 		 * and AF=>PF responses to VF's mbox region can be avoided.
379 		 */
380 		src_mdev = &src_mbox->dev[vf];
381 		mbox_hdr = src_mbox->hwbase +
382 				src_mbox->rx_start + (vf * MBOX_SIZE);
383 
384 		dst_mbox = &pf->mbox;
385 		dst_size = dst_mbox->mbox.tx_size -
386 				ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN);
387 		/* Check if msgs fit into destination area and has valid size */
388 		if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size)
389 			return -EINVAL;
390 
391 		dst_mdev = &dst_mbox->mbox.dev[0];
392 
393 		mutex_lock(&pf->mbox.lock);
394 		dst_mdev->mbase = src_mdev->mbase;
395 		dst_mdev->msg_size = mbox_hdr->msg_size;
396 		dst_mdev->num_msgs = num_msgs;
397 		err = otx2_sync_mbox_msg(dst_mbox);
398 		/* Error code -EIO indicate there is a communication failure
399 		 * to the AF. Rest of the error codes indicate that AF processed
400 		 * VF messages and set the error codes in response messages
401 		 * (if any) so simply forward responses to VF.
402 		 */
403 		if (err == -EIO) {
404 			dev_warn(pf->dev,
405 				 "AF not responding to VF%d messages\n", vf);
406 			/* restore PF mbase and exit */
407 			dst_mdev->mbase = pf->mbox.bbuf_base;
408 			mutex_unlock(&pf->mbox.lock);
409 			return err;
410 		}
411 		/* At this point, all the VF messages sent to AF are acked
412 		 * with proper responses and responses are copied to VF
413 		 * mailbox hence raise interrupt to VF.
414 		 */
415 		req_hdr = (struct mbox_hdr *)(dst_mdev->mbase +
416 					      dst_mbox->mbox.rx_start);
417 		req_hdr->num_msgs = num_msgs;
418 
419 		otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox,
420 				      pf->mbox.bbuf_base, vf);
421 		mutex_unlock(&pf->mbox.lock);
422 	} else if (dir == MBOX_DIR_PFVF_UP) {
423 		src_mdev = &src_mbox->dev[0];
424 		mbox_hdr = src_mbox->hwbase + src_mbox->rx_start;
425 		req_hdr = (struct mbox_hdr *)(src_mdev->mbase +
426 					      src_mbox->rx_start);
427 		req_hdr->num_msgs = num_msgs;
428 
429 		dst_mbox = &pf->mbox_pfvf[0];
430 		dst_size = dst_mbox->mbox_up.tx_size -
431 				ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN);
432 		/* Check if msgs fit into destination area */
433 		if (mbox_hdr->msg_size > dst_size)
434 			return -EINVAL;
435 
436 		dst_mdev = &dst_mbox->mbox_up.dev[vf];
437 		dst_mdev->mbase = src_mdev->mbase;
438 		dst_mdev->msg_size = mbox_hdr->msg_size;
439 		dst_mdev->num_msgs = mbox_hdr->num_msgs;
440 		err = otx2_sync_mbox_up_msg(dst_mbox, vf);
441 		if (err) {
442 			dev_warn(pf->dev,
443 				 "VF%d is not responding to mailbox\n", vf);
444 			return err;
445 		}
446 	} else if (dir == MBOX_DIR_VFPF_UP) {
447 		req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase +
448 					      src_mbox->rx_start);
449 		req_hdr->num_msgs = num_msgs;
450 		otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf],
451 				      &pf->mbox.mbox_up,
452 				      pf->mbox_pfvf[vf].bbuf_base,
453 				      0);
454 	}
455 
456 	return 0;
457 }
458 
otx2_pfvf_mbox_handler(struct work_struct * work)459 static void otx2_pfvf_mbox_handler(struct work_struct *work)
460 {
461 	struct mbox_msghdr *msg = NULL;
462 	int offset, vf_idx, id, err;
463 	struct otx2_mbox_dev *mdev;
464 	struct mbox_hdr *req_hdr;
465 	struct otx2_mbox *mbox;
466 	struct mbox *vf_mbox;
467 	struct otx2_nic *pf;
468 
469 	vf_mbox = container_of(work, struct mbox, mbox_wrk);
470 	pf = vf_mbox->pfvf;
471 	vf_idx = vf_mbox - pf->mbox_pfvf;
472 
473 	mbox = &pf->mbox_pfvf[0].mbox;
474 	mdev = &mbox->dev[vf_idx];
475 	req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
476 
477 	offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
478 
479 	for (id = 0; id < vf_mbox->num_msgs; id++) {
480 		msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start +
481 					     offset);
482 
483 		if (msg->sig != OTX2_MBOX_REQ_SIG)
484 			goto inval_msg;
485 
486 		/* Set VF's number in each of the msg */
487 		msg->pcifunc &= RVU_PFVF_FUNC_MASK;
488 		msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK;
489 		offset = msg->next_msgoff;
490 	}
491 	err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx,
492 					vf_mbox->num_msgs);
493 	if (err)
494 		goto inval_msg;
495 	return;
496 
497 inval_msg:
498 	otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id);
499 	otx2_mbox_msg_send(mbox, vf_idx);
500 }
501 
otx2_pfvf_mbox_up_handler(struct work_struct * work)502 static void otx2_pfvf_mbox_up_handler(struct work_struct *work)
503 {
504 	struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk);
505 	struct otx2_nic *pf = vf_mbox->pfvf;
506 	struct otx2_mbox_dev *mdev;
507 	int offset, id, vf_idx = 0;
508 	struct mbox_hdr *rsp_hdr;
509 	struct mbox_msghdr *msg;
510 	struct otx2_mbox *mbox;
511 
512 	vf_idx = vf_mbox - pf->mbox_pfvf;
513 	mbox = &pf->mbox_pfvf[0].mbox_up;
514 	mdev = &mbox->dev[vf_idx];
515 
516 	rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
517 	offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
518 
519 	for (id = 0; id < vf_mbox->up_num_msgs; id++) {
520 		msg = mdev->mbase + offset;
521 
522 		if (msg->id >= MBOX_MSG_MAX) {
523 			dev_err(pf->dev,
524 				"Mbox msg with unknown ID 0x%x\n", msg->id);
525 			goto end;
526 		}
527 
528 		if (msg->sig != OTX2_MBOX_RSP_SIG) {
529 			dev_err(pf->dev,
530 				"Mbox msg with wrong signature %x, ID 0x%x\n",
531 				msg->sig, msg->id);
532 			goto end;
533 		}
534 
535 		switch (msg->id) {
536 		case MBOX_MSG_CGX_LINK_EVENT:
537 			break;
538 		default:
539 			if (msg->rc)
540 				dev_err(pf->dev,
541 					"Mbox msg response has err %d, ID 0x%x\n",
542 					msg->rc, msg->id);
543 			break;
544 		}
545 
546 end:
547 		offset = mbox->rx_start + msg->next_msgoff;
548 		if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1))
549 			__otx2_mbox_reset(mbox, 0);
550 		mdev->msgs_acked++;
551 	}
552 }
553 
otx2_pfvf_mbox_intr_handler(int irq,void * pf_irq)554 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq)
555 {
556 	struct otx2_nic *pf = (struct otx2_nic *)(pf_irq);
557 	int vfs = pf->total_vfs;
558 	struct mbox *mbox;
559 	u64 intr;
560 
561 	mbox = pf->mbox_pfvf;
562 	/* Handle VF interrupts */
563 	if (vfs > 64) {
564 		intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1));
565 		otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr);
566 		otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr,
567 				TYPE_PFVF);
568 		vfs -= 64;
569 	}
570 
571 	intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0));
572 	otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr);
573 
574 	otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF);
575 
576 	trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr);
577 
578 	return IRQ_HANDLED;
579 }
580 
otx2_pfvf_mbox_init(struct otx2_nic * pf,int numvfs)581 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs)
582 {
583 	void __iomem *hwbase;
584 	struct mbox *mbox;
585 	int err, vf;
586 	u64 base;
587 
588 	if (!numvfs)
589 		return -EINVAL;
590 
591 	pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs,
592 				     sizeof(struct mbox), GFP_KERNEL);
593 	if (!pf->mbox_pfvf)
594 		return -ENOMEM;
595 
596 	pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox",
597 					   WQ_UNBOUND | WQ_HIGHPRI |
598 					   WQ_MEM_RECLAIM, 1);
599 	if (!pf->mbox_pfvf_wq)
600 		return -ENOMEM;
601 
602 	/* On CN10K platform, PF <-> VF mailbox region follows after
603 	 * PF <-> AF mailbox region.
604 	 */
605 	if (test_bit(CN10K_MBOX, &pf->hw.cap_flag))
606 		base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) +
607 		       MBOX_SIZE;
608 	else
609 		base = readq((void __iomem *)((u64)pf->reg_base +
610 					      RVU_PF_VF_BAR4_ADDR));
611 
612 	hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs);
613 	if (!hwbase) {
614 		err = -ENOMEM;
615 		goto free_wq;
616 	}
617 
618 	mbox = &pf->mbox_pfvf[0];
619 	err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
620 			     MBOX_DIR_PFVF, numvfs);
621 	if (err)
622 		goto free_iomem;
623 
624 	err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
625 			     MBOX_DIR_PFVF_UP, numvfs);
626 	if (err)
627 		goto free_iomem;
628 
629 	for (vf = 0; vf < numvfs; vf++) {
630 		mbox->pfvf = pf;
631 		INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler);
632 		INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler);
633 		mbox++;
634 	}
635 
636 	return 0;
637 
638 free_iomem:
639 	if (hwbase)
640 		iounmap(hwbase);
641 free_wq:
642 	destroy_workqueue(pf->mbox_pfvf_wq);
643 	return err;
644 }
645 
otx2_pfvf_mbox_destroy(struct otx2_nic * pf)646 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf)
647 {
648 	struct mbox *mbox = &pf->mbox_pfvf[0];
649 
650 	if (!mbox)
651 		return;
652 
653 	if (pf->mbox_pfvf_wq) {
654 		destroy_workqueue(pf->mbox_pfvf_wq);
655 		pf->mbox_pfvf_wq = NULL;
656 	}
657 
658 	if (mbox->mbox.hwbase)
659 		iounmap(mbox->mbox.hwbase);
660 
661 	otx2_mbox_destroy(&mbox->mbox);
662 }
663 
otx2_enable_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)664 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
665 {
666 	/* Clear PF <=> VF mailbox IRQ */
667 	otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
668 	otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
669 
670 	/* Enable PF <=> VF mailbox IRQ */
671 	otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs));
672 	if (numvfs > 64) {
673 		numvfs -= 64;
674 		otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
675 			     INTR_MASK(numvfs));
676 	}
677 }
678 
otx2_disable_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)679 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
680 {
681 	int vector;
682 
683 	/* Disable PF <=> VF mailbox IRQ */
684 	otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull);
685 	otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull);
686 
687 	otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
688 	vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0);
689 	free_irq(vector, pf);
690 
691 	if (numvfs > 64) {
692 		otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
693 		vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1);
694 		free_irq(vector, pf);
695 	}
696 }
697 
otx2_register_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)698 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
699 {
700 	struct otx2_hw *hw = &pf->hw;
701 	char *irq_name;
702 	int err;
703 
704 	/* Register MBOX0 interrupt handler */
705 	irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE];
706 	if (pf->pcifunc)
707 		snprintf(irq_name, NAME_SIZE,
708 			 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc));
709 	else
710 		snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0");
711 	err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0),
712 			  otx2_pfvf_mbox_intr_handler, 0, irq_name, pf);
713 	if (err) {
714 		dev_err(pf->dev,
715 			"RVUPF: IRQ registration failed for PFVF mbox0 irq\n");
716 		return err;
717 	}
718 
719 	if (numvfs > 64) {
720 		/* Register MBOX1 interrupt handler */
721 		irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE];
722 		if (pf->pcifunc)
723 			snprintf(irq_name, NAME_SIZE,
724 				 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc));
725 		else
726 			snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1");
727 		err = request_irq(pci_irq_vector(pf->pdev,
728 						 RVU_PF_INT_VEC_VFPF_MBOX1),
729 						 otx2_pfvf_mbox_intr_handler,
730 						 0, irq_name, pf);
731 		if (err) {
732 			dev_err(pf->dev,
733 				"RVUPF: IRQ registration failed for PFVF mbox1 irq\n");
734 			return err;
735 		}
736 	}
737 
738 	otx2_enable_pfvf_mbox_intr(pf, numvfs);
739 
740 	return 0;
741 }
742 
otx2_process_pfaf_mbox_msg(struct otx2_nic * pf,struct mbox_msghdr * msg)743 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf,
744 				       struct mbox_msghdr *msg)
745 {
746 	int devid;
747 
748 	if (msg->id >= MBOX_MSG_MAX) {
749 		dev_err(pf->dev,
750 			"Mbox msg with unknown ID 0x%x\n", msg->id);
751 		return;
752 	}
753 
754 	if (msg->sig != OTX2_MBOX_RSP_SIG) {
755 		dev_err(pf->dev,
756 			"Mbox msg with wrong signature %x, ID 0x%x\n",
757 			 msg->sig, msg->id);
758 		return;
759 	}
760 
761 	/* message response heading VF */
762 	devid = msg->pcifunc & RVU_PFVF_FUNC_MASK;
763 	if (devid) {
764 		struct otx2_vf_config *config = &pf->vf_configs[devid - 1];
765 		struct delayed_work *dwork;
766 
767 		switch (msg->id) {
768 		case MBOX_MSG_NIX_LF_START_RX:
769 			config->intf_down = false;
770 			dwork = &config->link_event_work;
771 			schedule_delayed_work(dwork, msecs_to_jiffies(100));
772 			break;
773 		case MBOX_MSG_NIX_LF_STOP_RX:
774 			config->intf_down = true;
775 			break;
776 		}
777 
778 		return;
779 	}
780 
781 	switch (msg->id) {
782 	case MBOX_MSG_READY:
783 		pf->pcifunc = msg->pcifunc;
784 		break;
785 	case MBOX_MSG_MSIX_OFFSET:
786 		mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg);
787 		break;
788 	case MBOX_MSG_NPA_LF_ALLOC:
789 		mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg);
790 		break;
791 	case MBOX_MSG_NIX_LF_ALLOC:
792 		mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg);
793 		break;
794 	case MBOX_MSG_NIX_TXSCH_ALLOC:
795 		mbox_handler_nix_txsch_alloc(pf,
796 					     (struct nix_txsch_alloc_rsp *)msg);
797 		break;
798 	case MBOX_MSG_NIX_BP_ENABLE:
799 		mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg);
800 		break;
801 	case MBOX_MSG_CGX_STATS:
802 		mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg);
803 		break;
804 	case MBOX_MSG_CGX_FEC_STATS:
805 		mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg);
806 		break;
807 	default:
808 		if (msg->rc)
809 			dev_err(pf->dev,
810 				"Mbox msg response has err %d, ID 0x%x\n",
811 				msg->rc, msg->id);
812 		break;
813 	}
814 }
815 
otx2_pfaf_mbox_handler(struct work_struct * work)816 static void otx2_pfaf_mbox_handler(struct work_struct *work)
817 {
818 	struct otx2_mbox_dev *mdev;
819 	struct mbox_hdr *rsp_hdr;
820 	struct mbox_msghdr *msg;
821 	struct otx2_mbox *mbox;
822 	struct mbox *af_mbox;
823 	struct otx2_nic *pf;
824 	int offset, id;
825 
826 	af_mbox = container_of(work, struct mbox, mbox_wrk);
827 	mbox = &af_mbox->mbox;
828 	mdev = &mbox->dev[0];
829 	rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
830 
831 	offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
832 	pf = af_mbox->pfvf;
833 
834 	for (id = 0; id < af_mbox->num_msgs; id++) {
835 		msg = (struct mbox_msghdr *)(mdev->mbase + offset);
836 		otx2_process_pfaf_mbox_msg(pf, msg);
837 		offset = mbox->rx_start + msg->next_msgoff;
838 		if (mdev->msgs_acked == (af_mbox->num_msgs - 1))
839 			__otx2_mbox_reset(mbox, 0);
840 		mdev->msgs_acked++;
841 	}
842 
843 }
844 
otx2_handle_link_event(struct otx2_nic * pf)845 static void otx2_handle_link_event(struct otx2_nic *pf)
846 {
847 	struct cgx_link_user_info *linfo = &pf->linfo;
848 	struct net_device *netdev = pf->netdev;
849 
850 	pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name,
851 		linfo->link_up ? "UP" : "DOWN", linfo->speed,
852 		linfo->full_duplex ? "Full" : "Half");
853 	if (linfo->link_up) {
854 		netif_carrier_on(netdev);
855 		netif_tx_start_all_queues(netdev);
856 	} else {
857 		netif_tx_stop_all_queues(netdev);
858 		netif_carrier_off(netdev);
859 	}
860 }
861 
otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic * pf,struct mcs_intr_info * event,struct msg_rsp * rsp)862 int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf,
863 					 struct mcs_intr_info *event,
864 					 struct msg_rsp *rsp)
865 {
866 	cn10k_handle_mcs_event(pf, event);
867 
868 	return 0;
869 }
870 
otx2_mbox_up_handler_cgx_link_event(struct otx2_nic * pf,struct cgx_link_info_msg * msg,struct msg_rsp * rsp)871 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf,
872 					struct cgx_link_info_msg *msg,
873 					struct msg_rsp *rsp)
874 {
875 	int i;
876 
877 	/* Copy the link info sent by AF */
878 	pf->linfo = msg->link_info;
879 
880 	/* notify VFs about link event */
881 	for (i = 0; i < pci_num_vf(pf->pdev); i++) {
882 		struct otx2_vf_config *config = &pf->vf_configs[i];
883 		struct delayed_work *dwork = &config->link_event_work;
884 
885 		if (config->intf_down)
886 			continue;
887 
888 		schedule_delayed_work(dwork, msecs_to_jiffies(100));
889 	}
890 
891 	/* interface has not been fully configured yet */
892 	if (pf->flags & OTX2_FLAG_INTF_DOWN)
893 		return 0;
894 
895 	otx2_handle_link_event(pf);
896 	return 0;
897 }
898 
otx2_process_mbox_msg_up(struct otx2_nic * pf,struct mbox_msghdr * req)899 static int otx2_process_mbox_msg_up(struct otx2_nic *pf,
900 				    struct mbox_msghdr *req)
901 {
902 	/* Check if valid, if not reply with a invalid msg */
903 	if (req->sig != OTX2_MBOX_REQ_SIG) {
904 		otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
905 		return -ENODEV;
906 	}
907 
908 	switch (req->id) {
909 #define M(_name, _id, _fn_name, _req_type, _rsp_type)			\
910 	case _id: {							\
911 		struct _rsp_type *rsp;					\
912 		int err;						\
913 									\
914 		rsp = (struct _rsp_type *)otx2_mbox_alloc_msg(		\
915 			&pf->mbox.mbox_up, 0,				\
916 			sizeof(struct _rsp_type));			\
917 		if (!rsp)						\
918 			return -ENOMEM;					\
919 									\
920 		rsp->hdr.id = _id;					\
921 		rsp->hdr.sig = OTX2_MBOX_RSP_SIG;			\
922 		rsp->hdr.pcifunc = 0;					\
923 		rsp->hdr.rc = 0;					\
924 									\
925 		err = otx2_mbox_up_handler_ ## _fn_name(		\
926 			pf, (struct _req_type *)req, rsp);		\
927 		return err;						\
928 	}
929 MBOX_UP_CGX_MESSAGES
930 MBOX_UP_MCS_MESSAGES
931 #undef M
932 		break;
933 	default:
934 		otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
935 		return -ENODEV;
936 	}
937 	return 0;
938 }
939 
otx2_pfaf_mbox_up_handler(struct work_struct * work)940 static void otx2_pfaf_mbox_up_handler(struct work_struct *work)
941 {
942 	struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk);
943 	struct otx2_mbox *mbox = &af_mbox->mbox_up;
944 	struct otx2_mbox_dev *mdev = &mbox->dev[0];
945 	struct otx2_nic *pf = af_mbox->pfvf;
946 	int offset, id, devid = 0;
947 	struct mbox_hdr *rsp_hdr;
948 	struct mbox_msghdr *msg;
949 
950 	rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
951 
952 	offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
953 
954 	for (id = 0; id < af_mbox->up_num_msgs; id++) {
955 		msg = (struct mbox_msghdr *)(mdev->mbase + offset);
956 
957 		devid = msg->pcifunc & RVU_PFVF_FUNC_MASK;
958 		/* Skip processing VF's messages */
959 		if (!devid)
960 			otx2_process_mbox_msg_up(pf, msg);
961 		offset = mbox->rx_start + msg->next_msgoff;
962 	}
963 	if (devid) {
964 		otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up,
965 					  MBOX_DIR_PFVF_UP, devid - 1,
966 					  af_mbox->up_num_msgs);
967 		return;
968 	}
969 
970 	otx2_mbox_msg_send(mbox, 0);
971 }
972 
otx2_pfaf_mbox_intr_handler(int irq,void * pf_irq)973 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq)
974 {
975 	struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
976 	struct mbox *mbox;
977 
978 	/* Clear the IRQ */
979 	otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
980 
981 	mbox = &pf->mbox;
982 
983 	trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0));
984 
985 	otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF);
986 
987 	return IRQ_HANDLED;
988 }
989 
otx2_disable_mbox_intr(struct otx2_nic * pf)990 static void otx2_disable_mbox_intr(struct otx2_nic *pf)
991 {
992 	int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX);
993 
994 	/* Disable AF => PF mailbox IRQ */
995 	otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0));
996 	free_irq(vector, pf);
997 }
998 
otx2_register_mbox_intr(struct otx2_nic * pf,bool probe_af)999 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af)
1000 {
1001 	struct otx2_hw *hw = &pf->hw;
1002 	struct msg_req *req;
1003 	char *irq_name;
1004 	int err;
1005 
1006 	/* Register mailbox interrupt handler */
1007 	irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE];
1008 	snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox");
1009 	err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX),
1010 			  otx2_pfaf_mbox_intr_handler, 0, irq_name, pf);
1011 	if (err) {
1012 		dev_err(pf->dev,
1013 			"RVUPF: IRQ registration failed for PFAF mbox irq\n");
1014 		return err;
1015 	}
1016 
1017 	/* Enable mailbox interrupt for msgs coming from AF.
1018 	 * First clear to avoid spurious interrupts, if any.
1019 	 */
1020 	otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
1021 	otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0));
1022 
1023 	if (!probe_af)
1024 		return 0;
1025 
1026 	/* Check mailbox communication with AF */
1027 	req = otx2_mbox_alloc_msg_ready(&pf->mbox);
1028 	if (!req) {
1029 		otx2_disable_mbox_intr(pf);
1030 		return -ENOMEM;
1031 	}
1032 	err = otx2_sync_mbox_msg(&pf->mbox);
1033 	if (err) {
1034 		dev_warn(pf->dev,
1035 			 "AF not responding to mailbox, deferring probe\n");
1036 		otx2_disable_mbox_intr(pf);
1037 		return -EPROBE_DEFER;
1038 	}
1039 
1040 	return 0;
1041 }
1042 
otx2_pfaf_mbox_destroy(struct otx2_nic * pf)1043 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf)
1044 {
1045 	struct mbox *mbox = &pf->mbox;
1046 
1047 	if (pf->mbox_wq) {
1048 		destroy_workqueue(pf->mbox_wq);
1049 		pf->mbox_wq = NULL;
1050 	}
1051 
1052 	if (mbox->mbox.hwbase)
1053 		iounmap((void __iomem *)mbox->mbox.hwbase);
1054 
1055 	otx2_mbox_destroy(&mbox->mbox);
1056 	otx2_mbox_destroy(&mbox->mbox_up);
1057 }
1058 
otx2_pfaf_mbox_init(struct otx2_nic * pf)1059 static int otx2_pfaf_mbox_init(struct otx2_nic *pf)
1060 {
1061 	struct mbox *mbox = &pf->mbox;
1062 	void __iomem *hwbase;
1063 	int err;
1064 
1065 	mbox->pfvf = pf;
1066 	pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox",
1067 				      WQ_UNBOUND | WQ_HIGHPRI |
1068 				      WQ_MEM_RECLAIM, 1);
1069 	if (!pf->mbox_wq)
1070 		return -ENOMEM;
1071 
1072 	/* Mailbox is a reserved memory (in RAM) region shared between
1073 	 * admin function (i.e AF) and this PF, shouldn't be mapped as
1074 	 * device memory to allow unaligned accesses.
1075 	 */
1076 	hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM),
1077 			    MBOX_SIZE);
1078 	if (!hwbase) {
1079 		dev_err(pf->dev, "Unable to map PFAF mailbox region\n");
1080 		err = -ENOMEM;
1081 		goto exit;
1082 	}
1083 
1084 	err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
1085 			     MBOX_DIR_PFAF, 1);
1086 	if (err)
1087 		goto exit;
1088 
1089 	err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
1090 			     MBOX_DIR_PFAF_UP, 1);
1091 	if (err)
1092 		goto exit;
1093 
1094 	err = otx2_mbox_bbuf_init(mbox, pf->pdev);
1095 	if (err)
1096 		goto exit;
1097 
1098 	INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler);
1099 	INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler);
1100 	mutex_init(&mbox->lock);
1101 
1102 	return 0;
1103 exit:
1104 	otx2_pfaf_mbox_destroy(pf);
1105 	return err;
1106 }
1107 
otx2_cgx_config_linkevents(struct otx2_nic * pf,bool enable)1108 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable)
1109 {
1110 	struct msg_req *msg;
1111 	int err;
1112 
1113 	mutex_lock(&pf->mbox.lock);
1114 	if (enable)
1115 		msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox);
1116 	else
1117 		msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox);
1118 
1119 	if (!msg) {
1120 		mutex_unlock(&pf->mbox.lock);
1121 		return -ENOMEM;
1122 	}
1123 
1124 	err = otx2_sync_mbox_msg(&pf->mbox);
1125 	mutex_unlock(&pf->mbox.lock);
1126 	return err;
1127 }
1128 
otx2_cgx_config_loopback(struct otx2_nic * pf,bool enable)1129 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable)
1130 {
1131 	struct msg_req *msg;
1132 	int err;
1133 
1134 	if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap,
1135 				    pf->flow_cfg->dmacflt_max_flows))
1136 		netdev_warn(pf->netdev,
1137 			    "CGX/RPM internal loopback might not work as DMAC filters are active\n");
1138 
1139 	mutex_lock(&pf->mbox.lock);
1140 	if (enable)
1141 		msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox);
1142 	else
1143 		msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox);
1144 
1145 	if (!msg) {
1146 		mutex_unlock(&pf->mbox.lock);
1147 		return -ENOMEM;
1148 	}
1149 
1150 	err = otx2_sync_mbox_msg(&pf->mbox);
1151 	mutex_unlock(&pf->mbox.lock);
1152 	return err;
1153 }
1154 
otx2_set_real_num_queues(struct net_device * netdev,int tx_queues,int rx_queues)1155 int otx2_set_real_num_queues(struct net_device *netdev,
1156 			     int tx_queues, int rx_queues)
1157 {
1158 	int err;
1159 
1160 	err = netif_set_real_num_tx_queues(netdev, tx_queues);
1161 	if (err) {
1162 		netdev_err(netdev,
1163 			   "Failed to set no of Tx queues: %d\n", tx_queues);
1164 		return err;
1165 	}
1166 
1167 	err = netif_set_real_num_rx_queues(netdev, rx_queues);
1168 	if (err)
1169 		netdev_err(netdev,
1170 			   "Failed to set no of Rx queues: %d\n", rx_queues);
1171 	return err;
1172 }
1173 EXPORT_SYMBOL(otx2_set_real_num_queues);
1174 
1175 static char *nix_sqoperr_e_str[NIX_SQOPERR_MAX] = {
1176 	"NIX_SQOPERR_OOR",
1177 	"NIX_SQOPERR_CTX_FAULT",
1178 	"NIX_SQOPERR_CTX_POISON",
1179 	"NIX_SQOPERR_DISABLED",
1180 	"NIX_SQOPERR_SIZE_ERR",
1181 	"NIX_SQOPERR_OFLOW",
1182 	"NIX_SQOPERR_SQB_NULL",
1183 	"NIX_SQOPERR_SQB_FAULT",
1184 	"NIX_SQOPERR_SQE_SZ_ZERO",
1185 };
1186 
1187 static char *nix_mnqerr_e_str[NIX_MNQERR_MAX] = {
1188 	"NIX_MNQERR_SQ_CTX_FAULT",
1189 	"NIX_MNQERR_SQ_CTX_POISON",
1190 	"NIX_MNQERR_SQB_FAULT",
1191 	"NIX_MNQERR_SQB_POISON",
1192 	"NIX_MNQERR_TOTAL_ERR",
1193 	"NIX_MNQERR_LSO_ERR",
1194 	"NIX_MNQERR_CQ_QUERY_ERR",
1195 	"NIX_MNQERR_MAX_SQE_SIZE_ERR",
1196 	"NIX_MNQERR_MAXLEN_ERR",
1197 	"NIX_MNQERR_SQE_SIZEM1_ZERO",
1198 };
1199 
1200 static char *nix_snd_status_e_str[NIX_SND_STATUS_MAX] =  {
1201 	"NIX_SND_STATUS_GOOD",
1202 	"NIX_SND_STATUS_SQ_CTX_FAULT",
1203 	"NIX_SND_STATUS_SQ_CTX_POISON",
1204 	"NIX_SND_STATUS_SQB_FAULT",
1205 	"NIX_SND_STATUS_SQB_POISON",
1206 	"NIX_SND_STATUS_HDR_ERR",
1207 	"NIX_SND_STATUS_EXT_ERR",
1208 	"NIX_SND_STATUS_JUMP_FAULT",
1209 	"NIX_SND_STATUS_JUMP_POISON",
1210 	"NIX_SND_STATUS_CRC_ERR",
1211 	"NIX_SND_STATUS_IMM_ERR",
1212 	"NIX_SND_STATUS_SG_ERR",
1213 	"NIX_SND_STATUS_MEM_ERR",
1214 	"NIX_SND_STATUS_INVALID_SUBDC",
1215 	"NIX_SND_STATUS_SUBDC_ORDER_ERR",
1216 	"NIX_SND_STATUS_DATA_FAULT",
1217 	"NIX_SND_STATUS_DATA_POISON",
1218 	"NIX_SND_STATUS_NPC_DROP_ACTION",
1219 	"NIX_SND_STATUS_LOCK_VIOL",
1220 	"NIX_SND_STATUS_NPC_UCAST_CHAN_ERR",
1221 	"NIX_SND_STATUS_NPC_MCAST_CHAN_ERR",
1222 	"NIX_SND_STATUS_NPC_MCAST_ABORT",
1223 	"NIX_SND_STATUS_NPC_VTAG_PTR_ERR",
1224 	"NIX_SND_STATUS_NPC_VTAG_SIZE_ERR",
1225 	"NIX_SND_STATUS_SEND_STATS_ERR",
1226 };
1227 
otx2_q_intr_handler(int irq,void * data)1228 static irqreturn_t otx2_q_intr_handler(int irq, void *data)
1229 {
1230 	struct otx2_nic *pf = data;
1231 	u64 val, *ptr;
1232 	u64 qidx = 0;
1233 
1234 	/* CQ */
1235 	for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) {
1236 		ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT);
1237 		val = otx2_atomic64_add((qidx << 44), ptr);
1238 
1239 		otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) |
1240 			     (val & NIX_CQERRINT_BITS));
1241 		if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42))))
1242 			continue;
1243 
1244 		if (val & BIT_ULL(42)) {
1245 			netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1246 				   qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1247 		} else {
1248 			if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR))
1249 				netdev_err(pf->netdev, "CQ%lld: Doorbell error",
1250 					   qidx);
1251 			if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT))
1252 				netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM",
1253 					   qidx);
1254 		}
1255 
1256 		schedule_work(&pf->reset_task);
1257 	}
1258 
1259 	/* SQ */
1260 	for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) {
1261 		u64 sq_op_err_dbg, mnq_err_dbg, snd_err_dbg;
1262 		u8 sq_op_err_code, mnq_err_code, snd_err_code;
1263 
1264 		/* Below debug registers captures first errors corresponding to
1265 		 * those registers. We don't have to check against SQ qid as
1266 		 * these are fatal errors.
1267 		 */
1268 
1269 		ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT);
1270 		val = otx2_atomic64_add((qidx << 44), ptr);
1271 		otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) |
1272 			     (val & NIX_SQINT_BITS));
1273 
1274 		if (val & BIT_ULL(42)) {
1275 			netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1276 				   qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1277 			goto done;
1278 		}
1279 
1280 		sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG);
1281 		if (!(sq_op_err_dbg & BIT(44)))
1282 			goto chk_mnq_err_dbg;
1283 
1284 		sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg);
1285 		netdev_err(pf->netdev, "SQ%lld: NIX_LF_SQ_OP_ERR_DBG(%llx)  err=%s\n",
1286 			   qidx, sq_op_err_dbg, nix_sqoperr_e_str[sq_op_err_code]);
1287 
1288 		otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44));
1289 
1290 		if (sq_op_err_code == NIX_SQOPERR_SQB_NULL)
1291 			goto chk_mnq_err_dbg;
1292 
1293 		/* Err is not NIX_SQOPERR_SQB_NULL, call aq function to read SQ structure.
1294 		 * TODO: But we are in irq context. How to call mbox functions which does sleep
1295 		 */
1296 
1297 chk_mnq_err_dbg:
1298 		mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG);
1299 		if (!(mnq_err_dbg & BIT(44)))
1300 			goto chk_snd_err_dbg;
1301 
1302 		mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg);
1303 		netdev_err(pf->netdev, "SQ%lld: NIX_LF_MNQ_ERR_DBG(%llx)  err=%s\n",
1304 			   qidx, mnq_err_dbg,  nix_mnqerr_e_str[mnq_err_code]);
1305 		otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44));
1306 
1307 chk_snd_err_dbg:
1308 		snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG);
1309 		if (snd_err_dbg & BIT(44)) {
1310 			snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg);
1311 			netdev_err(pf->netdev, "SQ%lld: NIX_LF_SND_ERR_DBG:0x%llx err=%s\n",
1312 				   qidx, snd_err_dbg, nix_snd_status_e_str[snd_err_code]);
1313 			otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44));
1314 		}
1315 
1316 done:
1317 		/* Print values and reset */
1318 		if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
1319 			netdev_err(pf->netdev, "SQ%lld: SQB allocation failed",
1320 				   qidx);
1321 
1322 		schedule_work(&pf->reset_task);
1323 	}
1324 
1325 	return IRQ_HANDLED;
1326 }
1327 
otx2_cq_intr_handler(int irq,void * cq_irq)1328 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq)
1329 {
1330 	struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq;
1331 	struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev;
1332 	int qidx = cq_poll->cint_idx;
1333 
1334 	/* Disable interrupts.
1335 	 *
1336 	 * Completion interrupts behave in a level-triggered interrupt
1337 	 * fashion, and hence have to be cleared only after it is serviced.
1338 	 */
1339 	otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1340 
1341 	/* Schedule NAPI */
1342 	pf->napi_events++;
1343 	napi_schedule_irqoff(&cq_poll->napi);
1344 
1345 	return IRQ_HANDLED;
1346 }
1347 
otx2_disable_napi(struct otx2_nic * pf)1348 static void otx2_disable_napi(struct otx2_nic *pf)
1349 {
1350 	struct otx2_qset *qset = &pf->qset;
1351 	struct otx2_cq_poll *cq_poll;
1352 	int qidx;
1353 
1354 	for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1355 		cq_poll = &qset->napi[qidx];
1356 		cancel_work_sync(&cq_poll->dim.work);
1357 		napi_disable(&cq_poll->napi);
1358 		netif_napi_del(&cq_poll->napi);
1359 	}
1360 }
1361 
otx2_free_cq_res(struct otx2_nic * pf)1362 static void otx2_free_cq_res(struct otx2_nic *pf)
1363 {
1364 	struct otx2_qset *qset = &pf->qset;
1365 	struct otx2_cq_queue *cq;
1366 	int qidx;
1367 
1368 	/* Disable CQs */
1369 	otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false);
1370 	for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
1371 		cq = &qset->cq[qidx];
1372 		qmem_free(pf->dev, cq->cqe);
1373 	}
1374 }
1375 
otx2_free_sq_res(struct otx2_nic * pf)1376 static void otx2_free_sq_res(struct otx2_nic *pf)
1377 {
1378 	struct otx2_qset *qset = &pf->qset;
1379 	struct otx2_snd_queue *sq;
1380 	int qidx;
1381 
1382 	/* Disable SQs */
1383 	otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false);
1384 	/* Free SQB pointers */
1385 	otx2_sq_free_sqbs(pf);
1386 	for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) {
1387 		sq = &qset->sq[qidx];
1388 		qmem_free(pf->dev, sq->sqe);
1389 		qmem_free(pf->dev, sq->tso_hdrs);
1390 		kfree(sq->sg);
1391 		kfree(sq->sqb_ptrs);
1392 	}
1393 }
1394 
otx2_get_rbuf_size(struct otx2_nic * pf,int mtu)1395 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu)
1396 {
1397 	int frame_size;
1398 	int total_size;
1399 	int rbuf_size;
1400 
1401 	if (pf->hw.rbuf_len)
1402 		return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM;
1403 
1404 	/* The data transferred by NIX to memory consists of actual packet
1405 	 * plus additional data which has timestamp and/or EDSA/HIGIG2
1406 	 * headers if interface is configured in corresponding modes.
1407 	 * NIX transfers entire data using 6 segments/buffers and writes
1408 	 * a CQE_RX descriptor with those segment addresses. First segment
1409 	 * has additional data prepended to packet. Also software omits a
1410 	 * headroom of 128 bytes in each segment. Hence the total size of
1411 	 * memory needed to receive a packet with 'mtu' is:
1412 	 * frame size =  mtu + additional data;
1413 	 * memory = frame_size + headroom * 6;
1414 	 * each receive buffer size = memory / 6;
1415 	 */
1416 	frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
1417 	total_size = frame_size + OTX2_HEAD_ROOM * 6;
1418 	rbuf_size = total_size / 6;
1419 
1420 	return ALIGN(rbuf_size, 2048);
1421 }
1422 
otx2_init_hw_resources(struct otx2_nic * pf)1423 static int otx2_init_hw_resources(struct otx2_nic *pf)
1424 {
1425 	struct nix_lf_free_req *free_req;
1426 	struct mbox *mbox = &pf->mbox;
1427 	struct otx2_hw *hw = &pf->hw;
1428 	struct msg_req *req;
1429 	int err = 0, lvl;
1430 
1431 	/* Set required NPA LF's pool counts
1432 	 * Auras and Pools are used in a 1:1 mapping,
1433 	 * so, aura count = pool count.
1434 	 */
1435 	hw->rqpool_cnt = hw->rx_queues;
1436 	hw->sqpool_cnt = hw->tot_tx_queues;
1437 	hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt;
1438 
1439 	/* Maximum hardware supported transmit length */
1440 	pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN;
1441 
1442 	pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu);
1443 
1444 	mutex_lock(&mbox->lock);
1445 	/* NPA init */
1446 	err = otx2_config_npa(pf);
1447 	if (err)
1448 		goto exit;
1449 
1450 	/* NIX init */
1451 	err = otx2_config_nix(pf);
1452 	if (err)
1453 		goto err_free_npa_lf;
1454 
1455 	/* Enable backpressure */
1456 	otx2_nix_config_bp(pf, true);
1457 
1458 	/* Init Auras and pools used by NIX RQ, for free buffer ptrs */
1459 	err = otx2_rq_aura_pool_init(pf);
1460 	if (err) {
1461 		mutex_unlock(&mbox->lock);
1462 		goto err_free_nix_lf;
1463 	}
1464 	/* Init Auras and pools used by NIX SQ, for queueing SQEs */
1465 	err = otx2_sq_aura_pool_init(pf);
1466 	if (err) {
1467 		mutex_unlock(&mbox->lock);
1468 		goto err_free_rq_ptrs;
1469 	}
1470 
1471 	err = otx2_txsch_alloc(pf);
1472 	if (err) {
1473 		mutex_unlock(&mbox->lock);
1474 		goto err_free_sq_ptrs;
1475 	}
1476 
1477 #ifdef CONFIG_DCB
1478 	if (pf->pfc_en) {
1479 		err = otx2_pfc_txschq_alloc(pf);
1480 		if (err) {
1481 			mutex_unlock(&mbox->lock);
1482 			goto err_free_sq_ptrs;
1483 		}
1484 	}
1485 #endif
1486 
1487 	err = otx2_config_nix_queues(pf);
1488 	if (err) {
1489 		mutex_unlock(&mbox->lock);
1490 		goto err_free_txsch;
1491 	}
1492 
1493 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
1494 		err = otx2_txschq_config(pf, lvl, 0, false);
1495 		if (err) {
1496 			mutex_unlock(&mbox->lock);
1497 			goto err_free_nix_queues;
1498 		}
1499 	}
1500 
1501 #ifdef CONFIG_DCB
1502 	if (pf->pfc_en) {
1503 		err = otx2_pfc_txschq_config(pf);
1504 		if (err) {
1505 			mutex_unlock(&mbox->lock);
1506 			goto err_free_nix_queues;
1507 		}
1508 	}
1509 #endif
1510 
1511 	mutex_unlock(&mbox->lock);
1512 	return err;
1513 
1514 err_free_nix_queues:
1515 	otx2_free_sq_res(pf);
1516 	otx2_free_cq_res(pf);
1517 	otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
1518 err_free_txsch:
1519 	if (otx2_txschq_stop(pf))
1520 		dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__);
1521 err_free_sq_ptrs:
1522 	otx2_sq_free_sqbs(pf);
1523 err_free_rq_ptrs:
1524 	otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1525 	otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);
1526 	otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
1527 	otx2_aura_pool_free(pf);
1528 err_free_nix_lf:
1529 	mutex_lock(&mbox->lock);
1530 	free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
1531 	if (free_req) {
1532 		free_req->flags = NIX_LF_DISABLE_FLOWS;
1533 		if (otx2_sync_mbox_msg(mbox))
1534 			dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1535 	}
1536 err_free_npa_lf:
1537 	/* Reset NPA LF */
1538 	req = otx2_mbox_alloc_msg_npa_lf_free(mbox);
1539 	if (req) {
1540 		if (otx2_sync_mbox_msg(mbox))
1541 			dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1542 	}
1543 exit:
1544 	mutex_unlock(&mbox->lock);
1545 	return err;
1546 }
1547 
otx2_free_hw_resources(struct otx2_nic * pf)1548 static void otx2_free_hw_resources(struct otx2_nic *pf)
1549 {
1550 	struct otx2_qset *qset = &pf->qset;
1551 	struct nix_lf_free_req *free_req;
1552 	struct mbox *mbox = &pf->mbox;
1553 	struct otx2_cq_queue *cq;
1554 	struct msg_req *req;
1555 	int qidx, err;
1556 
1557 	/* Ensure all SQE are processed */
1558 	otx2_sqb_flush(pf);
1559 
1560 	/* Stop transmission */
1561 	err = otx2_txschq_stop(pf);
1562 	if (err)
1563 		dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n");
1564 
1565 #ifdef CONFIG_DCB
1566 	if (pf->pfc_en)
1567 		otx2_pfc_txschq_stop(pf);
1568 #endif
1569 
1570 	mutex_lock(&mbox->lock);
1571 	/* Disable backpressure */
1572 	if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1573 		otx2_nix_config_bp(pf, false);
1574 	mutex_unlock(&mbox->lock);
1575 
1576 	/* Disable RQs */
1577 	otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
1578 
1579 	/*Dequeue all CQEs */
1580 	for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
1581 		cq = &qset->cq[qidx];
1582 		if (cq->cq_type == CQ_RX)
1583 			otx2_cleanup_rx_cqes(pf, cq);
1584 		else
1585 			otx2_cleanup_tx_cqes(pf, cq);
1586 	}
1587 
1588 	otx2_free_sq_res(pf);
1589 
1590 	/* Free RQ buffer pointers*/
1591 	otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1592 
1593 	otx2_free_cq_res(pf);
1594 
1595 	/* Free all ingress bandwidth profiles allocated */
1596 	cn10k_free_all_ipolicers(pf);
1597 
1598 	mutex_lock(&mbox->lock);
1599 	/* Reset NIX LF */
1600 	free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
1601 	if (free_req) {
1602 		free_req->flags = NIX_LF_DISABLE_FLOWS;
1603 		if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN))
1604 			free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG;
1605 		if (otx2_sync_mbox_msg(mbox))
1606 			dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1607 	}
1608 	mutex_unlock(&mbox->lock);
1609 
1610 	/* Disable NPA Pool and Aura hw context */
1611 	otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);
1612 	otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
1613 	otx2_aura_pool_free(pf);
1614 
1615 	mutex_lock(&mbox->lock);
1616 	/* Reset NPA LF */
1617 	req = otx2_mbox_alloc_msg_npa_lf_free(mbox);
1618 	if (req) {
1619 		if (otx2_sync_mbox_msg(mbox))
1620 			dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1621 	}
1622 	mutex_unlock(&mbox->lock);
1623 }
1624 
otx2_do_set_rx_mode(struct otx2_nic * pf)1625 static void otx2_do_set_rx_mode(struct otx2_nic *pf)
1626 {
1627 	struct net_device *netdev = pf->netdev;
1628 	struct nix_rx_mode *req;
1629 	bool promisc = false;
1630 
1631 	if (!(netdev->flags & IFF_UP))
1632 		return;
1633 
1634 	if ((netdev->flags & IFF_PROMISC) ||
1635 	    (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) {
1636 		promisc = true;
1637 	}
1638 
1639 	/* Write unicast address to mcam entries or del from mcam */
1640 	if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT)
1641 		__dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter);
1642 
1643 	mutex_lock(&pf->mbox.lock);
1644 	req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox);
1645 	if (!req) {
1646 		mutex_unlock(&pf->mbox.lock);
1647 		return;
1648 	}
1649 
1650 	req->mode = NIX_RX_MODE_UCAST;
1651 
1652 	if (promisc)
1653 		req->mode |= NIX_RX_MODE_PROMISC;
1654 	if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
1655 		req->mode |= NIX_RX_MODE_ALLMULTI;
1656 
1657 	req->mode |= NIX_RX_MODE_USE_MCE;
1658 
1659 	otx2_sync_mbox_msg(&pf->mbox);
1660 	mutex_unlock(&pf->mbox.lock);
1661 }
1662 
otx2_dim_work(struct work_struct * w)1663 static void otx2_dim_work(struct work_struct *w)
1664 {
1665 	struct dim_cq_moder cur_moder;
1666 	struct otx2_cq_poll *cq_poll;
1667 	struct otx2_nic *pfvf;
1668 	struct dim *dim;
1669 
1670 	dim = container_of(w, struct dim, work);
1671 	cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
1672 	cq_poll = container_of(dim, struct otx2_cq_poll, dim);
1673 	pfvf = (struct otx2_nic *)cq_poll->dev;
1674 	pfvf->hw.cq_time_wait = (cur_moder.usec > CQ_TIMER_THRESH_MAX) ?
1675 		CQ_TIMER_THRESH_MAX : cur_moder.usec;
1676 	pfvf->hw.cq_ecount_wait = (cur_moder.pkts > NAPI_POLL_WEIGHT) ?
1677 		NAPI_POLL_WEIGHT : cur_moder.pkts;
1678 	dim->state = DIM_START_MEASURE;
1679 }
1680 
otx2_open(struct net_device * netdev)1681 int otx2_open(struct net_device *netdev)
1682 {
1683 	struct otx2_nic *pf = netdev_priv(netdev);
1684 	struct otx2_cq_poll *cq_poll = NULL;
1685 	struct otx2_qset *qset = &pf->qset;
1686 	int err = 0, qidx, vec;
1687 	char *irq_name;
1688 
1689 	netif_carrier_off(netdev);
1690 
1691 	pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tot_tx_queues;
1692 	/* RQ and SQs are mapped to different CQs,
1693 	 * so find out max CQ IRQs (i.e CINTs) needed.
1694 	 */
1695 	pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues);
1696 	qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL);
1697 	if (!qset->napi)
1698 		return -ENOMEM;
1699 
1700 	/* CQ size of RQ */
1701 	qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256);
1702 	/* CQ size of SQ */
1703 	qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K);
1704 
1705 	err = -ENOMEM;
1706 	qset->cq = kcalloc(pf->qset.cq_cnt,
1707 			   sizeof(struct otx2_cq_queue), GFP_KERNEL);
1708 	if (!qset->cq)
1709 		goto err_free_mem;
1710 
1711 	qset->sq = kcalloc(pf->hw.tot_tx_queues,
1712 			   sizeof(struct otx2_snd_queue), GFP_KERNEL);
1713 	if (!qset->sq)
1714 		goto err_free_mem;
1715 
1716 	qset->rq = kcalloc(pf->hw.rx_queues,
1717 			   sizeof(struct otx2_rcv_queue), GFP_KERNEL);
1718 	if (!qset->rq)
1719 		goto err_free_mem;
1720 
1721 	err = otx2_init_hw_resources(pf);
1722 	if (err)
1723 		goto err_free_mem;
1724 
1725 	/* Register NAPI handler */
1726 	for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1727 		cq_poll = &qset->napi[qidx];
1728 		cq_poll->cint_idx = qidx;
1729 		/* RQ0 & SQ0 are mapped to CINT0 and so on..
1730 		 * 'cq_ids[0]' points to RQ's CQ and
1731 		 * 'cq_ids[1]' points to SQ's CQ and
1732 		 * 'cq_ids[2]' points to XDP's CQ and
1733 		 */
1734 		cq_poll->cq_ids[CQ_RX] =
1735 			(qidx <  pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ;
1736 		cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ?
1737 				      qidx + pf->hw.rx_queues : CINT_INVALID_CQ;
1738 		if (pf->xdp_prog)
1739 			cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ?
1740 						  (qidx + pf->hw.rx_queues +
1741 						  pf->hw.tx_queues) :
1742 						  CINT_INVALID_CQ;
1743 		else
1744 			cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ;
1745 
1746 		cq_poll->dev = (void *)pf;
1747 		cq_poll->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1748 		INIT_WORK(&cq_poll->dim.work, otx2_dim_work);
1749 		netif_napi_add(netdev, &cq_poll->napi, otx2_napi_handler);
1750 		napi_enable(&cq_poll->napi);
1751 	}
1752 
1753 	/* Set maximum frame size allowed in HW */
1754 	err = otx2_hw_set_mtu(pf, netdev->mtu);
1755 	if (err)
1756 		goto err_disable_napi;
1757 
1758 	/* Setup segmentation algorithms, if failed, clear offload capability */
1759 	otx2_setup_segmentation(pf);
1760 
1761 	/* Initialize RSS */
1762 	err = otx2_rss_init(pf);
1763 	if (err)
1764 		goto err_disable_napi;
1765 
1766 	/* Register Queue IRQ handlers */
1767 	vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START;
1768 	irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1769 
1770 	snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name);
1771 
1772 	err = request_irq(pci_irq_vector(pf->pdev, vec),
1773 			  otx2_q_intr_handler, 0, irq_name, pf);
1774 	if (err) {
1775 		dev_err(pf->dev,
1776 			"RVUPF%d: IRQ registration failed for QERR\n",
1777 			rvu_get_pf(pf->pcifunc));
1778 		goto err_disable_napi;
1779 	}
1780 
1781 	/* Enable QINT IRQ */
1782 	otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0));
1783 
1784 	/* Register CQ IRQ handlers */
1785 	vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1786 	for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1787 		irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1788 
1789 		snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name,
1790 			 qidx);
1791 
1792 		err = request_irq(pci_irq_vector(pf->pdev, vec),
1793 				  otx2_cq_intr_handler, 0, irq_name,
1794 				  &qset->napi[qidx]);
1795 		if (err) {
1796 			dev_err(pf->dev,
1797 				"RVUPF%d: IRQ registration failed for CQ%d\n",
1798 				rvu_get_pf(pf->pcifunc), qidx);
1799 			goto err_free_cints;
1800 		}
1801 		vec++;
1802 
1803 		otx2_config_irq_coalescing(pf, qidx);
1804 
1805 		/* Enable CQ IRQ */
1806 		otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0));
1807 		otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0));
1808 	}
1809 
1810 	otx2_set_cints_affinity(pf);
1811 
1812 	if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
1813 		otx2_enable_rxvlan(pf, true);
1814 
1815 	/* When reinitializing enable time stamping if it is enabled before */
1816 	if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) {
1817 		pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED;
1818 		otx2_config_hw_tx_tstamp(pf, true);
1819 	}
1820 	if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) {
1821 		pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED;
1822 		otx2_config_hw_rx_tstamp(pf, true);
1823 	}
1824 
1825 	pf->flags &= ~OTX2_FLAG_INTF_DOWN;
1826 	/* 'intf_down' may be checked on any cpu */
1827 	smp_wmb();
1828 
1829 	/* we have already received link status notification */
1830 	if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1831 		otx2_handle_link_event(pf);
1832 
1833 	/* Install DMAC Filters */
1834 	if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT)
1835 		otx2_dmacflt_reinstall_flows(pf);
1836 
1837 	err = otx2_rxtx_enable(pf, true);
1838 	if (err)
1839 		goto err_tx_stop_queues;
1840 
1841 	otx2_do_set_rx_mode(pf);
1842 
1843 	return 0;
1844 
1845 err_tx_stop_queues:
1846 	netif_tx_stop_all_queues(netdev);
1847 	netif_carrier_off(netdev);
1848 	pf->flags |= OTX2_FLAG_INTF_DOWN;
1849 err_free_cints:
1850 	otx2_free_cints(pf, qidx);
1851 	vec = pci_irq_vector(pf->pdev,
1852 			     pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1853 	otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1854 	free_irq(vec, pf);
1855 err_disable_napi:
1856 	otx2_disable_napi(pf);
1857 	otx2_free_hw_resources(pf);
1858 err_free_mem:
1859 	kfree(qset->sq);
1860 	kfree(qset->cq);
1861 	kfree(qset->rq);
1862 	kfree(qset->napi);
1863 	return err;
1864 }
1865 EXPORT_SYMBOL(otx2_open);
1866 
otx2_stop(struct net_device * netdev)1867 int otx2_stop(struct net_device *netdev)
1868 {
1869 	struct otx2_nic *pf = netdev_priv(netdev);
1870 	struct otx2_cq_poll *cq_poll = NULL;
1871 	struct otx2_qset *qset = &pf->qset;
1872 	struct otx2_rss_info *rss;
1873 	int qidx, vec, wrk;
1874 
1875 	/* If the DOWN flag is set resources are already freed */
1876 	if (pf->flags & OTX2_FLAG_INTF_DOWN)
1877 		return 0;
1878 
1879 	netif_carrier_off(netdev);
1880 	netif_tx_stop_all_queues(netdev);
1881 
1882 	pf->flags |= OTX2_FLAG_INTF_DOWN;
1883 	/* 'intf_down' may be checked on any cpu */
1884 	smp_wmb();
1885 
1886 	/* First stop packet Rx/Tx */
1887 	otx2_rxtx_enable(pf, false);
1888 
1889 	/* Clear RSS enable flag */
1890 	rss = &pf->hw.rss_info;
1891 	rss->enable = false;
1892 
1893 	/* Cleanup Queue IRQ */
1894 	vec = pci_irq_vector(pf->pdev,
1895 			     pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1896 	otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1897 	free_irq(vec, pf);
1898 
1899 	/* Cleanup CQ NAPI and IRQ */
1900 	vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1901 	for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1902 		/* Disable interrupt */
1903 		otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1904 
1905 		synchronize_irq(pci_irq_vector(pf->pdev, vec));
1906 
1907 		cq_poll = &qset->napi[qidx];
1908 		napi_synchronize(&cq_poll->napi);
1909 		vec++;
1910 	}
1911 
1912 	netif_tx_disable(netdev);
1913 
1914 	otx2_free_hw_resources(pf);
1915 	otx2_free_cints(pf, pf->hw.cint_cnt);
1916 	otx2_disable_napi(pf);
1917 
1918 	for (qidx = 0; qidx < netdev->num_tx_queues; qidx++)
1919 		netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx));
1920 
1921 	for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++)
1922 		cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work);
1923 	devm_kfree(pf->dev, pf->refill_wrk);
1924 
1925 	kfree(qset->sq);
1926 	kfree(qset->cq);
1927 	kfree(qset->rq);
1928 	kfree(qset->napi);
1929 	/* Do not clear RQ/SQ ringsize settings */
1930 	memset_startat(qset, 0, sqe_cnt);
1931 	return 0;
1932 }
1933 EXPORT_SYMBOL(otx2_stop);
1934 
otx2_xmit(struct sk_buff * skb,struct net_device * netdev)1935 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev)
1936 {
1937 	struct otx2_nic *pf = netdev_priv(netdev);
1938 	int qidx = skb_get_queue_mapping(skb);
1939 	struct otx2_snd_queue *sq;
1940 	struct netdev_queue *txq;
1941 
1942 	/* Check for minimum and maximum packet length */
1943 	if (skb->len <= ETH_HLEN ||
1944 	    (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) {
1945 		dev_kfree_skb(skb);
1946 		return NETDEV_TX_OK;
1947 	}
1948 
1949 	sq = &pf->qset.sq[qidx];
1950 	txq = netdev_get_tx_queue(netdev, qidx);
1951 
1952 	if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) {
1953 		netif_tx_stop_queue(txq);
1954 
1955 		/* Check again, incase SQBs got freed up */
1956 		smp_mb();
1957 		if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb)
1958 							> sq->sqe_thresh)
1959 			netif_tx_wake_queue(txq);
1960 
1961 		return NETDEV_TX_BUSY;
1962 	}
1963 
1964 	return NETDEV_TX_OK;
1965 }
1966 
otx2_select_queue(struct net_device * netdev,struct sk_buff * skb,struct net_device * sb_dev)1967 static u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb,
1968 			     struct net_device *sb_dev)
1969 {
1970 #ifdef CONFIG_DCB
1971 	struct otx2_nic *pf = netdev_priv(netdev);
1972 	u8 vlan_prio;
1973 #endif
1974 
1975 #ifdef CONFIG_DCB
1976 	if (!skb->vlan_present)
1977 		goto pick_tx;
1978 
1979 	vlan_prio = skb->vlan_tci >> 13;
1980 	if ((vlan_prio > pf->hw.tx_queues - 1) ||
1981 	    !pf->pfc_alloc_status[vlan_prio])
1982 		goto pick_tx;
1983 
1984 	return vlan_prio;
1985 
1986 pick_tx:
1987 #endif
1988 	return netdev_pick_tx(netdev, skb, NULL);
1989 }
1990 
otx2_fix_features(struct net_device * dev,netdev_features_t features)1991 static netdev_features_t otx2_fix_features(struct net_device *dev,
1992 					   netdev_features_t features)
1993 {
1994 	if (features & NETIF_F_HW_VLAN_CTAG_RX)
1995 		features |= NETIF_F_HW_VLAN_STAG_RX;
1996 	else
1997 		features &= ~NETIF_F_HW_VLAN_STAG_RX;
1998 
1999 	return features;
2000 }
2001 
otx2_set_rx_mode(struct net_device * netdev)2002 static void otx2_set_rx_mode(struct net_device *netdev)
2003 {
2004 	struct otx2_nic *pf = netdev_priv(netdev);
2005 
2006 	queue_work(pf->otx2_wq, &pf->rx_mode_work);
2007 }
2008 
otx2_rx_mode_wrk_handler(struct work_struct * work)2009 static void otx2_rx_mode_wrk_handler(struct work_struct *work)
2010 {
2011 	struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work);
2012 
2013 	otx2_do_set_rx_mode(pf);
2014 }
2015 
otx2_set_features(struct net_device * netdev,netdev_features_t features)2016 static int otx2_set_features(struct net_device *netdev,
2017 			     netdev_features_t features)
2018 {
2019 	netdev_features_t changed = features ^ netdev->features;
2020 	struct otx2_nic *pf = netdev_priv(netdev);
2021 
2022 	if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev))
2023 		return otx2_cgx_config_loopback(pf,
2024 						features & NETIF_F_LOOPBACK);
2025 
2026 	if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev))
2027 		return otx2_enable_rxvlan(pf,
2028 					  features & NETIF_F_HW_VLAN_CTAG_RX);
2029 
2030 	return otx2_handle_ntuple_tc_features(netdev, features);
2031 }
2032 
otx2_reset_task(struct work_struct * work)2033 static void otx2_reset_task(struct work_struct *work)
2034 {
2035 	struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task);
2036 
2037 	if (!netif_running(pf->netdev))
2038 		return;
2039 
2040 	rtnl_lock();
2041 	otx2_stop(pf->netdev);
2042 	pf->reset_count++;
2043 	otx2_open(pf->netdev);
2044 	netif_trans_update(pf->netdev);
2045 	rtnl_unlock();
2046 }
2047 
otx2_config_hw_rx_tstamp(struct otx2_nic * pfvf,bool enable)2048 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable)
2049 {
2050 	struct msg_req *req;
2051 	int err;
2052 
2053 	if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable)
2054 		return 0;
2055 
2056 	mutex_lock(&pfvf->mbox.lock);
2057 	if (enable)
2058 		req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox);
2059 	else
2060 		req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox);
2061 	if (!req) {
2062 		mutex_unlock(&pfvf->mbox.lock);
2063 		return -ENOMEM;
2064 	}
2065 
2066 	err = otx2_sync_mbox_msg(&pfvf->mbox);
2067 	if (err) {
2068 		mutex_unlock(&pfvf->mbox.lock);
2069 		return err;
2070 	}
2071 
2072 	mutex_unlock(&pfvf->mbox.lock);
2073 	if (enable)
2074 		pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED;
2075 	else
2076 		pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED;
2077 	return 0;
2078 }
2079 
otx2_config_hw_tx_tstamp(struct otx2_nic * pfvf,bool enable)2080 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable)
2081 {
2082 	struct msg_req *req;
2083 	int err;
2084 
2085 	if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable)
2086 		return 0;
2087 
2088 	mutex_lock(&pfvf->mbox.lock);
2089 	if (enable)
2090 		req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox);
2091 	else
2092 		req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox);
2093 	if (!req) {
2094 		mutex_unlock(&pfvf->mbox.lock);
2095 		return -ENOMEM;
2096 	}
2097 
2098 	err = otx2_sync_mbox_msg(&pfvf->mbox);
2099 	if (err) {
2100 		mutex_unlock(&pfvf->mbox.lock);
2101 		return err;
2102 	}
2103 
2104 	mutex_unlock(&pfvf->mbox.lock);
2105 	if (enable)
2106 		pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED;
2107 	else
2108 		pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED;
2109 	return 0;
2110 }
2111 
otx2_config_hwtstamp(struct net_device * netdev,struct ifreq * ifr)2112 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr)
2113 {
2114 	struct otx2_nic *pfvf = netdev_priv(netdev);
2115 	struct hwtstamp_config config;
2116 
2117 	if (!pfvf->ptp)
2118 		return -ENODEV;
2119 
2120 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2121 		return -EFAULT;
2122 
2123 	switch (config.tx_type) {
2124 	case HWTSTAMP_TX_OFF:
2125 		if (pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC)
2126 			pfvf->flags &= ~OTX2_FLAG_PTP_ONESTEP_SYNC;
2127 
2128 		cancel_delayed_work(&pfvf->ptp->synctstamp_work);
2129 		otx2_config_hw_tx_tstamp(pfvf, false);
2130 		break;
2131 	case HWTSTAMP_TX_ONESTEP_SYNC:
2132 		if (!test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag))
2133 			return -ERANGE;
2134 		pfvf->flags |= OTX2_FLAG_PTP_ONESTEP_SYNC;
2135 		schedule_delayed_work(&pfvf->ptp->synctstamp_work,
2136 				      msecs_to_jiffies(500));
2137 		fallthrough;
2138 	case HWTSTAMP_TX_ON:
2139 		otx2_config_hw_tx_tstamp(pfvf, true);
2140 		break;
2141 	default:
2142 		return -ERANGE;
2143 	}
2144 
2145 	switch (config.rx_filter) {
2146 	case HWTSTAMP_FILTER_NONE:
2147 		otx2_config_hw_rx_tstamp(pfvf, false);
2148 		break;
2149 	case HWTSTAMP_FILTER_ALL:
2150 	case HWTSTAMP_FILTER_SOME:
2151 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2152 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2153 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2154 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2155 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2156 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2157 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2158 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2159 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2160 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
2161 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
2162 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2163 		otx2_config_hw_rx_tstamp(pfvf, true);
2164 		config.rx_filter = HWTSTAMP_FILTER_ALL;
2165 		break;
2166 	default:
2167 		return -ERANGE;
2168 	}
2169 
2170 	memcpy(&pfvf->tstamp, &config, sizeof(config));
2171 
2172 	return copy_to_user(ifr->ifr_data, &config,
2173 			    sizeof(config)) ? -EFAULT : 0;
2174 }
2175 EXPORT_SYMBOL(otx2_config_hwtstamp);
2176 
otx2_ioctl(struct net_device * netdev,struct ifreq * req,int cmd)2177 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
2178 {
2179 	struct otx2_nic *pfvf = netdev_priv(netdev);
2180 	struct hwtstamp_config *cfg = &pfvf->tstamp;
2181 
2182 	switch (cmd) {
2183 	case SIOCSHWTSTAMP:
2184 		return otx2_config_hwtstamp(netdev, req);
2185 	case SIOCGHWTSTAMP:
2186 		return copy_to_user(req->ifr_data, cfg,
2187 				    sizeof(*cfg)) ? -EFAULT : 0;
2188 	default:
2189 		return -EOPNOTSUPP;
2190 	}
2191 }
2192 EXPORT_SYMBOL(otx2_ioctl);
2193 
otx2_do_set_vf_mac(struct otx2_nic * pf,int vf,const u8 * mac)2194 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac)
2195 {
2196 	struct npc_install_flow_req *req;
2197 	int err;
2198 
2199 	mutex_lock(&pf->mbox.lock);
2200 	req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2201 	if (!req) {
2202 		err = -ENOMEM;
2203 		goto out;
2204 	}
2205 
2206 	ether_addr_copy(req->packet.dmac, mac);
2207 	eth_broadcast_addr((u8 *)&req->mask.dmac);
2208 	req->features = BIT_ULL(NPC_DMAC);
2209 	req->channel = pf->hw.rx_chan_base;
2210 	req->intf = NIX_INTF_RX;
2211 	req->default_rule = 1;
2212 	req->append = 1;
2213 	req->vf = vf + 1;
2214 	req->op = NIX_RX_ACTION_DEFAULT;
2215 
2216 	err = otx2_sync_mbox_msg(&pf->mbox);
2217 out:
2218 	mutex_unlock(&pf->mbox.lock);
2219 	return err;
2220 }
2221 
otx2_set_vf_mac(struct net_device * netdev,int vf,u8 * mac)2222 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
2223 {
2224 	struct otx2_nic *pf = netdev_priv(netdev);
2225 	struct pci_dev *pdev = pf->pdev;
2226 	struct otx2_vf_config *config;
2227 	int ret;
2228 
2229 	if (!netif_running(netdev))
2230 		return -EAGAIN;
2231 
2232 	if (vf >= pf->total_vfs)
2233 		return -EINVAL;
2234 
2235 	if (!is_valid_ether_addr(mac))
2236 		return -EINVAL;
2237 
2238 	config = &pf->vf_configs[vf];
2239 	ether_addr_copy(config->mac, mac);
2240 
2241 	ret = otx2_do_set_vf_mac(pf, vf, mac);
2242 	if (ret == 0)
2243 		dev_info(&pdev->dev,
2244 			 "Load/Reload VF driver\n");
2245 
2246 	return ret;
2247 }
2248 
otx2_do_set_vf_vlan(struct otx2_nic * pf,int vf,u16 vlan,u8 qos,__be16 proto)2249 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos,
2250 			       __be16 proto)
2251 {
2252 	struct otx2_flow_config *flow_cfg = pf->flow_cfg;
2253 	struct nix_vtag_config_rsp *vtag_rsp;
2254 	struct npc_delete_flow_req *del_req;
2255 	struct nix_vtag_config *vtag_req;
2256 	struct npc_install_flow_req *req;
2257 	struct otx2_vf_config *config;
2258 	int err = 0;
2259 	u32 idx;
2260 
2261 	config = &pf->vf_configs[vf];
2262 
2263 	if (!vlan && !config->vlan)
2264 		goto out;
2265 
2266 	mutex_lock(&pf->mbox.lock);
2267 
2268 	/* free old tx vtag entry */
2269 	if (config->vlan) {
2270 		vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox);
2271 		if (!vtag_req) {
2272 			err = -ENOMEM;
2273 			goto out;
2274 		}
2275 		vtag_req->cfg_type = 0;
2276 		vtag_req->tx.free_vtag0 = 1;
2277 		vtag_req->tx.vtag0_idx = config->tx_vtag_idx;
2278 
2279 		err = otx2_sync_mbox_msg(&pf->mbox);
2280 		if (err)
2281 			goto out;
2282 	}
2283 
2284 	if (!vlan && config->vlan) {
2285 		/* rx */
2286 		del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox);
2287 		if (!del_req) {
2288 			err = -ENOMEM;
2289 			goto out;
2290 		}
2291 		idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX);
2292 		del_req->entry =
2293 			flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
2294 		err = otx2_sync_mbox_msg(&pf->mbox);
2295 		if (err)
2296 			goto out;
2297 
2298 		/* tx */
2299 		del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox);
2300 		if (!del_req) {
2301 			err = -ENOMEM;
2302 			goto out;
2303 		}
2304 		idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX);
2305 		del_req->entry =
2306 			flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
2307 		err = otx2_sync_mbox_msg(&pf->mbox);
2308 
2309 		goto out;
2310 	}
2311 
2312 	/* rx */
2313 	req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2314 	if (!req) {
2315 		err = -ENOMEM;
2316 		goto out;
2317 	}
2318 
2319 	idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX);
2320 	req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
2321 	req->packet.vlan_tci = htons(vlan);
2322 	req->mask.vlan_tci = htons(VLAN_VID_MASK);
2323 	/* af fills the destination mac addr */
2324 	eth_broadcast_addr((u8 *)&req->mask.dmac);
2325 	req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC);
2326 	req->channel = pf->hw.rx_chan_base;
2327 	req->intf = NIX_INTF_RX;
2328 	req->vf = vf + 1;
2329 	req->op = NIX_RX_ACTION_DEFAULT;
2330 	req->vtag0_valid = true;
2331 	req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7;
2332 	req->set_cntr = 1;
2333 
2334 	err = otx2_sync_mbox_msg(&pf->mbox);
2335 	if (err)
2336 		goto out;
2337 
2338 	/* tx */
2339 	vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox);
2340 	if (!vtag_req) {
2341 		err = -ENOMEM;
2342 		goto out;
2343 	}
2344 
2345 	/* configure tx vtag params */
2346 	vtag_req->vtag_size = VTAGSIZE_T4;
2347 	vtag_req->cfg_type = 0; /* tx vlan cfg */
2348 	vtag_req->tx.cfg_vtag0 = 1;
2349 	vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan;
2350 
2351 	err = otx2_sync_mbox_msg(&pf->mbox);
2352 	if (err)
2353 		goto out;
2354 
2355 	vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp
2356 			(&pf->mbox.mbox, 0, &vtag_req->hdr);
2357 	if (IS_ERR(vtag_rsp)) {
2358 		err = PTR_ERR(vtag_rsp);
2359 		goto out;
2360 	}
2361 	config->tx_vtag_idx = vtag_rsp->vtag0_idx;
2362 
2363 	req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2364 	if (!req) {
2365 		err = -ENOMEM;
2366 		goto out;
2367 	}
2368 
2369 	eth_zero_addr((u8 *)&req->mask.dmac);
2370 	idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX);
2371 	req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
2372 	req->features = BIT_ULL(NPC_DMAC);
2373 	req->channel = pf->hw.tx_chan_base;
2374 	req->intf = NIX_INTF_TX;
2375 	req->vf = vf + 1;
2376 	req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT;
2377 	req->vtag0_def = vtag_rsp->vtag0_idx;
2378 	req->vtag0_op = VTAG_INSERT;
2379 	req->set_cntr = 1;
2380 
2381 	err = otx2_sync_mbox_msg(&pf->mbox);
2382 out:
2383 	config->vlan = vlan;
2384 	mutex_unlock(&pf->mbox.lock);
2385 	return err;
2386 }
2387 
otx2_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 proto)2388 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos,
2389 			    __be16 proto)
2390 {
2391 	struct otx2_nic *pf = netdev_priv(netdev);
2392 	struct pci_dev *pdev = pf->pdev;
2393 
2394 	if (!netif_running(netdev))
2395 		return -EAGAIN;
2396 
2397 	if (vf >= pci_num_vf(pdev))
2398 		return -EINVAL;
2399 
2400 	/* qos is currently unsupported */
2401 	if (vlan >= VLAN_N_VID || qos)
2402 		return -EINVAL;
2403 
2404 	if (proto != htons(ETH_P_8021Q))
2405 		return -EPROTONOSUPPORT;
2406 
2407 	if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT))
2408 		return -EOPNOTSUPP;
2409 
2410 	return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto);
2411 }
2412 
otx2_get_vf_config(struct net_device * netdev,int vf,struct ifla_vf_info * ivi)2413 static int otx2_get_vf_config(struct net_device *netdev, int vf,
2414 			      struct ifla_vf_info *ivi)
2415 {
2416 	struct otx2_nic *pf = netdev_priv(netdev);
2417 	struct pci_dev *pdev = pf->pdev;
2418 	struct otx2_vf_config *config;
2419 
2420 	if (!netif_running(netdev))
2421 		return -EAGAIN;
2422 
2423 	if (vf >= pci_num_vf(pdev))
2424 		return -EINVAL;
2425 
2426 	config = &pf->vf_configs[vf];
2427 	ivi->vf = vf;
2428 	ether_addr_copy(ivi->mac, config->mac);
2429 	ivi->vlan = config->vlan;
2430 	ivi->trusted = config->trusted;
2431 
2432 	return 0;
2433 }
2434 
otx2_xdp_xmit_tx(struct otx2_nic * pf,struct xdp_frame * xdpf,int qidx)2435 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf,
2436 			    int qidx)
2437 {
2438 	struct page *page;
2439 	u64 dma_addr;
2440 	int err = 0;
2441 
2442 	dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data),
2443 				     offset_in_page(xdpf->data), xdpf->len,
2444 				     DMA_TO_DEVICE);
2445 	if (dma_mapping_error(pf->dev, dma_addr))
2446 		return -ENOMEM;
2447 
2448 	err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx);
2449 	if (!err) {
2450 		otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE);
2451 		page = virt_to_page(xdpf->data);
2452 		put_page(page);
2453 		return -ENOMEM;
2454 	}
2455 	return 0;
2456 }
2457 
otx2_xdp_xmit(struct net_device * netdev,int n,struct xdp_frame ** frames,u32 flags)2458 static int otx2_xdp_xmit(struct net_device *netdev, int n,
2459 			 struct xdp_frame **frames, u32 flags)
2460 {
2461 	struct otx2_nic *pf = netdev_priv(netdev);
2462 	int qidx = smp_processor_id();
2463 	struct otx2_snd_queue *sq;
2464 	int drops = 0, i;
2465 
2466 	if (!netif_running(netdev))
2467 		return -ENETDOWN;
2468 
2469 	qidx += pf->hw.tx_queues;
2470 	sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL;
2471 
2472 	/* Abort xmit if xdp queue is not */
2473 	if (unlikely(!sq))
2474 		return -ENXIO;
2475 
2476 	if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2477 		return -EINVAL;
2478 
2479 	for (i = 0; i < n; i++) {
2480 		struct xdp_frame *xdpf = frames[i];
2481 		int err;
2482 
2483 		err = otx2_xdp_xmit_tx(pf, xdpf, qidx);
2484 		if (err)
2485 			drops++;
2486 	}
2487 	return n - drops;
2488 }
2489 
otx2_xdp_setup(struct otx2_nic * pf,struct bpf_prog * prog)2490 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog)
2491 {
2492 	struct net_device *dev = pf->netdev;
2493 	bool if_up = netif_running(pf->netdev);
2494 	struct bpf_prog *old_prog;
2495 
2496 	if (prog && dev->mtu > MAX_XDP_MTU) {
2497 		netdev_warn(dev, "Jumbo frames not yet supported with XDP\n");
2498 		return -EOPNOTSUPP;
2499 	}
2500 
2501 	if (if_up)
2502 		otx2_stop(pf->netdev);
2503 
2504 	old_prog = xchg(&pf->xdp_prog, prog);
2505 
2506 	if (old_prog)
2507 		bpf_prog_put(old_prog);
2508 
2509 	if (pf->xdp_prog)
2510 		bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1);
2511 
2512 	/* Network stack and XDP shared same rx queues.
2513 	 * Use separate tx queues for XDP and network stack.
2514 	 */
2515 	if (pf->xdp_prog)
2516 		pf->hw.xdp_queues = pf->hw.rx_queues;
2517 	else
2518 		pf->hw.xdp_queues = 0;
2519 
2520 	pf->hw.tot_tx_queues += pf->hw.xdp_queues;
2521 
2522 	if (if_up)
2523 		otx2_open(pf->netdev);
2524 
2525 	return 0;
2526 }
2527 
otx2_xdp(struct net_device * netdev,struct netdev_bpf * xdp)2528 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp)
2529 {
2530 	struct otx2_nic *pf = netdev_priv(netdev);
2531 
2532 	switch (xdp->command) {
2533 	case XDP_SETUP_PROG:
2534 		return otx2_xdp_setup(pf, xdp->prog);
2535 	default:
2536 		return -EINVAL;
2537 	}
2538 }
2539 
otx2_set_vf_permissions(struct otx2_nic * pf,int vf,int req_perm)2540 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf,
2541 				   int req_perm)
2542 {
2543 	struct set_vf_perm *req;
2544 	int rc;
2545 
2546 	mutex_lock(&pf->mbox.lock);
2547 	req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox);
2548 	if (!req) {
2549 		rc = -ENOMEM;
2550 		goto out;
2551 	}
2552 
2553 	/* Let AF reset VF permissions as sriov is disabled */
2554 	if (req_perm == OTX2_RESET_VF_PERM) {
2555 		req->flags |= RESET_VF_PERM;
2556 	} else if (req_perm == OTX2_TRUSTED_VF) {
2557 		if (pf->vf_configs[vf].trusted)
2558 			req->flags |= VF_TRUSTED;
2559 	}
2560 
2561 	req->vf = vf;
2562 	rc = otx2_sync_mbox_msg(&pf->mbox);
2563 out:
2564 	mutex_unlock(&pf->mbox.lock);
2565 	return rc;
2566 }
2567 
otx2_ndo_set_vf_trust(struct net_device * netdev,int vf,bool enable)2568 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf,
2569 				 bool enable)
2570 {
2571 	struct otx2_nic *pf = netdev_priv(netdev);
2572 	struct pci_dev *pdev = pf->pdev;
2573 	int rc;
2574 
2575 	if (vf >= pci_num_vf(pdev))
2576 		return -EINVAL;
2577 
2578 	if (pf->vf_configs[vf].trusted == enable)
2579 		return 0;
2580 
2581 	pf->vf_configs[vf].trusted = enable;
2582 	rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF);
2583 
2584 	if (rc)
2585 		pf->vf_configs[vf].trusted = !enable;
2586 	else
2587 		netdev_info(pf->netdev, "VF %d is %strusted\n",
2588 			    vf, enable ? "" : "not ");
2589 	return rc;
2590 }
2591 
2592 static const struct net_device_ops otx2_netdev_ops = {
2593 	.ndo_open		= otx2_open,
2594 	.ndo_stop		= otx2_stop,
2595 	.ndo_start_xmit		= otx2_xmit,
2596 	.ndo_select_queue	= otx2_select_queue,
2597 	.ndo_fix_features	= otx2_fix_features,
2598 	.ndo_set_mac_address    = otx2_set_mac_address,
2599 	.ndo_change_mtu		= otx2_change_mtu,
2600 	.ndo_set_rx_mode	= otx2_set_rx_mode,
2601 	.ndo_set_features	= otx2_set_features,
2602 	.ndo_tx_timeout		= otx2_tx_timeout,
2603 	.ndo_get_stats64	= otx2_get_stats64,
2604 	.ndo_eth_ioctl		= otx2_ioctl,
2605 	.ndo_set_vf_mac		= otx2_set_vf_mac,
2606 	.ndo_set_vf_vlan	= otx2_set_vf_vlan,
2607 	.ndo_get_vf_config	= otx2_get_vf_config,
2608 	.ndo_bpf		= otx2_xdp,
2609 	.ndo_xdp_xmit           = otx2_xdp_xmit,
2610 	.ndo_setup_tc		= otx2_setup_tc,
2611 	.ndo_set_vf_trust	= otx2_ndo_set_vf_trust,
2612 };
2613 
otx2_wq_init(struct otx2_nic * pf)2614 static int otx2_wq_init(struct otx2_nic *pf)
2615 {
2616 	pf->otx2_wq = create_singlethread_workqueue("otx2_wq");
2617 	if (!pf->otx2_wq)
2618 		return -ENOMEM;
2619 
2620 	INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler);
2621 	INIT_WORK(&pf->reset_task, otx2_reset_task);
2622 	return 0;
2623 }
2624 
otx2_check_pf_usable(struct otx2_nic * nic)2625 static int otx2_check_pf_usable(struct otx2_nic *nic)
2626 {
2627 	u64 rev;
2628 
2629 	rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM));
2630 	rev = (rev >> 12) & 0xFF;
2631 	/* Check if AF has setup revision for RVUM block,
2632 	 * otherwise this driver probe should be deferred
2633 	 * until AF driver comes up.
2634 	 */
2635 	if (!rev) {
2636 		dev_warn(nic->dev,
2637 			 "AF is not initialized, deferring probe\n");
2638 		return -EPROBE_DEFER;
2639 	}
2640 	return 0;
2641 }
2642 
otx2_realloc_msix_vectors(struct otx2_nic * pf)2643 static int otx2_realloc_msix_vectors(struct otx2_nic *pf)
2644 {
2645 	struct otx2_hw *hw = &pf->hw;
2646 	int num_vec, err;
2647 
2648 	/* NPA interrupts are inot registered, so alloc only
2649 	 * upto NIX vector offset.
2650 	 */
2651 	num_vec = hw->nix_msixoff;
2652 	num_vec += NIX_LF_CINT_VEC_START + hw->max_queues;
2653 
2654 	otx2_disable_mbox_intr(pf);
2655 	pci_free_irq_vectors(hw->pdev);
2656 	err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
2657 	if (err < 0) {
2658 		dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n",
2659 			__func__, num_vec);
2660 		return err;
2661 	}
2662 
2663 	return otx2_register_mbox_intr(pf, false);
2664 }
2665 
otx2_sriov_vfcfg_init(struct otx2_nic * pf)2666 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf)
2667 {
2668 	int i;
2669 
2670 	pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs,
2671 				      sizeof(struct otx2_vf_config),
2672 				      GFP_KERNEL);
2673 	if (!pf->vf_configs)
2674 		return -ENOMEM;
2675 
2676 	for (i = 0; i < pf->total_vfs; i++) {
2677 		pf->vf_configs[i].pf = pf;
2678 		pf->vf_configs[i].intf_down = true;
2679 		pf->vf_configs[i].trusted = false;
2680 		INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work,
2681 				  otx2_vf_link_event_task);
2682 	}
2683 
2684 	return 0;
2685 }
2686 
otx2_sriov_vfcfg_cleanup(struct otx2_nic * pf)2687 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf)
2688 {
2689 	int i;
2690 
2691 	if (!pf->vf_configs)
2692 		return;
2693 
2694 	for (i = 0; i < pf->total_vfs; i++) {
2695 		cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work);
2696 		otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM);
2697 	}
2698 }
2699 
otx2_probe(struct pci_dev * pdev,const struct pci_device_id * id)2700 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2701 {
2702 	struct device *dev = &pdev->dev;
2703 	struct net_device *netdev;
2704 	struct otx2_nic *pf;
2705 	struct otx2_hw *hw;
2706 	int err, qcount;
2707 	int num_vec;
2708 
2709 	err = pcim_enable_device(pdev);
2710 	if (err) {
2711 		dev_err(dev, "Failed to enable PCI device\n");
2712 		return err;
2713 	}
2714 
2715 	err = pci_request_regions(pdev, DRV_NAME);
2716 	if (err) {
2717 		dev_err(dev, "PCI request regions failed 0x%x\n", err);
2718 		return err;
2719 	}
2720 
2721 	err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
2722 	if (err) {
2723 		dev_err(dev, "DMA mask config failed, abort\n");
2724 		goto err_release_regions;
2725 	}
2726 
2727 	pci_set_master(pdev);
2728 
2729 	/* Set number of queues */
2730 	qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT);
2731 
2732 	netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount);
2733 	if (!netdev) {
2734 		err = -ENOMEM;
2735 		goto err_release_regions;
2736 	}
2737 
2738 	pci_set_drvdata(pdev, netdev);
2739 	SET_NETDEV_DEV(netdev, &pdev->dev);
2740 	pf = netdev_priv(netdev);
2741 	pf->netdev = netdev;
2742 	pf->pdev = pdev;
2743 	pf->dev = dev;
2744 	pf->total_vfs = pci_sriov_get_totalvfs(pdev);
2745 	pf->flags |= OTX2_FLAG_INTF_DOWN;
2746 
2747 	hw = &pf->hw;
2748 	hw->pdev = pdev;
2749 	hw->rx_queues = qcount;
2750 	hw->tx_queues = qcount;
2751 	hw->tot_tx_queues = qcount;
2752 	hw->max_queues = qcount;
2753 	hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN;
2754 	/* Use CQE of 128 byte descriptor size by default */
2755 	hw->xqe_size = 128;
2756 
2757 	num_vec = pci_msix_vec_count(pdev);
2758 	hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE,
2759 					  GFP_KERNEL);
2760 	if (!hw->irq_name) {
2761 		err = -ENOMEM;
2762 		goto err_free_netdev;
2763 	}
2764 
2765 	hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec,
2766 					 sizeof(cpumask_var_t), GFP_KERNEL);
2767 	if (!hw->affinity_mask) {
2768 		err = -ENOMEM;
2769 		goto err_free_netdev;
2770 	}
2771 
2772 	/* Map CSRs */
2773 	pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
2774 	if (!pf->reg_base) {
2775 		dev_err(dev, "Unable to map physical function CSRs, aborting\n");
2776 		err = -ENOMEM;
2777 		goto err_free_netdev;
2778 	}
2779 
2780 	err = otx2_check_pf_usable(pf);
2781 	if (err)
2782 		goto err_free_netdev;
2783 
2784 	err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT,
2785 				    RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX);
2786 	if (err < 0) {
2787 		dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n",
2788 			__func__, num_vec);
2789 		goto err_free_netdev;
2790 	}
2791 
2792 	otx2_setup_dev_hw_settings(pf);
2793 
2794 	/* Init PF <=> AF mailbox stuff */
2795 	err = otx2_pfaf_mbox_init(pf);
2796 	if (err)
2797 		goto err_free_irq_vectors;
2798 
2799 	/* Register mailbox interrupt */
2800 	err = otx2_register_mbox_intr(pf, true);
2801 	if (err)
2802 		goto err_mbox_destroy;
2803 
2804 	/* Request AF to attach NPA and NIX LFs to this PF.
2805 	 * NIX and NPA LFs are needed for this PF to function as a NIC.
2806 	 */
2807 	err = otx2_attach_npa_nix(pf);
2808 	if (err)
2809 		goto err_disable_mbox_intr;
2810 
2811 	err = otx2_realloc_msix_vectors(pf);
2812 	if (err)
2813 		goto err_detach_rsrc;
2814 
2815 	err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues);
2816 	if (err)
2817 		goto err_detach_rsrc;
2818 
2819 	err = cn10k_lmtst_init(pf);
2820 	if (err)
2821 		goto err_detach_rsrc;
2822 
2823 	/* Assign default mac address */
2824 	otx2_get_mac_from_af(netdev);
2825 
2826 	/* Don't check for error.  Proceed without ptp */
2827 	otx2_ptp_init(pf);
2828 
2829 	/* NPA's pool is a stack to which SW frees buffer pointers via Aura.
2830 	 * HW allocates buffer pointer from stack and uses it for DMA'ing
2831 	 * ingress packet. In some scenarios HW can free back allocated buffer
2832 	 * pointers to pool. This makes it impossible for SW to maintain a
2833 	 * parallel list where physical addresses of buffer pointers (IOVAs)
2834 	 * given to HW can be saved for later reference.
2835 	 *
2836 	 * So the only way to convert Rx packet's buffer address is to use
2837 	 * IOMMU's iova_to_phys() handler which translates the address by
2838 	 * walking through the translation tables.
2839 	 */
2840 	pf->iommu_domain = iommu_get_domain_for_dev(dev);
2841 
2842 	netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
2843 			       NETIF_F_IPV6_CSUM | NETIF_F_RXHASH |
2844 			       NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
2845 			       NETIF_F_GSO_UDP_L4);
2846 	netdev->features |= netdev->hw_features;
2847 
2848 	err = otx2_mcam_flow_init(pf);
2849 	if (err)
2850 		goto err_ptp_destroy;
2851 
2852 	err = cn10k_mcs_init(pf);
2853 	if (err)
2854 		goto err_del_mcam_entries;
2855 
2856 	if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT)
2857 		netdev->hw_features |= NETIF_F_NTUPLE;
2858 
2859 	if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT)
2860 		netdev->priv_flags |= IFF_UNICAST_FLT;
2861 
2862 	/* Support TSO on tag interface */
2863 	netdev->vlan_features |= netdev->features;
2864 	netdev->hw_features  |= NETIF_F_HW_VLAN_CTAG_TX |
2865 				NETIF_F_HW_VLAN_STAG_TX;
2866 	if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
2867 		netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX |
2868 				       NETIF_F_HW_VLAN_STAG_RX;
2869 	netdev->features |= netdev->hw_features;
2870 
2871 	/* HW supports tc offload but mutually exclusive with n-tuple filters */
2872 	if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT)
2873 		netdev->hw_features |= NETIF_F_HW_TC;
2874 
2875 	netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL;
2876 
2877 	netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS);
2878 	netdev->watchdog_timeo = OTX2_TX_TIMEOUT;
2879 
2880 	netdev->netdev_ops = &otx2_netdev_ops;
2881 
2882 	netdev->min_mtu = OTX2_MIN_MTU;
2883 	netdev->max_mtu = otx2_get_max_mtu(pf);
2884 
2885 	err = register_netdev(netdev);
2886 	if (err) {
2887 		dev_err(dev, "Failed to register netdevice\n");
2888 		goto err_mcs_free;
2889 	}
2890 
2891 	err = otx2_wq_init(pf);
2892 	if (err)
2893 		goto err_unreg_netdev;
2894 
2895 	otx2_set_ethtool_ops(netdev);
2896 
2897 	err = otx2_init_tc(pf);
2898 	if (err)
2899 		goto err_mcam_flow_del;
2900 
2901 	err = otx2_register_dl(pf);
2902 	if (err)
2903 		goto err_mcam_flow_del;
2904 
2905 	/* Initialize SR-IOV resources */
2906 	err = otx2_sriov_vfcfg_init(pf);
2907 	if (err)
2908 		goto err_pf_sriov_init;
2909 
2910 	/* Enable link notifications */
2911 	otx2_cgx_config_linkevents(pf, true);
2912 
2913 #ifdef CONFIG_DCB
2914 	err = otx2_dcbnl_set_ops(netdev);
2915 	if (err)
2916 		goto err_pf_sriov_init;
2917 #endif
2918 
2919 	return 0;
2920 
2921 err_pf_sriov_init:
2922 	otx2_shutdown_tc(pf);
2923 err_mcam_flow_del:
2924 	otx2_mcam_flow_del(pf);
2925 err_unreg_netdev:
2926 	unregister_netdev(netdev);
2927 err_mcs_free:
2928 	cn10k_mcs_free(pf);
2929 err_del_mcam_entries:
2930 	otx2_mcam_flow_del(pf);
2931 err_ptp_destroy:
2932 	otx2_ptp_destroy(pf);
2933 err_detach_rsrc:
2934 	if (pf->hw.lmt_info)
2935 		free_percpu(pf->hw.lmt_info);
2936 	if (test_bit(CN10K_LMTST, &pf->hw.cap_flag))
2937 		qmem_free(pf->dev, pf->dync_lmt);
2938 	otx2_detach_resources(&pf->mbox);
2939 err_disable_mbox_intr:
2940 	otx2_disable_mbox_intr(pf);
2941 err_mbox_destroy:
2942 	otx2_pfaf_mbox_destroy(pf);
2943 err_free_irq_vectors:
2944 	pci_free_irq_vectors(hw->pdev);
2945 err_free_netdev:
2946 	pci_set_drvdata(pdev, NULL);
2947 	free_netdev(netdev);
2948 err_release_regions:
2949 	pci_release_regions(pdev);
2950 	return err;
2951 }
2952 
otx2_vf_link_event_task(struct work_struct * work)2953 static void otx2_vf_link_event_task(struct work_struct *work)
2954 {
2955 	struct otx2_vf_config *config;
2956 	struct cgx_link_info_msg *req;
2957 	struct mbox_msghdr *msghdr;
2958 	struct otx2_nic *pf;
2959 	int vf_idx;
2960 
2961 	config = container_of(work, struct otx2_vf_config,
2962 			      link_event_work.work);
2963 	vf_idx = config - config->pf->vf_configs;
2964 	pf = config->pf;
2965 
2966 	msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx,
2967 					 sizeof(*req), sizeof(struct msg_rsp));
2968 	if (!msghdr) {
2969 		dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx);
2970 		return;
2971 	}
2972 
2973 	req = (struct cgx_link_info_msg *)msghdr;
2974 	req->hdr.id = MBOX_MSG_CGX_LINK_EVENT;
2975 	req->hdr.sig = OTX2_MBOX_REQ_SIG;
2976 	memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info));
2977 
2978 	otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx);
2979 }
2980 
otx2_sriov_enable(struct pci_dev * pdev,int numvfs)2981 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs)
2982 {
2983 	struct net_device *netdev = pci_get_drvdata(pdev);
2984 	struct otx2_nic *pf = netdev_priv(netdev);
2985 	int ret;
2986 
2987 	/* Init PF <=> VF mailbox stuff */
2988 	ret = otx2_pfvf_mbox_init(pf, numvfs);
2989 	if (ret)
2990 		return ret;
2991 
2992 	ret = otx2_register_pfvf_mbox_intr(pf, numvfs);
2993 	if (ret)
2994 		goto free_mbox;
2995 
2996 	ret = otx2_pf_flr_init(pf, numvfs);
2997 	if (ret)
2998 		goto free_intr;
2999 
3000 	ret = otx2_register_flr_me_intr(pf, numvfs);
3001 	if (ret)
3002 		goto free_flr;
3003 
3004 	ret = pci_enable_sriov(pdev, numvfs);
3005 	if (ret)
3006 		goto free_flr_intr;
3007 
3008 	return numvfs;
3009 free_flr_intr:
3010 	otx2_disable_flr_me_intr(pf);
3011 free_flr:
3012 	otx2_flr_wq_destroy(pf);
3013 free_intr:
3014 	otx2_disable_pfvf_mbox_intr(pf, numvfs);
3015 free_mbox:
3016 	otx2_pfvf_mbox_destroy(pf);
3017 	return ret;
3018 }
3019 
otx2_sriov_disable(struct pci_dev * pdev)3020 static int otx2_sriov_disable(struct pci_dev *pdev)
3021 {
3022 	struct net_device *netdev = pci_get_drvdata(pdev);
3023 	struct otx2_nic *pf = netdev_priv(netdev);
3024 	int numvfs = pci_num_vf(pdev);
3025 
3026 	if (!numvfs)
3027 		return 0;
3028 
3029 	pci_disable_sriov(pdev);
3030 
3031 	otx2_disable_flr_me_intr(pf);
3032 	otx2_flr_wq_destroy(pf);
3033 	otx2_disable_pfvf_mbox_intr(pf, numvfs);
3034 	otx2_pfvf_mbox_destroy(pf);
3035 
3036 	return 0;
3037 }
3038 
otx2_sriov_configure(struct pci_dev * pdev,int numvfs)3039 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs)
3040 {
3041 	if (numvfs == 0)
3042 		return otx2_sriov_disable(pdev);
3043 	else
3044 		return otx2_sriov_enable(pdev, numvfs);
3045 }
3046 
otx2_remove(struct pci_dev * pdev)3047 static void otx2_remove(struct pci_dev *pdev)
3048 {
3049 	struct net_device *netdev = pci_get_drvdata(pdev);
3050 	struct otx2_nic *pf;
3051 
3052 	if (!netdev)
3053 		return;
3054 
3055 	pf = netdev_priv(netdev);
3056 
3057 	pf->flags |= OTX2_FLAG_PF_SHUTDOWN;
3058 
3059 	if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED)
3060 		otx2_config_hw_tx_tstamp(pf, false);
3061 	if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED)
3062 		otx2_config_hw_rx_tstamp(pf, false);
3063 
3064 	/* Disable 802.3x pause frames */
3065 	if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED ||
3066 	    (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) {
3067 		pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED;
3068 		pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED;
3069 		otx2_config_pause_frm(pf);
3070 	}
3071 
3072 	cn10k_mcs_free(pf);
3073 
3074 #ifdef CONFIG_DCB
3075 	/* Disable PFC config */
3076 	if (pf->pfc_en) {
3077 		pf->pfc_en = 0;
3078 		otx2_config_priority_flow_ctrl(pf);
3079 	}
3080 #endif
3081 	cancel_work_sync(&pf->reset_task);
3082 	/* Disable link notifications */
3083 	otx2_cgx_config_linkevents(pf, false);
3084 
3085 	otx2_unregister_dl(pf);
3086 	unregister_netdev(netdev);
3087 	otx2_sriov_disable(pf->pdev);
3088 	otx2_sriov_vfcfg_cleanup(pf);
3089 	if (pf->otx2_wq)
3090 		destroy_workqueue(pf->otx2_wq);
3091 
3092 	otx2_ptp_destroy(pf);
3093 	otx2_mcam_flow_del(pf);
3094 	otx2_shutdown_tc(pf);
3095 	otx2_detach_resources(&pf->mbox);
3096 	if (pf->hw.lmt_info)
3097 		free_percpu(pf->hw.lmt_info);
3098 	if (test_bit(CN10K_LMTST, &pf->hw.cap_flag))
3099 		qmem_free(pf->dev, pf->dync_lmt);
3100 	otx2_disable_mbox_intr(pf);
3101 	otx2_pfaf_mbox_destroy(pf);
3102 	pci_free_irq_vectors(pf->pdev);
3103 	pci_set_drvdata(pdev, NULL);
3104 	free_netdev(netdev);
3105 
3106 	pci_release_regions(pdev);
3107 }
3108 
3109 static struct pci_driver otx2_pf_driver = {
3110 	.name = DRV_NAME,
3111 	.id_table = otx2_pf_id_table,
3112 	.probe = otx2_probe,
3113 	.shutdown = otx2_remove,
3114 	.remove = otx2_remove,
3115 	.sriov_configure = otx2_sriov_configure
3116 };
3117 
otx2_rvupf_init_module(void)3118 static int __init otx2_rvupf_init_module(void)
3119 {
3120 	pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
3121 
3122 	return pci_register_driver(&otx2_pf_driver);
3123 }
3124 
otx2_rvupf_cleanup_module(void)3125 static void __exit otx2_rvupf_cleanup_module(void)
3126 {
3127 	pci_unregister_driver(&otx2_pf_driver);
3128 }
3129 
3130 module_init(otx2_rvupf_init_module);
3131 module_exit(otx2_rvupf_cleanup_module);
3132