1 /*
2 * arch/arm/plat-orion/addr-map.c
3 *
4 * Address map functions for Marvell Orion based SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/mbus.h>
15 #include <linux/io.h>
16 #include <plat/addr-map.h>
17
18 struct mbus_dram_target_info orion_mbus_dram_info;
19
mv_mbus_dram_info(void)20 const struct mbus_dram_target_info *mv_mbus_dram_info(void)
21 {
22 return &orion_mbus_dram_info;
23 }
24 EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
25
26 /*
27 * DDR target is the same on all Orion platforms.
28 */
29 #define TARGET_DDR 0
30
31 /*
32 * Helpers to get DDR bank info
33 */
34 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
35 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
36
37 /*
38 * CPU Address Decode Windows registers
39 */
40 #define WIN_CTRL_OFF 0x0000
41 #define WIN_BASE_OFF 0x0004
42 #define WIN_REMAP_LO_OFF 0x0008
43 #define WIN_REMAP_HI_OFF 0x000c
44
45 /*
46 * Default implementation
47 */
48 static void __init __iomem *
orion_win_cfg_base(const struct orion_addr_map_cfg * cfg,int win)49 orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
50 {
51 return (void __iomem *)(cfg->bridge_virt_base + (win << 4));
52 }
53
54 /*
55 * Default implementation
56 */
orion_cpu_win_can_remap(const struct orion_addr_map_cfg * cfg,const int win)57 static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
58 const int win)
59 {
60 if (win < cfg->remappable_wins)
61 return 1;
62
63 return 0;
64 }
65
orion_setup_cpu_win(const struct orion_addr_map_cfg * cfg,const int win,const u32 base,const u32 size,const u8 target,const u8 attr,const int remap)66 void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
67 const int win, const u32 base,
68 const u32 size, const u8 target,
69 const u8 attr, const int remap)
70 {
71 void __iomem *addr = cfg->win_cfg_base(cfg, win);
72 u32 ctrl, base_high, remap_addr;
73
74 if (win >= cfg->num_wins) {
75 printk(KERN_ERR "setup_cpu_win: trying to allocate window "
76 "%d when only %d allowed\n", win, cfg->num_wins);
77 }
78
79 base_high = base & 0xffff0000;
80 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
81
82 writel(base_high, addr + WIN_BASE_OFF);
83 writel(ctrl, addr + WIN_CTRL_OFF);
84 if (cfg->cpu_win_can_remap(cfg, win)) {
85 if (remap < 0)
86 remap_addr = base;
87 else
88 remap_addr = remap;
89 writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF);
90 writel(0, addr + WIN_REMAP_HI_OFF);
91 }
92 }
93
94 /*
95 * Configure a number of windows.
96 */
orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg,const struct orion_addr_map_info * info)97 static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg,
98 const struct orion_addr_map_info *info)
99 {
100 while (info->win != -1) {
101 orion_setup_cpu_win(cfg, info->win, info->base, info->size,
102 info->target, info->attr, info->remap);
103 info++;
104 }
105 }
106
orion_disable_wins(const struct orion_addr_map_cfg * cfg)107 static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg)
108 {
109 void __iomem *addr;
110 int i;
111
112 for (i = 0; i < cfg->num_wins; i++) {
113 addr = cfg->win_cfg_base(cfg, i);
114
115 writel(0, addr + WIN_BASE_OFF);
116 writel(0, addr + WIN_CTRL_OFF);
117 if (cfg->cpu_win_can_remap(cfg, i)) {
118 writel(0, addr + WIN_REMAP_LO_OFF);
119 writel(0, addr + WIN_REMAP_HI_OFF);
120 }
121 }
122 }
123
124 /*
125 * Disable, clear and configure windows.
126 */
orion_config_wins(struct orion_addr_map_cfg * cfg,const struct orion_addr_map_info * info)127 void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
128 const struct orion_addr_map_info *info)
129 {
130 if (!cfg->cpu_win_can_remap)
131 cfg->cpu_win_can_remap = orion_cpu_win_can_remap;
132
133 if (!cfg->win_cfg_base)
134 cfg->win_cfg_base = orion_win_cfg_base;
135
136 orion_disable_wins(cfg);
137
138 if (info)
139 orion_setup_cpu_wins(cfg, info);
140 }
141
142 /*
143 * Setup MBUS dram target info.
144 */
orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg * cfg,const u32 ddr_window_cpu_base)145 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
146 const u32 ddr_window_cpu_base)
147 {
148 void __iomem *addr;
149 int i;
150 int cs;
151
152 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
153
154 addr = (void __iomem *)ddr_window_cpu_base;
155
156 for (i = 0, cs = 0; i < 4; i++) {
157 u32 base = readl(addr + DDR_BASE_CS_OFF(i));
158 u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
159
160 /*
161 * Chip select enabled?
162 */
163 if (size & 1) {
164 struct mbus_dram_window *w;
165
166 w = &orion_mbus_dram_info.cs[cs++];
167 w->cs_index = i;
168 w->mbus_attr = 0xf & ~(1 << i);
169 w->base = base & 0xffff0000;
170 w->size = (size | 0x0000ffff) + 1;
171 }
172 }
173 orion_mbus_dram_info.num_cs = cs;
174 }
175