1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27 #include "dcn20_optc.h"
28 #include "dc.h"
29
30 #define REG(reg)\
31 optc1->tg_regs->reg
32
33 #define CTX \
34 optc1->base.ctx
35
36 #undef FN
37 #define FN(reg_name, field_name) \
38 optc1->tg_shift->field_name, optc1->tg_mask->field_name
39
40 /**
41 * Enable CRTC
42 * Enable CRTC - call ASIC Control Object to enable Timing generator.
43 */
optc2_enable_crtc(struct timing_generator * optc)44 bool optc2_enable_crtc(struct timing_generator *optc)
45 {
46 /* TODO FPGA wait for answer
47 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
48 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
49 */
50 struct optc *optc1 = DCN10TG_FROM_TG(optc);
51
52 /* opp instance for OTG. For DCN1.0, ODM is remoed.
53 * OPP and OPTC should 1:1 mapping
54 */
55 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
56 OPTC_SEG0_SRC_SEL, optc->inst);
57
58 /* VTG enable first is for HW workaround */
59 REG_UPDATE(CONTROL,
60 VTG0_ENABLE, 1);
61
62 REG_SEQ_START();
63
64 /* Enable CRTC */
65 REG_UPDATE_2(OTG_CONTROL,
66 OTG_DISABLE_POINT_CNTL, 3,
67 OTG_MASTER_EN, 1);
68
69 REG_SEQ_SUBMIT();
70 REG_SEQ_WAIT_DONE();
71
72 return true;
73 }
74
75 /**
76 *For the below, I'm not sure how your GSL parameters are stored in your env,
77 * so I will assume a gsl_params struct for now
78 */
optc2_set_gsl(struct timing_generator * optc,const struct gsl_params * params)79 void optc2_set_gsl(struct timing_generator *optc,
80 const struct gsl_params *params)
81 {
82 struct optc *optc1 = DCN10TG_FROM_TG(optc);
83
84 /**
85 * There are (MAX_OPTC+1)/2 gsl groups available for use.
86 * In each group (assign an OTG to a group by setting OTG_GSLX_EN = 1,
87 * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves.
88 */
89 REG_UPDATE_5(OTG_GSL_CONTROL,
90 OTG_GSL0_EN, params->gsl0_en,
91 OTG_GSL1_EN, params->gsl1_en,
92 OTG_GSL2_EN, params->gsl2_en,
93 OTG_GSL_MASTER_EN, params->gsl_master_en,
94 OTG_GSL_MASTER_MODE, params->gsl_master_mode);
95 }
96
97
optc2_set_gsl_source_select(struct timing_generator * optc,int group_idx,uint32_t gsl_ready_signal)98 void optc2_set_gsl_source_select(
99 struct timing_generator *optc,
100 int group_idx,
101 uint32_t gsl_ready_signal)
102 {
103 struct optc *optc1 = DCN10TG_FROM_TG(optc);
104
105 switch (group_idx) {
106 case 1:
107 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal);
108 break;
109 case 2:
110 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal);
111 break;
112 case 3:
113 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal);
114 break;
115 default:
116 break;
117 }
118 }
119
120 /* Set DSC-related configuration.
121 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
122 * sc_bytes_per_pixel: Bytes per pixel in u3.28 format
123 * dsc_slice_width: Slice width in pixels
124 */
optc2_set_dsc_config(struct timing_generator * optc,enum optc_dsc_mode dsc_mode,uint32_t dsc_bytes_per_pixel,uint32_t dsc_slice_width)125 void optc2_set_dsc_config(struct timing_generator *optc,
126 enum optc_dsc_mode dsc_mode,
127 uint32_t dsc_bytes_per_pixel,
128 uint32_t dsc_slice_width)
129 {
130 struct optc *optc1 = DCN10TG_FROM_TG(optc);
131
132 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
133 OPTC_DSC_MODE, dsc_mode);
134
135 REG_SET(OPTC_BYTES_PER_PIXEL, 0,
136 OPTC_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
137
138 REG_UPDATE(OPTC_WIDTH_CONTROL,
139 OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
140 }
141
142 /* Get DSC-related configuration.
143 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
144 */
optc2_get_dsc_status(struct timing_generator * optc,uint32_t * dsc_mode)145 void optc2_get_dsc_status(struct timing_generator *optc,
146 uint32_t *dsc_mode)
147 {
148 struct optc *optc1 = DCN10TG_FROM_TG(optc);
149
150 REG_GET(OPTC_DATA_FORMAT_CONTROL,
151 OPTC_DSC_MODE, dsc_mode);
152 }
153
154
155 /*TEMP: Need to figure out inheritance model here.*/
optc2_is_two_pixels_per_containter(const struct dc_crtc_timing * timing)156 bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
157 {
158 return optc1_is_two_pixels_per_containter(timing);
159 }
160
optc2_set_odm_bypass(struct timing_generator * optc,const struct dc_crtc_timing * dc_crtc_timing)161 void optc2_set_odm_bypass(struct timing_generator *optc,
162 const struct dc_crtc_timing *dc_crtc_timing)
163 {
164 struct optc *optc1 = DCN10TG_FROM_TG(optc);
165 uint32_t h_div_2 = 0;
166
167 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
168 OPTC_NUM_OF_INPUT_SEGMENT, 0,
169 OPTC_SEG0_SRC_SEL, optc->inst,
170 OPTC_SEG1_SRC_SEL, 0xf);
171 REG_WRITE(OTG_H_TIMING_CNTL, 0);
172
173 h_div_2 = optc2_is_two_pixels_per_containter(dc_crtc_timing);
174 REG_UPDATE(OTG_H_TIMING_CNTL,
175 OTG_H_TIMING_DIV_BY2, h_div_2);
176 REG_SET(OPTC_MEMORY_CONFIG, 0,
177 OPTC_MEM_SEL, 0);
178 optc1->opp_count = 1;
179 }
180
optc2_set_odm_combine(struct timing_generator * optc,int * opp_id,int opp_cnt,struct dc_crtc_timing * timing)181 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
182 struct dc_crtc_timing *timing)
183 {
184 struct optc *optc1 = DCN10TG_FROM_TG(optc);
185 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
186 / opp_cnt;
187 uint32_t memory_mask;
188
189 ASSERT(opp_cnt == 2);
190
191 /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
192 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
193 * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
194 * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
195 * MASTER_UPDATE_LOCK_DB_X, 160,
196 * MASTER_UPDATE_LOCK_DB_Y, 240);
197 */
198
199 /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
200 * however, for ODM combine we can simplify by always using 4.
201 * To make sure there's no overlap, each instance "reserves" 2 memories and
202 * they are uniquely combined here.
203 */
204 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
205
206 if (REG(OPTC_MEMORY_CONFIG))
207 REG_SET(OPTC_MEMORY_CONFIG, 0,
208 OPTC_MEM_SEL, memory_mask);
209
210 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
211 OPTC_NUM_OF_INPUT_SEGMENT, 1,
212 OPTC_SEG0_SRC_SEL, opp_id[0],
213 OPTC_SEG1_SRC_SEL, opp_id[1]);
214
215 REG_UPDATE(OPTC_WIDTH_CONTROL,
216 OPTC_SEGMENT_WIDTH, mpcc_hactive);
217
218 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
219 optc1->opp_count = opp_cnt;
220 }
221
optc2_get_optc_source(struct timing_generator * optc,uint32_t * num_of_src_opp,uint32_t * src_opp_id_0,uint32_t * src_opp_id_1)222 void optc2_get_optc_source(struct timing_generator *optc,
223 uint32_t *num_of_src_opp,
224 uint32_t *src_opp_id_0,
225 uint32_t *src_opp_id_1)
226 {
227 uint32_t num_of_input_segments;
228 struct optc *optc1 = DCN10TG_FROM_TG(optc);
229
230 REG_GET_3(OPTC_DATA_SOURCE_SELECT,
231 OPTC_NUM_OF_INPUT_SEGMENT, &num_of_input_segments,
232 OPTC_SEG0_SRC_SEL, src_opp_id_0,
233 OPTC_SEG1_SRC_SEL, src_opp_id_1);
234
235 if (num_of_input_segments == 1)
236 *num_of_src_opp = 2;
237 else
238 *num_of_src_opp = 1;
239
240 /* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */
241 if (*src_opp_id_1 == 0xf)
242 *num_of_src_opp = 1;
243 }
244
optc2_set_dwb_source(struct timing_generator * optc,uint32_t dwb_pipe_inst)245 static void optc2_set_dwb_source(struct timing_generator *optc,
246 uint32_t dwb_pipe_inst)
247 {
248 struct optc *optc1 = DCN10TG_FROM_TG(optc);
249
250 if (dwb_pipe_inst == 0)
251 REG_UPDATE(DWB_SOURCE_SELECT,
252 OPTC_DWB0_SOURCE_SELECT, optc->inst);
253 else if (dwb_pipe_inst == 1)
254 REG_UPDATE(DWB_SOURCE_SELECT,
255 OPTC_DWB1_SOURCE_SELECT, optc->inst);
256 }
257
optc2_align_vblanks(struct timing_generator * optc_master,struct timing_generator * optc_slave,uint32_t master_pixel_clock_100Hz,uint32_t slave_pixel_clock_100Hz,uint8_t master_clock_divider,uint8_t slave_clock_divider)258 static void optc2_align_vblanks(
259 struct timing_generator *optc_master,
260 struct timing_generator *optc_slave,
261 uint32_t master_pixel_clock_100Hz,
262 uint32_t slave_pixel_clock_100Hz,
263 uint8_t master_clock_divider,
264 uint8_t slave_clock_divider)
265 {
266 /* accessing slave OTG registers */
267 struct optc *optc1 = DCN10TG_FROM_TG(optc_slave);
268
269 uint32_t master_v_active = 0;
270 uint32_t master_h_total = 0;
271 uint32_t slave_h_total = 0;
272 uint64_t L, XY;
273 uint32_t X, Y, p = 10000;
274 uint32_t master_update_lock;
275
276 /* disable slave OTG */
277 REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
278 /* wait until disabled */
279 REG_WAIT(OTG_CONTROL,
280 OTG_CURRENT_MASTER_EN_STATE,
281 0, 10, 5000);
282
283 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total);
284
285 /* assign slave OTG to be controlled by master update lock */
286 REG_SET(OTG_GLOBAL_CONTROL0, 0,
287 OTG_MASTER_UPDATE_LOCK_SEL, optc_master->inst);
288
289 /* accessing master OTG registers */
290 optc1 = DCN10TG_FROM_TG(optc_master);
291
292 /* saving update lock state, not sure if it's needed */
293 REG_GET(OTG_MASTER_UPDATE_LOCK,
294 OTG_MASTER_UPDATE_LOCK, &master_update_lock);
295 /* unlocking master OTG */
296 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
297 OTG_MASTER_UPDATE_LOCK, 0);
298
299 REG_GET(OTG_V_BLANK_START_END,
300 OTG_V_BLANK_START, &master_v_active);
301 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total);
302
303 /* calculate when to enable slave OTG */
304 L = (uint64_t)p * slave_h_total * master_pixel_clock_100Hz;
305 L = div_u64(L, master_h_total);
306 L = div_u64(L, slave_pixel_clock_100Hz);
307 XY = div_u64(L, p);
308 Y = master_v_active - XY - 1;
309 X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider);
310
311 /*
312 * set master OTG to unlock when V/H
313 * counters reach calculated values
314 */
315 REG_UPDATE(OTG_GLOBAL_CONTROL1,
316 MASTER_UPDATE_LOCK_DB_EN, 1);
317 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
318 MASTER_UPDATE_LOCK_DB_X,
319 X,
320 MASTER_UPDATE_LOCK_DB_Y,
321 Y);
322
323 /* lock master OTG */
324 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
325 OTG_MASTER_UPDATE_LOCK, 1);
326 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
327 UPDATE_LOCK_STATUS, 1, 1, 10);
328
329 /* accessing slave OTG registers */
330 optc1 = DCN10TG_FROM_TG(optc_slave);
331
332 /*
333 * enable slave OTG, the OTG is locked with
334 * master's update lock, so it will not run
335 */
336 REG_UPDATE(OTG_CONTROL,
337 OTG_MASTER_EN, 1);
338
339 /* accessing master OTG registers */
340 optc1 = DCN10TG_FROM_TG(optc_master);
341
342 /*
343 * unlock master OTG. When master H/V counters reach
344 * DB_XY point, slave OTG will start
345 */
346 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
347 OTG_MASTER_UPDATE_LOCK, 0);
348
349 /* accessing slave OTG registers */
350 optc1 = DCN10TG_FROM_TG(optc_slave);
351
352 /* wait for slave OTG to start running*/
353 REG_WAIT(OTG_CONTROL,
354 OTG_CURRENT_MASTER_EN_STATE,
355 1, 10, 5000);
356
357 /* accessing master OTG registers */
358 optc1 = DCN10TG_FROM_TG(optc_master);
359
360 /* disable the XY point*/
361 REG_UPDATE(OTG_GLOBAL_CONTROL1,
362 MASTER_UPDATE_LOCK_DB_EN, 0);
363 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
364 MASTER_UPDATE_LOCK_DB_X,
365 0,
366 MASTER_UPDATE_LOCK_DB_Y,
367 0);
368
369 /*restore master update lock*/
370 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
371 OTG_MASTER_UPDATE_LOCK, master_update_lock);
372
373 /* accessing slave OTG registers */
374 optc1 = DCN10TG_FROM_TG(optc_slave);
375 /* restore slave to be controlled by it's own */
376 REG_SET(OTG_GLOBAL_CONTROL0, 0,
377 OTG_MASTER_UPDATE_LOCK_SEL, optc_slave->inst);
378
379 }
380
optc2_triplebuffer_lock(struct timing_generator * optc)381 void optc2_triplebuffer_lock(struct timing_generator *optc)
382 {
383 struct optc *optc1 = DCN10TG_FROM_TG(optc);
384
385 REG_SET(OTG_GLOBAL_CONTROL0, 0,
386 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
387
388 REG_SET(OTG_VUPDATE_KEEPOUT, 0,
389 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
390
391 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
392 OTG_MASTER_UPDATE_LOCK, 1);
393
394 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
395 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
396 UPDATE_LOCK_STATUS, 1,
397 1, 10);
398 }
399
optc2_triplebuffer_unlock(struct timing_generator * optc)400 void optc2_triplebuffer_unlock(struct timing_generator *optc)
401 {
402 struct optc *optc1 = DCN10TG_FROM_TG(optc);
403
404 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
405 OTG_MASTER_UPDATE_LOCK, 0);
406
407 REG_SET(OTG_VUPDATE_KEEPOUT, 0,
408 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);
409
410 }
411
optc2_lock_doublebuffer_enable(struct timing_generator * optc)412 void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
413 {
414 struct optc *optc1 = DCN10TG_FROM_TG(optc);
415 uint32_t v_blank_start = 0;
416 uint32_t h_blank_start = 0;
417
418 REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1);
419
420 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1,
421 DIG_UPDATE_LOCATION, 20);
422
423 REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
424
425 REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
426
427 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
428 MASTER_UPDATE_LOCK_DB_X,
429 (h_blank_start - 200 - 1) / optc1->opp_count,
430 MASTER_UPDATE_LOCK_DB_Y,
431 v_blank_start - 1);
432
433 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
434 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
435 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100,
436 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
437 }
438
optc2_lock_doublebuffer_disable(struct timing_generator * optc)439 void optc2_lock_doublebuffer_disable(struct timing_generator *optc)
440 {
441 struct optc *optc1 = DCN10TG_FROM_TG(optc);
442
443 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
444 MASTER_UPDATE_LOCK_DB_X,
445 0,
446 MASTER_UPDATE_LOCK_DB_Y,
447 0);
448
449 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0,
450 DIG_UPDATE_LOCATION, 0);
451
452 REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0);
453 }
454
optc2_setup_manual_trigger(struct timing_generator * optc)455 void optc2_setup_manual_trigger(struct timing_generator *optc)
456 {
457 struct optc *optc1 = DCN10TG_FROM_TG(optc);
458
459 REG_SET_8(OTG_TRIGA_CNTL, 0,
460 OTG_TRIGA_SOURCE_SELECT, 21,
461 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
462 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
463 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
464 OTG_TRIGA_POLARITY_SELECT, 0,
465 OTG_TRIGA_FREQUENCY_SELECT, 0,
466 OTG_TRIGA_DELAY, 0,
467 OTG_TRIGA_CLEAR, 1);
468 }
469
optc2_program_manual_trigger(struct timing_generator * optc)470 void optc2_program_manual_trigger(struct timing_generator *optc)
471 {
472 struct optc *optc1 = DCN10TG_FROM_TG(optc);
473
474 REG_SET(OTG_TRIGA_MANUAL_TRIG, 0,
475 OTG_TRIGA_MANUAL_TRIG, 1);
476 }
477
optc2_configure_crc(struct timing_generator * optc,const struct crc_params * params)478 bool optc2_configure_crc(struct timing_generator *optc,
479 const struct crc_params *params)
480 {
481 struct optc *optc1 = DCN10TG_FROM_TG(optc);
482
483 REG_SET_2(OTG_CRC_CNTL2, 0,
484 OTG_CRC_DSC_MODE, params->dsc_mode,
485 OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode);
486
487 return optc1_configure_crc(optc, params);
488 }
489
490
optc2_get_last_used_drr_vtotal(struct timing_generator * optc,uint32_t * refresh_rate)491 void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *refresh_rate)
492 {
493 struct optc *optc1 = DCN10TG_FROM_TG(optc);
494
495 REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate);
496 }
497
498 static struct timing_generator_funcs dcn20_tg_funcs = {
499 .validate_timing = optc1_validate_timing,
500 .program_timing = optc1_program_timing,
501 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
502 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
503 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
504 .program_global_sync = optc1_program_global_sync,
505 .enable_crtc = optc2_enable_crtc,
506 .disable_crtc = optc1_disable_crtc,
507 /* used by enable_timing_synchronization. Not need for FPGA */
508 .is_counter_moving = optc1_is_counter_moving,
509 .get_position = optc1_get_position,
510 .get_frame_count = optc1_get_vblank_counter,
511 .get_scanoutpos = optc1_get_crtc_scanoutpos,
512 .get_otg_active_size = optc1_get_otg_active_size,
513 .set_early_control = optc1_set_early_control,
514 /* used by enable_timing_synchronization. Not need for FPGA */
515 .wait_for_state = optc1_wait_for_state,
516 .set_blank = optc1_set_blank,
517 .is_blanked = optc1_is_blanked,
518 .set_blank_color = optc1_program_blank_color,
519 .enable_reset_trigger = optc1_enable_reset_trigger,
520 .enable_crtc_reset = optc1_enable_crtc_reset,
521 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
522 .triplebuffer_lock = optc2_triplebuffer_lock,
523 .triplebuffer_unlock = optc2_triplebuffer_unlock,
524 .disable_reset_trigger = optc1_disable_reset_trigger,
525 .lock = optc1_lock,
526 .unlock = optc1_unlock,
527 .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
528 .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
529 .enable_optc_clock = optc1_enable_optc_clock,
530 .set_drr = optc1_set_drr,
531 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
532 .set_static_screen_control = optc1_set_static_screen_control,
533 .program_stereo = optc1_program_stereo,
534 .is_stereo_left_eye = optc1_is_stereo_left_eye,
535 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
536 .tg_init = optc1_tg_init,
537 .is_tg_enabled = optc1_is_tg_enabled,
538 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
539 .clear_optc_underflow = optc1_clear_optc_underflow,
540 .setup_global_swap_lock = NULL,
541 .get_crc = optc1_get_crc,
542 .configure_crc = optc2_configure_crc,
543 .set_dsc_config = optc2_set_dsc_config,
544 .get_dsc_status = optc2_get_dsc_status,
545 .set_dwb_source = optc2_set_dwb_source,
546 .set_odm_bypass = optc2_set_odm_bypass,
547 .set_odm_combine = optc2_set_odm_combine,
548 .get_optc_source = optc2_get_optc_source,
549 .set_gsl = optc2_set_gsl,
550 .set_gsl_source_select = optc2_set_gsl_source_select,
551 .set_vtg_params = optc1_set_vtg_params,
552 .program_manual_trigger = optc2_program_manual_trigger,
553 .setup_manual_trigger = optc2_setup_manual_trigger,
554 .get_hw_timing = optc1_get_hw_timing,
555 .align_vblanks = optc2_align_vblanks,
556 };
557
dcn20_timing_generator_init(struct optc * optc1)558 void dcn20_timing_generator_init(struct optc *optc1)
559 {
560 optc1->base.funcs = &dcn20_tg_funcs;
561
562 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
563 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
564
565 optc1->min_h_blank = 32;
566 optc1->min_v_blank = 3;
567 optc1->min_v_blank_interlace = 5;
568 optc1->min_h_sync_width = 4;// Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
569 optc1->min_v_sync_width = 1;
570 }
571