1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "reg_helper.h"
28 #include "dcn10_optc.h"
29 #include "dc.h"
30
31 #define REG(reg)\
32 optc1->tg_regs->reg
33
34 #define CTX \
35 optc1->base.ctx
36
37 #undef FN
38 #define FN(reg_name, field_name) \
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
40
41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
42
43 /**
44 * apply_front_porch_workaround TODO FPGA still need?
45 *
46 * This is a workaround for a bug that has existed since R5xx and has not been
47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
48 */
apply_front_porch_workaround(struct dc_crtc_timing * timing)49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing)
50 {
51 if (timing->flags.INTERLACE == 1) {
52 if (timing->v_front_porch < 2)
53 timing->v_front_porch = 2;
54 } else {
55 if (timing->v_front_porch < 1)
56 timing->v_front_porch = 1;
57 }
58 }
59
optc1_program_global_sync(struct timing_generator * optc,int vready_offset,int vstartup_start,int vupdate_offset,int vupdate_width)60 void optc1_program_global_sync(
61 struct timing_generator *optc,
62 int vready_offset,
63 int vstartup_start,
64 int vupdate_offset,
65 int vupdate_width)
66 {
67 struct optc *optc1 = DCN10TG_FROM_TG(optc);
68
69 optc1->vready_offset = vready_offset;
70 optc1->vstartup_start = vstartup_start;
71 optc1->vupdate_offset = vupdate_offset;
72 optc1->vupdate_width = vupdate_width;
73
74 if (optc1->vstartup_start == 0) {
75 BREAK_TO_DEBUGGER();
76 return;
77 }
78
79 REG_SET(OTG_VSTARTUP_PARAM, 0,
80 VSTARTUP_START, optc1->vstartup_start);
81
82 REG_SET_2(OTG_VUPDATE_PARAM, 0,
83 VUPDATE_OFFSET, optc1->vupdate_offset,
84 VUPDATE_WIDTH, optc1->vupdate_width);
85
86 REG_SET(OTG_VREADY_PARAM, 0,
87 VREADY_OFFSET, optc1->vready_offset);
88 }
89
optc1_disable_stereo(struct timing_generator * optc)90 static void optc1_disable_stereo(struct timing_generator *optc)
91 {
92 struct optc *optc1 = DCN10TG_FROM_TG(optc);
93
94 REG_SET(OTG_STEREO_CONTROL, 0,
95 OTG_STEREO_EN, 0);
96
97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0,
98 OTG_3D_STRUCTURE_EN, 0,
99 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
100 }
101
optc1_setup_vertical_interrupt0(struct timing_generator * optc,uint32_t start_line,uint32_t end_line)102 void optc1_setup_vertical_interrupt0(
103 struct timing_generator *optc,
104 uint32_t start_line,
105 uint32_t end_line)
106 {
107 struct optc *optc1 = DCN10TG_FROM_TG(optc);
108
109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
110 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
111 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line);
112 }
113
optc1_setup_vertical_interrupt1(struct timing_generator * optc,uint32_t start_line)114 void optc1_setup_vertical_interrupt1(
115 struct timing_generator *optc,
116 uint32_t start_line)
117 {
118 struct optc *optc1 = DCN10TG_FROM_TG(optc);
119
120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,
121 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line);
122 }
123
optc1_setup_vertical_interrupt2(struct timing_generator * optc,uint32_t start_line)124 void optc1_setup_vertical_interrupt2(
125 struct timing_generator *optc,
126 uint32_t start_line)
127 {
128 struct optc *optc1 = DCN10TG_FROM_TG(optc);
129
130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
131 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line);
132 }
133
134 /**
135 * program_timing_generator used by mode timing set
136 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
137 * Including SYNC. Call BIOS command table to program Timings.
138 */
optc1_program_timing(struct timing_generator * optc,const struct dc_crtc_timing * dc_crtc_timing,int vready_offset,int vstartup_start,int vupdate_offset,int vupdate_width,const enum signal_type signal,bool use_vbios)139 void optc1_program_timing(
140 struct timing_generator *optc,
141 const struct dc_crtc_timing *dc_crtc_timing,
142 int vready_offset,
143 int vstartup_start,
144 int vupdate_offset,
145 int vupdate_width,
146 const enum signal_type signal,
147 bool use_vbios)
148 {
149 struct dc_crtc_timing patched_crtc_timing;
150 uint32_t asic_blank_end;
151 uint32_t asic_blank_start;
152 uint32_t v_total;
153 uint32_t v_sync_end;
154 uint32_t h_sync_polarity, v_sync_polarity;
155 uint32_t start_point = 0;
156 uint32_t field_num = 0;
157 enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
158
159 struct optc *optc1 = DCN10TG_FROM_TG(optc);
160
161 optc1->signal = signal;
162 optc1->vready_offset = vready_offset;
163 optc1->vstartup_start = vstartup_start;
164 optc1->vupdate_offset = vupdate_offset;
165 optc1->vupdate_width = vupdate_width;
166 patched_crtc_timing = *dc_crtc_timing;
167 apply_front_porch_workaround(&patched_crtc_timing);
168
169 /* Load horizontal timing */
170
171 /* CRTC_H_TOTAL = vesa.h_total - 1 */
172 REG_SET(OTG_H_TOTAL, 0,
173 OTG_H_TOTAL, patched_crtc_timing.h_total - 1);
174
175 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */
176 REG_UPDATE_2(OTG_H_SYNC_A,
177 OTG_H_SYNC_A_START, 0,
178 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
179
180 /* blank_start = line end - front porch */
181 asic_blank_start = patched_crtc_timing.h_total -
182 patched_crtc_timing.h_front_porch;
183
184 /* blank_end = blank_start - active */
185 asic_blank_end = asic_blank_start -
186 patched_crtc_timing.h_border_right -
187 patched_crtc_timing.h_addressable -
188 patched_crtc_timing.h_border_left;
189
190 REG_UPDATE_2(OTG_H_BLANK_START_END,
191 OTG_H_BLANK_START, asic_blank_start,
192 OTG_H_BLANK_END, asic_blank_end);
193
194 /* h_sync polarity */
195 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ?
196 0 : 1;
197
198 REG_UPDATE(OTG_H_SYNC_A_CNTL,
199 OTG_H_SYNC_A_POL, h_sync_polarity);
200
201 v_total = patched_crtc_timing.v_total - 1;
202
203 REG_SET(OTG_V_TOTAL, 0,
204 OTG_V_TOTAL, v_total);
205
206 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
207 * OTG_V_TOTAL_MIN are equal to V_TOTAL.
208 */
209 REG_SET(OTG_V_TOTAL_MAX, 0,
210 OTG_V_TOTAL_MAX, v_total);
211 REG_SET(OTG_V_TOTAL_MIN, 0,
212 OTG_V_TOTAL_MIN, v_total);
213
214 /* v_sync_start = 0, v_sync_end = v_sync_width */
215 v_sync_end = patched_crtc_timing.v_sync_width;
216
217 REG_UPDATE_2(OTG_V_SYNC_A,
218 OTG_V_SYNC_A_START, 0,
219 OTG_V_SYNC_A_END, v_sync_end);
220
221 /* blank_start = frame end - front porch */
222 asic_blank_start = patched_crtc_timing.v_total -
223 patched_crtc_timing.v_front_porch;
224
225 /* blank_end = blank_start - active */
226 asic_blank_end = asic_blank_start -
227 patched_crtc_timing.v_border_bottom -
228 patched_crtc_timing.v_addressable -
229 patched_crtc_timing.v_border_top;
230
231 REG_UPDATE_2(OTG_V_BLANK_START_END,
232 OTG_V_BLANK_START, asic_blank_start,
233 OTG_V_BLANK_END, asic_blank_end);
234
235 /* v_sync polarity */
236 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
237 0 : 1;
238
239 REG_UPDATE(OTG_V_SYNC_A_CNTL,
240 OTG_V_SYNC_A_POL, v_sync_polarity);
241
242 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT ||
243 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
244 optc1->signal == SIGNAL_TYPE_EDP) {
245 start_point = 1;
246 if (patched_crtc_timing.flags.INTERLACE == 1)
247 field_num = 1;
248 }
249
250 /* Interlace */
251 if (REG(OTG_INTERLACE_CONTROL)) {
252 if (patched_crtc_timing.flags.INTERLACE == 1)
253 REG_UPDATE(OTG_INTERLACE_CONTROL,
254 OTG_INTERLACE_ENABLE, 1);
255 else
256 REG_UPDATE(OTG_INTERLACE_CONTROL,
257 OTG_INTERLACE_ENABLE, 0);
258 }
259
260 /* VTG enable set to 0 first VInit */
261 REG_UPDATE(CONTROL,
262 VTG0_ENABLE, 0);
263
264 /* original code is using VTG offset to address OTG reg, seems wrong */
265 REG_UPDATE_2(OTG_CONTROL,
266 OTG_START_POINT_CNTL, start_point,
267 OTG_FIELD_NUMBER_CNTL, field_num);
268
269 optc->funcs->program_global_sync(optc,
270 vready_offset,
271 vstartup_start,
272 vupdate_offset,
273 vupdate_width);
274
275 optc->funcs->set_vtg_params(optc, dc_crtc_timing, true);
276
277 /* TODO
278 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
279 * program_horz_count_by_2
280 * for DVI 30bpp mode, 0 otherwise
281 * program_horz_count_by_2(optc, &patched_crtc_timing);
282 */
283
284 /* Enable stereo - only when we need to pack 3D frame. Other types
285 * of stereo handled in explicit call
286 */
287
288 if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
289 h_div = H_TIMING_DIV_BY2;
290
291 if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) {
292 uint32_t data_fmt = 0;
293
294 if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
295 data_fmt = 1;
296 else if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
297 data_fmt = 2;
298
299 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
300 }
301
302 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
303 if (optc1->opp_count == 4)
304 h_div = H_TIMING_DIV_BY4;
305
306 REG_UPDATE(OTG_H_TIMING_CNTL,
307 OTG_H_TIMING_DIV_MODE, h_div);
308 } else {
309 REG_UPDATE(OTG_H_TIMING_CNTL,
310 OTG_H_TIMING_DIV_BY2, h_div);
311 }
312 }
313
optc1_set_vtg_params(struct timing_generator * optc,const struct dc_crtc_timing * dc_crtc_timing,bool program_fp2)314 void optc1_set_vtg_params(struct timing_generator *optc,
315 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2)
316 {
317 struct dc_crtc_timing patched_crtc_timing;
318 uint32_t asic_blank_end;
319 uint32_t v_init;
320 uint32_t v_fp2 = 0;
321 int32_t vertical_line_start;
322
323 struct optc *optc1 = DCN10TG_FROM_TG(optc);
324
325 patched_crtc_timing = *dc_crtc_timing;
326 apply_front_porch_workaround(&patched_crtc_timing);
327
328 /* VCOUNT_INIT is the start of blank */
329 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch;
330
331 /* end of blank = v_init - active */
332 asic_blank_end = v_init -
333 patched_crtc_timing.v_border_bottom -
334 patched_crtc_timing.v_addressable -
335 patched_crtc_timing.v_border_top;
336
337 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */
338 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1;
339 if (vertical_line_start < 0)
340 v_fp2 = -vertical_line_start;
341
342 /* Interlace */
343 if (REG(OTG_INTERLACE_CONTROL)) {
344 if (patched_crtc_timing.flags.INTERLACE == 1) {
345 v_init = v_init / 2;
346 if ((optc1->vstartup_start/2)*2 > asic_blank_end)
347 v_fp2 = v_fp2 / 2;
348 }
349 }
350
351 if (program_fp2)
352 REG_UPDATE_2(CONTROL,
353 VTG0_FP2, v_fp2,
354 VTG0_VCOUNT_INIT, v_init);
355 else
356 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init);
357 }
358
optc1_set_blank_data_double_buffer(struct timing_generator * optc,bool enable)359 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
360 {
361 struct optc *optc1 = DCN10TG_FROM_TG(optc);
362
363 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
364
365 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
366 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
367 }
368
369 /**
370 * optc1_set_timing_double_buffer() - DRR double buffering control
371 *
372 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
373 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
374 *
375 * Options: any time, start of frame, dp start of frame (range timing)
376 */
optc1_set_timing_double_buffer(struct timing_generator * optc,bool enable)377 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)
378 {
379 struct optc *optc1 = DCN10TG_FROM_TG(optc);
380 uint32_t mode = enable ? 2 : 0;
381
382 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
383 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode);
384 }
385
386 /**
387 * unblank_crtc
388 * Call ASIC Control Object to UnBlank CRTC.
389 */
optc1_unblank_crtc(struct timing_generator * optc)390 static void optc1_unblank_crtc(struct timing_generator *optc)
391 {
392 struct optc *optc1 = DCN10TG_FROM_TG(optc);
393
394 REG_UPDATE_2(OTG_BLANK_CONTROL,
395 OTG_BLANK_DATA_EN, 0,
396 OTG_BLANK_DE_MODE, 0);
397
398 /* W/A for automated testing
399 * Automated testing will fail underflow test as there
400 * sporadic underflows which occur during the optc blank
401 * sequence. As a w/a, clear underflow on unblank.
402 * This prevents the failure, but will not mask actual
403 * underflow that affect real use cases.
404 */
405 optc1_clear_optc_underflow(optc);
406 }
407
408 /**
409 * blank_crtc
410 * Call ASIC Control Object to Blank CRTC.
411 */
412
optc1_blank_crtc(struct timing_generator * optc)413 static void optc1_blank_crtc(struct timing_generator *optc)
414 {
415 struct optc *optc1 = DCN10TG_FROM_TG(optc);
416
417 REG_UPDATE_2(OTG_BLANK_CONTROL,
418 OTG_BLANK_DATA_EN, 1,
419 OTG_BLANK_DE_MODE, 0);
420
421 optc1_set_blank_data_double_buffer(optc, false);
422 }
423
optc1_set_blank(struct timing_generator * optc,bool enable_blanking)424 void optc1_set_blank(struct timing_generator *optc,
425 bool enable_blanking)
426 {
427 if (enable_blanking)
428 optc1_blank_crtc(optc);
429 else
430 optc1_unblank_crtc(optc);
431 }
432
optc1_is_blanked(struct timing_generator * optc)433 bool optc1_is_blanked(struct timing_generator *optc)
434 {
435 struct optc *optc1 = DCN10TG_FROM_TG(optc);
436 uint32_t blank_en;
437 uint32_t blank_state;
438
439 REG_GET_2(OTG_BLANK_CONTROL,
440 OTG_BLANK_DATA_EN, &blank_en,
441 OTG_CURRENT_BLANK_STATE, &blank_state);
442
443 return blank_en && blank_state;
444 }
445
optc1_enable_optc_clock(struct timing_generator * optc,bool enable)446 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
447 {
448 struct optc *optc1 = DCN10TG_FROM_TG(optc);
449
450 if (enable) {
451 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
452 OPTC_INPUT_CLK_EN, 1,
453 OPTC_INPUT_CLK_GATE_DIS, 1);
454
455 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
456 OPTC_INPUT_CLK_ON, 1,
457 1, 1000);
458
459 /* Enable clock */
460 REG_UPDATE_2(OTG_CLOCK_CONTROL,
461 OTG_CLOCK_EN, 1,
462 OTG_CLOCK_GATE_DIS, 1);
463 REG_WAIT(OTG_CLOCK_CONTROL,
464 OTG_CLOCK_ON, 1,
465 1, 1000);
466 } else {
467
468 //last chance to clear underflow, otherwise, it will always there due to clock is off.
469 if (optc->funcs->is_optc_underflow_occurred(optc) == true)
470 optc->funcs->clear_optc_underflow(optc);
471
472 REG_UPDATE_2(OTG_CLOCK_CONTROL,
473 OTG_CLOCK_GATE_DIS, 0,
474 OTG_CLOCK_EN, 0);
475
476 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
477 OPTC_INPUT_CLK_GATE_DIS, 0,
478 OPTC_INPUT_CLK_EN, 0);
479 }
480 }
481
482 /**
483 * Enable CRTC
484 * Enable CRTC - call ASIC Control Object to enable Timing generator.
485 */
optc1_enable_crtc(struct timing_generator * optc)486 static bool optc1_enable_crtc(struct timing_generator *optc)
487 {
488 /* TODO FPGA wait for answer
489 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
490 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
491 */
492 struct optc *optc1 = DCN10TG_FROM_TG(optc);
493
494 /* opp instance for OTG. For DCN1.0, ODM is remoed.
495 * OPP and OPTC should 1:1 mapping
496 */
497 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
498 OPTC_SRC_SEL, optc->inst);
499
500 /* VTG enable first is for HW workaround */
501 REG_UPDATE(CONTROL,
502 VTG0_ENABLE, 1);
503
504 REG_SEQ_START();
505
506 /* Enable CRTC */
507 REG_UPDATE_2(OTG_CONTROL,
508 OTG_DISABLE_POINT_CNTL, 3,
509 OTG_MASTER_EN, 1);
510
511 REG_SEQ_SUBMIT();
512 REG_SEQ_WAIT_DONE();
513
514 return true;
515 }
516
517 /* disable_crtc - call ASIC Control Object to disable Timing generator. */
optc1_disable_crtc(struct timing_generator * optc)518 bool optc1_disable_crtc(struct timing_generator *optc)
519 {
520 struct optc *optc1 = DCN10TG_FROM_TG(optc);
521
522 /* disable otg request until end of the first line
523 * in the vertical blank region
524 */
525 REG_UPDATE_2(OTG_CONTROL,
526 OTG_DISABLE_POINT_CNTL, 3,
527 OTG_MASTER_EN, 0);
528
529 REG_UPDATE(CONTROL,
530 VTG0_ENABLE, 0);
531
532 /* CRTC disabled, so disable clock. */
533 REG_WAIT(OTG_CLOCK_CONTROL,
534 OTG_BUSY, 0,
535 1, 100000);
536
537 return true;
538 }
539
540
optc1_program_blank_color(struct timing_generator * optc,const struct tg_color * black_color)541 void optc1_program_blank_color(
542 struct timing_generator *optc,
543 const struct tg_color *black_color)
544 {
545 struct optc *optc1 = DCN10TG_FROM_TG(optc);
546
547 REG_SET_3(OTG_BLACK_COLOR, 0,
548 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
549 OTG_BLACK_COLOR_G_Y, black_color->color_g_y,
550 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
551 }
552
optc1_validate_timing(struct timing_generator * optc,const struct dc_crtc_timing * timing)553 bool optc1_validate_timing(
554 struct timing_generator *optc,
555 const struct dc_crtc_timing *timing)
556 {
557 uint32_t v_blank;
558 uint32_t h_blank;
559 uint32_t min_v_blank;
560 struct optc *optc1 = DCN10TG_FROM_TG(optc);
561
562 ASSERT(timing != NULL);
563
564 v_blank = (timing->v_total - timing->v_addressable -
565 timing->v_border_top - timing->v_border_bottom);
566
567 h_blank = (timing->h_total - timing->h_addressable -
568 timing->h_border_right -
569 timing->h_border_left);
570
571 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
572 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
573 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
574 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
575 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
576 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
577 return false;
578
579 /* Temporarily blocking interlacing mode until it's supported */
580 if (timing->flags.INTERLACE == 1)
581 return false;
582
583 /* Check maximum number of pixels supported by Timing Generator
584 * (Currently will never fail, in order to fail needs display which
585 * needs more than 8192 horizontal and
586 * more than 8192 vertical total pixels)
587 */
588 if (timing->h_total > optc1->max_h_total ||
589 timing->v_total > optc1->max_v_total)
590 return false;
591
592
593 if (h_blank < optc1->min_h_blank)
594 return false;
595
596 if (timing->h_sync_width < optc1->min_h_sync_width ||
597 timing->v_sync_width < optc1->min_v_sync_width)
598 return false;
599
600 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
601
602 if (v_blank < min_v_blank)
603 return false;
604
605 return true;
606
607 }
608
609 /*
610 * get_vblank_counter
611 *
612 * @brief
613 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
614 * holds the counter of frames.
615 *
616 * @param
617 * struct timing_generator *optc - [in] timing generator which controls the
618 * desired CRTC
619 *
620 * @return
621 * Counter of frames, which should equal to number of vblanks.
622 */
optc1_get_vblank_counter(struct timing_generator * optc)623 uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
624 {
625 struct optc *optc1 = DCN10TG_FROM_TG(optc);
626 uint32_t frame_count;
627
628 REG_GET(OTG_STATUS_FRAME_COUNT,
629 OTG_FRAME_COUNT, &frame_count);
630
631 return frame_count;
632 }
633
optc1_lock(struct timing_generator * optc)634 void optc1_lock(struct timing_generator *optc)
635 {
636 struct optc *optc1 = DCN10TG_FROM_TG(optc);
637 uint32_t regval = 0;
638
639 regval = REG_READ(OTG_CONTROL);
640
641 /* otg is not running, do not need to be locked */
642 if ((regval & 0x1) == 0x0)
643 return;
644
645 REG_SET(OTG_GLOBAL_CONTROL0, 0,
646 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
647 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
648 OTG_MASTER_UPDATE_LOCK, 1);
649
650 /* Should be fast, status does not update on maximus */
651 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) {
652
653 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
654 UPDATE_LOCK_STATUS, 1,
655 1, 10);
656 }
657 }
658
optc1_unlock(struct timing_generator * optc)659 void optc1_unlock(struct timing_generator *optc)
660 {
661 struct optc *optc1 = DCN10TG_FROM_TG(optc);
662
663 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
664 OTG_MASTER_UPDATE_LOCK, 0);
665 }
666
optc1_is_locked(struct timing_generator * optc)667 bool optc1_is_locked(struct timing_generator *optc)
668 {
669 struct optc *optc1 = DCN10TG_FROM_TG(optc);
670 uint32_t locked;
671
672 REG_GET(OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, &locked);
673
674 return (locked == 1);
675 }
676
optc1_get_position(struct timing_generator * optc,struct crtc_position * position)677 void optc1_get_position(struct timing_generator *optc,
678 struct crtc_position *position)
679 {
680 struct optc *optc1 = DCN10TG_FROM_TG(optc);
681
682 REG_GET_2(OTG_STATUS_POSITION,
683 OTG_HORZ_COUNT, &position->horizontal_count,
684 OTG_VERT_COUNT, &position->vertical_count);
685
686 REG_GET(OTG_NOM_VERT_POSITION,
687 OTG_VERT_COUNT_NOM, &position->nominal_vcount);
688 }
689
optc1_is_counter_moving(struct timing_generator * optc)690 bool optc1_is_counter_moving(struct timing_generator *optc)
691 {
692 struct crtc_position position1, position2;
693
694 optc->funcs->get_position(optc, &position1);
695 optc->funcs->get_position(optc, &position2);
696
697 if (position1.horizontal_count == position2.horizontal_count &&
698 position1.vertical_count == position2.vertical_count)
699 return false;
700 else
701 return true;
702 }
703
optc1_did_triggered_reset_occur(struct timing_generator * optc)704 bool optc1_did_triggered_reset_occur(
705 struct timing_generator *optc)
706 {
707 struct optc *optc1 = DCN10TG_FROM_TG(optc);
708 uint32_t occurred_force, occurred_vsync;
709
710 REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
711 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
712
713 REG_GET(OTG_VERT_SYNC_CONTROL,
714 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
715
716 return occurred_vsync != 0 || occurred_force != 0;
717 }
718
optc1_disable_reset_trigger(struct timing_generator * optc)719 void optc1_disable_reset_trigger(struct timing_generator *optc)
720 {
721 struct optc *optc1 = DCN10TG_FROM_TG(optc);
722
723 REG_WRITE(OTG_TRIGA_CNTL, 0);
724
725 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
726 OTG_FORCE_COUNT_NOW_CLEAR, 1);
727
728 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
729 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
730 }
731
optc1_enable_reset_trigger(struct timing_generator * optc,int source_tg_inst)732 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)
733 {
734 struct optc *optc1 = DCN10TG_FROM_TG(optc);
735 uint32_t falling_edge;
736
737 REG_GET(OTG_V_SYNC_A_CNTL,
738 OTG_V_SYNC_A_POL, &falling_edge);
739
740 if (falling_edge)
741 REG_SET_3(OTG_TRIGA_CNTL, 0,
742 /* vsync signal from selected OTG pipe based
743 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
744 */
745 OTG_TRIGA_SOURCE_SELECT, 20,
746 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
747 /* always detect falling edge */
748 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1);
749 else
750 REG_SET_3(OTG_TRIGA_CNTL, 0,
751 /* vsync signal from selected OTG pipe based
752 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
753 */
754 OTG_TRIGA_SOURCE_SELECT, 20,
755 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
756 /* always detect rising edge */
757 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1);
758
759 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
760 /* force H count to H_TOTAL and V count to V_TOTAL in
761 * progressive mode and V_TOTAL-1 in interlaced mode
762 */
763 OTG_FORCE_COUNT_NOW_MODE, 2);
764 }
765
optc1_enable_crtc_reset(struct timing_generator * optc,int source_tg_inst,struct crtc_trigger_info * crtc_tp)766 void optc1_enable_crtc_reset(
767 struct timing_generator *optc,
768 int source_tg_inst,
769 struct crtc_trigger_info *crtc_tp)
770 {
771 struct optc *optc1 = DCN10TG_FROM_TG(optc);
772 uint32_t falling_edge = 0;
773 uint32_t rising_edge = 0;
774
775 switch (crtc_tp->event) {
776
777 case CRTC_EVENT_VSYNC_RISING:
778 rising_edge = 1;
779 break;
780
781 case CRTC_EVENT_VSYNC_FALLING:
782 falling_edge = 1;
783 break;
784 }
785
786 REG_SET_4(OTG_TRIGA_CNTL, 0,
787 /* vsync signal from selected OTG pipe based
788 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
789 */
790 OTG_TRIGA_SOURCE_SELECT, 20,
791 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
792 /* always detect falling edge */
793 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
794 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
795
796 switch (crtc_tp->delay) {
797 case TRIGGER_DELAY_NEXT_LINE:
798 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
799 OTG_AUTO_FORCE_VSYNC_MODE, 1);
800 break;
801 case TRIGGER_DELAY_NEXT_PIXEL:
802 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
803 /* force H count to H_TOTAL and V count to V_TOTAL in
804 * progressive mode and V_TOTAL-1 in interlaced mode
805 */
806 OTG_FORCE_COUNT_NOW_MODE, 2);
807 break;
808 }
809 }
810
optc1_wait_for_state(struct timing_generator * optc,enum crtc_state state)811 void optc1_wait_for_state(struct timing_generator *optc,
812 enum crtc_state state)
813 {
814 struct optc *optc1 = DCN10TG_FROM_TG(optc);
815
816 switch (state) {
817 case CRTC_STATE_VBLANK:
818 REG_WAIT(OTG_STATUS,
819 OTG_V_BLANK, 1,
820 1, 100000); /* 1 vupdate at 10hz */
821 break;
822
823 case CRTC_STATE_VACTIVE:
824 REG_WAIT(OTG_STATUS,
825 OTG_V_ACTIVE_DISP, 1,
826 1, 100000); /* 1 vupdate at 10hz */
827 break;
828
829 default:
830 break;
831 }
832 }
833
optc1_set_early_control(struct timing_generator * optc,uint32_t early_cntl)834 void optc1_set_early_control(
835 struct timing_generator *optc,
836 uint32_t early_cntl)
837 {
838 /* asic design change, do not need this control
839 * empty for share caller logic
840 */
841 }
842
843
optc1_set_static_screen_control(struct timing_generator * optc,uint32_t event_triggers,uint32_t num_frames)844 void optc1_set_static_screen_control(
845 struct timing_generator *optc,
846 uint32_t event_triggers,
847 uint32_t num_frames)
848 {
849 struct optc *optc1 = DCN10TG_FROM_TG(optc);
850
851 // By register spec, it only takes 8 bit value
852 if (num_frames > 0xFF)
853 num_frames = 0xFF;
854
855 /* Bit 8 is no longer applicable in RV for PSR case,
856 * set bit 8 to 0 if given
857 */
858 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN)
859 != 0)
860 event_triggers = event_triggers &
861 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN;
862
863 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
864 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers,
865 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames);
866 }
867
optc1_setup_manual_trigger(struct timing_generator * optc)868 static void optc1_setup_manual_trigger(struct timing_generator *optc)
869 {
870 struct optc *optc1 = DCN10TG_FROM_TG(optc);
871
872 REG_SET(OTG_GLOBAL_CONTROL2, 0,
873 MANUAL_FLOW_CONTROL_SEL, optc->inst);
874
875 REG_SET_8(OTG_TRIGA_CNTL, 0,
876 OTG_TRIGA_SOURCE_SELECT, 22,
877 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
878 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
879 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
880 OTG_TRIGA_POLARITY_SELECT, 0,
881 OTG_TRIGA_FREQUENCY_SELECT, 0,
882 OTG_TRIGA_DELAY, 0,
883 OTG_TRIGA_CLEAR, 1);
884 }
885
optc1_program_manual_trigger(struct timing_generator * optc)886 static void optc1_program_manual_trigger(struct timing_generator *optc)
887 {
888 struct optc *optc1 = DCN10TG_FROM_TG(optc);
889
890 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
891 MANUAL_FLOW_CONTROL, 1);
892
893 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
894 MANUAL_FLOW_CONTROL, 0);
895 }
896
897
898 /**
899 *****************************************************************************
900 * Function: set_drr
901 *
902 * @brief
903 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
904 *
905 *****************************************************************************
906 */
optc1_set_drr(struct timing_generator * optc,const struct drr_params * params)907 void optc1_set_drr(
908 struct timing_generator *optc,
909 const struct drr_params *params)
910 {
911 struct optc *optc1 = DCN10TG_FROM_TG(optc);
912
913 if (params != NULL &&
914 params->vertical_total_max > 0 &&
915 params->vertical_total_min > 0) {
916
917 if (params->vertical_total_mid != 0) {
918
919 REG_SET(OTG_V_TOTAL_MID, 0,
920 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
921
922 REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
923 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
924 OTG_VTOTAL_MID_FRAME_NUM,
925 (uint8_t)params->vertical_total_mid_frame_num);
926
927 }
928
929 REG_SET(OTG_V_TOTAL_MAX, 0,
930 OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
931
932 REG_SET(OTG_V_TOTAL_MIN, 0,
933 OTG_V_TOTAL_MIN, params->vertical_total_min - 1);
934
935 REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
936 OTG_V_TOTAL_MIN_SEL, 1,
937 OTG_V_TOTAL_MAX_SEL, 1,
938 OTG_FORCE_LOCK_ON_EVENT, 0,
939 OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
940 OTG_SET_V_TOTAL_MIN_MASK, 0);
941
942 // Setup manual flow control for EOF via TRIG_A
943 optc->funcs->setup_manual_trigger(optc);
944
945 } else {
946 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
947 OTG_SET_V_TOTAL_MIN_MASK, 0,
948 OTG_V_TOTAL_MIN_SEL, 0,
949 OTG_V_TOTAL_MAX_SEL, 0,
950 OTG_FORCE_LOCK_ON_EVENT, 0);
951
952 REG_SET(OTG_V_TOTAL_MIN, 0,
953 OTG_V_TOTAL_MIN, 0);
954
955 REG_SET(OTG_V_TOTAL_MAX, 0,
956 OTG_V_TOTAL_MAX, 0);
957 }
958 }
959
optc1_set_vtotal_min_max(struct timing_generator * optc,int vtotal_min,int vtotal_max)960 void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
961 {
962 struct optc *optc1 = DCN10TG_FROM_TG(optc);
963
964 REG_SET(OTG_V_TOTAL_MAX, 0,
965 OTG_V_TOTAL_MAX, vtotal_max);
966
967 REG_SET(OTG_V_TOTAL_MIN, 0,
968 OTG_V_TOTAL_MIN, vtotal_min);
969 }
970
optc1_set_test_pattern(struct timing_generator * optc,enum controller_dp_test_pattern test_pattern,enum dc_color_depth color_depth)971 static void optc1_set_test_pattern(
972 struct timing_generator *optc,
973 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
974 * because this is not DP-specific (which is probably somewhere in DP
975 * encoder) */
976 enum controller_dp_test_pattern test_pattern,
977 enum dc_color_depth color_depth)
978 {
979 struct optc *optc1 = DCN10TG_FROM_TG(optc);
980 enum test_pattern_color_format bit_depth;
981 enum test_pattern_dyn_range dyn_range;
982 enum test_pattern_mode mode;
983 uint32_t pattern_mask;
984 uint32_t pattern_data;
985 /* color ramp generator mixes 16-bits color */
986 uint32_t src_bpc = 16;
987 /* requested bpc */
988 uint32_t dst_bpc;
989 uint32_t index;
990 /* RGB values of the color bars.
991 * Produce two RGB colors: RGB0 - white (all Fs)
992 * and RGB1 - black (all 0s)
993 * (three RGB components for two colors)
994 */
995 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
996 0x0000, 0x0000};
997 /* dest color (converted to the specified color format) */
998 uint16_t dst_color[6];
999 uint32_t inc_base;
1000
1001 /* translate to bit depth */
1002 switch (color_depth) {
1003 case COLOR_DEPTH_666:
1004 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
1005 break;
1006 case COLOR_DEPTH_888:
1007 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
1008 break;
1009 case COLOR_DEPTH_101010:
1010 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
1011 break;
1012 case COLOR_DEPTH_121212:
1013 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
1014 break;
1015 default:
1016 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
1017 break;
1018 }
1019
1020 switch (test_pattern) {
1021 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
1022 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
1023 {
1024 dyn_range = (test_pattern ==
1025 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
1026 TEST_PATTERN_DYN_RANGE_CEA :
1027 TEST_PATTERN_DYN_RANGE_VESA);
1028 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
1029
1030 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
1031 OTG_TEST_PATTERN_VRES, 6,
1032 OTG_TEST_PATTERN_HRES, 6);
1033
1034 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1035 OTG_TEST_PATTERN_EN, 1,
1036 OTG_TEST_PATTERN_MODE, mode,
1037 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
1038 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1039 }
1040 break;
1041
1042 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
1043 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
1044 {
1045 mode = (test_pattern ==
1046 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
1047 TEST_PATTERN_MODE_VERTICALBARS :
1048 TEST_PATTERN_MODE_HORIZONTALBARS);
1049
1050 switch (bit_depth) {
1051 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1052 dst_bpc = 6;
1053 break;
1054 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1055 dst_bpc = 8;
1056 break;
1057 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1058 dst_bpc = 10;
1059 break;
1060 default:
1061 dst_bpc = 8;
1062 break;
1063 }
1064
1065 /* adjust color to the required colorFormat */
1066 for (index = 0; index < 6; index++) {
1067 /* dst = 2^dstBpc * src / 2^srcBpc = src >>
1068 * (srcBpc - dstBpc);
1069 */
1070 dst_color[index] =
1071 src_color[index] >> (src_bpc - dst_bpc);
1072 /* CRTC_TEST_PATTERN_DATA has 16 bits,
1073 * lowest 6 are hardwired to ZERO
1074 * color bits should be left aligned aligned to MSB
1075 * XXXXXXXXXX000000 for 10 bit,
1076 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
1077 */
1078 dst_color[index] <<= (16 - dst_bpc);
1079 }
1080
1081 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1082
1083 /* We have to write the mask before data, similar to pipeline.
1084 * For example, for 8 bpc, if we want RGB0 to be magenta,
1085 * and RGB1 to be cyan,
1086 * we need to make 7 writes:
1087 * MASK DATA
1088 * 000001 00000000 00000000 set mask to R0
1089 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0
1090 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0
1091 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1
1092 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1
1093 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1
1094 * 100000 11111111 00000000 B1 255, 0xFF00
1095 *
1096 * we will make a loop of 6 in which we prepare the mask,
1097 * then write, then prepare the color for next write.
1098 * first iteration will write mask only,
1099 * but each next iteration color prepared in
1100 * previous iteration will be written within new mask,
1101 * the last component will written separately,
1102 * mask is not changing between 6th and 7th write
1103 * and color will be prepared by last iteration
1104 */
1105
1106 /* write color, color values mask in CRTC_TEST_PATTERN_MASK
1107 * is B1, G1, R1, B0, G0, R0
1108 */
1109 pattern_data = 0;
1110 for (index = 0; index < 6; index++) {
1111 /* prepare color mask, first write PATTERN_DATA
1112 * will have all zeros
1113 */
1114 pattern_mask = (1 << index);
1115
1116 /* write color component */
1117 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1118 OTG_TEST_PATTERN_MASK, pattern_mask,
1119 OTG_TEST_PATTERN_DATA, pattern_data);
1120
1121 /* prepare next color component,
1122 * will be written in the next iteration
1123 */
1124 pattern_data = dst_color[index];
1125 }
1126 /* write last color component,
1127 * it's been already prepared in the loop
1128 */
1129 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1130 OTG_TEST_PATTERN_MASK, pattern_mask,
1131 OTG_TEST_PATTERN_DATA, pattern_data);
1132
1133 /* enable test pattern */
1134 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1135 OTG_TEST_PATTERN_EN, 1,
1136 OTG_TEST_PATTERN_MODE, mode,
1137 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1138 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1139 }
1140 break;
1141
1142 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
1143 {
1144 mode = (bit_depth ==
1145 TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
1146 TEST_PATTERN_MODE_DUALRAMP_RGB :
1147 TEST_PATTERN_MODE_SINGLERAMP_RGB);
1148
1149 switch (bit_depth) {
1150 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1151 dst_bpc = 6;
1152 break;
1153 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1154 dst_bpc = 8;
1155 break;
1156 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1157 dst_bpc = 10;
1158 break;
1159 default:
1160 dst_bpc = 8;
1161 break;
1162 }
1163
1164 /* increment for the first ramp for one color gradation
1165 * 1 gradation for 6-bit color is 2^10
1166 * gradations in 16-bit color
1167 */
1168 inc_base = (src_bpc - dst_bpc);
1169
1170 switch (bit_depth) {
1171 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1172 {
1173 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1174 OTG_TEST_PATTERN_INC0, inc_base,
1175 OTG_TEST_PATTERN_INC1, 0,
1176 OTG_TEST_PATTERN_HRES, 6,
1177 OTG_TEST_PATTERN_VRES, 6,
1178 OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1179 }
1180 break;
1181 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1182 {
1183 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1184 OTG_TEST_PATTERN_INC0, inc_base,
1185 OTG_TEST_PATTERN_INC1, 0,
1186 OTG_TEST_PATTERN_HRES, 8,
1187 OTG_TEST_PATTERN_VRES, 6,
1188 OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1189 }
1190 break;
1191 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1192 {
1193 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1194 OTG_TEST_PATTERN_INC0, inc_base,
1195 OTG_TEST_PATTERN_INC1, inc_base + 2,
1196 OTG_TEST_PATTERN_HRES, 8,
1197 OTG_TEST_PATTERN_VRES, 5,
1198 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
1199 }
1200 break;
1201 default:
1202 break;
1203 }
1204
1205 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1206
1207 /* enable test pattern */
1208 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1209
1210 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
1211 OTG_TEST_PATTERN_EN, 1,
1212 OTG_TEST_PATTERN_MODE, mode,
1213 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1214 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1215 }
1216 break;
1217 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
1218 {
1219 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1220 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1221 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1222 }
1223 break;
1224 default:
1225 break;
1226
1227 }
1228 }
1229
optc1_get_crtc_scanoutpos(struct timing_generator * optc,uint32_t * v_blank_start,uint32_t * v_blank_end,uint32_t * h_position,uint32_t * v_position)1230 void optc1_get_crtc_scanoutpos(
1231 struct timing_generator *optc,
1232 uint32_t *v_blank_start,
1233 uint32_t *v_blank_end,
1234 uint32_t *h_position,
1235 uint32_t *v_position)
1236 {
1237 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1238 struct crtc_position position;
1239
1240 REG_GET_2(OTG_V_BLANK_START_END,
1241 OTG_V_BLANK_START, v_blank_start,
1242 OTG_V_BLANK_END, v_blank_end);
1243
1244 optc1_get_position(optc, &position);
1245
1246 *h_position = position.horizontal_count;
1247 *v_position = position.vertical_count;
1248 }
1249
optc1_enable_stereo(struct timing_generator * optc,const struct dc_crtc_timing * timing,struct crtc_stereo_flags * flags)1250 static void optc1_enable_stereo(struct timing_generator *optc,
1251 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1252 {
1253 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1254
1255 if (flags) {
1256 uint32_t stereo_en;
1257 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
1258
1259 if (flags->PROGRAM_STEREO)
1260 REG_UPDATE_3(OTG_STEREO_CONTROL,
1261 OTG_STEREO_EN, stereo_en,
1262 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
1263 OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1264
1265 if (flags->PROGRAM_POLARITY)
1266 REG_UPDATE(OTG_STEREO_CONTROL,
1267 OTG_STEREO_EYE_FLAG_POLARITY,
1268 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1269
1270 if (flags->DISABLE_STEREO_DP_SYNC)
1271 REG_UPDATE(OTG_STEREO_CONTROL,
1272 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
1273
1274 if (flags->PROGRAM_STEREO)
1275 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL,
1276 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
1277 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED);
1278
1279 }
1280 }
1281
optc1_program_stereo(struct timing_generator * optc,const struct dc_crtc_timing * timing,struct crtc_stereo_flags * flags)1282 void optc1_program_stereo(struct timing_generator *optc,
1283 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1284 {
1285 if (flags->PROGRAM_STEREO)
1286 optc1_enable_stereo(optc, timing, flags);
1287 else
1288 optc1_disable_stereo(optc);
1289 }
1290
1291
optc1_is_stereo_left_eye(struct timing_generator * optc)1292 bool optc1_is_stereo_left_eye(struct timing_generator *optc)
1293 {
1294 bool ret = false;
1295 uint32_t left_eye = 0;
1296 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1297
1298 REG_GET(OTG_STEREO_STATUS,
1299 OTG_STEREO_CURRENT_EYE, &left_eye);
1300 if (left_eye == 1)
1301 ret = true;
1302 else
1303 ret = false;
1304
1305 return ret;
1306 }
1307
optc1_get_hw_timing(struct timing_generator * tg,struct dc_crtc_timing * hw_crtc_timing)1308 bool optc1_get_hw_timing(struct timing_generator *tg,
1309 struct dc_crtc_timing *hw_crtc_timing)
1310 {
1311 struct dcn_otg_state s = {0};
1312
1313 if (tg == NULL || hw_crtc_timing == NULL)
1314 return false;
1315
1316 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
1317
1318 hw_crtc_timing->h_total = s.h_total + 1;
1319 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
1320 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start;
1321 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start;
1322
1323 hw_crtc_timing->v_total = s.v_total + 1;
1324 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
1325 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start;
1326 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start;
1327
1328 return true;
1329 }
1330
1331
optc1_read_otg_state(struct optc * optc1,struct dcn_otg_state * s)1332 void optc1_read_otg_state(struct optc *optc1,
1333 struct dcn_otg_state *s)
1334 {
1335 REG_GET(OTG_CONTROL,
1336 OTG_MASTER_EN, &s->otg_enabled);
1337
1338 REG_GET_2(OTG_V_BLANK_START_END,
1339 OTG_V_BLANK_START, &s->v_blank_start,
1340 OTG_V_BLANK_END, &s->v_blank_end);
1341
1342 REG_GET(OTG_V_SYNC_A_CNTL,
1343 OTG_V_SYNC_A_POL, &s->v_sync_a_pol);
1344
1345 REG_GET(OTG_V_TOTAL,
1346 OTG_V_TOTAL, &s->v_total);
1347
1348 REG_GET(OTG_V_TOTAL_MAX,
1349 OTG_V_TOTAL_MAX, &s->v_total_max);
1350
1351 REG_GET(OTG_V_TOTAL_MIN,
1352 OTG_V_TOTAL_MIN, &s->v_total_min);
1353
1354 REG_GET(OTG_V_TOTAL_CONTROL,
1355 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
1356
1357 REG_GET(OTG_V_TOTAL_CONTROL,
1358 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
1359
1360 REG_GET_2(OTG_V_SYNC_A,
1361 OTG_V_SYNC_A_START, &s->v_sync_a_start,
1362 OTG_V_SYNC_A_END, &s->v_sync_a_end);
1363
1364 REG_GET_2(OTG_H_BLANK_START_END,
1365 OTG_H_BLANK_START, &s->h_blank_start,
1366 OTG_H_BLANK_END, &s->h_blank_end);
1367
1368 REG_GET_2(OTG_H_SYNC_A,
1369 OTG_H_SYNC_A_START, &s->h_sync_a_start,
1370 OTG_H_SYNC_A_END, &s->h_sync_a_end);
1371
1372 REG_GET(OTG_H_SYNC_A_CNTL,
1373 OTG_H_SYNC_A_POL, &s->h_sync_a_pol);
1374
1375 REG_GET(OTG_H_TOTAL,
1376 OTG_H_TOTAL, &s->h_total);
1377
1378 REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1379 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
1380
1381 REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,
1382 OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en);
1383
1384 REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION,
1385 OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line);
1386 }
1387
optc1_get_otg_active_size(struct timing_generator * optc,uint32_t * otg_active_width,uint32_t * otg_active_height)1388 bool optc1_get_otg_active_size(struct timing_generator *optc,
1389 uint32_t *otg_active_width,
1390 uint32_t *otg_active_height)
1391 {
1392 uint32_t otg_enabled;
1393 uint32_t v_blank_start;
1394 uint32_t v_blank_end;
1395 uint32_t h_blank_start;
1396 uint32_t h_blank_end;
1397 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1398
1399
1400 REG_GET(OTG_CONTROL,
1401 OTG_MASTER_EN, &otg_enabled);
1402
1403 if (otg_enabled == 0)
1404 return false;
1405
1406 REG_GET_2(OTG_V_BLANK_START_END,
1407 OTG_V_BLANK_START, &v_blank_start,
1408 OTG_V_BLANK_END, &v_blank_end);
1409
1410 REG_GET_2(OTG_H_BLANK_START_END,
1411 OTG_H_BLANK_START, &h_blank_start,
1412 OTG_H_BLANK_END, &h_blank_end);
1413
1414 *otg_active_width = v_blank_start - v_blank_end;
1415 *otg_active_height = h_blank_start - h_blank_end;
1416 return true;
1417 }
1418
optc1_clear_optc_underflow(struct timing_generator * optc)1419 void optc1_clear_optc_underflow(struct timing_generator *optc)
1420 {
1421 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1422
1423 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
1424 }
1425
optc1_tg_init(struct timing_generator * optc)1426 void optc1_tg_init(struct timing_generator *optc)
1427 {
1428 optc1_set_blank_data_double_buffer(optc, true);
1429 optc1_set_timing_double_buffer(optc, true);
1430 optc1_clear_optc_underflow(optc);
1431 }
1432
optc1_is_tg_enabled(struct timing_generator * optc)1433 bool optc1_is_tg_enabled(struct timing_generator *optc)
1434 {
1435 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1436 uint32_t otg_enabled = 0;
1437
1438 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
1439
1440 return (otg_enabled != 0);
1441
1442 }
1443
optc1_is_optc_underflow_occurred(struct timing_generator * optc)1444 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
1445 {
1446 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1447 uint32_t underflow_occurred = 0;
1448
1449 REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1450 OPTC_UNDERFLOW_OCCURRED_STATUS,
1451 &underflow_occurred);
1452
1453 return (underflow_occurred == 1);
1454 }
1455
optc1_configure_crc(struct timing_generator * optc,const struct crc_params * params)1456 bool optc1_configure_crc(struct timing_generator *optc,
1457 const struct crc_params *params)
1458 {
1459 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1460
1461 /* Cannot configure crc on a CRTC that is disabled */
1462 if (!optc1_is_tg_enabled(optc))
1463 return false;
1464
1465 REG_WRITE(OTG_CRC_CNTL, 0);
1466
1467 if (!params->enable)
1468 return true;
1469
1470 /* Program frame boundaries */
1471 /* Window A x axis start and end. */
1472 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
1473 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
1474 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
1475
1476 /* Window A y axis start and end. */
1477 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
1478 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
1479 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
1480
1481 /* Window B x axis start and end. */
1482 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
1483 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
1484 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
1485
1486 /* Window B y axis start and end. */
1487 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
1488 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
1489 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
1490
1491 /* Set crc mode and selection, and enable. Only using CRC0*/
1492 REG_UPDATE_3(OTG_CRC_CNTL,
1493 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
1494 OTG_CRC0_SELECT, params->selection,
1495 OTG_CRC_EN, 1);
1496
1497 return true;
1498 }
1499
optc1_get_crc(struct timing_generator * optc,uint32_t * r_cr,uint32_t * g_y,uint32_t * b_cb)1500 bool optc1_get_crc(struct timing_generator *optc,
1501 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
1502 {
1503 uint32_t field = 0;
1504 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1505
1506 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
1507
1508 /* Early return if CRC is not enabled for this CRTC */
1509 if (!field)
1510 return false;
1511
1512 REG_GET_2(OTG_CRC0_DATA_RG,
1513 CRC0_R_CR, r_cr,
1514 CRC0_G_Y, g_y);
1515
1516 REG_GET(OTG_CRC0_DATA_B,
1517 CRC0_B_CB, b_cb);
1518
1519 return true;
1520 }
1521
1522 static const struct timing_generator_funcs dcn10_tg_funcs = {
1523 .validate_timing = optc1_validate_timing,
1524 .program_timing = optc1_program_timing,
1525 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
1526 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
1527 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
1528 .program_global_sync = optc1_program_global_sync,
1529 .enable_crtc = optc1_enable_crtc,
1530 .disable_crtc = optc1_disable_crtc,
1531 /* used by enable_timing_synchronization. Not need for FPGA */
1532 .is_counter_moving = optc1_is_counter_moving,
1533 .get_position = optc1_get_position,
1534 .get_frame_count = optc1_get_vblank_counter,
1535 .get_scanoutpos = optc1_get_crtc_scanoutpos,
1536 .get_otg_active_size = optc1_get_otg_active_size,
1537 .set_early_control = optc1_set_early_control,
1538 /* used by enable_timing_synchronization. Not need for FPGA */
1539 .wait_for_state = optc1_wait_for_state,
1540 .set_blank = optc1_set_blank,
1541 .is_blanked = optc1_is_blanked,
1542 .set_blank_color = optc1_program_blank_color,
1543 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
1544 .enable_reset_trigger = optc1_enable_reset_trigger,
1545 .enable_crtc_reset = optc1_enable_crtc_reset,
1546 .disable_reset_trigger = optc1_disable_reset_trigger,
1547 .lock = optc1_lock,
1548 .is_locked = optc1_is_locked,
1549 .unlock = optc1_unlock,
1550 .enable_optc_clock = optc1_enable_optc_clock,
1551 .set_drr = optc1_set_drr,
1552 .get_last_used_drr_vtotal = NULL,
1553 .set_static_screen_control = optc1_set_static_screen_control,
1554 .set_test_pattern = optc1_set_test_pattern,
1555 .program_stereo = optc1_program_stereo,
1556 .is_stereo_left_eye = optc1_is_stereo_left_eye,
1557 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
1558 .tg_init = optc1_tg_init,
1559 .is_tg_enabled = optc1_is_tg_enabled,
1560 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
1561 .clear_optc_underflow = optc1_clear_optc_underflow,
1562 .get_crc = optc1_get_crc,
1563 .configure_crc = optc1_configure_crc,
1564 .set_vtg_params = optc1_set_vtg_params,
1565 .program_manual_trigger = optc1_program_manual_trigger,
1566 .setup_manual_trigger = optc1_setup_manual_trigger,
1567 .get_hw_timing = optc1_get_hw_timing,
1568 };
1569
dcn10_timing_generator_init(struct optc * optc1)1570 void dcn10_timing_generator_init(struct optc *optc1)
1571 {
1572 optc1->base.funcs = &dcn10_tg_funcs;
1573
1574 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
1575 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
1576
1577 optc1->min_h_blank = 32;
1578 optc1->min_v_blank = 3;
1579 optc1->min_v_blank_interlace = 5;
1580 optc1->min_h_sync_width = 4;
1581 optc1->min_v_sync_width = 1;
1582 }
1583
1584 /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:
1585 *
1586 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as
1587 * containter rate.
1588 *
1589 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be
1590 * halved to maintain the correct pixel rate.
1591 *
1592 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied
1593 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.
1594 *
1595 */
optc1_is_two_pixels_per_containter(const struct dc_crtc_timing * timing)1596 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
1597 {
1598 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
1599
1600 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
1601 && !timing->dsc_cfg.ycbcr422_simple);
1602 return two_pix;
1603 }
1604
1605