1 /* $Id: hscx.c,v 1.1.4.1 2001/11/20 14:19:36 kai Exp $
2 *
3 * HSCX specific routines
4 *
5 * Author Karsten Keil
6 * Copyright by Karsten Keil <keil@isdn4linux.de>
7 *
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
10 *
11 */
12
13 #define __NO_VERSION__
14 #include <linux/init.h>
15 #include "hisax.h"
16 #include "hscx.h"
17 #include "isac.h"
18 #include "isdnl1.h"
19 #include <linux/interrupt.h>
20
21 static char *HSCXVer[] __initdata =
22 {"A1", "?1", "A2", "?3", "A3", "V2.1", "?6", "?7",
23 "?8", "?9", "?10", "?11", "?12", "?13", "?14", "???"};
24
25 int __init
HscxVersion(struct IsdnCardState * cs,char * s)26 HscxVersion(struct IsdnCardState *cs, char *s)
27 {
28 int verA, verB;
29
30 verA = cs->BC_Read_Reg(cs, 0, HSCX_VSTR) & 0xf;
31 verB = cs->BC_Read_Reg(cs, 1, HSCX_VSTR) & 0xf;
32 printk(KERN_INFO "%s HSCX version A: %s B: %s\n", s,
33 HSCXVer[verA], HSCXVer[verB]);
34 if ((verA == 0) | (verA == 0xf) | (verB == 0) | (verB == 0xf))
35 return (1);
36 else
37 return (0);
38 }
39
40 void
modehscx(struct BCState * bcs,int mode,int bc)41 modehscx(struct BCState *bcs, int mode, int bc)
42 {
43 struct IsdnCardState *cs = bcs->cs;
44 int hscx = bcs->hw.hscx.hscx;
45
46 if (cs->debug & L1_DEB_HSCX)
47 debugl1(cs, "hscx %c mode %d ichan %d",
48 'A' + hscx, mode, bc);
49 bcs->mode = mode;
50 bcs->channel = bc;
51 cs->BC_Write_Reg(cs, hscx, HSCX_XAD1, 0xFF);
52 cs->BC_Write_Reg(cs, hscx, HSCX_XAD2, 0xFF);
53 cs->BC_Write_Reg(cs, hscx, HSCX_RAH2, 0xFF);
54 cs->BC_Write_Reg(cs, hscx, HSCX_XBCH, 0x0);
55 cs->BC_Write_Reg(cs, hscx, HSCX_RLCR, 0x0);
56 cs->BC_Write_Reg(cs, hscx, HSCX_CCR1,
57 test_bit(HW_IPAC, &cs->HW_Flags) ? 0x82 : 0x85);
58 cs->BC_Write_Reg(cs, hscx, HSCX_CCR2, 0x30);
59 cs->BC_Write_Reg(cs, hscx, HSCX_XCCR, 7);
60 cs->BC_Write_Reg(cs, hscx, HSCX_RCCR, 7);
61
62 /* Switch IOM 1 SSI */
63 if (test_bit(HW_IOM1, &cs->HW_Flags) && (hscx == 0))
64 bc = 1 - bc;
65
66 if (bc == 0) {
67 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX,
68 test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0);
69 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR,
70 test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0);
71 } else {
72 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, bcs->hw.hscx.tsaxr1);
73 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, bcs->hw.hscx.tsaxr1);
74 }
75 switch (mode) {
76 case (L1_MODE_NULL):
77 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, 0x1f);
78 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, 0x1f);
79 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x84);
80 break;
81 case (L1_MODE_TRANS):
82 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0xe4);
83 break;
84 case (L1_MODE_HDLC):
85 cs->BC_Write_Reg(cs, hscx, HSCX_CCR1,
86 test_bit(HW_IPAC, &cs->HW_Flags) ? 0x8a : 0x8d);
87 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x8c);
88 break;
89 }
90 if (mode)
91 cs->BC_Write_Reg(cs, hscx, HSCX_CMDR, 0x41);
92 cs->BC_Write_Reg(cs, hscx, HSCX_ISTA, 0x00);
93 }
94
95 void
hscx_sched_event(struct BCState * bcs,int event)96 hscx_sched_event(struct BCState *bcs, int event)
97 {
98 bcs->event |= 1 << event;
99 queue_task(&bcs->tqueue, &tq_immediate);
100 mark_bh(IMMEDIATE_BH);
101 }
102
103 void
hscx_l2l1(struct PStack * st,int pr,void * arg)104 hscx_l2l1(struct PStack *st, int pr, void *arg)
105 {
106 struct sk_buff *skb = arg;
107 long flags;
108
109 switch (pr) {
110 case (PH_DATA | REQUEST):
111 save_flags(flags);
112 cli();
113 if (st->l1.bcs->tx_skb) {
114 skb_queue_tail(&st->l1.bcs->squeue, skb);
115 restore_flags(flags);
116 } else {
117 st->l1.bcs->tx_skb = skb;
118 test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
119 st->l1.bcs->hw.hscx.count = 0;
120 restore_flags(flags);
121 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
122 }
123 break;
124 case (PH_PULL | INDICATION):
125 if (st->l1.bcs->tx_skb) {
126 printk(KERN_WARNING "hscx_l2l1: this shouldn't happen\n");
127 break;
128 }
129 test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
130 st->l1.bcs->tx_skb = skb;
131 st->l1.bcs->hw.hscx.count = 0;
132 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
133 break;
134 case (PH_PULL | REQUEST):
135 if (!st->l1.bcs->tx_skb) {
136 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
137 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
138 } else
139 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
140 break;
141 case (PH_ACTIVATE | REQUEST):
142 test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
143 modehscx(st->l1.bcs, st->l1.mode, st->l1.bc);
144 l1_msg_b(st, pr, arg);
145 break;
146 case (PH_DEACTIVATE | REQUEST):
147 l1_msg_b(st, pr, arg);
148 break;
149 case (PH_DEACTIVATE | CONFIRM):
150 test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
151 test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
152 modehscx(st->l1.bcs, 0, st->l1.bc);
153 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
154 break;
155 }
156 }
157
158 void
close_hscxstate(struct BCState * bcs)159 close_hscxstate(struct BCState *bcs)
160 {
161 modehscx(bcs, 0, bcs->channel);
162 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
163 if (bcs->hw.hscx.rcvbuf) {
164 kfree(bcs->hw.hscx.rcvbuf);
165 bcs->hw.hscx.rcvbuf = NULL;
166 }
167 if (bcs->blog) {
168 kfree(bcs->blog);
169 bcs->blog = NULL;
170 }
171 skb_queue_purge(&bcs->rqueue);
172 skb_queue_purge(&bcs->squeue);
173 if (bcs->tx_skb) {
174 dev_kfree_skb_any(bcs->tx_skb);
175 bcs->tx_skb = NULL;
176 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
177 }
178 }
179 }
180
181 int
open_hscxstate(struct IsdnCardState * cs,struct BCState * bcs)182 open_hscxstate(struct IsdnCardState *cs, struct BCState *bcs)
183 {
184 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
185 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
186 printk(KERN_WARNING
187 "HiSax: No memory for hscx.rcvbuf\n");
188 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
189 return (1);
190 }
191 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
192 printk(KERN_WARNING
193 "HiSax: No memory for bcs->blog\n");
194 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
195 kfree(bcs->hw.hscx.rcvbuf);
196 bcs->hw.hscx.rcvbuf = NULL;
197 return (2);
198 }
199 skb_queue_head_init(&bcs->rqueue);
200 skb_queue_head_init(&bcs->squeue);
201 }
202 bcs->tx_skb = NULL;
203 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
204 bcs->event = 0;
205 bcs->hw.hscx.rcvidx = 0;
206 bcs->tx_cnt = 0;
207 return (0);
208 }
209
210 int
setstack_hscx(struct PStack * st,struct BCState * bcs)211 setstack_hscx(struct PStack *st, struct BCState *bcs)
212 {
213 bcs->channel = st->l1.bc;
214 if (open_hscxstate(st->l1.hardware, bcs))
215 return (-1);
216 st->l1.bcs = bcs;
217 st->l2.l2l1 = hscx_l2l1;
218 setstack_manager(st);
219 bcs->st = st;
220 setstack_l1_B(st);
221 return (0);
222 }
223
224 void __init
clear_pending_hscx_ints(struct IsdnCardState * cs)225 clear_pending_hscx_ints(struct IsdnCardState *cs)
226 {
227 int val, eval;
228
229 val = cs->BC_Read_Reg(cs, 1, HSCX_ISTA);
230 debugl1(cs, "HSCX B ISTA %x", val);
231 if (val & 0x01) {
232 eval = cs->BC_Read_Reg(cs, 1, HSCX_EXIR);
233 debugl1(cs, "HSCX B EXIR %x", eval);
234 }
235 if (val & 0x02) {
236 eval = cs->BC_Read_Reg(cs, 0, HSCX_EXIR);
237 debugl1(cs, "HSCX A EXIR %x", eval);
238 }
239 val = cs->BC_Read_Reg(cs, 0, HSCX_ISTA);
240 debugl1(cs, "HSCX A ISTA %x", val);
241 val = cs->BC_Read_Reg(cs, 1, HSCX_STAR);
242 debugl1(cs, "HSCX B STAR %x", val);
243 val = cs->BC_Read_Reg(cs, 0, HSCX_STAR);
244 debugl1(cs, "HSCX A STAR %x", val);
245 /* disable all IRQ */
246 cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0xFF);
247 cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0xFF);
248 }
249
250 void __init
inithscx(struct IsdnCardState * cs)251 inithscx(struct IsdnCardState *cs)
252 {
253 cs->bcs[0].BC_SetStack = setstack_hscx;
254 cs->bcs[1].BC_SetStack = setstack_hscx;
255 cs->bcs[0].BC_Close = close_hscxstate;
256 cs->bcs[1].BC_Close = close_hscxstate;
257 cs->bcs[0].hw.hscx.hscx = 0;
258 cs->bcs[1].hw.hscx.hscx = 1;
259 cs->bcs[0].hw.hscx.tsaxr0 = 0x2f;
260 cs->bcs[0].hw.hscx.tsaxr1 = 3;
261 cs->bcs[1].hw.hscx.tsaxr0 = 0x2f;
262 cs->bcs[1].hw.hscx.tsaxr1 = 3;
263 modehscx(cs->bcs, 0, 0);
264 modehscx(cs->bcs + 1, 0, 0);
265 }
266
267 void __init
inithscxisac(struct IsdnCardState * cs,int part)268 inithscxisac(struct IsdnCardState *cs, int part)
269 {
270 if (part & 1) {
271 clear_pending_isac_ints(cs);
272 clear_pending_hscx_ints(cs);
273 initisac(cs);
274 inithscx(cs);
275 }
276 if (part & 2) {
277 /* Reenable all IRQ */
278 cs->writeisac(cs, ISAC_MASK, 0);
279 cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0);
280 cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0);
281 /* RESET Receiver and Transmitter */
282 cs->writeisac(cs, ISAC_CMDR, 0x41);
283 }
284 }
285