1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * OMAP5 Clock init
4  *
5  * Copyright (C) 2013 Texas Instruments, Inc.
6  *
7  * Tero Kristo (t-kristo@ti.com)
8  */
9 
10 #include <linux/kernel.h>
11 #include <linux/list.h>
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/io.h>
15 #include <linux/clk/ti.h>
16 #include <dt-bindings/clock/omap5.h>
17 
18 #include "clock.h"
19 
20 #define OMAP5_DPLL_ABE_DEFFREQ				98304000
21 
22 /*
23  * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
24  * states it must be at 960MHz
25  */
26 #define OMAP5_DPLL_USB_DEFFREQ				960000000
27 
28 static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
29 	{ OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
30 	{ 0 },
31 };
32 
33 static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
34 	{ OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h11x2_ck" },
35 	{ 0 },
36 };
37 
38 static const char * const omap5_aess_fclk_parents[] __initconst = {
39 	"abe_clk",
40 	NULL,
41 };
42 
43 static const struct omap_clkctrl_div_data omap5_aess_fclk_data __initconst = {
44 	.max_div = 2,
45 };
46 
47 static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
48 	{ 24, TI_CLK_DIVIDER, omap5_aess_fclk_parents, &omap5_aess_fclk_data },
49 	{ 0 },
50 };
51 
52 static const char * const omap5_dmic_gfclk_parents[] __initconst = {
53 	"abe-clkctrl:0018:26",
54 	"pad_clks_ck",
55 	"slimbus_clk",
56 	NULL,
57 };
58 
59 static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
60 	"abe_24m_fclk",
61 	"dss_syc_gfclk_div",
62 	"func_24m_clk",
63 	NULL,
64 };
65 
66 static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
67 	{ 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
68 	{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
69 	{ 0 },
70 };
71 
72 static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
73 	"abe-clkctrl:0028:26",
74 	"pad_clks_ck",
75 	"slimbus_clk",
76 	NULL,
77 };
78 
79 static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
80 	{ 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
81 	{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
82 	{ 0 },
83 };
84 
85 static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
86 	"abe-clkctrl:0030:26",
87 	"pad_clks_ck",
88 	"slimbus_clk",
89 	NULL,
90 };
91 
92 static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = {
93 	{ 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
94 	{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
95 	{ 0 },
96 };
97 
98 static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
99 	"abe-clkctrl:0038:26",
100 	"pad_clks_ck",
101 	"slimbus_clk",
102 	NULL,
103 };
104 
105 static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = {
106 	{ 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
107 	{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
108 	{ 0 },
109 };
110 
111 static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = {
112 	"dss_syc_gfclk_div",
113 	"sys_32k_ck",
114 	NULL,
115 };
116 
117 static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = {
118 	{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
119 	{ 0 },
120 };
121 
122 static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = {
123 	{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
124 	{ 0 },
125 };
126 
127 static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = {
128 	{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
129 	{ 0 },
130 };
131 
132 static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = {
133 	{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
134 	{ 0 },
135 };
136 
137 static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
138 	{ OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
139 	{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
140 	{ OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
141 	{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
142 	{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
143 	{ OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
144 	{ OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
145 	{ OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
146 	{ OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
147 	{ OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
148 	{ OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
149 	{ 0 },
150 };
151 
152 static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = {
153 	{ OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
154 	{ 0 },
155 };
156 
157 static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = {
158 	{ OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
159 	{ OMAP5_L3_MAIN_2_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
160 	{ OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
161 	{ 0 },
162 };
163 
164 static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = {
165 	{ OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
166 	{ 0 },
167 };
168 
169 static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = {
170 	{ OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
171 	{ 0 },
172 };
173 
174 static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = {
175 	{ OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
176 	{ OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
177 	{ OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
178 	{ 0 },
179 };
180 
181 static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = {
182 	{ OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
183 	{ OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
184 	{ OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
185 	{ 0 },
186 };
187 
188 static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = {
189 	{ OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
190 	{ OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
191 	{ 0 },
192 };
193 
194 static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = {
195 	"sys_clkin",
196 	"sys_32k_ck",
197 	NULL,
198 };
199 
200 static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = {
201 	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
202 	{ 0 },
203 };
204 
205 static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = {
206 	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
207 	{ 0 },
208 };
209 
210 static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = {
211 	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
212 	{ 0 },
213 };
214 
215 static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = {
216 	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
217 	{ 0 },
218 };
219 
220 static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = {
221 	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
222 	{ 0 },
223 };
224 
225 static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = {
226 	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
227 	{ 0 },
228 };
229 
230 static const char * const omap5_gpio2_dbclk_parents[] __initconst = {
231 	"sys_32k_ck",
232 	NULL,
233 };
234 
235 static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = {
236 	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
237 	{ 0 },
238 };
239 
240 static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = {
241 	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
242 	{ 0 },
243 };
244 
245 static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = {
246 	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
247 	{ 0 },
248 };
249 
250 static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = {
251 	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
252 	{ 0 },
253 };
254 
255 static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = {
256 	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
257 	{ 0 },
258 };
259 
260 static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = {
261 	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
262 	{ 0 },
263 };
264 
265 static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
266 	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
267 	{ 0 },
268 };
269 
270 static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
271 	{ OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
272 	{ OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
273 	{ OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
274 	{ OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
275 	{ OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
276 	{ OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0030:24" },
277 	{ OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
278 	{ OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
279 	{ OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
280 	{ OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
281 	{ OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
282 	{ OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
283 	{ OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
284 	{ OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
285 	{ OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
286 	{ OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
287 	{ OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
288 	{ OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
289 	{ OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
290 	{ OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
291 	{ OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
292 	{ OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
293 	{ OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
294 	{ OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
295 	{ OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
296 	{ OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
297 	{ OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
298 	{ OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
299 	{ OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
300 	{ OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
301 	{ OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
302 	{ OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
303 	{ 0 },
304 };
305 
306 static const struct
307 omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = {
308 	{ OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
309 	{ OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
310 	{ OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
311 	{ OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
312 	{ OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
313 	{ OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
314 	{ OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div" },
315 	{ 0 },
316 };
317 
318 static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = {
319 	{ OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
320 	{ OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
321 	{ 0 },
322 };
323 
324 static const char * const omap5_dss_dss_clk_parents[] __initconst = {
325 	"dpll_per_h12x2_ck",
326 	NULL,
327 };
328 
329 static const char * const omap5_dss_48mhz_clk_parents[] __initconst = {
330 	"func_48m_fclk",
331 	NULL,
332 };
333 
334 static const char * const omap5_dss_sys_clk_parents[] __initconst = {
335 	"dss_syc_gfclk_div",
336 	NULL,
337 };
338 
339 static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = {
340 	{ 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
341 	{ 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
342 	{ 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
343 	{ 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
344 	{ 0 },
345 };
346 
347 static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
348 	{ OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
349 	{ 0 },
350 };
351 
352 static const char * const omap5_gpu_core_mux_parents[] __initconst = {
353 	"dpll_core_h14x2_ck",
354 	"dpll_per_h14x2_ck",
355 	NULL,
356 };
357 
358 static const char * const omap5_gpu_hyd_mux_parents[] __initconst = {
359 	"dpll_core_h14x2_ck",
360 	"dpll_per_h14x2_ck",
361 	NULL,
362 };
363 
364 static const char * const omap5_gpu_sys_clk_parents[] __initconst = {
365 	"sys_clkin",
366 	NULL,
367 };
368 
369 static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = {
370 	.max_div = 2,
371 };
372 
373 static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = {
374 	{ 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
375 	{ 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
376 	{ 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data },
377 	{ 0 },
378 };
379 
380 static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
381 	{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24" },
382 	{ 0 },
383 };
384 
385 static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
386 	"func_128m_clk",
387 	"dpll_per_m2x2_ck",
388 	NULL,
389 };
390 
391 static const char * const omap5_mmc1_fclk_parents[] __initconst = {
392 	"l3init-clkctrl:0008:24",
393 	NULL,
394 };
395 
396 static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = {
397 	.max_div = 2,
398 };
399 
400 static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
401 	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
402 	{ 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
403 	{ 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data },
404 	{ 0 },
405 };
406 
407 static const char * const omap5_mmc2_fclk_parents[] __initconst = {
408 	"l3init-clkctrl:0010:24",
409 	NULL,
410 };
411 
412 static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = {
413 	.max_div = 2,
414 };
415 
416 static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = {
417 	{ 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
418 	{ 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data },
419 	{ 0 },
420 };
421 
422 static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = {
423 	"l3init_60m_fclk",
424 	NULL,
425 };
426 
427 static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = {
428 	"dpll_usb_m2_ck",
429 	NULL,
430 };
431 
432 static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
433 	"l3init-clkctrl:0038:24",
434 	NULL,
435 };
436 
437 static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
438 	"l3init-clkctrl:0038:25",
439 	NULL,
440 };
441 
442 static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = {
443 	"l3init_60m_fclk",
444 	"xclk60mhsp1_ck",
445 	NULL,
446 };
447 
448 static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = {
449 	"l3init_60m_fclk",
450 	"xclk60mhsp2_ck",
451 	NULL,
452 };
453 
454 static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = {
455 	{ 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
456 	{ 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
457 	{ 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
458 	{ 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
459 	{ 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
460 	{ 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
461 	{ 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
462 	{ 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
463 	{ 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
464 	{ 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
465 	{ 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
466 	{ 0 },
467 };
468 
469 static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = {
470 	{ 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
471 	{ 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
472 	{ 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
473 	{ 0 },
474 };
475 
476 static const char * const omap5_sata_ref_clk_parents[] __initconst = {
477 	"sys_clkin",
478 	NULL,
479 };
480 
481 static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = {
482 	{ 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
483 	{ 0 },
484 };
485 
486 static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = {
487 	"dpll_usb_clkdcoldo",
488 	NULL,
489 };
490 
491 static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = {
492 	{ 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
493 	{ 0 },
494 };
495 
496 static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
497 	{ OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
498 	{ OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
499 	{ OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
500 	{ OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
501 	{ OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
502 	{ OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
503 	{ OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
504 	{ OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
505 	{ 0 },
506 };
507 
508 static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = {
509 	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
510 	{ 0 },
511 };
512 
513 static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = {
514 	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
515 	{ 0 },
516 };
517 
518 static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = {
519 	{ OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
520 	{ OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
521 	{ OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
522 	{ OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
523 	{ OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
524 	{ OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
525 	{ 0 },
526 };
527 
528 const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
529 	{ 0x4a004320, omap5_mpu_clkctrl_regs },
530 	{ 0x4a004420, omap5_dsp_clkctrl_regs },
531 	{ 0x4a004520, omap5_abe_clkctrl_regs },
532 	{ 0x4a008720, omap5_l3main1_clkctrl_regs },
533 	{ 0x4a008820, omap5_l3main2_clkctrl_regs },
534 	{ 0x4a008920, omap5_ipu_clkctrl_regs },
535 	{ 0x4a008a20, omap5_dma_clkctrl_regs },
536 	{ 0x4a008b20, omap5_emif_clkctrl_regs },
537 	{ 0x4a008d20, omap5_l4cfg_clkctrl_regs },
538 	{ 0x4a008e20, omap5_l3instr_clkctrl_regs },
539 	{ 0x4a009020, omap5_l4per_clkctrl_regs },
540 	{ 0x4a0091a0, omap5_l4_secure_clkctrl_regs },
541 	{ 0x4a009220, omap5_iva_clkctrl_regs },
542 	{ 0x4a009420, omap5_dss_clkctrl_regs },
543 	{ 0x4a009520, omap5_gpu_clkctrl_regs },
544 	{ 0x4a009620, omap5_l3init_clkctrl_regs },
545 	{ 0x4ae07920, omap5_wkupaon_clkctrl_regs },
546 	{ 0 },
547 };
548 
549 static struct ti_dt_clk omap54xx_clks[] = {
550 	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
551 	DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
552 	DT_CLK(NULL, "dmic_gfclk", "abe-clkctrl:0018:24"),
553 	DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
554 	DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
555 	DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
556 	DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
557 	DT_CLK(NULL, "dss_sys_clk", "dss-clkctrl:0000:10"),
558 	DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
559 	DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0040:8"),
560 	DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0048:8"),
561 	DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0050:8"),
562 	DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0058:8"),
563 	DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0060:8"),
564 	DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00f0:8"),
565 	DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"),
566 	DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"),
567 	DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
568 	DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"),
569 	DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
570 	DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"),
571 	DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
572 	DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"),
573 	DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"),
574 	DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
575 	DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"),
576 	DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
577 	DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
578 	DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"),
579 	DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"),
580 	DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
581 	DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0018:24"),
582 	DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0020:24"),
583 	DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0028:24"),
584 	DT_CLK(NULL, "timer5_gfclk_mux", "abe-clkctrl:0048:24"),
585 	DT_CLK(NULL, "timer6_gfclk_mux", "abe-clkctrl:0050:24"),
586 	DT_CLK(NULL, "timer7_gfclk_mux", "abe-clkctrl:0058:24"),
587 	DT_CLK(NULL, "timer8_gfclk_mux", "abe-clkctrl:0060:24"),
588 	DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0030:24"),
589 	DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init-clkctrl:0038:13"),
590 	DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init-clkctrl:0038:14"),
591 	DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init-clkctrl:0038:7"),
592 	DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init-clkctrl:0038:11"),
593 	DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init-clkctrl:0038:12"),
594 	DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init-clkctrl:0038:6"),
595 	DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init-clkctrl:0038:8"),
596 	DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init-clkctrl:0038:9"),
597 	DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init-clkctrl:0038:10"),
598 	DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init-clkctrl:00d0:8"),
599 	DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init-clkctrl:0048:8"),
600 	DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init-clkctrl:0048:9"),
601 	DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init-clkctrl:0048:10"),
602 	DT_CLK(NULL, "utmi_p1_gfclk", "l3init-clkctrl:0038:24"),
603 	DT_CLK(NULL, "utmi_p2_gfclk", "l3init-clkctrl:0038:25"),
604 	{ .node_name = NULL },
605 };
606 
omap5xxx_dt_clk_init(void)607 int __init omap5xxx_dt_clk_init(void)
608 {
609 	int rc;
610 	struct clk *abe_dpll_ref, *abe_dpll, *abe_dpll_byp, *sys_32k_ck, *usb_dpll;
611 
612 	ti_dt_clocks_register(omap54xx_clks);
613 
614 	omap2_clk_disable_autoidle_all();
615 
616 	ti_clk_add_aliases();
617 
618 	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
619 	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
620 	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
621 
622 	/*
623 	 * This must also be set to sys_32k_ck to match or
624 	 * the ABE DPLL will not lock on a warm reboot when
625 	 * ABE timers are used.
626 	 */
627 	abe_dpll_byp = clk_get_sys(NULL, "abe_dpll_bypass_clk_mux");
628 	if (!rc)
629 		rc = clk_set_parent(abe_dpll_byp, sys_32k_ck);
630 
631 	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
632 	if (!rc)
633 		rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
634 	if (rc)
635 		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
636 
637 	abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
638 	if (!rc)
639 		rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2);
640 	if (rc)
641 		pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__);
642 
643 	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
644 	rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
645 	if (rc)
646 		pr_err("%s: failed to configure USB DPLL!\n", __func__);
647 
648 	usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
649 	rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
650 	if (rc)
651 		pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
652 
653 	return 0;
654 }
655