1 /*
2 * linux/arch/arm/mach-omap1/clock.c
3 *
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 *
7 * Modified to use omap shared clock framework by
8 * Tony Lindgren <tony@atomide.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14 #include <linux/kernel.h>
15 #include <linux/list.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/clkdev.h>
21
22 #include <asm/mach-types.h>
23
24 #include <plat/cpu.h>
25 #include <plat/usb.h>
26 #include <plat/clock.h>
27 #include <plat/sram.h>
28 #include <plat/clkdev_omap.h>
29
30 #include <mach/hardware.h>
31
32 #include "iomap.h"
33 #include "clock.h"
34 #include "opp.h"
35
36 __u32 arm_idlect1_mask;
37 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
38
39 /*
40 * Omap1 specific clock functions
41 */
42
omap1_uart_recalc(struct clk * clk)43 unsigned long omap1_uart_recalc(struct clk *clk)
44 {
45 unsigned int val = __raw_readl(clk->enable_reg);
46 return val & clk->enable_bit ? 48000000 : 12000000;
47 }
48
omap1_sossi_recalc(struct clk * clk)49 unsigned long omap1_sossi_recalc(struct clk *clk)
50 {
51 u32 div = omap_readl(MOD_CONF_CTRL_1);
52
53 div = (div >> 17) & 0x7;
54 div++;
55
56 return clk->parent->rate / div;
57 }
58
omap1_clk_allow_idle(struct clk * clk)59 static void omap1_clk_allow_idle(struct clk *clk)
60 {
61 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
62
63 if (!(clk->flags & CLOCK_IDLE_CONTROL))
64 return;
65
66 if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
67 arm_idlect1_mask |= 1 << iclk->idlect_shift;
68 }
69
omap1_clk_deny_idle(struct clk * clk)70 static void omap1_clk_deny_idle(struct clk *clk)
71 {
72 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
73
74 if (!(clk->flags & CLOCK_IDLE_CONTROL))
75 return;
76
77 if (iclk->no_idle_count++ == 0)
78 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
79 }
80
verify_ckctl_value(__u16 newval)81 static __u16 verify_ckctl_value(__u16 newval)
82 {
83 /* This function checks for following limitations set
84 * by the hardware (all conditions must be true):
85 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
86 * ARM_CK >= TC_CK
87 * DSP_CK >= TC_CK
88 * DSPMMU_CK >= TC_CK
89 *
90 * In addition following rules are enforced:
91 * LCD_CK <= TC_CK
92 * ARMPER_CK <= TC_CK
93 *
94 * However, maximum frequencies are not checked for!
95 */
96 __u8 per_exp;
97 __u8 lcd_exp;
98 __u8 arm_exp;
99 __u8 dsp_exp;
100 __u8 tc_exp;
101 __u8 dspmmu_exp;
102
103 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
104 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
105 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
106 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
107 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
108 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
109
110 if (dspmmu_exp < dsp_exp)
111 dspmmu_exp = dsp_exp;
112 if (dspmmu_exp > dsp_exp+1)
113 dspmmu_exp = dsp_exp+1;
114 if (tc_exp < arm_exp)
115 tc_exp = arm_exp;
116 if (tc_exp < dspmmu_exp)
117 tc_exp = dspmmu_exp;
118 if (tc_exp > lcd_exp)
119 lcd_exp = tc_exp;
120 if (tc_exp > per_exp)
121 per_exp = tc_exp;
122
123 newval &= 0xf000;
124 newval |= per_exp << CKCTL_PERDIV_OFFSET;
125 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
126 newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
127 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
128 newval |= tc_exp << CKCTL_TCDIV_OFFSET;
129 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
130
131 return newval;
132 }
133
calc_dsor_exp(struct clk * clk,unsigned long rate)134 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
135 {
136 /* Note: If target frequency is too low, this function will return 4,
137 * which is invalid value. Caller must check for this value and act
138 * accordingly.
139 *
140 * Note: This function does not check for following limitations set
141 * by the hardware (all conditions must be true):
142 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
143 * ARM_CK >= TC_CK
144 * DSP_CK >= TC_CK
145 * DSPMMU_CK >= TC_CK
146 */
147 unsigned long realrate;
148 struct clk * parent;
149 unsigned dsor_exp;
150
151 parent = clk->parent;
152 if (unlikely(parent == NULL))
153 return -EIO;
154
155 realrate = parent->rate;
156 for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
157 if (realrate <= rate)
158 break;
159
160 realrate /= 2;
161 }
162
163 return dsor_exp;
164 }
165
omap1_ckctl_recalc(struct clk * clk)166 unsigned long omap1_ckctl_recalc(struct clk *clk)
167 {
168 /* Calculate divisor encoded as 2-bit exponent */
169 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
170
171 return clk->parent->rate / dsor;
172 }
173
omap1_ckctl_recalc_dsp_domain(struct clk * clk)174 unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
175 {
176 int dsor;
177
178 /* Calculate divisor encoded as 2-bit exponent
179 *
180 * The clock control bits are in DSP domain,
181 * so api_ck is needed for access.
182 * Note that DSP_CKCTL virt addr = phys addr, so
183 * we must use __raw_readw() instead of omap_readw().
184 */
185 omap1_clk_enable(api_ck_p);
186 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
187 omap1_clk_disable(api_ck_p);
188
189 return clk->parent->rate / dsor;
190 }
191
192 /* MPU virtual clock functions */
omap1_select_table_rate(struct clk * clk,unsigned long rate)193 int omap1_select_table_rate(struct clk *clk, unsigned long rate)
194 {
195 /* Find the highest supported frequency <= rate and switch to it */
196 struct mpu_rate * ptr;
197 unsigned long dpll1_rate, ref_rate;
198
199 dpll1_rate = ck_dpll1_p->rate;
200 ref_rate = ck_ref_p->rate;
201
202 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
203 if (!(ptr->flags & cpu_mask))
204 continue;
205
206 if (ptr->xtal != ref_rate)
207 continue;
208
209 /* Can check only after xtal frequency check */
210 if (ptr->rate <= rate)
211 break;
212 }
213
214 if (!ptr->rate)
215 return -EINVAL;
216
217 /*
218 * In most cases we should not need to reprogram DPLL.
219 * Reprogramming the DPLL is tricky, it must be done from SRAM.
220 */
221 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
222
223 /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
224 ck_dpll1_p->rate = ptr->pll_rate;
225
226 return 0;
227 }
228
omap1_clk_set_rate_dsp_domain(struct clk * clk,unsigned long rate)229 int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
230 {
231 int dsor_exp;
232 u16 regval;
233
234 dsor_exp = calc_dsor_exp(clk, rate);
235 if (dsor_exp > 3)
236 dsor_exp = -EINVAL;
237 if (dsor_exp < 0)
238 return dsor_exp;
239
240 regval = __raw_readw(DSP_CKCTL);
241 regval &= ~(3 << clk->rate_offset);
242 regval |= dsor_exp << clk->rate_offset;
243 __raw_writew(regval, DSP_CKCTL);
244 clk->rate = clk->parent->rate / (1 << dsor_exp);
245
246 return 0;
247 }
248
omap1_clk_round_rate_ckctl_arm(struct clk * clk,unsigned long rate)249 long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
250 {
251 int dsor_exp = calc_dsor_exp(clk, rate);
252 if (dsor_exp < 0)
253 return dsor_exp;
254 if (dsor_exp > 3)
255 dsor_exp = 3;
256 return clk->parent->rate / (1 << dsor_exp);
257 }
258
omap1_clk_set_rate_ckctl_arm(struct clk * clk,unsigned long rate)259 int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
260 {
261 int dsor_exp;
262 u16 regval;
263
264 dsor_exp = calc_dsor_exp(clk, rate);
265 if (dsor_exp > 3)
266 dsor_exp = -EINVAL;
267 if (dsor_exp < 0)
268 return dsor_exp;
269
270 regval = omap_readw(ARM_CKCTL);
271 regval &= ~(3 << clk->rate_offset);
272 regval |= dsor_exp << clk->rate_offset;
273 regval = verify_ckctl_value(regval);
274 omap_writew(regval, ARM_CKCTL);
275 clk->rate = clk->parent->rate / (1 << dsor_exp);
276 return 0;
277 }
278
omap1_round_to_table_rate(struct clk * clk,unsigned long rate)279 long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
280 {
281 /* Find the highest supported frequency <= rate */
282 struct mpu_rate * ptr;
283 long highest_rate;
284 unsigned long ref_rate;
285
286 ref_rate = ck_ref_p->rate;
287
288 highest_rate = -EINVAL;
289
290 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
291 if (!(ptr->flags & cpu_mask))
292 continue;
293
294 if (ptr->xtal != ref_rate)
295 continue;
296
297 highest_rate = ptr->rate;
298
299 /* Can check only after xtal frequency check */
300 if (ptr->rate <= rate)
301 break;
302 }
303
304 return highest_rate;
305 }
306
calc_ext_dsor(unsigned long rate)307 static unsigned calc_ext_dsor(unsigned long rate)
308 {
309 unsigned dsor;
310
311 /* MCLK and BCLK divisor selection is not linear:
312 * freq = 96MHz / dsor
313 *
314 * RATIO_SEL range: dsor <-> RATIO_SEL
315 * 0..6: (RATIO_SEL+2) <-> (dsor-2)
316 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
317 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
318 * can not be used.
319 */
320 for (dsor = 2; dsor < 96; ++dsor) {
321 if ((dsor & 1) && dsor > 8)
322 continue;
323 if (rate >= 96000000 / dsor)
324 break;
325 }
326 return dsor;
327 }
328
329 /* XXX Only needed on 1510 */
omap1_set_uart_rate(struct clk * clk,unsigned long rate)330 int omap1_set_uart_rate(struct clk *clk, unsigned long rate)
331 {
332 unsigned int val;
333
334 val = __raw_readl(clk->enable_reg);
335 if (rate == 12000000)
336 val &= ~(1 << clk->enable_bit);
337 else if (rate == 48000000)
338 val |= (1 << clk->enable_bit);
339 else
340 return -EINVAL;
341 __raw_writel(val, clk->enable_reg);
342 clk->rate = rate;
343
344 return 0;
345 }
346
347 /* External clock (MCLK & BCLK) functions */
omap1_set_ext_clk_rate(struct clk * clk,unsigned long rate)348 int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
349 {
350 unsigned dsor;
351 __u16 ratio_bits;
352
353 dsor = calc_ext_dsor(rate);
354 clk->rate = 96000000 / dsor;
355 if (dsor > 8)
356 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
357 else
358 ratio_bits = (dsor - 2) << 2;
359
360 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
361 __raw_writew(ratio_bits, clk->enable_reg);
362
363 return 0;
364 }
365
omap1_set_sossi_rate(struct clk * clk,unsigned long rate)366 int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
367 {
368 u32 l;
369 int div;
370 unsigned long p_rate;
371
372 p_rate = clk->parent->rate;
373 /* Round towards slower frequency */
374 div = (p_rate + rate - 1) / rate;
375 div--;
376 if (div < 0 || div > 7)
377 return -EINVAL;
378
379 l = omap_readl(MOD_CONF_CTRL_1);
380 l &= ~(7 << 17);
381 l |= div << 17;
382 omap_writel(l, MOD_CONF_CTRL_1);
383
384 clk->rate = p_rate / (div + 1);
385
386 return 0;
387 }
388
omap1_round_ext_clk_rate(struct clk * clk,unsigned long rate)389 long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate)
390 {
391 return 96000000 / calc_ext_dsor(rate);
392 }
393
omap1_init_ext_clk(struct clk * clk)394 void omap1_init_ext_clk(struct clk *clk)
395 {
396 unsigned dsor;
397 __u16 ratio_bits;
398
399 /* Determine current rate and ensure clock is based on 96MHz APLL */
400 ratio_bits = __raw_readw(clk->enable_reg) & ~1;
401 __raw_writew(ratio_bits, clk->enable_reg);
402
403 ratio_bits = (ratio_bits & 0xfc) >> 2;
404 if (ratio_bits > 6)
405 dsor = (ratio_bits - 6) * 2 + 8;
406 else
407 dsor = ratio_bits + 2;
408
409 clk-> rate = 96000000 / dsor;
410 }
411
omap1_clk_enable(struct clk * clk)412 int omap1_clk_enable(struct clk *clk)
413 {
414 int ret = 0;
415
416 if (clk->usecount++ == 0) {
417 if (clk->parent) {
418 ret = omap1_clk_enable(clk->parent);
419 if (ret)
420 goto err;
421
422 if (clk->flags & CLOCK_NO_IDLE_PARENT)
423 omap1_clk_deny_idle(clk->parent);
424 }
425
426 ret = clk->ops->enable(clk);
427 if (ret) {
428 if (clk->parent)
429 omap1_clk_disable(clk->parent);
430 goto err;
431 }
432 }
433 return ret;
434
435 err:
436 clk->usecount--;
437 return ret;
438 }
439
omap1_clk_disable(struct clk * clk)440 void omap1_clk_disable(struct clk *clk)
441 {
442 if (clk->usecount > 0 && !(--clk->usecount)) {
443 clk->ops->disable(clk);
444 if (likely(clk->parent)) {
445 omap1_clk_disable(clk->parent);
446 if (clk->flags & CLOCK_NO_IDLE_PARENT)
447 omap1_clk_allow_idle(clk->parent);
448 }
449 }
450 }
451
omap1_clk_enable_generic(struct clk * clk)452 static int omap1_clk_enable_generic(struct clk *clk)
453 {
454 __u16 regval16;
455 __u32 regval32;
456
457 if (unlikely(clk->enable_reg == NULL)) {
458 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
459 clk->name);
460 return -EINVAL;
461 }
462
463 if (clk->flags & ENABLE_REG_32BIT) {
464 regval32 = __raw_readl(clk->enable_reg);
465 regval32 |= (1 << clk->enable_bit);
466 __raw_writel(regval32, clk->enable_reg);
467 } else {
468 regval16 = __raw_readw(clk->enable_reg);
469 regval16 |= (1 << clk->enable_bit);
470 __raw_writew(regval16, clk->enable_reg);
471 }
472
473 return 0;
474 }
475
omap1_clk_disable_generic(struct clk * clk)476 static void omap1_clk_disable_generic(struct clk *clk)
477 {
478 __u16 regval16;
479 __u32 regval32;
480
481 if (clk->enable_reg == NULL)
482 return;
483
484 if (clk->flags & ENABLE_REG_32BIT) {
485 regval32 = __raw_readl(clk->enable_reg);
486 regval32 &= ~(1 << clk->enable_bit);
487 __raw_writel(regval32, clk->enable_reg);
488 } else {
489 regval16 = __raw_readw(clk->enable_reg);
490 regval16 &= ~(1 << clk->enable_bit);
491 __raw_writew(regval16, clk->enable_reg);
492 }
493 }
494
495 const struct clkops clkops_generic = {
496 .enable = omap1_clk_enable_generic,
497 .disable = omap1_clk_disable_generic,
498 };
499
omap1_clk_enable_dsp_domain(struct clk * clk)500 static int omap1_clk_enable_dsp_domain(struct clk *clk)
501 {
502 int retval;
503
504 retval = omap1_clk_enable(api_ck_p);
505 if (!retval) {
506 retval = omap1_clk_enable_generic(clk);
507 omap1_clk_disable(api_ck_p);
508 }
509
510 return retval;
511 }
512
omap1_clk_disable_dsp_domain(struct clk * clk)513 static void omap1_clk_disable_dsp_domain(struct clk *clk)
514 {
515 if (omap1_clk_enable(api_ck_p) == 0) {
516 omap1_clk_disable_generic(clk);
517 omap1_clk_disable(api_ck_p);
518 }
519 }
520
521 const struct clkops clkops_dspck = {
522 .enable = omap1_clk_enable_dsp_domain,
523 .disable = omap1_clk_disable_dsp_domain,
524 };
525
526 /* XXX SYSC register handling does not belong in the clock framework */
omap1_clk_enable_uart_functional_16xx(struct clk * clk)527 static int omap1_clk_enable_uart_functional_16xx(struct clk *clk)
528 {
529 int ret;
530 struct uart_clk *uclk;
531
532 ret = omap1_clk_enable_generic(clk);
533 if (ret == 0) {
534 /* Set smart idle acknowledgement mode */
535 uclk = (struct uart_clk *)clk;
536 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
537 uclk->sysc_addr);
538 }
539
540 return ret;
541 }
542
543 /* XXX SYSC register handling does not belong in the clock framework */
omap1_clk_disable_uart_functional_16xx(struct clk * clk)544 static void omap1_clk_disable_uart_functional_16xx(struct clk *clk)
545 {
546 struct uart_clk *uclk;
547
548 /* Set force idle acknowledgement mode */
549 uclk = (struct uart_clk *)clk;
550 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
551
552 omap1_clk_disable_generic(clk);
553 }
554
555 /* XXX SYSC register handling does not belong in the clock framework */
556 const struct clkops clkops_uart_16xx = {
557 .enable = omap1_clk_enable_uart_functional_16xx,
558 .disable = omap1_clk_disable_uart_functional_16xx,
559 };
560
omap1_clk_round_rate(struct clk * clk,unsigned long rate)561 long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
562 {
563 if (clk->round_rate != NULL)
564 return clk->round_rate(clk, rate);
565
566 return clk->rate;
567 }
568
omap1_clk_set_rate(struct clk * clk,unsigned long rate)569 int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
570 {
571 int ret = -EINVAL;
572
573 if (clk->set_rate)
574 ret = clk->set_rate(clk, rate);
575 return ret;
576 }
577
578 /*
579 * Omap1 clock reset and init functions
580 */
581
582 #ifdef CONFIG_OMAP_RESET_CLOCKS
583
omap1_clk_disable_unused(struct clk * clk)584 void omap1_clk_disable_unused(struct clk *clk)
585 {
586 __u32 regval32;
587
588 /* Clocks in the DSP domain need api_ck. Just assume bootloader
589 * has not enabled any DSP clocks */
590 if (clk->enable_reg == DSP_IDLECT2) {
591 printk(KERN_INFO "Skipping reset check for DSP domain "
592 "clock \"%s\"\n", clk->name);
593 return;
594 }
595
596 /* Is the clock already disabled? */
597 if (clk->flags & ENABLE_REG_32BIT)
598 regval32 = __raw_readl(clk->enable_reg);
599 else
600 regval32 = __raw_readw(clk->enable_reg);
601
602 if ((regval32 & (1 << clk->enable_bit)) == 0)
603 return;
604
605 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
606 clk->ops->disable(clk);
607 printk(" done\n");
608 }
609
610 #endif
611