1 /*
2 * Copyright © 2008,2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "i915_drm.h"
32 #include "i915_drv.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/dma_remapping.h>
36
37 struct change_domains {
38 uint32_t invalidate_domains;
39 uint32_t flush_domains;
40 uint32_t flush_rings;
41 uint32_t flips;
42 };
43
44 /*
45 * Set the next domain for the specified object. This
46 * may not actually perform the necessary flushing/invaliding though,
47 * as that may want to be batched with other set_domain operations
48 *
49 * This is (we hope) the only really tricky part of gem. The goal
50 * is fairly simple -- track which caches hold bits of the object
51 * and make sure they remain coherent. A few concrete examples may
52 * help to explain how it works. For shorthand, we use the notation
53 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
54 * a pair of read and write domain masks.
55 *
56 * Case 1: the batch buffer
57 *
58 * 1. Allocated
59 * 2. Written by CPU
60 * 3. Mapped to GTT
61 * 4. Read by GPU
62 * 5. Unmapped from GTT
63 * 6. Freed
64 *
65 * Let's take these a step at a time
66 *
67 * 1. Allocated
68 * Pages allocated from the kernel may still have
69 * cache contents, so we set them to (CPU, CPU) always.
70 * 2. Written by CPU (using pwrite)
71 * The pwrite function calls set_domain (CPU, CPU) and
72 * this function does nothing (as nothing changes)
73 * 3. Mapped by GTT
74 * This function asserts that the object is not
75 * currently in any GPU-based read or write domains
76 * 4. Read by GPU
77 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
78 * As write_domain is zero, this function adds in the
79 * current read domains (CPU+COMMAND, 0).
80 * flush_domains is set to CPU.
81 * invalidate_domains is set to COMMAND
82 * clflush is run to get data out of the CPU caches
83 * then i915_dev_set_domain calls i915_gem_flush to
84 * emit an MI_FLUSH and drm_agp_chipset_flush
85 * 5. Unmapped from GTT
86 * i915_gem_object_unbind calls set_domain (CPU, CPU)
87 * flush_domains and invalidate_domains end up both zero
88 * so no flushing/invalidating happens
89 * 6. Freed
90 * yay, done
91 *
92 * Case 2: The shared render buffer
93 *
94 * 1. Allocated
95 * 2. Mapped to GTT
96 * 3. Read/written by GPU
97 * 4. set_domain to (CPU,CPU)
98 * 5. Read/written by CPU
99 * 6. Read/written by GPU
100 *
101 * 1. Allocated
102 * Same as last example, (CPU, CPU)
103 * 2. Mapped to GTT
104 * Nothing changes (assertions find that it is not in the GPU)
105 * 3. Read/written by GPU
106 * execbuffer calls set_domain (RENDER, RENDER)
107 * flush_domains gets CPU
108 * invalidate_domains gets GPU
109 * clflush (obj)
110 * MI_FLUSH and drm_agp_chipset_flush
111 * 4. set_domain (CPU, CPU)
112 * flush_domains gets GPU
113 * invalidate_domains gets CPU
114 * wait_rendering (obj) to make sure all drawing is complete.
115 * This will include an MI_FLUSH to get the data from GPU
116 * to memory
117 * clflush (obj) to invalidate the CPU cache
118 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
119 * 5. Read/written by CPU
120 * cache lines are loaded and dirtied
121 * 6. Read written by GPU
122 * Same as last GPU access
123 *
124 * Case 3: The constant buffer
125 *
126 * 1. Allocated
127 * 2. Written by CPU
128 * 3. Read by GPU
129 * 4. Updated (written) by CPU again
130 * 5. Read by GPU
131 *
132 * 1. Allocated
133 * (CPU, CPU)
134 * 2. Written by CPU
135 * (CPU, CPU)
136 * 3. Read by GPU
137 * (CPU+RENDER, 0)
138 * flush_domains = CPU
139 * invalidate_domains = RENDER
140 * clflush (obj)
141 * MI_FLUSH
142 * drm_agp_chipset_flush
143 * 4. Updated (written) by CPU again
144 * (CPU, CPU)
145 * flush_domains = 0 (no previous write domain)
146 * invalidate_domains = 0 (no new read domains)
147 * 5. Read by GPU
148 * (CPU+RENDER, 0)
149 * flush_domains = CPU
150 * invalidate_domains = RENDER
151 * clflush (obj)
152 * MI_FLUSH
153 * drm_agp_chipset_flush
154 */
155 static void
i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object * obj,struct intel_ring_buffer * ring,struct change_domains * cd)156 i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj,
157 struct intel_ring_buffer *ring,
158 struct change_domains *cd)
159 {
160 uint32_t invalidate_domains = 0, flush_domains = 0;
161
162 /*
163 * If the object isn't moving to a new write domain,
164 * let the object stay in multiple read domains
165 */
166 if (obj->base.pending_write_domain == 0)
167 obj->base.pending_read_domains |= obj->base.read_domains;
168
169 /*
170 * Flush the current write domain if
171 * the new read domains don't match. Invalidate
172 * any read domains which differ from the old
173 * write domain
174 */
175 if (obj->base.write_domain &&
176 (((obj->base.write_domain != obj->base.pending_read_domains ||
177 obj->ring != ring)) ||
178 (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) {
179 flush_domains |= obj->base.write_domain;
180 invalidate_domains |=
181 obj->base.pending_read_domains & ~obj->base.write_domain;
182 }
183 /*
184 * Invalidate any read caches which may have
185 * stale data. That is, any new read domains.
186 */
187 invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains;
188 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
189 i915_gem_clflush_object(obj);
190
191 if (obj->base.pending_write_domain)
192 cd->flips |= atomic_read(&obj->pending_flip);
193
194 /* The actual obj->write_domain will be updated with
195 * pending_write_domain after we emit the accumulated flush for all
196 * of our domain changes in execbuffers (which clears objects'
197 * write_domains). So if we have a current write domain that we
198 * aren't changing, set pending_write_domain to that.
199 */
200 if (flush_domains == 0 && obj->base.pending_write_domain == 0)
201 obj->base.pending_write_domain = obj->base.write_domain;
202
203 cd->invalidate_domains |= invalidate_domains;
204 cd->flush_domains |= flush_domains;
205 if (flush_domains & I915_GEM_GPU_DOMAINS)
206 cd->flush_rings |= intel_ring_flag(obj->ring);
207 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
208 cd->flush_rings |= intel_ring_flag(ring);
209 }
210
211 struct eb_objects {
212 int and;
213 struct hlist_head buckets[0];
214 };
215
216 static struct eb_objects *
eb_create(int size)217 eb_create(int size)
218 {
219 struct eb_objects *eb;
220 int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
221 while (count > size)
222 count >>= 1;
223 eb = kzalloc(count*sizeof(struct hlist_head) +
224 sizeof(struct eb_objects),
225 GFP_KERNEL);
226 if (eb == NULL)
227 return eb;
228
229 eb->and = count - 1;
230 return eb;
231 }
232
233 static void
eb_reset(struct eb_objects * eb)234 eb_reset(struct eb_objects *eb)
235 {
236 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
237 }
238
239 static void
eb_add_object(struct eb_objects * eb,struct drm_i915_gem_object * obj)240 eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
241 {
242 hlist_add_head(&obj->exec_node,
243 &eb->buckets[obj->exec_handle & eb->and]);
244 }
245
246 static struct drm_i915_gem_object *
eb_get_object(struct eb_objects * eb,unsigned long handle)247 eb_get_object(struct eb_objects *eb, unsigned long handle)
248 {
249 struct hlist_head *head;
250 struct hlist_node *node;
251 struct drm_i915_gem_object *obj;
252
253 head = &eb->buckets[handle & eb->and];
254 hlist_for_each(node, head) {
255 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
256 if (obj->exec_handle == handle)
257 return obj;
258 }
259
260 return NULL;
261 }
262
263 static void
eb_destroy(struct eb_objects * eb)264 eb_destroy(struct eb_objects *eb)
265 {
266 kfree(eb);
267 }
268
269 static int
i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object * obj,struct eb_objects * eb,struct drm_i915_gem_relocation_entry * reloc)270 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
271 struct eb_objects *eb,
272 struct drm_i915_gem_relocation_entry *reloc)
273 {
274 struct drm_device *dev = obj->base.dev;
275 struct drm_gem_object *target_obj;
276 uint32_t target_offset;
277 int ret = -EINVAL;
278
279 /* we've already hold a reference to all valid objects */
280 target_obj = &eb_get_object(eb, reloc->target_handle)->base;
281 if (unlikely(target_obj == NULL))
282 return -ENOENT;
283
284 target_offset = to_intel_bo(target_obj)->gtt_offset;
285
286 /* The target buffer should have appeared before us in the
287 * exec_object list, so it should have a GTT space bound by now.
288 */
289 if (unlikely(target_offset == 0)) {
290 DRM_DEBUG("No GTT space found for object %d\n",
291 reloc->target_handle);
292 return ret;
293 }
294
295 /* Validate that the target is in a valid r/w GPU domain */
296 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
297 DRM_DEBUG("reloc with multiple write domains: "
298 "obj %p target %d offset %d "
299 "read %08x write %08x",
300 obj, reloc->target_handle,
301 (int) reloc->offset,
302 reloc->read_domains,
303 reloc->write_domain);
304 return ret;
305 }
306 if (unlikely((reloc->write_domain | reloc->read_domains)
307 & ~I915_GEM_GPU_DOMAINS)) {
308 DRM_DEBUG("reloc with read/write non-GPU domains: "
309 "obj %p target %d offset %d "
310 "read %08x write %08x",
311 obj, reloc->target_handle,
312 (int) reloc->offset,
313 reloc->read_domains,
314 reloc->write_domain);
315 return ret;
316 }
317 if (unlikely(reloc->write_domain && target_obj->pending_write_domain &&
318 reloc->write_domain != target_obj->pending_write_domain)) {
319 DRM_DEBUG("Write domain conflict: "
320 "obj %p target %d offset %d "
321 "new %08x old %08x\n",
322 obj, reloc->target_handle,
323 (int) reloc->offset,
324 reloc->write_domain,
325 target_obj->pending_write_domain);
326 return ret;
327 }
328
329 target_obj->pending_read_domains |= reloc->read_domains;
330 target_obj->pending_write_domain |= reloc->write_domain;
331
332 /* If the relocation already has the right value in it, no
333 * more work needs to be done.
334 */
335 if (target_offset == reloc->presumed_offset)
336 return 0;
337
338 /* Check that the relocation address is valid... */
339 if (unlikely(reloc->offset > obj->base.size - 4)) {
340 DRM_DEBUG("Relocation beyond object bounds: "
341 "obj %p target %d offset %d size %d.\n",
342 obj, reloc->target_handle,
343 (int) reloc->offset,
344 (int) obj->base.size);
345 return ret;
346 }
347 if (unlikely(reloc->offset & 3)) {
348 DRM_DEBUG("Relocation not 4-byte aligned: "
349 "obj %p target %d offset %d.\n",
350 obj, reloc->target_handle,
351 (int) reloc->offset);
352 return ret;
353 }
354
355 reloc->delta += target_offset;
356 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
357 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
358 char *vaddr;
359
360 vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]);
361 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
362 kunmap_atomic(vaddr);
363 } else {
364 struct drm_i915_private *dev_priv = dev->dev_private;
365 uint32_t __iomem *reloc_entry;
366 void __iomem *reloc_page;
367
368 /* We can't wait for rendering with pagefaults disabled */
369 if (obj->active && in_atomic())
370 return -EFAULT;
371
372 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
373 if (ret)
374 return ret;
375
376 /* Map the page containing the relocation we're going to perform. */
377 reloc->offset += obj->gtt_offset;
378 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
379 reloc->offset & PAGE_MASK);
380 reloc_entry = (uint32_t __iomem *)
381 (reloc_page + (reloc->offset & ~PAGE_MASK));
382 iowrite32(reloc->delta, reloc_entry);
383 io_mapping_unmap_atomic(reloc_page);
384 }
385
386 /* and update the user's relocation entry */
387 reloc->presumed_offset = target_offset;
388
389 return 0;
390 }
391
392 static int
i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object * obj,struct eb_objects * eb)393 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
394 struct eb_objects *eb)
395 {
396 struct drm_i915_gem_relocation_entry __user *user_relocs;
397 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
398 int i, ret;
399
400 user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
401 for (i = 0; i < entry->relocation_count; i++) {
402 struct drm_i915_gem_relocation_entry reloc;
403
404 if (__copy_from_user_inatomic(&reloc,
405 user_relocs+i,
406 sizeof(reloc)))
407 return -EFAULT;
408
409 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &reloc);
410 if (ret)
411 return ret;
412
413 if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset,
414 &reloc.presumed_offset,
415 sizeof(reloc.presumed_offset)))
416 return -EFAULT;
417 }
418
419 return 0;
420 }
421
422 static int
i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object * obj,struct eb_objects * eb,struct drm_i915_gem_relocation_entry * relocs)423 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
424 struct eb_objects *eb,
425 struct drm_i915_gem_relocation_entry *relocs)
426 {
427 const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
428 int i, ret;
429
430 for (i = 0; i < entry->relocation_count; i++) {
431 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
432 if (ret)
433 return ret;
434 }
435
436 return 0;
437 }
438
439 static int
i915_gem_execbuffer_relocate(struct drm_device * dev,struct eb_objects * eb,struct list_head * objects)440 i915_gem_execbuffer_relocate(struct drm_device *dev,
441 struct eb_objects *eb,
442 struct list_head *objects)
443 {
444 struct drm_i915_gem_object *obj;
445 int ret = 0;
446
447 /* This is the fast path and we cannot handle a pagefault whilst
448 * holding the struct mutex lest the user pass in the relocations
449 * contained within a mmaped bo. For in such a case we, the page
450 * fault handler would call i915_gem_fault() and we would try to
451 * acquire the struct mutex again. Obviously this is bad and so
452 * lockdep complains vehemently.
453 */
454 pagefault_disable();
455 list_for_each_entry(obj, objects, exec_list) {
456 ret = i915_gem_execbuffer_relocate_object(obj, eb);
457 if (ret)
458 break;
459 }
460 pagefault_enable();
461
462 return ret;
463 }
464
465 #define __EXEC_OBJECT_HAS_FENCE (1<<31)
466
467 static int
pin_and_fence_object(struct drm_i915_gem_object * obj,struct intel_ring_buffer * ring)468 pin_and_fence_object(struct drm_i915_gem_object *obj,
469 struct intel_ring_buffer *ring)
470 {
471 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
472 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
473 bool need_fence, need_mappable;
474 int ret;
475
476 need_fence =
477 has_fenced_gpu_access &&
478 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
479 obj->tiling_mode != I915_TILING_NONE;
480 need_mappable =
481 entry->relocation_count ? true : need_fence;
482
483 ret = i915_gem_object_pin(obj, entry->alignment, need_mappable);
484 if (ret)
485 return ret;
486
487 if (has_fenced_gpu_access) {
488 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
489 if (obj->tiling_mode) {
490 ret = i915_gem_object_get_fence(obj, ring);
491 if (ret)
492 goto err_unpin;
493
494 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
495 i915_gem_object_pin_fence(obj);
496 } else {
497 ret = i915_gem_object_put_fence(obj);
498 if (ret)
499 goto err_unpin;
500 }
501 obj->pending_fenced_gpu_access = true;
502 }
503 }
504
505 entry->offset = obj->gtt_offset;
506 return 0;
507
508 err_unpin:
509 i915_gem_object_unpin(obj);
510 return ret;
511 }
512
513 static int
i915_gem_execbuffer_reserve(struct intel_ring_buffer * ring,struct drm_file * file,struct list_head * objects)514 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
515 struct drm_file *file,
516 struct list_head *objects)
517 {
518 drm_i915_private_t *dev_priv = ring->dev->dev_private;
519 struct drm_i915_gem_object *obj;
520 int ret, retry;
521 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
522 struct list_head ordered_objects;
523
524 INIT_LIST_HEAD(&ordered_objects);
525 while (!list_empty(objects)) {
526 struct drm_i915_gem_exec_object2 *entry;
527 bool need_fence, need_mappable;
528
529 obj = list_first_entry(objects,
530 struct drm_i915_gem_object,
531 exec_list);
532 entry = obj->exec_entry;
533
534 need_fence =
535 has_fenced_gpu_access &&
536 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
537 obj->tiling_mode != I915_TILING_NONE;
538 need_mappable =
539 entry->relocation_count ? true : need_fence;
540
541 if (need_mappable)
542 list_move(&obj->exec_list, &ordered_objects);
543 else
544 list_move_tail(&obj->exec_list, &ordered_objects);
545
546 obj->base.pending_read_domains = 0;
547 obj->base.pending_write_domain = 0;
548 }
549 list_splice(&ordered_objects, objects);
550
551 /* Attempt to pin all of the buffers into the GTT.
552 * This is done in 3 phases:
553 *
554 * 1a. Unbind all objects that do not match the GTT constraints for
555 * the execbuffer (fenceable, mappable, alignment etc).
556 * 1b. Increment pin count for already bound objects.
557 * 2. Bind new objects.
558 * 3. Decrement pin count.
559 *
560 * This avoid unnecessary unbinding of later objects in order to makr
561 * room for the earlier objects *unless* we need to defragment.
562 */
563 retry = 0;
564 do {
565 ret = 0;
566
567 /* Unbind any ill-fitting objects or pin. */
568 list_for_each_entry(obj, objects, exec_list) {
569 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
570 bool need_fence, need_mappable;
571
572 if (!obj->gtt_space)
573 continue;
574
575 need_fence =
576 has_fenced_gpu_access &&
577 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
578 obj->tiling_mode != I915_TILING_NONE;
579 need_mappable =
580 entry->relocation_count ? true : need_fence;
581
582 if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
583 (need_mappable && !obj->map_and_fenceable))
584 ret = i915_gem_object_unbind(obj);
585 else
586 ret = pin_and_fence_object(obj, ring);
587 if (ret)
588 goto err;
589 }
590
591 /* Bind fresh objects */
592 list_for_each_entry(obj, objects, exec_list) {
593 if (obj->gtt_space)
594 continue;
595
596 ret = pin_and_fence_object(obj, ring);
597 if (ret) {
598 int ret_ignore;
599
600 /* This can potentially raise a harmless
601 * -EINVAL if we failed to bind in the above
602 * call. It cannot raise -EINTR since we know
603 * that the bo is freshly bound and so will
604 * not need to be flushed or waited upon.
605 */
606 ret_ignore = i915_gem_object_unbind(obj);
607 (void)ret_ignore;
608 WARN_ON(obj->gtt_space);
609 break;
610 }
611 }
612
613 /* Decrement pin count for bound objects */
614 list_for_each_entry(obj, objects, exec_list) {
615 struct drm_i915_gem_exec_object2 *entry;
616
617 if (!obj->gtt_space)
618 continue;
619
620 entry = obj->exec_entry;
621 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
622 i915_gem_object_unpin_fence(obj);
623 entry->flags &= ~__EXEC_OBJECT_HAS_FENCE;
624 }
625
626 i915_gem_object_unpin(obj);
627
628 /* ... and ensure ppgtt mapping exist if needed. */
629 if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
630 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
631 obj, obj->cache_level);
632
633 obj->has_aliasing_ppgtt_mapping = 1;
634 }
635 }
636
637 if (ret != -ENOSPC || retry > 1)
638 return ret;
639
640 /* First attempt, just clear anything that is purgeable.
641 * Second attempt, clear the entire GTT.
642 */
643 ret = i915_gem_evict_everything(ring->dev, retry == 0);
644 if (ret)
645 return ret;
646
647 retry++;
648 } while (1);
649
650 err:
651 list_for_each_entry_continue_reverse(obj, objects, exec_list) {
652 struct drm_i915_gem_exec_object2 *entry;
653
654 if (!obj->gtt_space)
655 continue;
656
657 entry = obj->exec_entry;
658 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
659 i915_gem_object_unpin_fence(obj);
660 entry->flags &= ~__EXEC_OBJECT_HAS_FENCE;
661 }
662
663 i915_gem_object_unpin(obj);
664 }
665
666 return ret;
667 }
668
669 static int
i915_gem_execbuffer_relocate_slow(struct drm_device * dev,struct drm_file * file,struct intel_ring_buffer * ring,struct list_head * objects,struct eb_objects * eb,struct drm_i915_gem_exec_object2 * exec,int count)670 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
671 struct drm_file *file,
672 struct intel_ring_buffer *ring,
673 struct list_head *objects,
674 struct eb_objects *eb,
675 struct drm_i915_gem_exec_object2 *exec,
676 int count)
677 {
678 struct drm_i915_gem_relocation_entry *reloc;
679 struct drm_i915_gem_object *obj;
680 int *reloc_offset;
681 int i, total, ret;
682
683 /* We may process another execbuffer during the unlock... */
684 while (!list_empty(objects)) {
685 obj = list_first_entry(objects,
686 struct drm_i915_gem_object,
687 exec_list);
688 list_del_init(&obj->exec_list);
689 drm_gem_object_unreference(&obj->base);
690 }
691
692 mutex_unlock(&dev->struct_mutex);
693
694 total = 0;
695 for (i = 0; i < count; i++)
696 total += exec[i].relocation_count;
697
698 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
699 reloc = drm_malloc_ab(total, sizeof(*reloc));
700 if (reloc == NULL || reloc_offset == NULL) {
701 drm_free_large(reloc);
702 drm_free_large(reloc_offset);
703 mutex_lock(&dev->struct_mutex);
704 return -ENOMEM;
705 }
706
707 total = 0;
708 for (i = 0; i < count; i++) {
709 struct drm_i915_gem_relocation_entry __user *user_relocs;
710 u64 invalid_offset = (u64)-1;
711 int j;
712
713 user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
714
715 if (copy_from_user(reloc+total, user_relocs,
716 exec[i].relocation_count * sizeof(*reloc))) {
717 ret = -EFAULT;
718 mutex_lock(&dev->struct_mutex);
719 goto err;
720 }
721
722 /* As we do not update the known relocation offsets after
723 * relocating (due to the complexities in lock handling),
724 * we need to mark them as invalid now so that we force the
725 * relocation processing next time. Just in case the target
726 * object is evicted and then rebound into its old
727 * presumed_offset before the next execbuffer - if that
728 * happened we would make the mistake of assuming that the
729 * relocations were valid.
730 */
731 for (j = 0; j < exec[i].relocation_count; j++) {
732 if (copy_to_user(&user_relocs[j].presumed_offset,
733 &invalid_offset,
734 sizeof(invalid_offset))) {
735 ret = -EFAULT;
736 mutex_lock(&dev->struct_mutex);
737 goto err;
738 }
739 }
740
741 reloc_offset[i] = total;
742 total += exec[i].relocation_count;
743 }
744
745 ret = i915_mutex_lock_interruptible(dev);
746 if (ret) {
747 mutex_lock(&dev->struct_mutex);
748 goto err;
749 }
750
751 /* reacquire the objects */
752 eb_reset(eb);
753 for (i = 0; i < count; i++) {
754 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
755 exec[i].handle));
756 if (&obj->base == NULL) {
757 DRM_DEBUG("Invalid object handle %d at index %d\n",
758 exec[i].handle, i);
759 ret = -ENOENT;
760 goto err;
761 }
762
763 list_add_tail(&obj->exec_list, objects);
764 obj->exec_handle = exec[i].handle;
765 obj->exec_entry = &exec[i];
766 eb_add_object(eb, obj);
767 }
768
769 ret = i915_gem_execbuffer_reserve(ring, file, objects);
770 if (ret)
771 goto err;
772
773 list_for_each_entry(obj, objects, exec_list) {
774 int offset = obj->exec_entry - exec;
775 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
776 reloc + reloc_offset[offset]);
777 if (ret)
778 goto err;
779 }
780
781 /* Leave the user relocations as are, this is the painfully slow path,
782 * and we want to avoid the complication of dropping the lock whilst
783 * having buffers reserved in the aperture and so causing spurious
784 * ENOSPC for random operations.
785 */
786
787 err:
788 drm_free_large(reloc);
789 drm_free_large(reloc_offset);
790 return ret;
791 }
792
793 static int
i915_gem_execbuffer_flush(struct drm_device * dev,uint32_t invalidate_domains,uint32_t flush_domains,uint32_t flush_rings)794 i915_gem_execbuffer_flush(struct drm_device *dev,
795 uint32_t invalidate_domains,
796 uint32_t flush_domains,
797 uint32_t flush_rings)
798 {
799 drm_i915_private_t *dev_priv = dev->dev_private;
800 int i, ret;
801
802 if (flush_domains & I915_GEM_DOMAIN_CPU)
803 intel_gtt_chipset_flush();
804
805 if (flush_domains & I915_GEM_DOMAIN_GTT)
806 wmb();
807
808 if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
809 for (i = 0; i < I915_NUM_RINGS; i++)
810 if (flush_rings & (1 << i)) {
811 ret = i915_gem_flush_ring(&dev_priv->ring[i],
812 invalidate_domains,
813 flush_domains);
814 if (ret)
815 return ret;
816 }
817 }
818
819 return 0;
820 }
821
822 static bool
intel_enable_semaphores(struct drm_device * dev)823 intel_enable_semaphores(struct drm_device *dev)
824 {
825 if (INTEL_INFO(dev)->gen < 6)
826 return 0;
827
828 if (i915_semaphores >= 0)
829 return i915_semaphores;
830
831 /* Disable semaphores on SNB */
832 if (INTEL_INFO(dev)->gen == 6)
833 return 0;
834
835 return 1;
836 }
837
838 static int
i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object * obj,struct intel_ring_buffer * to)839 i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
840 struct intel_ring_buffer *to)
841 {
842 struct intel_ring_buffer *from = obj->ring;
843 u32 seqno;
844 int ret, idx;
845
846 if (from == NULL || to == from)
847 return 0;
848
849 /* XXX gpu semaphores are implicated in various hard hangs on SNB */
850 if (!intel_enable_semaphores(obj->base.dev))
851 return i915_gem_object_wait_rendering(obj);
852
853 idx = intel_ring_sync_index(from, to);
854
855 seqno = obj->last_rendering_seqno;
856 if (seqno <= from->sync_seqno[idx])
857 return 0;
858
859 if (seqno == from->outstanding_lazy_request) {
860 struct drm_i915_gem_request *request;
861
862 request = kzalloc(sizeof(*request), GFP_KERNEL);
863 if (request == NULL)
864 return -ENOMEM;
865
866 ret = i915_add_request(from, NULL, request);
867 if (ret) {
868 kfree(request);
869 return ret;
870 }
871
872 seqno = request->seqno;
873 }
874
875 from->sync_seqno[idx] = seqno;
876
877 return to->sync_to(to, from, seqno - 1);
878 }
879
880 static int
i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer * ring,u32 flips)881 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips)
882 {
883 u32 plane, flip_mask;
884 int ret;
885
886 /* Check for any pending flips. As we only maintain a flip queue depth
887 * of 1, we can simply insert a WAIT for the next display flip prior
888 * to executing the batch and avoid stalling the CPU.
889 */
890
891 for (plane = 0; flips >> plane; plane++) {
892 if (((flips >> plane) & 1) == 0)
893 continue;
894
895 if (plane)
896 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
897 else
898 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
899
900 ret = intel_ring_begin(ring, 2);
901 if (ret)
902 return ret;
903
904 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
905 intel_ring_emit(ring, MI_NOOP);
906 intel_ring_advance(ring);
907 }
908
909 return 0;
910 }
911
912
913 static int
i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer * ring,struct list_head * objects)914 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
915 struct list_head *objects)
916 {
917 struct drm_i915_gem_object *obj;
918 struct change_domains cd;
919 int ret;
920
921 memset(&cd, 0, sizeof(cd));
922 list_for_each_entry(obj, objects, exec_list)
923 i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
924
925 if (cd.invalidate_domains | cd.flush_domains) {
926 ret = i915_gem_execbuffer_flush(ring->dev,
927 cd.invalidate_domains,
928 cd.flush_domains,
929 cd.flush_rings);
930 if (ret)
931 return ret;
932 }
933
934 if (cd.flips) {
935 ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips);
936 if (ret)
937 return ret;
938 }
939
940 list_for_each_entry(obj, objects, exec_list) {
941 ret = i915_gem_execbuffer_sync_rings(obj, ring);
942 if (ret)
943 return ret;
944 }
945
946 return 0;
947 }
948
949 static bool
i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 * exec)950 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
951 {
952 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
953 }
954
955 static int
validate_exec_list(struct drm_i915_gem_exec_object2 * exec,int count)956 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
957 int count)
958 {
959 int i;
960 int relocs_total = 0;
961 int relocs_max = INT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
962
963 for (i = 0; i < count; i++) {
964 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
965 int length; /* limited by fault_in_pages_readable() */
966
967 /* First check for malicious input causing overflow in
968 * the worst case where we need to allocate the entire
969 * relocation tree as a single array.
970 */
971 if (exec[i].relocation_count > relocs_max - relocs_total)
972 return -EINVAL;
973 relocs_total += exec[i].relocation_count;
974
975 length = exec[i].relocation_count *
976 sizeof(struct drm_i915_gem_relocation_entry);
977 if (!access_ok(VERIFY_READ, ptr, length))
978 return -EFAULT;
979
980 /* we may also need to update the presumed offsets */
981 if (!access_ok(VERIFY_WRITE, ptr, length))
982 return -EFAULT;
983
984 if (fault_in_pages_readable(ptr, length))
985 return -EFAULT;
986 }
987
988 return 0;
989 }
990
991 static void
i915_gem_execbuffer_move_to_active(struct list_head * objects,struct intel_ring_buffer * ring,u32 seqno)992 i915_gem_execbuffer_move_to_active(struct list_head *objects,
993 struct intel_ring_buffer *ring,
994 u32 seqno)
995 {
996 struct drm_i915_gem_object *obj;
997
998 list_for_each_entry(obj, objects, exec_list) {
999 u32 old_read = obj->base.read_domains;
1000 u32 old_write = obj->base.write_domain;
1001
1002
1003 obj->base.read_domains = obj->base.pending_read_domains;
1004 obj->base.write_domain = obj->base.pending_write_domain;
1005 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
1006
1007 i915_gem_object_move_to_active(obj, ring, seqno);
1008 if (obj->base.write_domain) {
1009 obj->dirty = 1;
1010 obj->pending_gpu_write = true;
1011 list_move_tail(&obj->gpu_write_list,
1012 &ring->gpu_write_list);
1013 intel_mark_busy(ring->dev, obj);
1014 }
1015
1016 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1017 }
1018 }
1019
1020 static void
i915_gem_execbuffer_retire_commands(struct drm_device * dev,struct drm_file * file,struct intel_ring_buffer * ring)1021 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
1022 struct drm_file *file,
1023 struct intel_ring_buffer *ring)
1024 {
1025 struct drm_i915_gem_request *request;
1026 u32 invalidate;
1027
1028 /*
1029 * Ensure that the commands in the batch buffer are
1030 * finished before the interrupt fires.
1031 *
1032 * The sampler always gets flushed on i965 (sigh).
1033 */
1034 invalidate = I915_GEM_DOMAIN_COMMAND;
1035 if (INTEL_INFO(dev)->gen >= 4)
1036 invalidate |= I915_GEM_DOMAIN_SAMPLER;
1037 if (ring->flush(ring, invalidate, 0)) {
1038 i915_gem_next_request_seqno(ring);
1039 return;
1040 }
1041
1042 /* Add a breadcrumb for the completion of the batch buffer */
1043 request = kzalloc(sizeof(*request), GFP_KERNEL);
1044 if (request == NULL || i915_add_request(ring, file, request)) {
1045 i915_gem_next_request_seqno(ring);
1046 kfree(request);
1047 }
1048 }
1049
1050 static int
i915_reset_gen7_sol_offsets(struct drm_device * dev,struct intel_ring_buffer * ring)1051 i915_reset_gen7_sol_offsets(struct drm_device *dev,
1052 struct intel_ring_buffer *ring)
1053 {
1054 drm_i915_private_t *dev_priv = dev->dev_private;
1055 int ret, i;
1056
1057 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
1058 return 0;
1059
1060 ret = intel_ring_begin(ring, 4 * 3);
1061 if (ret)
1062 return ret;
1063
1064 for (i = 0; i < 4; i++) {
1065 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1066 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
1067 intel_ring_emit(ring, 0);
1068 }
1069
1070 intel_ring_advance(ring);
1071
1072 return 0;
1073 }
1074
1075 static int
i915_gem_do_execbuffer(struct drm_device * dev,void * data,struct drm_file * file,struct drm_i915_gem_execbuffer2 * args,struct drm_i915_gem_exec_object2 * exec)1076 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1077 struct drm_file *file,
1078 struct drm_i915_gem_execbuffer2 *args,
1079 struct drm_i915_gem_exec_object2 *exec)
1080 {
1081 drm_i915_private_t *dev_priv = dev->dev_private;
1082 struct list_head objects;
1083 struct eb_objects *eb;
1084 struct drm_i915_gem_object *batch_obj;
1085 struct drm_clip_rect *cliprects = NULL;
1086 struct intel_ring_buffer *ring;
1087 u32 exec_start, exec_len;
1088 u32 seqno;
1089 u32 mask;
1090 int ret, mode, i;
1091
1092 if (!i915_gem_check_execbuffer(args)) {
1093 DRM_DEBUG("execbuf with invalid offset/length\n");
1094 return -EINVAL;
1095 }
1096
1097 ret = validate_exec_list(exec, args->buffer_count);
1098 if (ret)
1099 return ret;
1100
1101 switch (args->flags & I915_EXEC_RING_MASK) {
1102 case I915_EXEC_DEFAULT:
1103 case I915_EXEC_RENDER:
1104 ring = &dev_priv->ring[RCS];
1105 break;
1106 case I915_EXEC_BSD:
1107 if (!HAS_BSD(dev)) {
1108 DRM_DEBUG("execbuf with invalid ring (BSD)\n");
1109 return -EINVAL;
1110 }
1111 ring = &dev_priv->ring[VCS];
1112 break;
1113 case I915_EXEC_BLT:
1114 if (!HAS_BLT(dev)) {
1115 DRM_DEBUG("execbuf with invalid ring (BLT)\n");
1116 return -EINVAL;
1117 }
1118 ring = &dev_priv->ring[BCS];
1119 break;
1120 default:
1121 DRM_DEBUG("execbuf with unknown ring: %d\n",
1122 (int)(args->flags & I915_EXEC_RING_MASK));
1123 return -EINVAL;
1124 }
1125
1126 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1127 mask = I915_EXEC_CONSTANTS_MASK;
1128 switch (mode) {
1129 case I915_EXEC_CONSTANTS_REL_GENERAL:
1130 case I915_EXEC_CONSTANTS_ABSOLUTE:
1131 case I915_EXEC_CONSTANTS_REL_SURFACE:
1132 if (ring == &dev_priv->ring[RCS] &&
1133 mode != dev_priv->relative_constants_mode) {
1134 if (INTEL_INFO(dev)->gen < 4)
1135 return -EINVAL;
1136
1137 if (INTEL_INFO(dev)->gen > 5 &&
1138 mode == I915_EXEC_CONSTANTS_REL_SURFACE)
1139 return -EINVAL;
1140
1141 /* The HW changed the meaning on this bit on gen6 */
1142 if (INTEL_INFO(dev)->gen >= 6)
1143 mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1144 }
1145 break;
1146 default:
1147 DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
1148 return -EINVAL;
1149 }
1150
1151 if (args->buffer_count < 1) {
1152 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1153 return -EINVAL;
1154 }
1155
1156 if (args->num_cliprects != 0) {
1157 if (ring != &dev_priv->ring[RCS]) {
1158 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1159 return -EINVAL;
1160 }
1161
1162 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
1163 DRM_DEBUG("execbuf with %u cliprects\n",
1164 args->num_cliprects);
1165 return -EINVAL;
1166 }
1167 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
1168 GFP_KERNEL);
1169 if (cliprects == NULL) {
1170 ret = -ENOMEM;
1171 goto pre_mutex_err;
1172 }
1173
1174 if (copy_from_user(cliprects,
1175 (struct drm_clip_rect __user *)(uintptr_t)
1176 args->cliprects_ptr,
1177 sizeof(*cliprects)*args->num_cliprects)) {
1178 ret = -EFAULT;
1179 goto pre_mutex_err;
1180 }
1181 }
1182
1183 ret = i915_mutex_lock_interruptible(dev);
1184 if (ret)
1185 goto pre_mutex_err;
1186
1187 if (dev_priv->mm.suspended) {
1188 mutex_unlock(&dev->struct_mutex);
1189 ret = -EBUSY;
1190 goto pre_mutex_err;
1191 }
1192
1193 eb = eb_create(args->buffer_count);
1194 if (eb == NULL) {
1195 mutex_unlock(&dev->struct_mutex);
1196 ret = -ENOMEM;
1197 goto pre_mutex_err;
1198 }
1199
1200 /* Look up object handles */
1201 INIT_LIST_HEAD(&objects);
1202 for (i = 0; i < args->buffer_count; i++) {
1203 struct drm_i915_gem_object *obj;
1204
1205 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
1206 exec[i].handle));
1207 if (&obj->base == NULL) {
1208 DRM_DEBUG("Invalid object handle %d at index %d\n",
1209 exec[i].handle, i);
1210 /* prevent error path from reading uninitialized data */
1211 ret = -ENOENT;
1212 goto err;
1213 }
1214
1215 if (!list_empty(&obj->exec_list)) {
1216 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
1217 obj, exec[i].handle, i);
1218 ret = -EINVAL;
1219 goto err;
1220 }
1221
1222 list_add_tail(&obj->exec_list, &objects);
1223 obj->exec_handle = exec[i].handle;
1224 obj->exec_entry = &exec[i];
1225 eb_add_object(eb, obj);
1226 }
1227
1228 /* take note of the batch buffer before we might reorder the lists */
1229 batch_obj = list_entry(objects.prev,
1230 struct drm_i915_gem_object,
1231 exec_list);
1232
1233 /* Move the objects en-masse into the GTT, evicting if necessary. */
1234 ret = i915_gem_execbuffer_reserve(ring, file, &objects);
1235 if (ret)
1236 goto err;
1237
1238 /* The objects are in their final locations, apply the relocations. */
1239 ret = i915_gem_execbuffer_relocate(dev, eb, &objects);
1240 if (ret) {
1241 if (ret == -EFAULT) {
1242 ret = i915_gem_execbuffer_relocate_slow(dev, file, ring,
1243 &objects, eb,
1244 exec,
1245 args->buffer_count);
1246 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1247 }
1248 if (ret)
1249 goto err;
1250 }
1251
1252 /* Set the pending read domains for the batch buffer to COMMAND */
1253 if (batch_obj->base.pending_write_domain) {
1254 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1255 ret = -EINVAL;
1256 goto err;
1257 }
1258 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1259
1260 ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
1261 if (ret)
1262 goto err;
1263
1264 seqno = i915_gem_next_request_seqno(ring);
1265 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) {
1266 if (seqno < ring->sync_seqno[i]) {
1267 /* The GPU can not handle its semaphore value wrapping,
1268 * so every billion or so execbuffers, we need to stall
1269 * the GPU in order to reset the counters.
1270 */
1271 ret = i915_gpu_idle(dev, true);
1272 if (ret)
1273 goto err;
1274
1275 BUG_ON(ring->sync_seqno[i]);
1276 }
1277 }
1278
1279 if (ring == &dev_priv->ring[RCS] &&
1280 mode != dev_priv->relative_constants_mode) {
1281 ret = intel_ring_begin(ring, 4);
1282 if (ret)
1283 goto err;
1284
1285 intel_ring_emit(ring, MI_NOOP);
1286 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1287 intel_ring_emit(ring, INSTPM);
1288 intel_ring_emit(ring, mask << 16 | mode);
1289 intel_ring_advance(ring);
1290
1291 dev_priv->relative_constants_mode = mode;
1292 }
1293
1294 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1295 ret = i915_reset_gen7_sol_offsets(dev, ring);
1296 if (ret)
1297 goto err;
1298 }
1299
1300 trace_i915_gem_ring_dispatch(ring, seqno);
1301
1302 exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1303 exec_len = args->batch_len;
1304 if (cliprects) {
1305 for (i = 0; i < args->num_cliprects; i++) {
1306 ret = i915_emit_box(dev, &cliprects[i],
1307 args->DR1, args->DR4);
1308 if (ret)
1309 goto err;
1310
1311 ret = ring->dispatch_execbuffer(ring,
1312 exec_start, exec_len);
1313 if (ret)
1314 goto err;
1315 }
1316 } else {
1317 ret = ring->dispatch_execbuffer(ring, exec_start, exec_len);
1318 if (ret)
1319 goto err;
1320 }
1321
1322 i915_gem_execbuffer_move_to_active(&objects, ring, seqno);
1323 i915_gem_execbuffer_retire_commands(dev, file, ring);
1324
1325 err:
1326 eb_destroy(eb);
1327 while (!list_empty(&objects)) {
1328 struct drm_i915_gem_object *obj;
1329
1330 obj = list_first_entry(&objects,
1331 struct drm_i915_gem_object,
1332 exec_list);
1333 list_del_init(&obj->exec_list);
1334 drm_gem_object_unreference(&obj->base);
1335 }
1336
1337 mutex_unlock(&dev->struct_mutex);
1338
1339 pre_mutex_err:
1340 kfree(cliprects);
1341 return ret;
1342 }
1343
1344 /*
1345 * Legacy execbuffer just creates an exec2 list from the original exec object
1346 * list array and passes it to the real function.
1347 */
1348 int
i915_gem_execbuffer(struct drm_device * dev,void * data,struct drm_file * file)1349 i915_gem_execbuffer(struct drm_device *dev, void *data,
1350 struct drm_file *file)
1351 {
1352 struct drm_i915_gem_execbuffer *args = data;
1353 struct drm_i915_gem_execbuffer2 exec2;
1354 struct drm_i915_gem_exec_object *exec_list = NULL;
1355 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1356 int ret, i;
1357
1358 if (args->buffer_count < 1) {
1359 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1360 return -EINVAL;
1361 }
1362
1363 /* Copy in the exec list from userland */
1364 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1365 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1366 if (exec_list == NULL || exec2_list == NULL) {
1367 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1368 args->buffer_count);
1369 drm_free_large(exec_list);
1370 drm_free_large(exec2_list);
1371 return -ENOMEM;
1372 }
1373 ret = copy_from_user(exec_list,
1374 (struct drm_i915_relocation_entry __user *)
1375 (uintptr_t) args->buffers_ptr,
1376 sizeof(*exec_list) * args->buffer_count);
1377 if (ret != 0) {
1378 DRM_DEBUG("copy %d exec entries failed %d\n",
1379 args->buffer_count, ret);
1380 drm_free_large(exec_list);
1381 drm_free_large(exec2_list);
1382 return -EFAULT;
1383 }
1384
1385 for (i = 0; i < args->buffer_count; i++) {
1386 exec2_list[i].handle = exec_list[i].handle;
1387 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1388 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1389 exec2_list[i].alignment = exec_list[i].alignment;
1390 exec2_list[i].offset = exec_list[i].offset;
1391 if (INTEL_INFO(dev)->gen < 4)
1392 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1393 else
1394 exec2_list[i].flags = 0;
1395 }
1396
1397 exec2.buffers_ptr = args->buffers_ptr;
1398 exec2.buffer_count = args->buffer_count;
1399 exec2.batch_start_offset = args->batch_start_offset;
1400 exec2.batch_len = args->batch_len;
1401 exec2.DR1 = args->DR1;
1402 exec2.DR4 = args->DR4;
1403 exec2.num_cliprects = args->num_cliprects;
1404 exec2.cliprects_ptr = args->cliprects_ptr;
1405 exec2.flags = I915_EXEC_RENDER;
1406
1407 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1408 if (!ret) {
1409 /* Copy the new buffer offsets back to the user's exec list. */
1410 for (i = 0; i < args->buffer_count; i++)
1411 exec_list[i].offset = exec2_list[i].offset;
1412 /* ... and back out to userspace */
1413 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1414 (uintptr_t) args->buffers_ptr,
1415 exec_list,
1416 sizeof(*exec_list) * args->buffer_count);
1417 if (ret) {
1418 ret = -EFAULT;
1419 DRM_DEBUG("failed to copy %d exec entries "
1420 "back to user (%d)\n",
1421 args->buffer_count, ret);
1422 }
1423 }
1424
1425 drm_free_large(exec_list);
1426 drm_free_large(exec2_list);
1427 return ret;
1428 }
1429
1430 int
i915_gem_execbuffer2(struct drm_device * dev,void * data,struct drm_file * file)1431 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1432 struct drm_file *file)
1433 {
1434 struct drm_i915_gem_execbuffer2 *args = data;
1435 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1436 int ret;
1437
1438 if (args->buffer_count < 1 ||
1439 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1440 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1441 return -EINVAL;
1442 }
1443
1444 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1445 GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
1446 if (exec2_list == NULL)
1447 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1448 args->buffer_count);
1449 if (exec2_list == NULL) {
1450 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1451 args->buffer_count);
1452 return -ENOMEM;
1453 }
1454 ret = copy_from_user(exec2_list,
1455 (struct drm_i915_relocation_entry __user *)
1456 (uintptr_t) args->buffers_ptr,
1457 sizeof(*exec2_list) * args->buffer_count);
1458 if (ret != 0) {
1459 DRM_DEBUG("copy %d exec entries failed %d\n",
1460 args->buffer_count, ret);
1461 drm_free_large(exec2_list);
1462 return -EFAULT;
1463 }
1464
1465 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1466 if (!ret) {
1467 /* Copy the new buffer offsets back to the user's exec list. */
1468 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1469 (uintptr_t) args->buffers_ptr,
1470 exec2_list,
1471 sizeof(*exec2_list) * args->buffer_count);
1472 if (ret) {
1473 ret = -EFAULT;
1474 DRM_DEBUG("failed to copy %d exec entries "
1475 "back to user (%d)\n",
1476 args->buffer_count, ret);
1477 }
1478 }
1479
1480 drm_free_large(exec2_list);
1481 return ret;
1482 }
1483