1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
9 #include <linux/of_device.h>
10 #include <linux/of_mdio.h>
11 #include <linux/of_net.h>
12 #include <linux/of_address.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/regmap.h>
15 #include <linux/clk.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/if_vlan.h>
18 #include <linux/reset.h>
19 #include <linux/tcp.h>
20 #include <linux/interrupt.h>
21 #include <linux/pinctrl/devinfo.h>
22 #include <linux/phylink.h>
23 #include <linux/jhash.h>
24 #include <linux/bitfield.h>
25 #include <net/dsa.h>
26
27 #include "mtk_eth_soc.h"
28 #include "mtk_wed.h"
29
30 static int mtk_msg_level = -1;
31 module_param_named(msg_level, mtk_msg_level, int, 0);
32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
33
34 #define MTK_ETHTOOL_STAT(x) { #x, \
35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
36
37 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \
38 offsetof(struct mtk_hw_stats, xdp_stats.x) / \
39 sizeof(u64) }
40
41 static const struct mtk_reg_map mtk_reg_map = {
42 .tx_irq_mask = 0x1a1c,
43 .tx_irq_status = 0x1a18,
44 .pdma = {
45 .rx_ptr = 0x0900,
46 .rx_cnt_cfg = 0x0904,
47 .pcrx_ptr = 0x0908,
48 .glo_cfg = 0x0a04,
49 .rst_idx = 0x0a08,
50 .delay_irq = 0x0a0c,
51 .irq_status = 0x0a20,
52 .irq_mask = 0x0a28,
53 .int_grp = 0x0a50,
54 },
55 .qdma = {
56 .qtx_cfg = 0x1800,
57 .rx_ptr = 0x1900,
58 .rx_cnt_cfg = 0x1904,
59 .qcrx_ptr = 0x1908,
60 .glo_cfg = 0x1a04,
61 .rst_idx = 0x1a08,
62 .delay_irq = 0x1a0c,
63 .fc_th = 0x1a10,
64 .int_grp = 0x1a20,
65 .hred = 0x1a44,
66 .ctx_ptr = 0x1b00,
67 .dtx_ptr = 0x1b04,
68 .crx_ptr = 0x1b10,
69 .drx_ptr = 0x1b14,
70 .fq_head = 0x1b20,
71 .fq_tail = 0x1b24,
72 .fq_count = 0x1b28,
73 .fq_blen = 0x1b2c,
74 },
75 .gdm1_cnt = 0x2400,
76 .gdma_to_ppe = 0x4444,
77 .ppe_base = 0x0c00,
78 .wdma_base = {
79 [0] = 0x2800,
80 [1] = 0x2c00,
81 },
82 };
83
84 static const struct mtk_reg_map mt7628_reg_map = {
85 .tx_irq_mask = 0x0a28,
86 .tx_irq_status = 0x0a20,
87 .pdma = {
88 .rx_ptr = 0x0900,
89 .rx_cnt_cfg = 0x0904,
90 .pcrx_ptr = 0x0908,
91 .glo_cfg = 0x0a04,
92 .rst_idx = 0x0a08,
93 .delay_irq = 0x0a0c,
94 .irq_status = 0x0a20,
95 .irq_mask = 0x0a28,
96 .int_grp = 0x0a50,
97 },
98 };
99
100 static const struct mtk_reg_map mt7986_reg_map = {
101 .tx_irq_mask = 0x461c,
102 .tx_irq_status = 0x4618,
103 .pdma = {
104 .rx_ptr = 0x6100,
105 .rx_cnt_cfg = 0x6104,
106 .pcrx_ptr = 0x6108,
107 .glo_cfg = 0x6204,
108 .rst_idx = 0x6208,
109 .delay_irq = 0x620c,
110 .irq_status = 0x6220,
111 .irq_mask = 0x6228,
112 .int_grp = 0x6250,
113 },
114 .qdma = {
115 .qtx_cfg = 0x4400,
116 .rx_ptr = 0x4500,
117 .rx_cnt_cfg = 0x4504,
118 .qcrx_ptr = 0x4508,
119 .glo_cfg = 0x4604,
120 .rst_idx = 0x4608,
121 .delay_irq = 0x460c,
122 .fc_th = 0x4610,
123 .int_grp = 0x4620,
124 .hred = 0x4644,
125 .ctx_ptr = 0x4700,
126 .dtx_ptr = 0x4704,
127 .crx_ptr = 0x4710,
128 .drx_ptr = 0x4714,
129 .fq_head = 0x4720,
130 .fq_tail = 0x4724,
131 .fq_count = 0x4728,
132 .fq_blen = 0x472c,
133 },
134 .gdm1_cnt = 0x1c00,
135 .gdma_to_ppe = 0x3333,
136 .ppe_base = 0x2000,
137 .wdma_base = {
138 [0] = 0x4800,
139 [1] = 0x4c00,
140 },
141 };
142
143 /* strings used by ethtool */
144 static const struct mtk_ethtool_stats {
145 char str[ETH_GSTRING_LEN];
146 u32 offset;
147 } mtk_ethtool_stats[] = {
148 MTK_ETHTOOL_STAT(tx_bytes),
149 MTK_ETHTOOL_STAT(tx_packets),
150 MTK_ETHTOOL_STAT(tx_skip),
151 MTK_ETHTOOL_STAT(tx_collisions),
152 MTK_ETHTOOL_STAT(rx_bytes),
153 MTK_ETHTOOL_STAT(rx_packets),
154 MTK_ETHTOOL_STAT(rx_overflow),
155 MTK_ETHTOOL_STAT(rx_fcs_errors),
156 MTK_ETHTOOL_STAT(rx_short_errors),
157 MTK_ETHTOOL_STAT(rx_long_errors),
158 MTK_ETHTOOL_STAT(rx_checksum_errors),
159 MTK_ETHTOOL_STAT(rx_flow_control_packets),
160 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect),
161 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass),
162 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop),
163 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx),
164 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors),
165 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit),
166 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors),
167 };
168
169 static const char * const mtk_clks_source_name[] = {
170 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
171 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
172 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
173 "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1"
174 };
175
mtk_w32(struct mtk_eth * eth,u32 val,unsigned reg)176 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
177 {
178 __raw_writel(val, eth->base + reg);
179 }
180
mtk_r32(struct mtk_eth * eth,unsigned reg)181 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
182 {
183 return __raw_readl(eth->base + reg);
184 }
185
mtk_m32(struct mtk_eth * eth,u32 mask,u32 set,unsigned reg)186 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
187 {
188 u32 val;
189
190 val = mtk_r32(eth, reg);
191 val &= ~mask;
192 val |= set;
193 mtk_w32(eth, val, reg);
194 return reg;
195 }
196
mtk_mdio_busy_wait(struct mtk_eth * eth)197 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
198 {
199 unsigned long t_start = jiffies;
200
201 while (1) {
202 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
203 return 0;
204 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
205 break;
206 cond_resched();
207 }
208
209 dev_err(eth->dev, "mdio: MDIO timeout\n");
210 return -ETIMEDOUT;
211 }
212
_mtk_mdio_write(struct mtk_eth * eth,u32 phy_addr,u32 phy_reg,u32 write_data)213 static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,
214 u32 write_data)
215 {
216 int ret;
217
218 ret = mtk_mdio_busy_wait(eth);
219 if (ret < 0)
220 return ret;
221
222 if (phy_reg & MII_ADDR_C45) {
223 mtk_w32(eth, PHY_IAC_ACCESS |
224 PHY_IAC_START_C45 |
225 PHY_IAC_CMD_C45_ADDR |
226 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
227 PHY_IAC_ADDR(phy_addr) |
228 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
229 MTK_PHY_IAC);
230
231 ret = mtk_mdio_busy_wait(eth);
232 if (ret < 0)
233 return ret;
234
235 mtk_w32(eth, PHY_IAC_ACCESS |
236 PHY_IAC_START_C45 |
237 PHY_IAC_CMD_WRITE |
238 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
239 PHY_IAC_ADDR(phy_addr) |
240 PHY_IAC_DATA(write_data),
241 MTK_PHY_IAC);
242 } else {
243 mtk_w32(eth, PHY_IAC_ACCESS |
244 PHY_IAC_START_C22 |
245 PHY_IAC_CMD_WRITE |
246 PHY_IAC_REG(phy_reg) |
247 PHY_IAC_ADDR(phy_addr) |
248 PHY_IAC_DATA(write_data),
249 MTK_PHY_IAC);
250 }
251
252 ret = mtk_mdio_busy_wait(eth);
253 if (ret < 0)
254 return ret;
255
256 return 0;
257 }
258
_mtk_mdio_read(struct mtk_eth * eth,u32 phy_addr,u32 phy_reg)259 static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)
260 {
261 int ret;
262
263 ret = mtk_mdio_busy_wait(eth);
264 if (ret < 0)
265 return ret;
266
267 if (phy_reg & MII_ADDR_C45) {
268 mtk_w32(eth, PHY_IAC_ACCESS |
269 PHY_IAC_START_C45 |
270 PHY_IAC_CMD_C45_ADDR |
271 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
272 PHY_IAC_ADDR(phy_addr) |
273 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
274 MTK_PHY_IAC);
275
276 ret = mtk_mdio_busy_wait(eth);
277 if (ret < 0)
278 return ret;
279
280 mtk_w32(eth, PHY_IAC_ACCESS |
281 PHY_IAC_START_C45 |
282 PHY_IAC_CMD_C45_READ |
283 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
284 PHY_IAC_ADDR(phy_addr),
285 MTK_PHY_IAC);
286 } else {
287 mtk_w32(eth, PHY_IAC_ACCESS |
288 PHY_IAC_START_C22 |
289 PHY_IAC_CMD_C22_READ |
290 PHY_IAC_REG(phy_reg) |
291 PHY_IAC_ADDR(phy_addr),
292 MTK_PHY_IAC);
293 }
294
295 ret = mtk_mdio_busy_wait(eth);
296 if (ret < 0)
297 return ret;
298
299 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
300 }
301
mtk_mdio_write(struct mii_bus * bus,int phy_addr,int phy_reg,u16 val)302 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
303 int phy_reg, u16 val)
304 {
305 struct mtk_eth *eth = bus->priv;
306
307 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
308 }
309
mtk_mdio_read(struct mii_bus * bus,int phy_addr,int phy_reg)310 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
311 {
312 struct mtk_eth *eth = bus->priv;
313
314 return _mtk_mdio_read(eth, phy_addr, phy_reg);
315 }
316
mt7621_gmac0_rgmii_adjust(struct mtk_eth * eth,phy_interface_t interface)317 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
318 phy_interface_t interface)
319 {
320 u32 val;
321
322 /* Check DDR memory type.
323 * Currently TRGMII mode with DDR2 memory is not supported.
324 */
325 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
326 if (interface == PHY_INTERFACE_MODE_TRGMII &&
327 val & SYSCFG_DRAM_TYPE_DDR2) {
328 dev_err(eth->dev,
329 "TRGMII mode with DDR2 memory is not supported!\n");
330 return -EOPNOTSUPP;
331 }
332
333 val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
334 ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
335
336 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
337 ETHSYS_TRGMII_MT7621_MASK, val);
338
339 return 0;
340 }
341
mtk_gmac0_rgmii_adjust(struct mtk_eth * eth,phy_interface_t interface,int speed)342 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
343 phy_interface_t interface, int speed)
344 {
345 u32 val;
346 int ret;
347
348 if (interface == PHY_INTERFACE_MODE_TRGMII) {
349 mtk_w32(eth, TRGMII_MODE, INTF_MODE);
350 val = 500000000;
351 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
352 if (ret)
353 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
354 return;
355 }
356
357 val = (speed == SPEED_1000) ?
358 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
359 mtk_w32(eth, val, INTF_MODE);
360
361 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
362 ETHSYS_TRGMII_CLK_SEL362_5,
363 ETHSYS_TRGMII_CLK_SEL362_5);
364
365 val = (speed == SPEED_1000) ? 250000000 : 500000000;
366 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
367 if (ret)
368 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
369
370 val = (speed == SPEED_1000) ?
371 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
372 mtk_w32(eth, val, TRGMII_RCK_CTRL);
373
374 val = (speed == SPEED_1000) ?
375 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
376 mtk_w32(eth, val, TRGMII_TCK_CTRL);
377 }
378
mtk_mac_select_pcs(struct phylink_config * config,phy_interface_t interface)379 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
380 phy_interface_t interface)
381 {
382 struct mtk_mac *mac = container_of(config, struct mtk_mac,
383 phylink_config);
384 struct mtk_eth *eth = mac->hw;
385 unsigned int sid;
386
387 if (interface == PHY_INTERFACE_MODE_SGMII ||
388 phy_interface_mode_is_8023z(interface)) {
389 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
390 0 : mac->id;
391
392 return mtk_sgmii_select_pcs(eth->sgmii, sid);
393 }
394
395 return NULL;
396 }
397
mtk_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)398 static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
399 const struct phylink_link_state *state)
400 {
401 struct mtk_mac *mac = container_of(config, struct mtk_mac,
402 phylink_config);
403 struct mtk_eth *eth = mac->hw;
404 int val, ge_mode, err = 0;
405 u32 i;
406
407 /* MT76x8 has no hardware settings between for the MAC */
408 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
409 mac->interface != state->interface) {
410 /* Setup soc pin functions */
411 switch (state->interface) {
412 case PHY_INTERFACE_MODE_TRGMII:
413 if (mac->id)
414 goto err_phy;
415 if (!MTK_HAS_CAPS(mac->hw->soc->caps,
416 MTK_GMAC1_TRGMII))
417 goto err_phy;
418 fallthrough;
419 case PHY_INTERFACE_MODE_RGMII_TXID:
420 case PHY_INTERFACE_MODE_RGMII_RXID:
421 case PHY_INTERFACE_MODE_RGMII_ID:
422 case PHY_INTERFACE_MODE_RGMII:
423 case PHY_INTERFACE_MODE_MII:
424 case PHY_INTERFACE_MODE_REVMII:
425 case PHY_INTERFACE_MODE_RMII:
426 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
427 err = mtk_gmac_rgmii_path_setup(eth, mac->id);
428 if (err)
429 goto init_err;
430 }
431 break;
432 case PHY_INTERFACE_MODE_1000BASEX:
433 case PHY_INTERFACE_MODE_2500BASEX:
434 case PHY_INTERFACE_MODE_SGMII:
435 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
436 err = mtk_gmac_sgmii_path_setup(eth, mac->id);
437 if (err)
438 goto init_err;
439 }
440 break;
441 case PHY_INTERFACE_MODE_GMII:
442 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
443 err = mtk_gmac_gephy_path_setup(eth, mac->id);
444 if (err)
445 goto init_err;
446 }
447 break;
448 default:
449 goto err_phy;
450 }
451
452 /* Setup clock for 1st gmac */
453 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII &&
454 !phy_interface_mode_is_8023z(state->interface) &&
455 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) {
456 if (MTK_HAS_CAPS(mac->hw->soc->caps,
457 MTK_TRGMII_MT7621_CLK)) {
458 if (mt7621_gmac0_rgmii_adjust(mac->hw,
459 state->interface))
460 goto err_phy;
461 } else {
462 /* FIXME: this is incorrect. Not only does it
463 * use state->speed (which is not guaranteed
464 * to be correct) but it also makes use of it
465 * in a code path that will only be reachable
466 * when the PHY interface mode changes, not
467 * when the speed changes. Consequently, RGMII
468 * is probably broken.
469 */
470 mtk_gmac0_rgmii_adjust(mac->hw,
471 state->interface,
472 state->speed);
473
474 /* mt7623_pad_clk_setup */
475 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
476 mtk_w32(mac->hw,
477 TD_DM_DRVP(8) | TD_DM_DRVN(8),
478 TRGMII_TD_ODT(i));
479
480 /* Assert/release MT7623 RXC reset */
481 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
482 TRGMII_RCK_CTRL);
483 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
484 }
485 }
486
487 ge_mode = 0;
488 switch (state->interface) {
489 case PHY_INTERFACE_MODE_MII:
490 case PHY_INTERFACE_MODE_GMII:
491 ge_mode = 1;
492 break;
493 case PHY_INTERFACE_MODE_REVMII:
494 ge_mode = 2;
495 break;
496 case PHY_INTERFACE_MODE_RMII:
497 if (mac->id)
498 goto err_phy;
499 ge_mode = 3;
500 break;
501 default:
502 break;
503 }
504
505 /* put the gmac into the right mode */
506 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
507 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
508 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
509 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
510
511 mac->interface = state->interface;
512 }
513
514 /* SGMII */
515 if (state->interface == PHY_INTERFACE_MODE_SGMII ||
516 phy_interface_mode_is_8023z(state->interface)) {
517 /* The path GMAC to SGMII will be enabled once the SGMIISYS is
518 * being setup done.
519 */
520 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
521
522 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
523 SYSCFG0_SGMII_MASK,
524 ~(u32)SYSCFG0_SGMII_MASK);
525
526 /* Save the syscfg0 value for mac_finish */
527 mac->syscfg0 = val;
528 } else if (phylink_autoneg_inband(mode)) {
529 dev_err(eth->dev,
530 "In-band mode not supported in non SGMII mode!\n");
531 return;
532 }
533
534 return;
535
536 err_phy:
537 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__,
538 mac->id, phy_modes(state->interface));
539 return;
540
541 init_err:
542 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__,
543 mac->id, phy_modes(state->interface), err);
544 }
545
mtk_mac_finish(struct phylink_config * config,unsigned int mode,phy_interface_t interface)546 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
547 phy_interface_t interface)
548 {
549 struct mtk_mac *mac = container_of(config, struct mtk_mac,
550 phylink_config);
551 struct mtk_eth *eth = mac->hw;
552 u32 mcr_cur, mcr_new;
553
554 /* Enable SGMII */
555 if (interface == PHY_INTERFACE_MODE_SGMII ||
556 phy_interface_mode_is_8023z(interface))
557 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
558 SYSCFG0_SGMII_MASK, mac->syscfg0);
559
560 /* Setup gmac */
561 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
562 mcr_new = mcr_cur;
563 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
564 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK;
565
566 /* Only update control register when needed! */
567 if (mcr_new != mcr_cur)
568 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
569
570 return 0;
571 }
572
mtk_mac_pcs_get_state(struct phylink_config * config,struct phylink_link_state * state)573 static void mtk_mac_pcs_get_state(struct phylink_config *config,
574 struct phylink_link_state *state)
575 {
576 struct mtk_mac *mac = container_of(config, struct mtk_mac,
577 phylink_config);
578 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id));
579
580 state->link = (pmsr & MAC_MSR_LINK);
581 state->duplex = (pmsr & MAC_MSR_DPX) >> 1;
582
583 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) {
584 case 0:
585 state->speed = SPEED_10;
586 break;
587 case MAC_MSR_SPEED_100:
588 state->speed = SPEED_100;
589 break;
590 case MAC_MSR_SPEED_1000:
591 state->speed = SPEED_1000;
592 break;
593 default:
594 state->speed = SPEED_UNKNOWN;
595 break;
596 }
597
598 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
599 if (pmsr & MAC_MSR_RX_FC)
600 state->pause |= MLO_PAUSE_RX;
601 if (pmsr & MAC_MSR_TX_FC)
602 state->pause |= MLO_PAUSE_TX;
603 }
604
mtk_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)605 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
606 phy_interface_t interface)
607 {
608 struct mtk_mac *mac = container_of(config, struct mtk_mac,
609 phylink_config);
610 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
611
612 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
613 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
614 }
615
mtk_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)616 static void mtk_mac_link_up(struct phylink_config *config,
617 struct phy_device *phy,
618 unsigned int mode, phy_interface_t interface,
619 int speed, int duplex, bool tx_pause, bool rx_pause)
620 {
621 struct mtk_mac *mac = container_of(config, struct mtk_mac,
622 phylink_config);
623 u32 mcr;
624
625 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
626 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
627 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
628 MAC_MCR_FORCE_RX_FC);
629
630 /* Configure speed */
631 switch (speed) {
632 case SPEED_2500:
633 case SPEED_1000:
634 mcr |= MAC_MCR_SPEED_1000;
635 break;
636 case SPEED_100:
637 mcr |= MAC_MCR_SPEED_100;
638 break;
639 }
640
641 /* Configure duplex */
642 if (duplex == DUPLEX_FULL)
643 mcr |= MAC_MCR_FORCE_DPX;
644
645 /* Configure pause modes - phylink will avoid these for half duplex */
646 if (tx_pause)
647 mcr |= MAC_MCR_FORCE_TX_FC;
648 if (rx_pause)
649 mcr |= MAC_MCR_FORCE_RX_FC;
650
651 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN;
652 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
653 }
654
655 static const struct phylink_mac_ops mtk_phylink_ops = {
656 .validate = phylink_generic_validate,
657 .mac_select_pcs = mtk_mac_select_pcs,
658 .mac_pcs_get_state = mtk_mac_pcs_get_state,
659 .mac_config = mtk_mac_config,
660 .mac_finish = mtk_mac_finish,
661 .mac_link_down = mtk_mac_link_down,
662 .mac_link_up = mtk_mac_link_up,
663 };
664
mtk_mdio_init(struct mtk_eth * eth)665 static int mtk_mdio_init(struct mtk_eth *eth)
666 {
667 struct device_node *mii_np;
668 int ret;
669
670 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
671 if (!mii_np) {
672 dev_err(eth->dev, "no %s child node found", "mdio-bus");
673 return -ENODEV;
674 }
675
676 if (!of_device_is_available(mii_np)) {
677 ret = -ENODEV;
678 goto err_put_node;
679 }
680
681 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
682 if (!eth->mii_bus) {
683 ret = -ENOMEM;
684 goto err_put_node;
685 }
686
687 eth->mii_bus->name = "mdio";
688 eth->mii_bus->read = mtk_mdio_read;
689 eth->mii_bus->write = mtk_mdio_write;
690 eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
691 eth->mii_bus->priv = eth;
692 eth->mii_bus->parent = eth->dev;
693
694 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
695 ret = of_mdiobus_register(eth->mii_bus, mii_np);
696
697 err_put_node:
698 of_node_put(mii_np);
699 return ret;
700 }
701
mtk_mdio_cleanup(struct mtk_eth * eth)702 static void mtk_mdio_cleanup(struct mtk_eth *eth)
703 {
704 if (!eth->mii_bus)
705 return;
706
707 mdiobus_unregister(eth->mii_bus);
708 }
709
mtk_tx_irq_disable(struct mtk_eth * eth,u32 mask)710 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
711 {
712 unsigned long flags;
713 u32 val;
714
715 spin_lock_irqsave(ð->tx_irq_lock, flags);
716 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
717 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask);
718 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
719 }
720
mtk_tx_irq_enable(struct mtk_eth * eth,u32 mask)721 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
722 {
723 unsigned long flags;
724 u32 val;
725
726 spin_lock_irqsave(ð->tx_irq_lock, flags);
727 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
728 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask);
729 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
730 }
731
mtk_rx_irq_disable(struct mtk_eth * eth,u32 mask)732 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
733 {
734 unsigned long flags;
735 u32 val;
736
737 spin_lock_irqsave(ð->rx_irq_lock, flags);
738 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
739 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask);
740 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
741 }
742
mtk_rx_irq_enable(struct mtk_eth * eth,u32 mask)743 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
744 {
745 unsigned long flags;
746 u32 val;
747
748 spin_lock_irqsave(ð->rx_irq_lock, flags);
749 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
750 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask);
751 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
752 }
753
mtk_set_mac_address(struct net_device * dev,void * p)754 static int mtk_set_mac_address(struct net_device *dev, void *p)
755 {
756 int ret = eth_mac_addr(dev, p);
757 struct mtk_mac *mac = netdev_priv(dev);
758 struct mtk_eth *eth = mac->hw;
759 const char *macaddr = dev->dev_addr;
760
761 if (ret)
762 return ret;
763
764 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
765 return -EBUSY;
766
767 spin_lock_bh(&mac->hw->page_lock);
768 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
769 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
770 MT7628_SDM_MAC_ADRH);
771 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
772 (macaddr[4] << 8) | macaddr[5],
773 MT7628_SDM_MAC_ADRL);
774 } else {
775 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
776 MTK_GDMA_MAC_ADRH(mac->id));
777 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
778 (macaddr[4] << 8) | macaddr[5],
779 MTK_GDMA_MAC_ADRL(mac->id));
780 }
781 spin_unlock_bh(&mac->hw->page_lock);
782
783 return 0;
784 }
785
mtk_stats_update_mac(struct mtk_mac * mac)786 void mtk_stats_update_mac(struct mtk_mac *mac)
787 {
788 struct mtk_hw_stats *hw_stats = mac->hw_stats;
789 struct mtk_eth *eth = mac->hw;
790
791 u64_stats_update_begin(&hw_stats->syncp);
792
793 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
794 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT);
795 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT);
796 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT);
797 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT);
798 hw_stats->rx_checksum_errors +=
799 mtk_r32(mac->hw, MT7628_SDM_CS_ERR);
800 } else {
801 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
802 unsigned int offs = hw_stats->reg_offset;
803 u64 stats;
804
805 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs);
806 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs);
807 if (stats)
808 hw_stats->rx_bytes += (stats << 32);
809 hw_stats->rx_packets +=
810 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs);
811 hw_stats->rx_overflow +=
812 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs);
813 hw_stats->rx_fcs_errors +=
814 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs);
815 hw_stats->rx_short_errors +=
816 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs);
817 hw_stats->rx_long_errors +=
818 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs);
819 hw_stats->rx_checksum_errors +=
820 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
821 hw_stats->rx_flow_control_packets +=
822 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
823 hw_stats->tx_skip +=
824 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs);
825 hw_stats->tx_collisions +=
826 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs);
827 hw_stats->tx_bytes +=
828 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs);
829 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs);
830 if (stats)
831 hw_stats->tx_bytes += (stats << 32);
832 hw_stats->tx_packets +=
833 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);
834 }
835
836 u64_stats_update_end(&hw_stats->syncp);
837 }
838
mtk_stats_update(struct mtk_eth * eth)839 static void mtk_stats_update(struct mtk_eth *eth)
840 {
841 int i;
842
843 for (i = 0; i < MTK_MAC_COUNT; i++) {
844 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
845 continue;
846 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
847 mtk_stats_update_mac(eth->mac[i]);
848 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
849 }
850 }
851 }
852
mtk_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * storage)853 static void mtk_get_stats64(struct net_device *dev,
854 struct rtnl_link_stats64 *storage)
855 {
856 struct mtk_mac *mac = netdev_priv(dev);
857 struct mtk_hw_stats *hw_stats = mac->hw_stats;
858 unsigned int start;
859
860 if (netif_running(dev) && netif_device_present(dev)) {
861 if (spin_trylock_bh(&hw_stats->stats_lock)) {
862 mtk_stats_update_mac(mac);
863 spin_unlock_bh(&hw_stats->stats_lock);
864 }
865 }
866
867 do {
868 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
869 storage->rx_packets = hw_stats->rx_packets;
870 storage->tx_packets = hw_stats->tx_packets;
871 storage->rx_bytes = hw_stats->rx_bytes;
872 storage->tx_bytes = hw_stats->tx_bytes;
873 storage->collisions = hw_stats->tx_collisions;
874 storage->rx_length_errors = hw_stats->rx_short_errors +
875 hw_stats->rx_long_errors;
876 storage->rx_over_errors = hw_stats->rx_overflow;
877 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
878 storage->rx_errors = hw_stats->rx_checksum_errors;
879 storage->tx_aborted_errors = hw_stats->tx_skip;
880 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
881
882 storage->tx_errors = dev->stats.tx_errors;
883 storage->rx_dropped = dev->stats.rx_dropped;
884 storage->tx_dropped = dev->stats.tx_dropped;
885 }
886
mtk_max_frag_size(int mtu)887 static inline int mtk_max_frag_size(int mtu)
888 {
889 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
890 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K)
891 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
892
893 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
894 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
895 }
896
mtk_max_buf_size(int frag_size)897 static inline int mtk_max_buf_size(int frag_size)
898 {
899 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
900 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
901
902 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K);
903
904 return buf_size;
905 }
906
mtk_rx_get_desc(struct mtk_eth * eth,struct mtk_rx_dma_v2 * rxd,struct mtk_rx_dma_v2 * dma_rxd)907 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd,
908 struct mtk_rx_dma_v2 *dma_rxd)
909 {
910 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
911 if (!(rxd->rxd2 & RX_DMA_DONE))
912 return false;
913
914 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
915 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
916 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
917 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
918 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
919 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
920 }
921
922 return true;
923 }
924
mtk_max_lro_buf_alloc(gfp_t gfp_mask)925 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask)
926 {
927 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH);
928 unsigned long data;
929
930 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN,
931 get_order(size));
932
933 return (void *)data;
934 }
935
936 /* the qdma core needs scratch memory to be setup */
mtk_init_fq_dma(struct mtk_eth * eth)937 static int mtk_init_fq_dma(struct mtk_eth *eth)
938 {
939 const struct mtk_soc_data *soc = eth->soc;
940 dma_addr_t phy_ring_tail;
941 int cnt = MTK_DMA_SIZE;
942 dma_addr_t dma_addr;
943 int i;
944
945 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
946 cnt * soc->txrx.txd_size,
947 ð->phy_scratch_ring,
948 GFP_KERNEL);
949 if (unlikely(!eth->scratch_ring))
950 return -ENOMEM;
951
952 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL);
953 if (unlikely(!eth->scratch_head))
954 return -ENOMEM;
955
956 dma_addr = dma_map_single(eth->dma_dev,
957 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
958 DMA_FROM_DEVICE);
959 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
960 return -ENOMEM;
961
962 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
963
964 for (i = 0; i < cnt; i++) {
965 struct mtk_tx_dma_v2 *txd;
966
967 txd = eth->scratch_ring + i * soc->txrx.txd_size;
968 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
969 if (i < cnt - 1)
970 txd->txd2 = eth->phy_scratch_ring +
971 (i + 1) * soc->txrx.txd_size;
972
973 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
974 txd->txd4 = 0;
975 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
976 txd->txd5 = 0;
977 txd->txd6 = 0;
978 txd->txd7 = 0;
979 txd->txd8 = 0;
980 }
981 }
982
983 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head);
984 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail);
985 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count);
986 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen);
987
988 return 0;
989 }
990
mtk_qdma_phys_to_virt(struct mtk_tx_ring * ring,u32 desc)991 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
992 {
993 return ring->dma + (desc - ring->phys);
994 }
995
mtk_desc_to_tx_buf(struct mtk_tx_ring * ring,void * txd,u32 txd_size)996 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
997 void *txd, u32 txd_size)
998 {
999 int idx = (txd - ring->dma) / txd_size;
1000
1001 return &ring->buf[idx];
1002 }
1003
qdma_to_pdma(struct mtk_tx_ring * ring,struct mtk_tx_dma * dma)1004 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring,
1005 struct mtk_tx_dma *dma)
1006 {
1007 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma;
1008 }
1009
txd_to_idx(struct mtk_tx_ring * ring,void * dma,u32 txd_size)1010 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size)
1011 {
1012 return (dma - ring->dma) / txd_size;
1013 }
1014
mtk_tx_unmap(struct mtk_eth * eth,struct mtk_tx_buf * tx_buf,struct xdp_frame_bulk * bq,bool napi)1015 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
1016 struct xdp_frame_bulk *bq, bool napi)
1017 {
1018 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1019 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
1020 dma_unmap_single(eth->dma_dev,
1021 dma_unmap_addr(tx_buf, dma_addr0),
1022 dma_unmap_len(tx_buf, dma_len0),
1023 DMA_TO_DEVICE);
1024 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
1025 dma_unmap_page(eth->dma_dev,
1026 dma_unmap_addr(tx_buf, dma_addr0),
1027 dma_unmap_len(tx_buf, dma_len0),
1028 DMA_TO_DEVICE);
1029 }
1030 } else {
1031 if (dma_unmap_len(tx_buf, dma_len0)) {
1032 dma_unmap_page(eth->dma_dev,
1033 dma_unmap_addr(tx_buf, dma_addr0),
1034 dma_unmap_len(tx_buf, dma_len0),
1035 DMA_TO_DEVICE);
1036 }
1037
1038 if (dma_unmap_len(tx_buf, dma_len1)) {
1039 dma_unmap_page(eth->dma_dev,
1040 dma_unmap_addr(tx_buf, dma_addr1),
1041 dma_unmap_len(tx_buf, dma_len1),
1042 DMA_TO_DEVICE);
1043 }
1044 }
1045
1046 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
1047 if (tx_buf->type == MTK_TYPE_SKB) {
1048 struct sk_buff *skb = tx_buf->data;
1049
1050 if (napi)
1051 napi_consume_skb(skb, napi);
1052 else
1053 dev_kfree_skb_any(skb);
1054 } else {
1055 struct xdp_frame *xdpf = tx_buf->data;
1056
1057 if (napi && tx_buf->type == MTK_TYPE_XDP_TX)
1058 xdp_return_frame_rx_napi(xdpf);
1059 else if (bq)
1060 xdp_return_frame_bulk(xdpf, bq);
1061 else
1062 xdp_return_frame(xdpf);
1063 }
1064 }
1065 tx_buf->flags = 0;
1066 tx_buf->data = NULL;
1067 }
1068
setup_tx_buf(struct mtk_eth * eth,struct mtk_tx_buf * tx_buf,struct mtk_tx_dma * txd,dma_addr_t mapped_addr,size_t size,int idx)1069 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
1070 struct mtk_tx_dma *txd, dma_addr_t mapped_addr,
1071 size_t size, int idx)
1072 {
1073 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1074 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1075 dma_unmap_len_set(tx_buf, dma_len0, size);
1076 } else {
1077 if (idx & 1) {
1078 txd->txd3 = mapped_addr;
1079 txd->txd2 |= TX_DMA_PLEN1(size);
1080 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
1081 dma_unmap_len_set(tx_buf, dma_len1, size);
1082 } else {
1083 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1084 txd->txd1 = mapped_addr;
1085 txd->txd2 = TX_DMA_PLEN0(size);
1086 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1087 dma_unmap_len_set(tx_buf, dma_len0, size);
1088 }
1089 }
1090 }
1091
mtk_tx_set_dma_desc_v1(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1092 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd,
1093 struct mtk_tx_dma_desc_info *info)
1094 {
1095 struct mtk_mac *mac = netdev_priv(dev);
1096 struct mtk_eth *eth = mac->hw;
1097 struct mtk_tx_dma *desc = txd;
1098 u32 data;
1099
1100 WRITE_ONCE(desc->txd1, info->addr);
1101
1102 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size);
1103 if (info->last)
1104 data |= TX_DMA_LS0;
1105 WRITE_ONCE(desc->txd3, data);
1106
1107 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */
1108 if (info->first) {
1109 if (info->gso)
1110 data |= TX_DMA_TSO;
1111 /* tx checksum offload */
1112 if (info->csum)
1113 data |= TX_DMA_CHKSUM;
1114 /* vlan header offload */
1115 if (info->vlan)
1116 data |= TX_DMA_INS_VLAN | info->vlan_tci;
1117 }
1118 WRITE_ONCE(desc->txd4, data);
1119 }
1120
mtk_tx_set_dma_desc_v2(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1121 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd,
1122 struct mtk_tx_dma_desc_info *info)
1123 {
1124 struct mtk_mac *mac = netdev_priv(dev);
1125 struct mtk_tx_dma_v2 *desc = txd;
1126 struct mtk_eth *eth = mac->hw;
1127 u32 data;
1128
1129 WRITE_ONCE(desc->txd1, info->addr);
1130
1131 data = TX_DMA_PLEN0(info->size);
1132 if (info->last)
1133 data |= TX_DMA_LS0;
1134 WRITE_ONCE(desc->txd3, data);
1135
1136 if (!info->qid && mac->id)
1137 info->qid = MTK_QDMA_GMAC2_QID;
1138
1139 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
1140 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
1141 WRITE_ONCE(desc->txd4, data);
1142
1143 data = 0;
1144 if (info->first) {
1145 if (info->gso)
1146 data |= TX_DMA_TSO_V2;
1147 /* tx checksum offload */
1148 if (info->csum)
1149 data |= TX_DMA_CHKSUM_V2;
1150 }
1151 WRITE_ONCE(desc->txd5, data);
1152
1153 data = 0;
1154 if (info->first && info->vlan)
1155 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci;
1156 WRITE_ONCE(desc->txd6, data);
1157
1158 WRITE_ONCE(desc->txd7, 0);
1159 WRITE_ONCE(desc->txd8, 0);
1160 }
1161
mtk_tx_set_dma_desc(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1162 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd,
1163 struct mtk_tx_dma_desc_info *info)
1164 {
1165 struct mtk_mac *mac = netdev_priv(dev);
1166 struct mtk_eth *eth = mac->hw;
1167
1168 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1169 mtk_tx_set_dma_desc_v2(dev, txd, info);
1170 else
1171 mtk_tx_set_dma_desc_v1(dev, txd, info);
1172 }
1173
mtk_tx_map(struct sk_buff * skb,struct net_device * dev,int tx_num,struct mtk_tx_ring * ring,bool gso)1174 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
1175 int tx_num, struct mtk_tx_ring *ring, bool gso)
1176 {
1177 struct mtk_tx_dma_desc_info txd_info = {
1178 .size = skb_headlen(skb),
1179 .gso = gso,
1180 .csum = skb->ip_summed == CHECKSUM_PARTIAL,
1181 .vlan = skb_vlan_tag_present(skb),
1182 .qid = skb->mark & MTK_QDMA_TX_MASK,
1183 .vlan_tci = skb_vlan_tag_get(skb),
1184 .first = true,
1185 .last = !skb_is_nonlinear(skb),
1186 };
1187 struct mtk_mac *mac = netdev_priv(dev);
1188 struct mtk_eth *eth = mac->hw;
1189 const struct mtk_soc_data *soc = eth->soc;
1190 struct mtk_tx_dma *itxd, *txd;
1191 struct mtk_tx_dma *itxd_pdma, *txd_pdma;
1192 struct mtk_tx_buf *itx_buf, *tx_buf;
1193 int i, n_desc = 1;
1194 int k = 0;
1195
1196 itxd = ring->next_free;
1197 itxd_pdma = qdma_to_pdma(ring, itxd);
1198 if (itxd == ring->last_free)
1199 return -ENOMEM;
1200
1201 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
1202 memset(itx_buf, 0, sizeof(*itx_buf));
1203
1204 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
1205 DMA_TO_DEVICE);
1206 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
1207 return -ENOMEM;
1208
1209 mtk_tx_set_dma_desc(dev, itxd, &txd_info);
1210
1211 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
1212 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
1213 MTK_TX_FLAGS_FPORT1;
1214 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
1215 k++);
1216
1217 /* TX SG offload */
1218 txd = itxd;
1219 txd_pdma = qdma_to_pdma(ring, txd);
1220
1221 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1222 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1223 unsigned int offset = 0;
1224 int frag_size = skb_frag_size(frag);
1225
1226 while (frag_size) {
1227 bool new_desc = true;
1228
1229 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) ||
1230 (i & 0x1)) {
1231 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1232 txd_pdma = qdma_to_pdma(ring, txd);
1233 if (txd == ring->last_free)
1234 goto err_dma;
1235
1236 n_desc++;
1237 } else {
1238 new_desc = false;
1239 }
1240
1241 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
1242 txd_info.size = min_t(unsigned int, frag_size,
1243 soc->txrx.dma_max_len);
1244 txd_info.qid = skb->mark & MTK_QDMA_TX_MASK;
1245 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
1246 !(frag_size - txd_info.size);
1247 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag,
1248 offset, txd_info.size,
1249 DMA_TO_DEVICE);
1250 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
1251 goto err_dma;
1252
1253 mtk_tx_set_dma_desc(dev, txd, &txd_info);
1254
1255 tx_buf = mtk_desc_to_tx_buf(ring, txd,
1256 soc->txrx.txd_size);
1257 if (new_desc)
1258 memset(tx_buf, 0, sizeof(*tx_buf));
1259 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1260 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
1261 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
1262 MTK_TX_FLAGS_FPORT1;
1263
1264 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
1265 txd_info.size, k++);
1266
1267 frag_size -= txd_info.size;
1268 offset += txd_info.size;
1269 }
1270 }
1271
1272 /* store skb to cleanup */
1273 itx_buf->type = MTK_TYPE_SKB;
1274 itx_buf->data = skb;
1275
1276 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1277 if (k & 0x1)
1278 txd_pdma->txd2 |= TX_DMA_LS0;
1279 else
1280 txd_pdma->txd2 |= TX_DMA_LS1;
1281 }
1282
1283 netdev_sent_queue(dev, skb->len);
1284 skb_tx_timestamp(skb);
1285
1286 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1287 atomic_sub(n_desc, &ring->free_count);
1288
1289 /* make sure that all changes to the dma ring are flushed before we
1290 * continue
1291 */
1292 wmb();
1293
1294 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1295 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) ||
1296 !netdev_xmit_more())
1297 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1298 } else {
1299 int next_idx;
1300
1301 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size),
1302 ring->dma_size);
1303 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
1304 }
1305
1306 return 0;
1307
1308 err_dma:
1309 do {
1310 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
1311
1312 /* unmap dma */
1313 mtk_tx_unmap(eth, tx_buf, NULL, false);
1314
1315 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1316 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA))
1317 itxd_pdma->txd2 = TX_DMA_DESP2_DEF;
1318
1319 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
1320 itxd_pdma = qdma_to_pdma(ring, itxd);
1321 } while (itxd != txd);
1322
1323 return -ENOMEM;
1324 }
1325
mtk_cal_txd_req(struct mtk_eth * eth,struct sk_buff * skb)1326 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb)
1327 {
1328 int i, nfrags = 1;
1329 skb_frag_t *frag;
1330
1331 if (skb_is_gso(skb)) {
1332 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1333 frag = &skb_shinfo(skb)->frags[i];
1334 nfrags += DIV_ROUND_UP(skb_frag_size(frag),
1335 eth->soc->txrx.dma_max_len);
1336 }
1337 } else {
1338 nfrags += skb_shinfo(skb)->nr_frags;
1339 }
1340
1341 return nfrags;
1342 }
1343
mtk_queue_stopped(struct mtk_eth * eth)1344 static int mtk_queue_stopped(struct mtk_eth *eth)
1345 {
1346 int i;
1347
1348 for (i = 0; i < MTK_MAC_COUNT; i++) {
1349 if (!eth->netdev[i])
1350 continue;
1351 if (netif_queue_stopped(eth->netdev[i]))
1352 return 1;
1353 }
1354
1355 return 0;
1356 }
1357
mtk_wake_queue(struct mtk_eth * eth)1358 static void mtk_wake_queue(struct mtk_eth *eth)
1359 {
1360 int i;
1361
1362 for (i = 0; i < MTK_MAC_COUNT; i++) {
1363 if (!eth->netdev[i])
1364 continue;
1365 netif_wake_queue(eth->netdev[i]);
1366 }
1367 }
1368
mtk_start_xmit(struct sk_buff * skb,struct net_device * dev)1369 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
1370 {
1371 struct mtk_mac *mac = netdev_priv(dev);
1372 struct mtk_eth *eth = mac->hw;
1373 struct mtk_tx_ring *ring = ð->tx_ring;
1374 struct net_device_stats *stats = &dev->stats;
1375 bool gso = false;
1376 int tx_num;
1377
1378 /* normally we can rely on the stack not calling this more than once,
1379 * however we have 2 queues running on the same ring so we need to lock
1380 * the ring access
1381 */
1382 spin_lock(ð->page_lock);
1383
1384 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1385 goto drop;
1386
1387 tx_num = mtk_cal_txd_req(eth, skb);
1388 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
1389 netif_stop_queue(dev);
1390 netif_err(eth, tx_queued, dev,
1391 "Tx Ring full when queue awake!\n");
1392 spin_unlock(ð->page_lock);
1393 return NETDEV_TX_BUSY;
1394 }
1395
1396 /* TSO: fill MSS info in tcp checksum field */
1397 if (skb_is_gso(skb)) {
1398 if (skb_cow_head(skb, 0)) {
1399 netif_warn(eth, tx_err, dev,
1400 "GSO expand head fail.\n");
1401 goto drop;
1402 }
1403
1404 if (skb_shinfo(skb)->gso_type &
1405 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1406 gso = true;
1407 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1408 }
1409 }
1410
1411 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
1412 goto drop;
1413
1414 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
1415 netif_stop_queue(dev);
1416
1417 spin_unlock(ð->page_lock);
1418
1419 return NETDEV_TX_OK;
1420
1421 drop:
1422 spin_unlock(ð->page_lock);
1423 stats->tx_dropped++;
1424 dev_kfree_skb_any(skb);
1425 return NETDEV_TX_OK;
1426 }
1427
mtk_get_rx_ring(struct mtk_eth * eth)1428 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
1429 {
1430 int i;
1431 struct mtk_rx_ring *ring;
1432 int idx;
1433
1434 if (!eth->hwlro)
1435 return ð->rx_ring[0];
1436
1437 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1438 struct mtk_rx_dma *rxd;
1439
1440 ring = ð->rx_ring[i];
1441 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1442 rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
1443 if (rxd->rxd2 & RX_DMA_DONE) {
1444 ring->calc_idx_update = true;
1445 return ring;
1446 }
1447 }
1448
1449 return NULL;
1450 }
1451
mtk_update_rx_cpu_idx(struct mtk_eth * eth)1452 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
1453 {
1454 struct mtk_rx_ring *ring;
1455 int i;
1456
1457 if (!eth->hwlro) {
1458 ring = ð->rx_ring[0];
1459 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1460 } else {
1461 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1462 ring = ð->rx_ring[i];
1463 if (ring->calc_idx_update) {
1464 ring->calc_idx_update = false;
1465 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1466 }
1467 }
1468 }
1469 }
1470
mtk_page_pool_enabled(struct mtk_eth * eth)1471 static bool mtk_page_pool_enabled(struct mtk_eth *eth)
1472 {
1473 return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2);
1474 }
1475
mtk_create_page_pool(struct mtk_eth * eth,struct xdp_rxq_info * xdp_q,int id,int size)1476 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
1477 struct xdp_rxq_info *xdp_q,
1478 int id, int size)
1479 {
1480 struct page_pool_params pp_params = {
1481 .order = 0,
1482 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
1483 .pool_size = size,
1484 .nid = NUMA_NO_NODE,
1485 .dev = eth->dma_dev,
1486 .offset = MTK_PP_HEADROOM,
1487 .max_len = MTK_PP_MAX_BUF_SIZE,
1488 };
1489 struct page_pool *pp;
1490 int err;
1491
1492 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL
1493 : DMA_FROM_DEVICE;
1494 pp = page_pool_create(&pp_params);
1495 if (IS_ERR(pp))
1496 return pp;
1497
1498 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, eth->rx_napi.napi_id,
1499 id, PAGE_SIZE);
1500 if (err < 0)
1501 goto err_free_pp;
1502
1503 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp);
1504 if (err)
1505 goto err_unregister_rxq;
1506
1507 return pp;
1508
1509 err_unregister_rxq:
1510 xdp_rxq_info_unreg(xdp_q);
1511 err_free_pp:
1512 page_pool_destroy(pp);
1513
1514 return ERR_PTR(err);
1515 }
1516
mtk_page_pool_get_buff(struct page_pool * pp,dma_addr_t * dma_addr,gfp_t gfp_mask)1517 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr,
1518 gfp_t gfp_mask)
1519 {
1520 struct page *page;
1521
1522 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN);
1523 if (!page)
1524 return NULL;
1525
1526 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM;
1527 return page_address(page);
1528 }
1529
mtk_rx_put_buff(struct mtk_rx_ring * ring,void * data,bool napi)1530 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi)
1531 {
1532 if (ring->page_pool)
1533 page_pool_put_full_page(ring->page_pool,
1534 virt_to_head_page(data), napi);
1535 else
1536 skb_free_frag(data);
1537 }
1538
mtk_xdp_frame_map(struct mtk_eth * eth,struct net_device * dev,struct mtk_tx_dma_desc_info * txd_info,struct mtk_tx_dma * txd,struct mtk_tx_buf * tx_buf,void * data,u16 headroom,int index,bool dma_map)1539 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev,
1540 struct mtk_tx_dma_desc_info *txd_info,
1541 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf,
1542 void *data, u16 headroom, int index, bool dma_map)
1543 {
1544 struct mtk_tx_ring *ring = ð->tx_ring;
1545 struct mtk_mac *mac = netdev_priv(dev);
1546 struct mtk_tx_dma *txd_pdma;
1547
1548 if (dma_map) { /* ndo_xdp_xmit */
1549 txd_info->addr = dma_map_single(eth->dma_dev, data,
1550 txd_info->size, DMA_TO_DEVICE);
1551 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr)))
1552 return -ENOMEM;
1553
1554 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
1555 } else {
1556 struct page *page = virt_to_head_page(data);
1557
1558 txd_info->addr = page_pool_get_dma_addr(page) +
1559 sizeof(struct xdp_frame) + headroom;
1560 dma_sync_single_for_device(eth->dma_dev, txd_info->addr,
1561 txd_info->size, DMA_BIDIRECTIONAL);
1562 }
1563 mtk_tx_set_dma_desc(dev, txd, txd_info);
1564
1565 tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1;
1566 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX;
1567 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1568
1569 txd_pdma = qdma_to_pdma(ring, txd);
1570 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size,
1571 index);
1572
1573 return 0;
1574 }
1575
mtk_xdp_submit_frame(struct mtk_eth * eth,struct xdp_frame * xdpf,struct net_device * dev,bool dma_map)1576 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf,
1577 struct net_device *dev, bool dma_map)
1578 {
1579 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
1580 const struct mtk_soc_data *soc = eth->soc;
1581 struct mtk_tx_ring *ring = ð->tx_ring;
1582 struct mtk_tx_dma_desc_info txd_info = {
1583 .size = xdpf->len,
1584 .first = true,
1585 .last = !xdp_frame_has_frags(xdpf),
1586 };
1587 int err, index = 0, n_desc = 1, nr_frags;
1588 struct mtk_tx_buf *htx_buf, *tx_buf;
1589 struct mtk_tx_dma *htxd, *txd;
1590 void *data = xdpf->data;
1591
1592 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1593 return -EBUSY;
1594
1595 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
1596 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags))
1597 return -EBUSY;
1598
1599 spin_lock(ð->page_lock);
1600
1601 txd = ring->next_free;
1602 if (txd == ring->last_free) {
1603 spin_unlock(ð->page_lock);
1604 return -ENOMEM;
1605 }
1606 htxd = txd;
1607
1608 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size);
1609 memset(tx_buf, 0, sizeof(*tx_buf));
1610 htx_buf = tx_buf;
1611
1612 for (;;) {
1613 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf,
1614 data, xdpf->headroom, index, dma_map);
1615 if (err < 0)
1616 goto unmap;
1617
1618 if (txd_info.last)
1619 break;
1620
1621 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) {
1622 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1623 if (txd == ring->last_free)
1624 goto unmap;
1625
1626 tx_buf = mtk_desc_to_tx_buf(ring, txd,
1627 soc->txrx.txd_size);
1628 memset(tx_buf, 0, sizeof(*tx_buf));
1629 n_desc++;
1630 }
1631
1632 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
1633 txd_info.size = skb_frag_size(&sinfo->frags[index]);
1634 txd_info.last = index + 1 == nr_frags;
1635 data = skb_frag_address(&sinfo->frags[index]);
1636
1637 index++;
1638 }
1639 /* store xdpf for cleanup */
1640 htx_buf->data = xdpf;
1641
1642 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1643 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd);
1644
1645 if (index & 1)
1646 txd_pdma->txd2 |= TX_DMA_LS0;
1647 else
1648 txd_pdma->txd2 |= TX_DMA_LS1;
1649 }
1650
1651 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1652 atomic_sub(n_desc, &ring->free_count);
1653
1654 /* make sure that all changes to the dma ring are flushed before we
1655 * continue
1656 */
1657 wmb();
1658
1659 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1660 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1661 } else {
1662 int idx;
1663
1664 idx = txd_to_idx(ring, txd, soc->txrx.txd_size);
1665 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
1666 MT7628_TX_CTX_IDX0);
1667 }
1668
1669 spin_unlock(ð->page_lock);
1670
1671 return 0;
1672
1673 unmap:
1674 while (htxd != txd) {
1675 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size);
1676 mtk_tx_unmap(eth, tx_buf, NULL, false);
1677
1678 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1679 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1680 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd);
1681
1682 txd_pdma->txd2 = TX_DMA_DESP2_DEF;
1683 }
1684
1685 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2);
1686 }
1687
1688 spin_unlock(ð->page_lock);
1689
1690 return err;
1691 }
1692
mtk_xdp_xmit(struct net_device * dev,int num_frame,struct xdp_frame ** frames,u32 flags)1693 static int mtk_xdp_xmit(struct net_device *dev, int num_frame,
1694 struct xdp_frame **frames, u32 flags)
1695 {
1696 struct mtk_mac *mac = netdev_priv(dev);
1697 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1698 struct mtk_eth *eth = mac->hw;
1699 int i, nxmit = 0;
1700
1701 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
1702 return -EINVAL;
1703
1704 for (i = 0; i < num_frame; i++) {
1705 if (mtk_xdp_submit_frame(eth, frames[i], dev, true))
1706 break;
1707 nxmit++;
1708 }
1709
1710 u64_stats_update_begin(&hw_stats->syncp);
1711 hw_stats->xdp_stats.tx_xdp_xmit += nxmit;
1712 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit;
1713 u64_stats_update_end(&hw_stats->syncp);
1714
1715 return nxmit;
1716 }
1717
mtk_xdp_run(struct mtk_eth * eth,struct mtk_rx_ring * ring,struct xdp_buff * xdp,struct net_device * dev)1718 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring,
1719 struct xdp_buff *xdp, struct net_device *dev)
1720 {
1721 struct mtk_mac *mac = netdev_priv(dev);
1722 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1723 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop;
1724 struct bpf_prog *prog;
1725 u32 act = XDP_PASS;
1726
1727 rcu_read_lock();
1728
1729 prog = rcu_dereference(eth->prog);
1730 if (!prog)
1731 goto out;
1732
1733 act = bpf_prog_run_xdp(prog, xdp);
1734 switch (act) {
1735 case XDP_PASS:
1736 count = &hw_stats->xdp_stats.rx_xdp_pass;
1737 goto update_stats;
1738 case XDP_REDIRECT:
1739 if (unlikely(xdp_do_redirect(dev, xdp, prog))) {
1740 act = XDP_DROP;
1741 break;
1742 }
1743
1744 count = &hw_stats->xdp_stats.rx_xdp_redirect;
1745 goto update_stats;
1746 case XDP_TX: {
1747 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
1748
1749 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) {
1750 count = &hw_stats->xdp_stats.rx_xdp_tx_errors;
1751 act = XDP_DROP;
1752 break;
1753 }
1754
1755 count = &hw_stats->xdp_stats.rx_xdp_tx;
1756 goto update_stats;
1757 }
1758 default:
1759 bpf_warn_invalid_xdp_action(dev, prog, act);
1760 fallthrough;
1761 case XDP_ABORTED:
1762 trace_xdp_exception(dev, prog, act);
1763 fallthrough;
1764 case XDP_DROP:
1765 break;
1766 }
1767
1768 page_pool_put_full_page(ring->page_pool,
1769 virt_to_head_page(xdp->data), true);
1770
1771 update_stats:
1772 u64_stats_update_begin(&hw_stats->syncp);
1773 *count = *count + 1;
1774 u64_stats_update_end(&hw_stats->syncp);
1775 out:
1776 rcu_read_unlock();
1777
1778 return act;
1779 }
1780
mtk_poll_rx(struct napi_struct * napi,int budget,struct mtk_eth * eth)1781 static int mtk_poll_rx(struct napi_struct *napi, int budget,
1782 struct mtk_eth *eth)
1783 {
1784 struct dim_sample dim_sample = {};
1785 struct mtk_rx_ring *ring;
1786 bool xdp_flush = false;
1787 int idx;
1788 struct sk_buff *skb;
1789 u8 *data, *new_data;
1790 struct mtk_rx_dma_v2 *rxd, trxd;
1791 int done = 0, bytes = 0;
1792
1793 while (done < budget) {
1794 unsigned int pktlen, *rxdcsum;
1795 struct net_device *netdev;
1796 dma_addr_t dma_addr;
1797 u32 hash, reason;
1798 int mac = 0;
1799
1800 ring = mtk_get_rx_ring(eth);
1801 if (unlikely(!ring))
1802 goto rx_done;
1803
1804 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1805 rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
1806 data = ring->data[idx];
1807
1808 if (!mtk_rx_get_desc(eth, &trxd, rxd))
1809 break;
1810
1811 /* find out which mac the packet come from. values start at 1 */
1812 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1813 mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
1814 else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
1815 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
1816 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
1817
1818 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
1819 !eth->netdev[mac]))
1820 goto release_desc;
1821
1822 netdev = eth->netdev[mac];
1823
1824 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1825 goto release_desc;
1826
1827 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1828
1829 /* alloc new buffer */
1830 if (ring->page_pool) {
1831 struct page *page = virt_to_head_page(data);
1832 struct xdp_buff xdp;
1833 u32 ret;
1834
1835 new_data = mtk_page_pool_get_buff(ring->page_pool,
1836 &dma_addr,
1837 GFP_ATOMIC);
1838 if (unlikely(!new_data)) {
1839 netdev->stats.rx_dropped++;
1840 goto release_desc;
1841 }
1842
1843 dma_sync_single_for_cpu(eth->dma_dev,
1844 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM,
1845 pktlen, page_pool_get_dma_dir(ring->page_pool));
1846
1847 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q);
1848 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen,
1849 false);
1850 xdp_buff_clear_frags_flag(&xdp);
1851
1852 ret = mtk_xdp_run(eth, ring, &xdp, netdev);
1853 if (ret == XDP_REDIRECT)
1854 xdp_flush = true;
1855
1856 if (ret != XDP_PASS)
1857 goto skip_rx;
1858
1859 skb = build_skb(data, PAGE_SIZE);
1860 if (unlikely(!skb)) {
1861 page_pool_put_full_page(ring->page_pool,
1862 page, true);
1863 netdev->stats.rx_dropped++;
1864 goto skip_rx;
1865 }
1866
1867 skb_reserve(skb, xdp.data - xdp.data_hard_start);
1868 skb_put(skb, xdp.data_end - xdp.data);
1869 skb_mark_for_recycle(skb);
1870 } else {
1871 if (ring->frag_size <= PAGE_SIZE)
1872 new_data = napi_alloc_frag(ring->frag_size);
1873 else
1874 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC);
1875
1876 if (unlikely(!new_data)) {
1877 netdev->stats.rx_dropped++;
1878 goto release_desc;
1879 }
1880
1881 dma_addr = dma_map_single(eth->dma_dev,
1882 new_data + NET_SKB_PAD + eth->ip_align,
1883 ring->buf_size, DMA_FROM_DEVICE);
1884 if (unlikely(dma_mapping_error(eth->dma_dev,
1885 dma_addr))) {
1886 skb_free_frag(new_data);
1887 netdev->stats.rx_dropped++;
1888 goto release_desc;
1889 }
1890
1891 dma_unmap_single(eth->dma_dev, trxd.rxd1,
1892 ring->buf_size, DMA_FROM_DEVICE);
1893
1894 skb = build_skb(data, ring->frag_size);
1895 if (unlikely(!skb)) {
1896 netdev->stats.rx_dropped++;
1897 skb_free_frag(data);
1898 goto skip_rx;
1899 }
1900
1901 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1902 skb_put(skb, pktlen);
1903 }
1904
1905 skb->dev = netdev;
1906 bytes += skb->len;
1907
1908 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
1909 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
1910 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
1911 if (hash != MTK_RXD5_FOE_ENTRY)
1912 skb_set_hash(skb, jhash_1word(hash, 0),
1913 PKT_HASH_TYPE_L4);
1914 rxdcsum = &trxd.rxd3;
1915 } else {
1916 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4);
1917 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
1918 if (hash != MTK_RXD4_FOE_ENTRY)
1919 skb_set_hash(skb, jhash_1word(hash, 0),
1920 PKT_HASH_TYPE_L4);
1921 rxdcsum = &trxd.rxd4;
1922 }
1923
1924 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
1925 skb->ip_summed = CHECKSUM_UNNECESSARY;
1926 else
1927 skb_checksum_none_assert(skb);
1928 skb->protocol = eth_type_trans(skb, netdev);
1929
1930 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
1931 mtk_ppe_check_skb(eth->ppe[0], skb, hash);
1932
1933 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
1934 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
1935 if (trxd.rxd3 & RX_DMA_VTAG_V2)
1936 __vlan_hwaccel_put_tag(skb,
1937 htons(RX_DMA_VPID(trxd.rxd4)),
1938 RX_DMA_VID(trxd.rxd4));
1939 } else if (trxd.rxd2 & RX_DMA_VTAG) {
1940 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1941 RX_DMA_VID(trxd.rxd3));
1942 }
1943
1944 /* If the device is attached to a dsa switch, the special
1945 * tag inserted in VLAN field by hw switch can * be offloaded
1946 * by RX HW VLAN offload. Clear vlan info.
1947 */
1948 if (netdev_uses_dsa(netdev))
1949 __vlan_hwaccel_clear_tag(skb);
1950 }
1951
1952 skb_record_rx_queue(skb, 0);
1953 napi_gro_receive(napi, skb);
1954
1955 skip_rx:
1956 ring->data[idx] = new_data;
1957 rxd->rxd1 = (unsigned int)dma_addr;
1958 release_desc:
1959 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
1960 rxd->rxd2 = RX_DMA_LSO;
1961 else
1962 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
1963
1964 ring->calc_idx = idx;
1965 done++;
1966 }
1967
1968 rx_done:
1969 if (done) {
1970 /* make sure that all changes to the dma ring are flushed before
1971 * we continue
1972 */
1973 wmb();
1974 mtk_update_rx_cpu_idx(eth);
1975 }
1976
1977 eth->rx_packets += done;
1978 eth->rx_bytes += bytes;
1979 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes,
1980 &dim_sample);
1981 net_dim(ð->rx_dim, dim_sample);
1982
1983 if (xdp_flush)
1984 xdp_do_flush_map();
1985
1986 return done;
1987 }
1988
mtk_poll_tx_qdma(struct mtk_eth * eth,int budget,unsigned int * done,unsigned int * bytes)1989 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
1990 unsigned int *done, unsigned int *bytes)
1991 {
1992 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
1993 struct mtk_tx_ring *ring = ð->tx_ring;
1994 struct mtk_tx_buf *tx_buf;
1995 struct xdp_frame_bulk bq;
1996 struct mtk_tx_dma *desc;
1997 u32 cpu, dma;
1998
1999 cpu = ring->last_free_ptr;
2000 dma = mtk_r32(eth, reg_map->qdma.drx_ptr);
2001
2002 desc = mtk_qdma_phys_to_virt(ring, cpu);
2003 xdp_frame_bulk_init(&bq);
2004
2005 while ((cpu != dma) && budget) {
2006 u32 next_cpu = desc->txd2;
2007 int mac = 0;
2008
2009 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
2010 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
2011 break;
2012
2013 tx_buf = mtk_desc_to_tx_buf(ring, desc,
2014 eth->soc->txrx.txd_size);
2015 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
2016 mac = 1;
2017
2018 if (!tx_buf->data)
2019 break;
2020
2021 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
2022 if (tx_buf->type == MTK_TYPE_SKB) {
2023 struct sk_buff *skb = tx_buf->data;
2024
2025 bytes[mac] += skb->len;
2026 done[mac]++;
2027 }
2028 budget--;
2029 }
2030 mtk_tx_unmap(eth, tx_buf, &bq, true);
2031
2032 ring->last_free = desc;
2033 atomic_inc(&ring->free_count);
2034
2035 cpu = next_cpu;
2036 }
2037 xdp_flush_frame_bulk(&bq);
2038
2039 ring->last_free_ptr = cpu;
2040 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr);
2041
2042 return budget;
2043 }
2044
mtk_poll_tx_pdma(struct mtk_eth * eth,int budget,unsigned int * done,unsigned int * bytes)2045 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
2046 unsigned int *done, unsigned int *bytes)
2047 {
2048 struct mtk_tx_ring *ring = ð->tx_ring;
2049 struct mtk_tx_buf *tx_buf;
2050 struct xdp_frame_bulk bq;
2051 struct mtk_tx_dma *desc;
2052 u32 cpu, dma;
2053
2054 cpu = ring->cpu_idx;
2055 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0);
2056 xdp_frame_bulk_init(&bq);
2057
2058 while ((cpu != dma) && budget) {
2059 tx_buf = &ring->buf[cpu];
2060 if (!tx_buf->data)
2061 break;
2062
2063 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
2064 if (tx_buf->type == MTK_TYPE_SKB) {
2065 struct sk_buff *skb = tx_buf->data;
2066
2067 bytes[0] += skb->len;
2068 done[0]++;
2069 }
2070 budget--;
2071 }
2072 mtk_tx_unmap(eth, tx_buf, &bq, true);
2073
2074 desc = ring->dma + cpu * eth->soc->txrx.txd_size;
2075 ring->last_free = desc;
2076 atomic_inc(&ring->free_count);
2077
2078 cpu = NEXT_DESP_IDX(cpu, ring->dma_size);
2079 }
2080 xdp_flush_frame_bulk(&bq);
2081
2082 ring->cpu_idx = cpu;
2083
2084 return budget;
2085 }
2086
mtk_poll_tx(struct mtk_eth * eth,int budget)2087 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
2088 {
2089 struct mtk_tx_ring *ring = ð->tx_ring;
2090 struct dim_sample dim_sample = {};
2091 unsigned int done[MTK_MAX_DEVS];
2092 unsigned int bytes[MTK_MAX_DEVS];
2093 int total = 0, i;
2094
2095 memset(done, 0, sizeof(done));
2096 memset(bytes, 0, sizeof(bytes));
2097
2098 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2099 budget = mtk_poll_tx_qdma(eth, budget, done, bytes);
2100 else
2101 budget = mtk_poll_tx_pdma(eth, budget, done, bytes);
2102
2103 for (i = 0; i < MTK_MAC_COUNT; i++) {
2104 if (!eth->netdev[i] || !done[i])
2105 continue;
2106 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
2107 total += done[i];
2108 eth->tx_packets += done[i];
2109 eth->tx_bytes += bytes[i];
2110 }
2111
2112 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes,
2113 &dim_sample);
2114 net_dim(ð->tx_dim, dim_sample);
2115
2116 if (mtk_queue_stopped(eth) &&
2117 (atomic_read(&ring->free_count) > ring->thresh))
2118 mtk_wake_queue(eth);
2119
2120 return total;
2121 }
2122
mtk_handle_status_irq(struct mtk_eth * eth)2123 static void mtk_handle_status_irq(struct mtk_eth *eth)
2124 {
2125 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
2126
2127 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
2128 mtk_stats_update(eth);
2129 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
2130 MTK_INT_STATUS2);
2131 }
2132 }
2133
mtk_napi_tx(struct napi_struct * napi,int budget)2134 static int mtk_napi_tx(struct napi_struct *napi, int budget)
2135 {
2136 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
2137 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2138 int tx_done = 0;
2139
2140 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2141 mtk_handle_status_irq(eth);
2142 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status);
2143 tx_done = mtk_poll_tx(eth, budget);
2144
2145 if (unlikely(netif_msg_intr(eth))) {
2146 dev_info(eth->dev,
2147 "done tx %d, intr 0x%08x/0x%x\n", tx_done,
2148 mtk_r32(eth, reg_map->tx_irq_status),
2149 mtk_r32(eth, reg_map->tx_irq_mask));
2150 }
2151
2152 if (tx_done == budget)
2153 return budget;
2154
2155 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
2156 return budget;
2157
2158 if (napi_complete_done(napi, tx_done))
2159 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2160
2161 return tx_done;
2162 }
2163
mtk_napi_rx(struct napi_struct * napi,int budget)2164 static int mtk_napi_rx(struct napi_struct *napi, int budget)
2165 {
2166 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
2167 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2168 int rx_done_total = 0;
2169
2170 mtk_handle_status_irq(eth);
2171
2172 do {
2173 int rx_done;
2174
2175 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
2176 reg_map->pdma.irq_status);
2177 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
2178 rx_done_total += rx_done;
2179
2180 if (unlikely(netif_msg_intr(eth))) {
2181 dev_info(eth->dev,
2182 "done rx %d, intr 0x%08x/0x%x\n", rx_done,
2183 mtk_r32(eth, reg_map->pdma.irq_status),
2184 mtk_r32(eth, reg_map->pdma.irq_mask));
2185 }
2186
2187 if (rx_done_total == budget)
2188 return budget;
2189
2190 } while (mtk_r32(eth, reg_map->pdma.irq_status) &
2191 eth->soc->txrx.rx_irq_done_mask);
2192
2193 if (napi_complete_done(napi, rx_done_total))
2194 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
2195
2196 return rx_done_total;
2197 }
2198
mtk_tx_alloc(struct mtk_eth * eth)2199 static int mtk_tx_alloc(struct mtk_eth *eth)
2200 {
2201 const struct mtk_soc_data *soc = eth->soc;
2202 struct mtk_tx_ring *ring = ð->tx_ring;
2203 int i, sz = soc->txrx.txd_size;
2204 struct mtk_tx_dma_v2 *txd;
2205
2206 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
2207 GFP_KERNEL);
2208 if (!ring->buf)
2209 goto no_tx_mem;
2210
2211 ring->dma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz,
2212 &ring->phys, GFP_KERNEL);
2213 if (!ring->dma)
2214 goto no_tx_mem;
2215
2216 for (i = 0; i < MTK_DMA_SIZE; i++) {
2217 int next = (i + 1) % MTK_DMA_SIZE;
2218 u32 next_ptr = ring->phys + next * sz;
2219
2220 txd = ring->dma + i * sz;
2221 txd->txd2 = next_ptr;
2222 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
2223 txd->txd4 = 0;
2224 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
2225 txd->txd5 = 0;
2226 txd->txd6 = 0;
2227 txd->txd7 = 0;
2228 txd->txd8 = 0;
2229 }
2230 }
2231
2232 /* On MT7688 (PDMA only) this driver uses the ring->dma structs
2233 * only as the framework. The real HW descriptors are the PDMA
2234 * descriptors in ring->dma_pdma.
2235 */
2236 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
2237 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz,
2238 &ring->phys_pdma, GFP_KERNEL);
2239 if (!ring->dma_pdma)
2240 goto no_tx_mem;
2241
2242 for (i = 0; i < MTK_DMA_SIZE; i++) {
2243 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF;
2244 ring->dma_pdma[i].txd4 = 0;
2245 }
2246 }
2247
2248 ring->dma_size = MTK_DMA_SIZE;
2249 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
2250 ring->next_free = ring->dma;
2251 ring->last_free = (void *)txd;
2252 ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz));
2253 ring->thresh = MAX_SKB_FRAGS;
2254
2255 /* make sure that all changes to the dma ring are flushed before we
2256 * continue
2257 */
2258 wmb();
2259
2260 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
2261 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr);
2262 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr);
2263 mtk_w32(eth,
2264 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
2265 soc->reg_map->qdma.crx_ptr);
2266 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr);
2267 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES,
2268 soc->reg_map->qdma.qtx_cfg);
2269 } else {
2270 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
2271 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0);
2272 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
2273 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);
2274 }
2275
2276 return 0;
2277
2278 no_tx_mem:
2279 return -ENOMEM;
2280 }
2281
mtk_tx_clean(struct mtk_eth * eth)2282 static void mtk_tx_clean(struct mtk_eth *eth)
2283 {
2284 const struct mtk_soc_data *soc = eth->soc;
2285 struct mtk_tx_ring *ring = ð->tx_ring;
2286 int i;
2287
2288 if (ring->buf) {
2289 for (i = 0; i < MTK_DMA_SIZE; i++)
2290 mtk_tx_unmap(eth, &ring->buf[i], NULL, false);
2291 kfree(ring->buf);
2292 ring->buf = NULL;
2293 }
2294
2295 if (ring->dma) {
2296 dma_free_coherent(eth->dma_dev,
2297 MTK_DMA_SIZE * soc->txrx.txd_size,
2298 ring->dma, ring->phys);
2299 ring->dma = NULL;
2300 }
2301
2302 if (ring->dma_pdma) {
2303 dma_free_coherent(eth->dma_dev,
2304 MTK_DMA_SIZE * soc->txrx.txd_size,
2305 ring->dma_pdma, ring->phys_pdma);
2306 ring->dma_pdma = NULL;
2307 }
2308 }
2309
mtk_rx_alloc(struct mtk_eth * eth,int ring_no,int rx_flag)2310 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
2311 {
2312 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2313 struct mtk_rx_ring *ring;
2314 int rx_data_len, rx_dma_size;
2315 int i;
2316
2317 if (rx_flag == MTK_RX_FLAGS_QDMA) {
2318 if (ring_no)
2319 return -EINVAL;
2320 ring = ð->rx_ring_qdma;
2321 } else {
2322 ring = ð->rx_ring[ring_no];
2323 }
2324
2325 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
2326 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
2327 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
2328 } else {
2329 rx_data_len = ETH_DATA_LEN;
2330 rx_dma_size = MTK_DMA_SIZE;
2331 }
2332
2333 ring->frag_size = mtk_max_frag_size(rx_data_len);
2334 ring->buf_size = mtk_max_buf_size(ring->frag_size);
2335 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
2336 GFP_KERNEL);
2337 if (!ring->data)
2338 return -ENOMEM;
2339
2340 if (mtk_page_pool_enabled(eth)) {
2341 struct page_pool *pp;
2342
2343 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no,
2344 rx_dma_size);
2345 if (IS_ERR(pp))
2346 return PTR_ERR(pp);
2347
2348 ring->page_pool = pp;
2349 }
2350
2351 ring->dma = dma_alloc_coherent(eth->dma_dev,
2352 rx_dma_size * eth->soc->txrx.rxd_size,
2353 &ring->phys, GFP_KERNEL);
2354 if (!ring->dma)
2355 return -ENOMEM;
2356
2357 for (i = 0; i < rx_dma_size; i++) {
2358 struct mtk_rx_dma_v2 *rxd;
2359 dma_addr_t dma_addr;
2360 void *data;
2361
2362 rxd = ring->dma + i * eth->soc->txrx.rxd_size;
2363 if (ring->page_pool) {
2364 data = mtk_page_pool_get_buff(ring->page_pool,
2365 &dma_addr, GFP_KERNEL);
2366 if (!data)
2367 return -ENOMEM;
2368 } else {
2369 if (ring->frag_size <= PAGE_SIZE)
2370 data = netdev_alloc_frag(ring->frag_size);
2371 else
2372 data = mtk_max_lro_buf_alloc(GFP_KERNEL);
2373
2374 if (!data)
2375 return -ENOMEM;
2376
2377 dma_addr = dma_map_single(eth->dma_dev,
2378 data + NET_SKB_PAD + eth->ip_align,
2379 ring->buf_size, DMA_FROM_DEVICE);
2380 if (unlikely(dma_mapping_error(eth->dma_dev,
2381 dma_addr))) {
2382 skb_free_frag(data);
2383 return -ENOMEM;
2384 }
2385 }
2386 rxd->rxd1 = (unsigned int)dma_addr;
2387 ring->data[i] = data;
2388
2389 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2390 rxd->rxd2 = RX_DMA_LSO;
2391 else
2392 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
2393
2394 rxd->rxd3 = 0;
2395 rxd->rxd4 = 0;
2396 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
2397 rxd->rxd5 = 0;
2398 rxd->rxd6 = 0;
2399 rxd->rxd7 = 0;
2400 rxd->rxd8 = 0;
2401 }
2402 }
2403
2404 ring->dma_size = rx_dma_size;
2405 ring->calc_idx_update = false;
2406 ring->calc_idx = rx_dma_size - 1;
2407 if (rx_flag == MTK_RX_FLAGS_QDMA)
2408 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr +
2409 ring_no * MTK_QRX_OFFSET;
2410 else
2411 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr +
2412 ring_no * MTK_QRX_OFFSET;
2413 /* make sure that all changes to the dma ring are flushed before we
2414 * continue
2415 */
2416 wmb();
2417
2418 if (rx_flag == MTK_RX_FLAGS_QDMA) {
2419 mtk_w32(eth, ring->phys,
2420 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET);
2421 mtk_w32(eth, rx_dma_size,
2422 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);
2423 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2424 reg_map->qdma.rst_idx);
2425 } else {
2426 mtk_w32(eth, ring->phys,
2427 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET);
2428 mtk_w32(eth, rx_dma_size,
2429 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);
2430 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2431 reg_map->pdma.rst_idx);
2432 }
2433 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
2434
2435 return 0;
2436 }
2437
mtk_rx_clean(struct mtk_eth * eth,struct mtk_rx_ring * ring)2438 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
2439 {
2440 int i;
2441
2442 if (ring->data && ring->dma) {
2443 for (i = 0; i < ring->dma_size; i++) {
2444 struct mtk_rx_dma *rxd;
2445
2446 if (!ring->data[i])
2447 continue;
2448
2449 rxd = ring->dma + i * eth->soc->txrx.rxd_size;
2450 if (!rxd->rxd1)
2451 continue;
2452
2453 dma_unmap_single(eth->dma_dev, rxd->rxd1,
2454 ring->buf_size, DMA_FROM_DEVICE);
2455 mtk_rx_put_buff(ring, ring->data[i], false);
2456 }
2457 kfree(ring->data);
2458 ring->data = NULL;
2459 }
2460
2461 if (ring->dma) {
2462 dma_free_coherent(eth->dma_dev,
2463 ring->dma_size * eth->soc->txrx.rxd_size,
2464 ring->dma, ring->phys);
2465 ring->dma = NULL;
2466 }
2467
2468 if (ring->page_pool) {
2469 if (xdp_rxq_info_is_reg(&ring->xdp_q))
2470 xdp_rxq_info_unreg(&ring->xdp_q);
2471 page_pool_destroy(ring->page_pool);
2472 ring->page_pool = NULL;
2473 }
2474 }
2475
mtk_hwlro_rx_init(struct mtk_eth * eth)2476 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
2477 {
2478 int i;
2479 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
2480 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
2481
2482 /* set LRO rings to auto-learn modes */
2483 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
2484
2485 /* validate LRO ring */
2486 ring_ctrl_dw2 |= MTK_RING_VLD;
2487
2488 /* set AGE timer (unit: 20us) */
2489 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
2490 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
2491
2492 /* set max AGG timer (unit: 20us) */
2493 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
2494
2495 /* set max LRO AGG count */
2496 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
2497 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
2498
2499 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2500 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
2501 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
2502 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
2503 }
2504
2505 /* IPv4 checksum update enable */
2506 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
2507
2508 /* switch priority comparison to packet count mode */
2509 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
2510
2511 /* bandwidth threshold setting */
2512 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
2513
2514 /* auto-learn score delta setting */
2515 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
2516
2517 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
2518 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
2519 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
2520
2521 /* set HW LRO mode & the max aggregation count for rx packets */
2522 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
2523
2524 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
2525 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
2526
2527 /* enable HW LRO */
2528 lro_ctrl_dw0 |= MTK_LRO_EN;
2529
2530 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
2531 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
2532
2533 return 0;
2534 }
2535
mtk_hwlro_rx_uninit(struct mtk_eth * eth)2536 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
2537 {
2538 int i;
2539 u32 val;
2540
2541 /* relinquish lro rings, flush aggregated packets */
2542 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
2543
2544 /* wait for relinquishments done */
2545 for (i = 0; i < 10; i++) {
2546 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
2547 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
2548 msleep(20);
2549 continue;
2550 }
2551 break;
2552 }
2553
2554 /* invalidate lro rings */
2555 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
2556 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
2557
2558 /* disable HW LRO */
2559 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
2560 }
2561
mtk_hwlro_val_ipaddr(struct mtk_eth * eth,int idx,__be32 ip)2562 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
2563 {
2564 u32 reg_val;
2565
2566 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
2567
2568 /* invalidate the IP setting */
2569 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2570
2571 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
2572
2573 /* validate the IP setting */
2574 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2575 }
2576
mtk_hwlro_inval_ipaddr(struct mtk_eth * eth,int idx)2577 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
2578 {
2579 u32 reg_val;
2580
2581 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
2582
2583 /* invalidate the IP setting */
2584 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2585
2586 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
2587 }
2588
mtk_hwlro_get_ip_cnt(struct mtk_mac * mac)2589 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
2590 {
2591 int cnt = 0;
2592 int i;
2593
2594 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2595 if (mac->hwlro_ip[i])
2596 cnt++;
2597 }
2598
2599 return cnt;
2600 }
2601
mtk_hwlro_add_ipaddr(struct net_device * dev,struct ethtool_rxnfc * cmd)2602 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
2603 struct ethtool_rxnfc *cmd)
2604 {
2605 struct ethtool_rx_flow_spec *fsp =
2606 (struct ethtool_rx_flow_spec *)&cmd->fs;
2607 struct mtk_mac *mac = netdev_priv(dev);
2608 struct mtk_eth *eth = mac->hw;
2609 int hwlro_idx;
2610
2611 if ((fsp->flow_type != TCP_V4_FLOW) ||
2612 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
2613 (fsp->location > 1))
2614 return -EINVAL;
2615
2616 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
2617 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
2618
2619 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2620
2621 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
2622
2623 return 0;
2624 }
2625
mtk_hwlro_del_ipaddr(struct net_device * dev,struct ethtool_rxnfc * cmd)2626 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
2627 struct ethtool_rxnfc *cmd)
2628 {
2629 struct ethtool_rx_flow_spec *fsp =
2630 (struct ethtool_rx_flow_spec *)&cmd->fs;
2631 struct mtk_mac *mac = netdev_priv(dev);
2632 struct mtk_eth *eth = mac->hw;
2633 int hwlro_idx;
2634
2635 if (fsp->location > 1)
2636 return -EINVAL;
2637
2638 mac->hwlro_ip[fsp->location] = 0;
2639 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
2640
2641 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2642
2643 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
2644
2645 return 0;
2646 }
2647
mtk_hwlro_netdev_disable(struct net_device * dev)2648 static void mtk_hwlro_netdev_disable(struct net_device *dev)
2649 {
2650 struct mtk_mac *mac = netdev_priv(dev);
2651 struct mtk_eth *eth = mac->hw;
2652 int i, hwlro_idx;
2653
2654 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2655 mac->hwlro_ip[i] = 0;
2656 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
2657
2658 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
2659 }
2660
2661 mac->hwlro_ip_cnt = 0;
2662 }
2663
mtk_hwlro_get_fdir_entry(struct net_device * dev,struct ethtool_rxnfc * cmd)2664 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
2665 struct ethtool_rxnfc *cmd)
2666 {
2667 struct mtk_mac *mac = netdev_priv(dev);
2668 struct ethtool_rx_flow_spec *fsp =
2669 (struct ethtool_rx_flow_spec *)&cmd->fs;
2670
2671 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip))
2672 return -EINVAL;
2673
2674 /* only tcp dst ipv4 is meaningful, others are meaningless */
2675 fsp->flow_type = TCP_V4_FLOW;
2676 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
2677 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
2678
2679 fsp->h_u.tcp_ip4_spec.ip4src = 0;
2680 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
2681 fsp->h_u.tcp_ip4_spec.psrc = 0;
2682 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
2683 fsp->h_u.tcp_ip4_spec.pdst = 0;
2684 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
2685 fsp->h_u.tcp_ip4_spec.tos = 0;
2686 fsp->m_u.tcp_ip4_spec.tos = 0xff;
2687
2688 return 0;
2689 }
2690
mtk_hwlro_get_fdir_all(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)2691 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
2692 struct ethtool_rxnfc *cmd,
2693 u32 *rule_locs)
2694 {
2695 struct mtk_mac *mac = netdev_priv(dev);
2696 int cnt = 0;
2697 int i;
2698
2699 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2700 if (mac->hwlro_ip[i]) {
2701 rule_locs[cnt] = i;
2702 cnt++;
2703 }
2704 }
2705
2706 cmd->rule_cnt = cnt;
2707
2708 return 0;
2709 }
2710
mtk_fix_features(struct net_device * dev,netdev_features_t features)2711 static netdev_features_t mtk_fix_features(struct net_device *dev,
2712 netdev_features_t features)
2713 {
2714 if (!(features & NETIF_F_LRO)) {
2715 struct mtk_mac *mac = netdev_priv(dev);
2716 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2717
2718 if (ip_cnt) {
2719 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
2720
2721 features |= NETIF_F_LRO;
2722 }
2723 }
2724
2725 return features;
2726 }
2727
mtk_set_features(struct net_device * dev,netdev_features_t features)2728 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
2729 {
2730 int err = 0;
2731
2732 if (!((dev->features ^ features) & NETIF_F_LRO))
2733 return 0;
2734
2735 if (!(features & NETIF_F_LRO))
2736 mtk_hwlro_netdev_disable(dev);
2737
2738 return err;
2739 }
2740
2741 /* wait for DMA to finish whatever it is doing before we start using it again */
mtk_dma_busy_wait(struct mtk_eth * eth)2742 static int mtk_dma_busy_wait(struct mtk_eth *eth)
2743 {
2744 unsigned int reg;
2745 int ret;
2746 u32 val;
2747
2748 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2749 reg = eth->soc->reg_map->qdma.glo_cfg;
2750 else
2751 reg = eth->soc->reg_map->pdma.glo_cfg;
2752
2753 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val,
2754 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)),
2755 5, MTK_DMA_BUSY_TIMEOUT_US);
2756 if (ret)
2757 dev_err(eth->dev, "DMA init timeout\n");
2758
2759 return ret;
2760 }
2761
mtk_dma_init(struct mtk_eth * eth)2762 static int mtk_dma_init(struct mtk_eth *eth)
2763 {
2764 int err;
2765 u32 i;
2766
2767 if (mtk_dma_busy_wait(eth))
2768 return -EBUSY;
2769
2770 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2771 /* QDMA needs scratch memory for internal reordering of the
2772 * descriptors
2773 */
2774 err = mtk_init_fq_dma(eth);
2775 if (err)
2776 return err;
2777 }
2778
2779 err = mtk_tx_alloc(eth);
2780 if (err)
2781 return err;
2782
2783 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2784 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
2785 if (err)
2786 return err;
2787 }
2788
2789 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
2790 if (err)
2791 return err;
2792
2793 if (eth->hwlro) {
2794 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2795 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
2796 if (err)
2797 return err;
2798 }
2799 err = mtk_hwlro_rx_init(eth);
2800 if (err)
2801 return err;
2802 }
2803
2804 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2805 /* Enable random early drop and set drop threshold
2806 * automatically
2807 */
2808 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
2809 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th);
2810 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred);
2811 }
2812
2813 return 0;
2814 }
2815
mtk_dma_free(struct mtk_eth * eth)2816 static void mtk_dma_free(struct mtk_eth *eth)
2817 {
2818 const struct mtk_soc_data *soc = eth->soc;
2819 int i;
2820
2821 for (i = 0; i < MTK_MAC_COUNT; i++)
2822 if (eth->netdev[i])
2823 netdev_reset_queue(eth->netdev[i]);
2824 if (eth->scratch_ring) {
2825 dma_free_coherent(eth->dma_dev,
2826 MTK_DMA_SIZE * soc->txrx.txd_size,
2827 eth->scratch_ring, eth->phy_scratch_ring);
2828 eth->scratch_ring = NULL;
2829 eth->phy_scratch_ring = 0;
2830 }
2831 mtk_tx_clean(eth);
2832 mtk_rx_clean(eth, ð->rx_ring[0]);
2833 mtk_rx_clean(eth, ð->rx_ring_qdma);
2834
2835 if (eth->hwlro) {
2836 mtk_hwlro_rx_uninit(eth);
2837 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
2838 mtk_rx_clean(eth, ð->rx_ring[i]);
2839 }
2840
2841 kfree(eth->scratch_head);
2842 }
2843
mtk_tx_timeout(struct net_device * dev,unsigned int txqueue)2844 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue)
2845 {
2846 struct mtk_mac *mac = netdev_priv(dev);
2847 struct mtk_eth *eth = mac->hw;
2848
2849 eth->netdev[mac->id]->stats.tx_errors++;
2850 netif_err(eth, tx_err, dev,
2851 "transmit timed out\n");
2852 schedule_work(ð->pending_work);
2853 }
2854
mtk_handle_irq_rx(int irq,void * _eth)2855 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
2856 {
2857 struct mtk_eth *eth = _eth;
2858
2859 eth->rx_events++;
2860 if (likely(napi_schedule_prep(ð->rx_napi))) {
2861 __napi_schedule(ð->rx_napi);
2862 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
2863 }
2864
2865 return IRQ_HANDLED;
2866 }
2867
mtk_handle_irq_tx(int irq,void * _eth)2868 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
2869 {
2870 struct mtk_eth *eth = _eth;
2871
2872 eth->tx_events++;
2873 if (likely(napi_schedule_prep(ð->tx_napi))) {
2874 __napi_schedule(ð->tx_napi);
2875 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2876 }
2877
2878 return IRQ_HANDLED;
2879 }
2880
mtk_handle_irq(int irq,void * _eth)2881 static irqreturn_t mtk_handle_irq(int irq, void *_eth)
2882 {
2883 struct mtk_eth *eth = _eth;
2884 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2885
2886 if (mtk_r32(eth, reg_map->pdma.irq_mask) &
2887 eth->soc->txrx.rx_irq_done_mask) {
2888 if (mtk_r32(eth, reg_map->pdma.irq_status) &
2889 eth->soc->txrx.rx_irq_done_mask)
2890 mtk_handle_irq_rx(irq, _eth);
2891 }
2892 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
2893 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
2894 mtk_handle_irq_tx(irq, _eth);
2895 }
2896
2897 return IRQ_HANDLED;
2898 }
2899
2900 #ifdef CONFIG_NET_POLL_CONTROLLER
mtk_poll_controller(struct net_device * dev)2901 static void mtk_poll_controller(struct net_device *dev)
2902 {
2903 struct mtk_mac *mac = netdev_priv(dev);
2904 struct mtk_eth *eth = mac->hw;
2905
2906 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2907 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
2908 mtk_handle_irq_rx(eth->irq[2], dev);
2909 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2910 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
2911 }
2912 #endif
2913
mtk_start_dma(struct mtk_eth * eth)2914 static int mtk_start_dma(struct mtk_eth *eth)
2915 {
2916 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
2917 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2918 int err;
2919
2920 err = mtk_dma_init(eth);
2921 if (err) {
2922 mtk_dma_free(eth);
2923 return err;
2924 }
2925
2926 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2927 val = mtk_r32(eth, reg_map->qdma.glo_cfg);
2928 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN |
2929 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
2930 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
2931
2932 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
2933 val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
2934 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
2935 MTK_CHK_DDONE_EN;
2936 else
2937 val |= MTK_RX_BT_32DWORDS;
2938 mtk_w32(eth, val, reg_map->qdma.glo_cfg);
2939
2940 mtk_w32(eth,
2941 MTK_RX_DMA_EN | rx_2b_offset |
2942 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
2943 reg_map->pdma.glo_cfg);
2944 } else {
2945 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
2946 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS,
2947 reg_map->pdma.glo_cfg);
2948 }
2949
2950 return 0;
2951 }
2952
mtk_gdm_config(struct mtk_eth * eth,u32 config)2953 static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
2954 {
2955 int i;
2956
2957 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2958 return;
2959
2960 for (i = 0; i < MTK_MAC_COUNT; i++) {
2961 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
2962
2963 /* default setup the forward port to send frame to PDMA */
2964 val &= ~0xffff;
2965
2966 /* Enable RX checksum */
2967 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
2968
2969 val |= config;
2970
2971 if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0]))
2972 val |= MTK_GDMA_SPECIAL_TAG;
2973
2974 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
2975 }
2976 /* Reset and enable PSE */
2977 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
2978 mtk_w32(eth, 0, MTK_RST_GL);
2979 }
2980
mtk_open(struct net_device * dev)2981 static int mtk_open(struct net_device *dev)
2982 {
2983 struct mtk_mac *mac = netdev_priv(dev);
2984 struct mtk_eth *eth = mac->hw;
2985 int err;
2986
2987 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
2988 if (err) {
2989 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
2990 err);
2991 return err;
2992 }
2993
2994 /* we run 2 netdevs on the same dma ring so we only bring it up once */
2995 if (!refcount_read(ð->dma_refcnt)) {
2996 const struct mtk_soc_data *soc = eth->soc;
2997 u32 gdm_config;
2998 int i;
2999
3000 err = mtk_start_dma(eth);
3001 if (err) {
3002 phylink_disconnect_phy(mac->phylink);
3003 return err;
3004 }
3005
3006 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3007 mtk_ppe_start(eth->ppe[i]);
3008
3009 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe
3010 : MTK_GDMA_TO_PDMA;
3011 mtk_gdm_config(eth, gdm_config);
3012
3013 napi_enable(ð->tx_napi);
3014 napi_enable(ð->rx_napi);
3015 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
3016 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask);
3017 refcount_set(ð->dma_refcnt, 1);
3018 }
3019 else
3020 refcount_inc(ð->dma_refcnt);
3021
3022 phylink_start(mac->phylink);
3023 netif_start_queue(dev);
3024 return 0;
3025 }
3026
mtk_stop_dma(struct mtk_eth * eth,u32 glo_cfg)3027 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
3028 {
3029 u32 val;
3030 int i;
3031
3032 /* stop the dma engine */
3033 spin_lock_bh(ð->page_lock);
3034 val = mtk_r32(eth, glo_cfg);
3035 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
3036 glo_cfg);
3037 spin_unlock_bh(ð->page_lock);
3038
3039 /* wait for dma stop */
3040 for (i = 0; i < 10; i++) {
3041 val = mtk_r32(eth, glo_cfg);
3042 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
3043 msleep(20);
3044 continue;
3045 }
3046 break;
3047 }
3048 }
3049
mtk_stop(struct net_device * dev)3050 static int mtk_stop(struct net_device *dev)
3051 {
3052 struct mtk_mac *mac = netdev_priv(dev);
3053 struct mtk_eth *eth = mac->hw;
3054 int i;
3055
3056 phylink_stop(mac->phylink);
3057
3058 netif_tx_disable(dev);
3059
3060 phylink_disconnect_phy(mac->phylink);
3061
3062 /* only shutdown DMA if this is the last user */
3063 if (!refcount_dec_and_test(ð->dma_refcnt))
3064 return 0;
3065
3066 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
3067
3068 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
3069 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
3070 napi_disable(ð->tx_napi);
3071 napi_disable(ð->rx_napi);
3072
3073 cancel_work_sync(ð->rx_dim.work);
3074 cancel_work_sync(ð->tx_dim.work);
3075
3076 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3077 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg);
3078 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg);
3079
3080 mtk_dma_free(eth);
3081
3082 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3083 mtk_ppe_stop(eth->ppe[i]);
3084
3085 return 0;
3086 }
3087
mtk_xdp_setup(struct net_device * dev,struct bpf_prog * prog,struct netlink_ext_ack * extack)3088 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog,
3089 struct netlink_ext_ack *extack)
3090 {
3091 struct mtk_mac *mac = netdev_priv(dev);
3092 struct mtk_eth *eth = mac->hw;
3093 struct bpf_prog *old_prog;
3094 bool need_update;
3095
3096 if (eth->hwlro) {
3097 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO");
3098 return -EOPNOTSUPP;
3099 }
3100
3101 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) {
3102 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP");
3103 return -EOPNOTSUPP;
3104 }
3105
3106 need_update = !!eth->prog != !!prog;
3107 if (netif_running(dev) && need_update)
3108 mtk_stop(dev);
3109
3110 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held());
3111 if (old_prog)
3112 bpf_prog_put(old_prog);
3113
3114 if (netif_running(dev) && need_update)
3115 return mtk_open(dev);
3116
3117 return 0;
3118 }
3119
mtk_xdp(struct net_device * dev,struct netdev_bpf * xdp)3120 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3121 {
3122 switch (xdp->command) {
3123 case XDP_SETUP_PROG:
3124 return mtk_xdp_setup(dev, xdp->prog, xdp->extack);
3125 default:
3126 return -EINVAL;
3127 }
3128 }
3129
ethsys_reset(struct mtk_eth * eth,u32 reset_bits)3130 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
3131 {
3132 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
3133 reset_bits,
3134 reset_bits);
3135
3136 usleep_range(1000, 1100);
3137 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
3138 reset_bits,
3139 ~reset_bits);
3140 mdelay(10);
3141 }
3142
mtk_clk_disable(struct mtk_eth * eth)3143 static void mtk_clk_disable(struct mtk_eth *eth)
3144 {
3145 int clk;
3146
3147 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
3148 clk_disable_unprepare(eth->clks[clk]);
3149 }
3150
mtk_clk_enable(struct mtk_eth * eth)3151 static int mtk_clk_enable(struct mtk_eth *eth)
3152 {
3153 int clk, ret;
3154
3155 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
3156 ret = clk_prepare_enable(eth->clks[clk]);
3157 if (ret)
3158 goto err_disable_clks;
3159 }
3160
3161 return 0;
3162
3163 err_disable_clks:
3164 while (--clk >= 0)
3165 clk_disable_unprepare(eth->clks[clk]);
3166
3167 return ret;
3168 }
3169
mtk_dim_rx(struct work_struct * work)3170 static void mtk_dim_rx(struct work_struct *work)
3171 {
3172 struct dim *dim = container_of(work, struct dim, work);
3173 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim);
3174 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3175 struct dim_cq_moder cur_profile;
3176 u32 val, cur;
3177
3178 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode,
3179 dim->profile_ix);
3180 spin_lock_bh(ð->dim_lock);
3181
3182 val = mtk_r32(eth, reg_map->pdma.delay_irq);
3183 val &= MTK_PDMA_DELAY_TX_MASK;
3184 val |= MTK_PDMA_DELAY_RX_EN;
3185
3186 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
3187 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT;
3188
3189 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
3190 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT;
3191
3192 mtk_w32(eth, val, reg_map->pdma.delay_irq);
3193 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3194 mtk_w32(eth, val, reg_map->qdma.delay_irq);
3195
3196 spin_unlock_bh(ð->dim_lock);
3197
3198 dim->state = DIM_START_MEASURE;
3199 }
3200
mtk_dim_tx(struct work_struct * work)3201 static void mtk_dim_tx(struct work_struct *work)
3202 {
3203 struct dim *dim = container_of(work, struct dim, work);
3204 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim);
3205 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3206 struct dim_cq_moder cur_profile;
3207 u32 val, cur;
3208
3209 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode,
3210 dim->profile_ix);
3211 spin_lock_bh(ð->dim_lock);
3212
3213 val = mtk_r32(eth, reg_map->pdma.delay_irq);
3214 val &= MTK_PDMA_DELAY_RX_MASK;
3215 val |= MTK_PDMA_DELAY_TX_EN;
3216
3217 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
3218 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT;
3219
3220 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
3221 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT;
3222
3223 mtk_w32(eth, val, reg_map->pdma.delay_irq);
3224 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3225 mtk_w32(eth, val, reg_map->qdma.delay_irq);
3226
3227 spin_unlock_bh(ð->dim_lock);
3228
3229 dim->state = DIM_START_MEASURE;
3230 }
3231
mtk_set_mcr_max_rx(struct mtk_mac * mac,u32 val)3232 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val)
3233 {
3234 struct mtk_eth *eth = mac->hw;
3235 u32 mcr_cur, mcr_new;
3236
3237 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3238 return;
3239
3240 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
3241 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK;
3242
3243 if (val <= 1518)
3244 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518);
3245 else if (val <= 1536)
3246 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536);
3247 else if (val <= 1552)
3248 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552);
3249 else
3250 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048);
3251
3252 if (mcr_new != mcr_cur)
3253 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
3254 }
3255
mtk_hw_init(struct mtk_eth * eth)3256 static int mtk_hw_init(struct mtk_eth *eth)
3257 {
3258 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
3259 ETHSYS_DMA_AG_MAP_PPE;
3260 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3261 int i, val, ret;
3262
3263 if (test_and_set_bit(MTK_HW_INIT, ð->state))
3264 return 0;
3265
3266 pm_runtime_enable(eth->dev);
3267 pm_runtime_get_sync(eth->dev);
3268
3269 ret = mtk_clk_enable(eth);
3270 if (ret)
3271 goto err_disable_pm;
3272
3273 if (eth->ethsys)
3274 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,
3275 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask);
3276
3277 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
3278 ret = device_reset(eth->dev);
3279 if (ret) {
3280 dev_err(eth->dev, "MAC reset failed!\n");
3281 goto err_disable_pm;
3282 }
3283
3284 /* set interrupt delays based on current Net DIM sample */
3285 mtk_dim_rx(ð->rx_dim.work);
3286 mtk_dim_tx(ð->tx_dim.work);
3287
3288 /* disable delay and normal interrupt */
3289 mtk_tx_irq_disable(eth, ~0);
3290 mtk_rx_irq_disable(eth, ~0);
3291
3292 return 0;
3293 }
3294
3295 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
3296 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
3297 val = RSTCTRL_PPE0_V2;
3298 } else {
3299 val = RSTCTRL_PPE0;
3300 }
3301
3302 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3303 val |= RSTCTRL_PPE1;
3304
3305 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
3306
3307 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
3308 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
3309 0x3ffffff);
3310
3311 /* Set FE to PDMAv2 if necessary */
3312 val = mtk_r32(eth, MTK_FE_GLO_MISC);
3313 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
3314 }
3315
3316 if (eth->pctl) {
3317 /* Set GE2 driving and slew rate */
3318 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
3319
3320 /* set GE2 TDSEL */
3321 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
3322
3323 /* set GE2 TUNE */
3324 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
3325 }
3326
3327 /* Set linkdown as the default for each GMAC. Its own MCR would be set
3328 * up with the more appropriate value when mtk_mac_config call is being
3329 * invoked.
3330 */
3331 for (i = 0; i < MTK_MAC_COUNT; i++) {
3332 struct net_device *dev = eth->netdev[i];
3333
3334 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
3335 if (dev) {
3336 struct mtk_mac *mac = netdev_priv(dev);
3337
3338 mtk_set_mcr_max_rx(mac, dev->mtu + MTK_RX_ETH_HLEN);
3339 }
3340 }
3341
3342 /* Indicates CDM to parse the MTK special tag from CPU
3343 * which also is working out for untag packets.
3344 */
3345 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
3346 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
3347
3348 /* Enable RX VLan Offloading */
3349 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
3350
3351 /* set interrupt delays based on current Net DIM sample */
3352 mtk_dim_rx(ð->rx_dim.work);
3353 mtk_dim_tx(ð->tx_dim.work);
3354
3355 /* disable delay and normal interrupt */
3356 mtk_tx_irq_disable(eth, ~0);
3357 mtk_rx_irq_disable(eth, ~0);
3358
3359 /* FE int grouping */
3360 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
3361 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);
3362 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
3363 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
3364 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
3365
3366 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
3367 /* PSE should not drop port8 and port9 packets from WDMA Tx */
3368 mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
3369
3370 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */
3371 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP);
3372
3373 /* PSE Free Queue Flow Control */
3374 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2);
3375
3376 /* PSE config input queue threshold */
3377 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1));
3378 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2));
3379 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3));
3380 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4));
3381 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5));
3382 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6));
3383 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7));
3384 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8));
3385
3386 /* PSE config output queue threshold */
3387 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1));
3388 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2));
3389 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3));
3390 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4));
3391 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5));
3392 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6));
3393 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7));
3394 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8));
3395
3396 /* GDM and CDM Threshold */
3397 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES);
3398 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES);
3399 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES);
3400 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES);
3401 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES);
3402 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES);
3403 }
3404
3405 return 0;
3406
3407 err_disable_pm:
3408 pm_runtime_put_sync(eth->dev);
3409 pm_runtime_disable(eth->dev);
3410
3411 return ret;
3412 }
3413
mtk_hw_deinit(struct mtk_eth * eth)3414 static int mtk_hw_deinit(struct mtk_eth *eth)
3415 {
3416 if (!test_and_clear_bit(MTK_HW_INIT, ð->state))
3417 return 0;
3418
3419 mtk_clk_disable(eth);
3420
3421 pm_runtime_put_sync(eth->dev);
3422 pm_runtime_disable(eth->dev);
3423
3424 return 0;
3425 }
3426
mtk_init(struct net_device * dev)3427 static int __init mtk_init(struct net_device *dev)
3428 {
3429 struct mtk_mac *mac = netdev_priv(dev);
3430 struct mtk_eth *eth = mac->hw;
3431 int ret;
3432
3433 ret = of_get_ethdev_address(mac->of_node, dev);
3434 if (ret) {
3435 /* If the mac address is invalid, use random mac address */
3436 eth_hw_addr_random(dev);
3437 dev_err(eth->dev, "generated random MAC address %pM\n",
3438 dev->dev_addr);
3439 }
3440
3441 return 0;
3442 }
3443
mtk_uninit(struct net_device * dev)3444 static void mtk_uninit(struct net_device *dev)
3445 {
3446 struct mtk_mac *mac = netdev_priv(dev);
3447 struct mtk_eth *eth = mac->hw;
3448
3449 phylink_disconnect_phy(mac->phylink);
3450 mtk_tx_irq_disable(eth, ~0);
3451 mtk_rx_irq_disable(eth, ~0);
3452 }
3453
mtk_change_mtu(struct net_device * dev,int new_mtu)3454 static int mtk_change_mtu(struct net_device *dev, int new_mtu)
3455 {
3456 int length = new_mtu + MTK_RX_ETH_HLEN;
3457 struct mtk_mac *mac = netdev_priv(dev);
3458 struct mtk_eth *eth = mac->hw;
3459
3460 if (rcu_access_pointer(eth->prog) &&
3461 length > MTK_PP_MAX_BUF_SIZE) {
3462 netdev_err(dev, "Invalid MTU for XDP mode\n");
3463 return -EINVAL;
3464 }
3465
3466 mtk_set_mcr_max_rx(mac, length);
3467 dev->mtu = new_mtu;
3468
3469 return 0;
3470 }
3471
mtk_do_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)3472 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3473 {
3474 struct mtk_mac *mac = netdev_priv(dev);
3475
3476 switch (cmd) {
3477 case SIOCGMIIPHY:
3478 case SIOCGMIIREG:
3479 case SIOCSMIIREG:
3480 return phylink_mii_ioctl(mac->phylink, ifr, cmd);
3481 default:
3482 break;
3483 }
3484
3485 return -EOPNOTSUPP;
3486 }
3487
mtk_pending_work(struct work_struct * work)3488 static void mtk_pending_work(struct work_struct *work)
3489 {
3490 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
3491 int err, i;
3492 unsigned long restart = 0;
3493
3494 rtnl_lock();
3495
3496 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
3497
3498 while (test_and_set_bit_lock(MTK_RESETTING, ð->state))
3499 cpu_relax();
3500
3501 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
3502 /* stop all devices to make sure that dma is properly shut down */
3503 for (i = 0; i < MTK_MAC_COUNT; i++) {
3504 if (!eth->netdev[i])
3505 continue;
3506 mtk_stop(eth->netdev[i]);
3507 __set_bit(i, &restart);
3508 }
3509 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
3510
3511 /* restart underlying hardware such as power, clock, pin mux
3512 * and the connected phy
3513 */
3514 mtk_hw_deinit(eth);
3515
3516 if (eth->dev->pins)
3517 pinctrl_select_state(eth->dev->pins->p,
3518 eth->dev->pins->default_state);
3519 mtk_hw_init(eth);
3520
3521 /* restart DMA and enable IRQs */
3522 for (i = 0; i < MTK_MAC_COUNT; i++) {
3523 if (!test_bit(i, &restart))
3524 continue;
3525 err = mtk_open(eth->netdev[i]);
3526 if (err) {
3527 netif_alert(eth, ifup, eth->netdev[i],
3528 "Driver up/down cycle failed, closing device.\n");
3529 dev_close(eth->netdev[i]);
3530 }
3531 }
3532
3533 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
3534
3535 clear_bit_unlock(MTK_RESETTING, ð->state);
3536
3537 rtnl_unlock();
3538 }
3539
mtk_free_dev(struct mtk_eth * eth)3540 static int mtk_free_dev(struct mtk_eth *eth)
3541 {
3542 int i;
3543
3544 for (i = 0; i < MTK_MAC_COUNT; i++) {
3545 if (!eth->netdev[i])
3546 continue;
3547 free_netdev(eth->netdev[i]);
3548 }
3549
3550 return 0;
3551 }
3552
mtk_unreg_dev(struct mtk_eth * eth)3553 static int mtk_unreg_dev(struct mtk_eth *eth)
3554 {
3555 int i;
3556
3557 for (i = 0; i < MTK_MAC_COUNT; i++) {
3558 if (!eth->netdev[i])
3559 continue;
3560 unregister_netdev(eth->netdev[i]);
3561 }
3562
3563 return 0;
3564 }
3565
mtk_cleanup(struct mtk_eth * eth)3566 static int mtk_cleanup(struct mtk_eth *eth)
3567 {
3568 mtk_unreg_dev(eth);
3569 mtk_free_dev(eth);
3570 cancel_work_sync(ð->pending_work);
3571
3572 return 0;
3573 }
3574
mtk_get_link_ksettings(struct net_device * ndev,struct ethtool_link_ksettings * cmd)3575 static int mtk_get_link_ksettings(struct net_device *ndev,
3576 struct ethtool_link_ksettings *cmd)
3577 {
3578 struct mtk_mac *mac = netdev_priv(ndev);
3579
3580 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
3581 return -EBUSY;
3582
3583 return phylink_ethtool_ksettings_get(mac->phylink, cmd);
3584 }
3585
mtk_set_link_ksettings(struct net_device * ndev,const struct ethtool_link_ksettings * cmd)3586 static int mtk_set_link_ksettings(struct net_device *ndev,
3587 const struct ethtool_link_ksettings *cmd)
3588 {
3589 struct mtk_mac *mac = netdev_priv(ndev);
3590
3591 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
3592 return -EBUSY;
3593
3594 return phylink_ethtool_ksettings_set(mac->phylink, cmd);
3595 }
3596
mtk_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)3597 static void mtk_get_drvinfo(struct net_device *dev,
3598 struct ethtool_drvinfo *info)
3599 {
3600 struct mtk_mac *mac = netdev_priv(dev);
3601
3602 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
3603 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
3604 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
3605 }
3606
mtk_get_msglevel(struct net_device * dev)3607 static u32 mtk_get_msglevel(struct net_device *dev)
3608 {
3609 struct mtk_mac *mac = netdev_priv(dev);
3610
3611 return mac->hw->msg_enable;
3612 }
3613
mtk_set_msglevel(struct net_device * dev,u32 value)3614 static void mtk_set_msglevel(struct net_device *dev, u32 value)
3615 {
3616 struct mtk_mac *mac = netdev_priv(dev);
3617
3618 mac->hw->msg_enable = value;
3619 }
3620
mtk_nway_reset(struct net_device * dev)3621 static int mtk_nway_reset(struct net_device *dev)
3622 {
3623 struct mtk_mac *mac = netdev_priv(dev);
3624
3625 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
3626 return -EBUSY;
3627
3628 if (!mac->phylink)
3629 return -ENOTSUPP;
3630
3631 return phylink_ethtool_nway_reset(mac->phylink);
3632 }
3633
mtk_get_strings(struct net_device * dev,u32 stringset,u8 * data)3634 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3635 {
3636 int i;
3637
3638 switch (stringset) {
3639 case ETH_SS_STATS: {
3640 struct mtk_mac *mac = netdev_priv(dev);
3641
3642 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
3643 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
3644 data += ETH_GSTRING_LEN;
3645 }
3646 if (mtk_page_pool_enabled(mac->hw))
3647 page_pool_ethtool_stats_get_strings(data);
3648 break;
3649 }
3650 default:
3651 break;
3652 }
3653 }
3654
mtk_get_sset_count(struct net_device * dev,int sset)3655 static int mtk_get_sset_count(struct net_device *dev, int sset)
3656 {
3657 switch (sset) {
3658 case ETH_SS_STATS: {
3659 int count = ARRAY_SIZE(mtk_ethtool_stats);
3660 struct mtk_mac *mac = netdev_priv(dev);
3661
3662 if (mtk_page_pool_enabled(mac->hw))
3663 count += page_pool_ethtool_stats_get_count();
3664 return count;
3665 }
3666 default:
3667 return -EOPNOTSUPP;
3668 }
3669 }
3670
mtk_ethtool_pp_stats(struct mtk_eth * eth,u64 * data)3671 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data)
3672 {
3673 struct page_pool_stats stats = {};
3674 int i;
3675
3676 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) {
3677 struct mtk_rx_ring *ring = ð->rx_ring[i];
3678
3679 if (!ring->page_pool)
3680 continue;
3681
3682 page_pool_get_stats(ring->page_pool, &stats);
3683 }
3684 page_pool_ethtool_stats_get(data, &stats);
3685 }
3686
mtk_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)3687 static void mtk_get_ethtool_stats(struct net_device *dev,
3688 struct ethtool_stats *stats, u64 *data)
3689 {
3690 struct mtk_mac *mac = netdev_priv(dev);
3691 struct mtk_hw_stats *hwstats = mac->hw_stats;
3692 u64 *data_src, *data_dst;
3693 unsigned int start;
3694 int i;
3695
3696 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
3697 return;
3698
3699 if (netif_running(dev) && netif_device_present(dev)) {
3700 if (spin_trylock_bh(&hwstats->stats_lock)) {
3701 mtk_stats_update_mac(mac);
3702 spin_unlock_bh(&hwstats->stats_lock);
3703 }
3704 }
3705
3706 data_src = (u64 *)hwstats;
3707
3708 do {
3709 data_dst = data;
3710 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
3711
3712 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
3713 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
3714 if (mtk_page_pool_enabled(mac->hw))
3715 mtk_ethtool_pp_stats(mac->hw, data_dst);
3716 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
3717 }
3718
mtk_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)3719 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
3720 u32 *rule_locs)
3721 {
3722 int ret = -EOPNOTSUPP;
3723
3724 switch (cmd->cmd) {
3725 case ETHTOOL_GRXRINGS:
3726 if (dev->hw_features & NETIF_F_LRO) {
3727 cmd->data = MTK_MAX_RX_RING_NUM;
3728 ret = 0;
3729 }
3730 break;
3731 case ETHTOOL_GRXCLSRLCNT:
3732 if (dev->hw_features & NETIF_F_LRO) {
3733 struct mtk_mac *mac = netdev_priv(dev);
3734
3735 cmd->rule_cnt = mac->hwlro_ip_cnt;
3736 ret = 0;
3737 }
3738 break;
3739 case ETHTOOL_GRXCLSRULE:
3740 if (dev->hw_features & NETIF_F_LRO)
3741 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
3742 break;
3743 case ETHTOOL_GRXCLSRLALL:
3744 if (dev->hw_features & NETIF_F_LRO)
3745 ret = mtk_hwlro_get_fdir_all(dev, cmd,
3746 rule_locs);
3747 break;
3748 default:
3749 break;
3750 }
3751
3752 return ret;
3753 }
3754
mtk_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)3755 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
3756 {
3757 int ret = -EOPNOTSUPP;
3758
3759 switch (cmd->cmd) {
3760 case ETHTOOL_SRXCLSRLINS:
3761 if (dev->hw_features & NETIF_F_LRO)
3762 ret = mtk_hwlro_add_ipaddr(dev, cmd);
3763 break;
3764 case ETHTOOL_SRXCLSRLDEL:
3765 if (dev->hw_features & NETIF_F_LRO)
3766 ret = mtk_hwlro_del_ipaddr(dev, cmd);
3767 break;
3768 default:
3769 break;
3770 }
3771
3772 return ret;
3773 }
3774
3775 static const struct ethtool_ops mtk_ethtool_ops = {
3776 .get_link_ksettings = mtk_get_link_ksettings,
3777 .set_link_ksettings = mtk_set_link_ksettings,
3778 .get_drvinfo = mtk_get_drvinfo,
3779 .get_msglevel = mtk_get_msglevel,
3780 .set_msglevel = mtk_set_msglevel,
3781 .nway_reset = mtk_nway_reset,
3782 .get_link = ethtool_op_get_link,
3783 .get_strings = mtk_get_strings,
3784 .get_sset_count = mtk_get_sset_count,
3785 .get_ethtool_stats = mtk_get_ethtool_stats,
3786 .get_rxnfc = mtk_get_rxnfc,
3787 .set_rxnfc = mtk_set_rxnfc,
3788 };
3789
3790 static const struct net_device_ops mtk_netdev_ops = {
3791 .ndo_init = mtk_init,
3792 .ndo_uninit = mtk_uninit,
3793 .ndo_open = mtk_open,
3794 .ndo_stop = mtk_stop,
3795 .ndo_start_xmit = mtk_start_xmit,
3796 .ndo_set_mac_address = mtk_set_mac_address,
3797 .ndo_validate_addr = eth_validate_addr,
3798 .ndo_eth_ioctl = mtk_do_ioctl,
3799 .ndo_change_mtu = mtk_change_mtu,
3800 .ndo_tx_timeout = mtk_tx_timeout,
3801 .ndo_get_stats64 = mtk_get_stats64,
3802 .ndo_fix_features = mtk_fix_features,
3803 .ndo_set_features = mtk_set_features,
3804 #ifdef CONFIG_NET_POLL_CONTROLLER
3805 .ndo_poll_controller = mtk_poll_controller,
3806 #endif
3807 .ndo_setup_tc = mtk_eth_setup_tc,
3808 .ndo_bpf = mtk_xdp,
3809 .ndo_xdp_xmit = mtk_xdp_xmit,
3810 };
3811
mtk_add_mac(struct mtk_eth * eth,struct device_node * np)3812 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
3813 {
3814 const __be32 *_id = of_get_property(np, "reg", NULL);
3815 phy_interface_t phy_mode;
3816 struct phylink *phylink;
3817 struct mtk_mac *mac;
3818 int id, err;
3819
3820 if (!_id) {
3821 dev_err(eth->dev, "missing mac id\n");
3822 return -EINVAL;
3823 }
3824
3825 id = be32_to_cpup(_id);
3826 if (id >= MTK_MAC_COUNT) {
3827 dev_err(eth->dev, "%d is not a valid mac id\n", id);
3828 return -EINVAL;
3829 }
3830
3831 if (eth->netdev[id]) {
3832 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
3833 return -EINVAL;
3834 }
3835
3836 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
3837 if (!eth->netdev[id]) {
3838 dev_err(eth->dev, "alloc_etherdev failed\n");
3839 return -ENOMEM;
3840 }
3841 mac = netdev_priv(eth->netdev[id]);
3842 eth->mac[id] = mac;
3843 mac->id = id;
3844 mac->hw = eth;
3845 mac->of_node = np;
3846
3847 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
3848 mac->hwlro_ip_cnt = 0;
3849
3850 mac->hw_stats = devm_kzalloc(eth->dev,
3851 sizeof(*mac->hw_stats),
3852 GFP_KERNEL);
3853 if (!mac->hw_stats) {
3854 dev_err(eth->dev, "failed to allocate counter memory\n");
3855 err = -ENOMEM;
3856 goto free_netdev;
3857 }
3858 spin_lock_init(&mac->hw_stats->stats_lock);
3859 u64_stats_init(&mac->hw_stats->syncp);
3860 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
3861
3862 /* phylink create */
3863 err = of_get_phy_mode(np, &phy_mode);
3864 if (err) {
3865 dev_err(eth->dev, "incorrect phy-mode\n");
3866 goto free_netdev;
3867 }
3868
3869 /* mac config is not set */
3870 mac->interface = PHY_INTERFACE_MODE_NA;
3871 mac->speed = SPEED_UNKNOWN;
3872
3873 mac->phylink_config.dev = ð->netdev[id]->dev;
3874 mac->phylink_config.type = PHYLINK_NETDEV;
3875 /* This driver makes use of state->speed in mac_config */
3876 mac->phylink_config.legacy_pre_march2020 = true;
3877 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
3878 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
3879
3880 __set_bit(PHY_INTERFACE_MODE_MII,
3881 mac->phylink_config.supported_interfaces);
3882 __set_bit(PHY_INTERFACE_MODE_GMII,
3883 mac->phylink_config.supported_interfaces);
3884
3885 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
3886 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
3887
3888 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
3889 __set_bit(PHY_INTERFACE_MODE_TRGMII,
3890 mac->phylink_config.supported_interfaces);
3891
3892 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
3893 __set_bit(PHY_INTERFACE_MODE_SGMII,
3894 mac->phylink_config.supported_interfaces);
3895 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
3896 mac->phylink_config.supported_interfaces);
3897 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
3898 mac->phylink_config.supported_interfaces);
3899 }
3900
3901 phylink = phylink_create(&mac->phylink_config,
3902 of_fwnode_handle(mac->of_node),
3903 phy_mode, &mtk_phylink_ops);
3904 if (IS_ERR(phylink)) {
3905 err = PTR_ERR(phylink);
3906 goto free_netdev;
3907 }
3908
3909 mac->phylink = phylink;
3910
3911 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
3912 eth->netdev[id]->watchdog_timeo = 5 * HZ;
3913 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
3914 eth->netdev[id]->base_addr = (unsigned long)eth->base;
3915
3916 eth->netdev[id]->hw_features = eth->soc->hw_features;
3917 if (eth->hwlro)
3918 eth->netdev[id]->hw_features |= NETIF_F_LRO;
3919
3920 eth->netdev[id]->vlan_features = eth->soc->hw_features &
3921 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
3922 eth->netdev[id]->features |= eth->soc->hw_features;
3923 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
3924
3925 eth->netdev[id]->irq = eth->irq[0];
3926 eth->netdev[id]->dev.of_node = np;
3927
3928 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3929 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
3930 else
3931 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
3932
3933 return 0;
3934
3935 free_netdev:
3936 free_netdev(eth->netdev[id]);
3937 return err;
3938 }
3939
mtk_eth_set_dma_device(struct mtk_eth * eth,struct device * dma_dev)3940 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
3941 {
3942 struct net_device *dev, *tmp;
3943 LIST_HEAD(dev_list);
3944 int i;
3945
3946 rtnl_lock();
3947
3948 for (i = 0; i < MTK_MAC_COUNT; i++) {
3949 dev = eth->netdev[i];
3950
3951 if (!dev || !(dev->flags & IFF_UP))
3952 continue;
3953
3954 list_add_tail(&dev->close_list, &dev_list);
3955 }
3956
3957 dev_close_many(&dev_list, false);
3958
3959 eth->dma_dev = dma_dev;
3960
3961 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) {
3962 list_del_init(&dev->close_list);
3963 dev_open(dev, NULL);
3964 }
3965
3966 rtnl_unlock();
3967 }
3968
mtk_probe(struct platform_device * pdev)3969 static int mtk_probe(struct platform_device *pdev)
3970 {
3971 struct resource *res = NULL;
3972 struct device_node *mac_np;
3973 struct mtk_eth *eth;
3974 int err, i;
3975
3976 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
3977 if (!eth)
3978 return -ENOMEM;
3979
3980 eth->soc = of_device_get_match_data(&pdev->dev);
3981
3982 eth->dev = &pdev->dev;
3983 eth->dma_dev = &pdev->dev;
3984 eth->base = devm_platform_ioremap_resource(pdev, 0);
3985 if (IS_ERR(eth->base))
3986 return PTR_ERR(eth->base);
3987
3988 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3989 eth->ip_align = NET_IP_ALIGN;
3990
3991 spin_lock_init(ð->page_lock);
3992 spin_lock_init(ð->tx_irq_lock);
3993 spin_lock_init(ð->rx_irq_lock);
3994 spin_lock_init(ð->dim_lock);
3995
3996 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
3997 INIT_WORK(ð->rx_dim.work, mtk_dim_rx);
3998
3999 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4000 INIT_WORK(ð->tx_dim.work, mtk_dim_tx);
4001
4002 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
4003 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4004 "mediatek,ethsys");
4005 if (IS_ERR(eth->ethsys)) {
4006 dev_err(&pdev->dev, "no ethsys regmap found\n");
4007 return PTR_ERR(eth->ethsys);
4008 }
4009 }
4010
4011 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) {
4012 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4013 "mediatek,infracfg");
4014 if (IS_ERR(eth->infra)) {
4015 dev_err(&pdev->dev, "no infracfg regmap found\n");
4016 return PTR_ERR(eth->infra);
4017 }
4018 }
4019
4020 if (of_dma_is_coherent(pdev->dev.of_node)) {
4021 struct regmap *cci;
4022
4023 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4024 "cci-control-port");
4025 /* enable CPU/bus coherency */
4026 if (!IS_ERR(cci))
4027 regmap_write(cci, 0, 3);
4028 }
4029
4030 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
4031 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
4032 GFP_KERNEL);
4033 if (!eth->sgmii)
4034 return -ENOMEM;
4035
4036 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node,
4037 eth->soc->ana_rgc3);
4038
4039 if (err)
4040 return err;
4041 }
4042
4043 if (eth->soc->required_pctl) {
4044 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4045 "mediatek,pctl");
4046 if (IS_ERR(eth->pctl)) {
4047 dev_err(&pdev->dev, "no pctl regmap found\n");
4048 return PTR_ERR(eth->pctl);
4049 }
4050 }
4051
4052 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
4053 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4054 if (!res)
4055 return -EINVAL;
4056 }
4057
4058 if (eth->soc->offload_version) {
4059 for (i = 0;; i++) {
4060 struct device_node *np;
4061 phys_addr_t wdma_phy;
4062 u32 wdma_base;
4063
4064 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base))
4065 break;
4066
4067 np = of_parse_phandle(pdev->dev.of_node,
4068 "mediatek,wed", i);
4069 if (!np)
4070 break;
4071
4072 wdma_base = eth->soc->reg_map->wdma_base[i];
4073 wdma_phy = res ? res->start + wdma_base : 0;
4074 mtk_wed_add_hw(np, eth, eth->base + wdma_base,
4075 wdma_phy, i);
4076 }
4077 }
4078
4079 for (i = 0; i < 3; i++) {
4080 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
4081 eth->irq[i] = eth->irq[0];
4082 else
4083 eth->irq[i] = platform_get_irq(pdev, i);
4084 if (eth->irq[i] < 0) {
4085 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
4086 err = -ENXIO;
4087 goto err_wed_exit;
4088 }
4089 }
4090 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
4091 eth->clks[i] = devm_clk_get(eth->dev,
4092 mtk_clks_source_name[i]);
4093 if (IS_ERR(eth->clks[i])) {
4094 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) {
4095 err = -EPROBE_DEFER;
4096 goto err_wed_exit;
4097 }
4098 if (eth->soc->required_clks & BIT(i)) {
4099 dev_err(&pdev->dev, "clock %s not found\n",
4100 mtk_clks_source_name[i]);
4101 err = -EINVAL;
4102 goto err_wed_exit;
4103 }
4104 eth->clks[i] = NULL;
4105 }
4106 }
4107
4108 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
4109 INIT_WORK(ð->pending_work, mtk_pending_work);
4110
4111 err = mtk_hw_init(eth);
4112 if (err)
4113 goto err_wed_exit;
4114
4115 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
4116
4117 for_each_child_of_node(pdev->dev.of_node, mac_np) {
4118 if (!of_device_is_compatible(mac_np,
4119 "mediatek,eth-mac"))
4120 continue;
4121
4122 if (!of_device_is_available(mac_np))
4123 continue;
4124
4125 err = mtk_add_mac(eth, mac_np);
4126 if (err) {
4127 of_node_put(mac_np);
4128 goto err_deinit_hw;
4129 }
4130 }
4131
4132 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
4133 err = devm_request_irq(eth->dev, eth->irq[0],
4134 mtk_handle_irq, 0,
4135 dev_name(eth->dev), eth);
4136 } else {
4137 err = devm_request_irq(eth->dev, eth->irq[1],
4138 mtk_handle_irq_tx, 0,
4139 dev_name(eth->dev), eth);
4140 if (err)
4141 goto err_free_dev;
4142
4143 err = devm_request_irq(eth->dev, eth->irq[2],
4144 mtk_handle_irq_rx, 0,
4145 dev_name(eth->dev), eth);
4146 }
4147 if (err)
4148 goto err_free_dev;
4149
4150 /* No MT7628/88 support yet */
4151 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
4152 err = mtk_mdio_init(eth);
4153 if (err)
4154 goto err_free_dev;
4155 }
4156
4157 if (eth->soc->offload_version) {
4158 u32 num_ppe;
4159
4160 num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
4161 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);
4162 for (i = 0; i < num_ppe; i++) {
4163 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
4164
4165 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr,
4166 eth->soc->offload_version, i);
4167 if (!eth->ppe[i]) {
4168 err = -ENOMEM;
4169 goto err_deinit_ppe;
4170 }
4171 }
4172
4173 err = mtk_eth_offload_init(eth);
4174 if (err)
4175 goto err_deinit_ppe;
4176 }
4177
4178 for (i = 0; i < MTK_MAX_DEVS; i++) {
4179 if (!eth->netdev[i])
4180 continue;
4181
4182 err = register_netdev(eth->netdev[i]);
4183 if (err) {
4184 dev_err(eth->dev, "error bringing up device\n");
4185 goto err_deinit_ppe;
4186 } else
4187 netif_info(eth, probe, eth->netdev[i],
4188 "mediatek frame engine at 0x%08lx, irq %d\n",
4189 eth->netdev[i]->base_addr, eth->irq[0]);
4190 }
4191
4192 /* we run 2 devices on the same DMA ring so we need a dummy device
4193 * for NAPI to work
4194 */
4195 init_dummy_netdev(ð->dummy_dev);
4196 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx);
4197 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx);
4198
4199 platform_set_drvdata(pdev, eth);
4200
4201 return 0;
4202
4203 err_deinit_ppe:
4204 mtk_ppe_deinit(eth);
4205 mtk_mdio_cleanup(eth);
4206 err_free_dev:
4207 mtk_free_dev(eth);
4208 err_deinit_hw:
4209 mtk_hw_deinit(eth);
4210 err_wed_exit:
4211 mtk_wed_exit();
4212
4213 return err;
4214 }
4215
mtk_remove(struct platform_device * pdev)4216 static int mtk_remove(struct platform_device *pdev)
4217 {
4218 struct mtk_eth *eth = platform_get_drvdata(pdev);
4219 struct mtk_mac *mac;
4220 int i;
4221
4222 /* stop all devices to make sure that dma is properly shut down */
4223 for (i = 0; i < MTK_MAC_COUNT; i++) {
4224 if (!eth->netdev[i])
4225 continue;
4226 mtk_stop(eth->netdev[i]);
4227 mac = netdev_priv(eth->netdev[i]);
4228 phylink_disconnect_phy(mac->phylink);
4229 }
4230
4231 mtk_wed_exit();
4232 mtk_hw_deinit(eth);
4233
4234 netif_napi_del(ð->tx_napi);
4235 netif_napi_del(ð->rx_napi);
4236 mtk_cleanup(eth);
4237 mtk_mdio_cleanup(eth);
4238
4239 return 0;
4240 }
4241
4242 static const struct mtk_soc_data mt2701_data = {
4243 .reg_map = &mtk_reg_map,
4244 .caps = MT7623_CAPS | MTK_HWLRO,
4245 .hw_features = MTK_HW_FEATURES,
4246 .required_clks = MT7623_CLKS_BITMAP,
4247 .required_pctl = true,
4248 .txrx = {
4249 .txd_size = sizeof(struct mtk_tx_dma),
4250 .rxd_size = sizeof(struct mtk_rx_dma),
4251 .rx_irq_done_mask = MTK_RX_DONE_INT,
4252 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4253 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4254 .dma_len_offset = 16,
4255 },
4256 };
4257
4258 static const struct mtk_soc_data mt7621_data = {
4259 .reg_map = &mtk_reg_map,
4260 .caps = MT7621_CAPS,
4261 .hw_features = MTK_HW_FEATURES,
4262 .required_clks = MT7621_CLKS_BITMAP,
4263 .required_pctl = false,
4264 .offload_version = 2,
4265 .hash_offset = 2,
4266 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
4267 .txrx = {
4268 .txd_size = sizeof(struct mtk_tx_dma),
4269 .rxd_size = sizeof(struct mtk_rx_dma),
4270 .rx_irq_done_mask = MTK_RX_DONE_INT,
4271 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4272 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4273 .dma_len_offset = 16,
4274 },
4275 };
4276
4277 static const struct mtk_soc_data mt7622_data = {
4278 .reg_map = &mtk_reg_map,
4279 .ana_rgc3 = 0x2028,
4280 .caps = MT7622_CAPS | MTK_HWLRO,
4281 .hw_features = MTK_HW_FEATURES,
4282 .required_clks = MT7622_CLKS_BITMAP,
4283 .required_pctl = false,
4284 .offload_version = 2,
4285 .hash_offset = 2,
4286 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
4287 .txrx = {
4288 .txd_size = sizeof(struct mtk_tx_dma),
4289 .rxd_size = sizeof(struct mtk_rx_dma),
4290 .rx_irq_done_mask = MTK_RX_DONE_INT,
4291 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4292 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4293 .dma_len_offset = 16,
4294 },
4295 };
4296
4297 static const struct mtk_soc_data mt7623_data = {
4298 .reg_map = &mtk_reg_map,
4299 .caps = MT7623_CAPS | MTK_HWLRO,
4300 .hw_features = MTK_HW_FEATURES,
4301 .required_clks = MT7623_CLKS_BITMAP,
4302 .required_pctl = true,
4303 .offload_version = 2,
4304 .hash_offset = 2,
4305 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
4306 .txrx = {
4307 .txd_size = sizeof(struct mtk_tx_dma),
4308 .rxd_size = sizeof(struct mtk_rx_dma),
4309 .rx_irq_done_mask = MTK_RX_DONE_INT,
4310 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4311 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4312 .dma_len_offset = 16,
4313 },
4314 };
4315
4316 static const struct mtk_soc_data mt7629_data = {
4317 .reg_map = &mtk_reg_map,
4318 .ana_rgc3 = 0x128,
4319 .caps = MT7629_CAPS | MTK_HWLRO,
4320 .hw_features = MTK_HW_FEATURES,
4321 .required_clks = MT7629_CLKS_BITMAP,
4322 .required_pctl = false,
4323 .txrx = {
4324 .txd_size = sizeof(struct mtk_tx_dma),
4325 .rxd_size = sizeof(struct mtk_rx_dma),
4326 .rx_irq_done_mask = MTK_RX_DONE_INT,
4327 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4328 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4329 .dma_len_offset = 16,
4330 },
4331 };
4332
4333 static const struct mtk_soc_data mt7986_data = {
4334 .reg_map = &mt7986_reg_map,
4335 .ana_rgc3 = 0x128,
4336 .caps = MT7986_CAPS,
4337 .hw_features = MTK_HW_FEATURES,
4338 .required_clks = MT7986_CLKS_BITMAP,
4339 .required_pctl = false,
4340 .hash_offset = 4,
4341 .foe_entry_size = sizeof(struct mtk_foe_entry),
4342 .txrx = {
4343 .txd_size = sizeof(struct mtk_tx_dma_v2),
4344 .rxd_size = sizeof(struct mtk_rx_dma_v2),
4345 .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
4346 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
4347 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
4348 .dma_len_offset = 8,
4349 },
4350 };
4351
4352 static const struct mtk_soc_data rt5350_data = {
4353 .reg_map = &mt7628_reg_map,
4354 .caps = MT7628_CAPS,
4355 .hw_features = MTK_HW_FEATURES_MT7628,
4356 .required_clks = MT7628_CLKS_BITMAP,
4357 .required_pctl = false,
4358 .txrx = {
4359 .txd_size = sizeof(struct mtk_tx_dma),
4360 .rxd_size = sizeof(struct mtk_rx_dma),
4361 .rx_irq_done_mask = MTK_RX_DONE_INT,
4362 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA,
4363 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4364 .dma_len_offset = 16,
4365 },
4366 };
4367
4368 const struct of_device_id of_mtk_match[] = {
4369 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
4370 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
4371 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
4372 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
4373 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
4374 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
4375 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
4376 {},
4377 };
4378 MODULE_DEVICE_TABLE(of, of_mtk_match);
4379
4380 static struct platform_driver mtk_driver = {
4381 .probe = mtk_probe,
4382 .remove = mtk_remove,
4383 .driver = {
4384 .name = "mtk_soc_eth",
4385 .of_match_table = of_mtk_match,
4386 },
4387 };
4388
4389 module_platform_driver(mtk_driver);
4390
4391 MODULE_LICENSE("GPL");
4392 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4393 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
4394