1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3  * Microsemi Ocelot Switch driver
4  *
5  * Copyright (c) 2017 Microsemi Corporation
6  */
7 #include <linux/dsa/ocelot.h>
8 #include <linux/if_bridge.h>
9 #include <soc/mscc/ocelot_vcap.h>
10 #include "ocelot.h"
11 #include "ocelot_vcap.h"
12 
13 #define TABLE_UPDATE_SLEEP_US 10
14 #define TABLE_UPDATE_TIMEOUT_US 100000
15 #define OCELOT_RSV_VLAN_RANGE_START 4000
16 
17 struct ocelot_mact_entry {
18 	u8 mac[ETH_ALEN];
19 	u16 vid;
20 	enum macaccess_entry_type type;
21 };
22 
23 /* Caller must hold &ocelot->mact_lock */
ocelot_mact_read_macaccess(struct ocelot * ocelot)24 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
25 {
26 	return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
27 }
28 
29 /* Caller must hold &ocelot->mact_lock */
ocelot_mact_wait_for_completion(struct ocelot * ocelot)30 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
31 {
32 	u32 val;
33 
34 	return readx_poll_timeout(ocelot_mact_read_macaccess,
35 		ocelot, val,
36 		(val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
37 		MACACCESS_CMD_IDLE,
38 		TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
39 }
40 
41 /* Caller must hold &ocelot->mact_lock */
ocelot_mact_select(struct ocelot * ocelot,const unsigned char mac[ETH_ALEN],unsigned int vid)42 static void ocelot_mact_select(struct ocelot *ocelot,
43 			       const unsigned char mac[ETH_ALEN],
44 			       unsigned int vid)
45 {
46 	u32 macl = 0, mach = 0;
47 
48 	/* Set the MAC address to handle and the vlan associated in a format
49 	 * understood by the hardware.
50 	 */
51 	mach |= vid    << 16;
52 	mach |= mac[0] << 8;
53 	mach |= mac[1] << 0;
54 	macl |= mac[2] << 24;
55 	macl |= mac[3] << 16;
56 	macl |= mac[4] << 8;
57 	macl |= mac[5] << 0;
58 
59 	ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
60 	ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
61 
62 }
63 
__ocelot_mact_learn(struct ocelot * ocelot,int port,const unsigned char mac[ETH_ALEN],unsigned int vid,enum macaccess_entry_type type)64 static int __ocelot_mact_learn(struct ocelot *ocelot, int port,
65 			       const unsigned char mac[ETH_ALEN],
66 			       unsigned int vid, enum macaccess_entry_type type)
67 {
68 	u32 cmd = ANA_TABLES_MACACCESS_VALID |
69 		ANA_TABLES_MACACCESS_DEST_IDX(port) |
70 		ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
71 		ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN);
72 	unsigned int mc_ports;
73 	int err;
74 
75 	/* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */
76 	if (type == ENTRYTYPE_MACv4)
77 		mc_ports = (mac[1] << 8) | mac[2];
78 	else if (type == ENTRYTYPE_MACv6)
79 		mc_ports = (mac[0] << 8) | mac[1];
80 	else
81 		mc_ports = 0;
82 
83 	if (mc_ports & BIT(ocelot->num_phys_ports))
84 		cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY;
85 
86 	ocelot_mact_select(ocelot, mac, vid);
87 
88 	/* Issue a write command */
89 	ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
90 
91 	err = ocelot_mact_wait_for_completion(ocelot);
92 
93 	return err;
94 }
95 
ocelot_mact_learn(struct ocelot * ocelot,int port,const unsigned char mac[ETH_ALEN],unsigned int vid,enum macaccess_entry_type type)96 int ocelot_mact_learn(struct ocelot *ocelot, int port,
97 		      const unsigned char mac[ETH_ALEN],
98 		      unsigned int vid, enum macaccess_entry_type type)
99 {
100 	int ret;
101 
102 	mutex_lock(&ocelot->mact_lock);
103 	ret = __ocelot_mact_learn(ocelot, port, mac, vid, type);
104 	mutex_unlock(&ocelot->mact_lock);
105 
106 	return ret;
107 }
108 EXPORT_SYMBOL(ocelot_mact_learn);
109 
ocelot_mact_forget(struct ocelot * ocelot,const unsigned char mac[ETH_ALEN],unsigned int vid)110 int ocelot_mact_forget(struct ocelot *ocelot,
111 		       const unsigned char mac[ETH_ALEN], unsigned int vid)
112 {
113 	int err;
114 
115 	mutex_lock(&ocelot->mact_lock);
116 
117 	ocelot_mact_select(ocelot, mac, vid);
118 
119 	/* Issue a forget command */
120 	ocelot_write(ocelot,
121 		     ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
122 		     ANA_TABLES_MACACCESS);
123 
124 	err = ocelot_mact_wait_for_completion(ocelot);
125 
126 	mutex_unlock(&ocelot->mact_lock);
127 
128 	return err;
129 }
130 EXPORT_SYMBOL(ocelot_mact_forget);
131 
ocelot_mact_lookup(struct ocelot * ocelot,int * dst_idx,const unsigned char mac[ETH_ALEN],unsigned int vid,enum macaccess_entry_type * type)132 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
133 		       const unsigned char mac[ETH_ALEN],
134 		       unsigned int vid, enum macaccess_entry_type *type)
135 {
136 	int val;
137 
138 	mutex_lock(&ocelot->mact_lock);
139 
140 	ocelot_mact_select(ocelot, mac, vid);
141 
142 	/* Issue a read command with MACACCESS_VALID=1. */
143 	ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
144 		     ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
145 		     ANA_TABLES_MACACCESS);
146 
147 	if (ocelot_mact_wait_for_completion(ocelot)) {
148 		mutex_unlock(&ocelot->mact_lock);
149 		return -ETIMEDOUT;
150 	}
151 
152 	/* Read back the entry flags */
153 	val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
154 
155 	mutex_unlock(&ocelot->mact_lock);
156 
157 	if (!(val & ANA_TABLES_MACACCESS_VALID))
158 		return -ENOENT;
159 
160 	*dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val);
161 	*type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val);
162 
163 	return 0;
164 }
165 EXPORT_SYMBOL(ocelot_mact_lookup);
166 
ocelot_mact_learn_streamdata(struct ocelot * ocelot,int dst_idx,const unsigned char mac[ETH_ALEN],unsigned int vid,enum macaccess_entry_type type,int sfid,int ssid)167 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
168 				 const unsigned char mac[ETH_ALEN],
169 				 unsigned int vid,
170 				 enum macaccess_entry_type type,
171 				 int sfid, int ssid)
172 {
173 	int ret;
174 
175 	mutex_lock(&ocelot->mact_lock);
176 
177 	ocelot_write(ocelot,
178 		     (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) |
179 		     ANA_TABLES_STREAMDATA_SFID(sfid) |
180 		     (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) |
181 		     ANA_TABLES_STREAMDATA_SSID(ssid),
182 		     ANA_TABLES_STREAMDATA);
183 
184 	ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type);
185 
186 	mutex_unlock(&ocelot->mact_lock);
187 
188 	return ret;
189 }
190 EXPORT_SYMBOL(ocelot_mact_learn_streamdata);
191 
ocelot_mact_init(struct ocelot * ocelot)192 static void ocelot_mact_init(struct ocelot *ocelot)
193 {
194 	/* Configure the learning mode entries attributes:
195 	 * - Do not copy the frame to the CPU extraction queues.
196 	 * - Use the vlan and mac_cpoy for dmac lookup.
197 	 */
198 	ocelot_rmw(ocelot, 0,
199 		   ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
200 		   | ANA_AGENCTRL_LEARN_FWD_KILL
201 		   | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
202 		   ANA_AGENCTRL);
203 
204 	/* Clear the MAC table. We are not concurrent with anyone, so
205 	 * holding &ocelot->mact_lock is pointless.
206 	 */
207 	ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
208 }
209 
ocelot_vcap_enable(struct ocelot * ocelot,int port)210 static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
211 {
212 	ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
213 			 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
214 			 ANA_PORT_VCAP_S2_CFG, port);
215 
216 	ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
217 			 ANA_PORT_VCAP_CFG, port);
218 
219 	ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
220 		       REW_PORT_CFG_ES0_EN,
221 		       REW_PORT_CFG, port);
222 }
223 
ocelot_single_vlan_aware_bridge(struct ocelot * ocelot,struct netlink_ext_ack * extack)224 static int ocelot_single_vlan_aware_bridge(struct ocelot *ocelot,
225 					   struct netlink_ext_ack *extack)
226 {
227 	struct net_device *bridge = NULL;
228 	int port;
229 
230 	for (port = 0; port < ocelot->num_phys_ports; port++) {
231 		struct ocelot_port *ocelot_port = ocelot->ports[port];
232 
233 		if (!ocelot_port || !ocelot_port->bridge ||
234 		    !br_vlan_enabled(ocelot_port->bridge))
235 			continue;
236 
237 		if (!bridge) {
238 			bridge = ocelot_port->bridge;
239 			continue;
240 		}
241 
242 		if (bridge == ocelot_port->bridge)
243 			continue;
244 
245 		NL_SET_ERR_MSG_MOD(extack,
246 				   "Only one VLAN-aware bridge is supported");
247 		return -EBUSY;
248 	}
249 
250 	return 0;
251 }
252 
ocelot_vlant_read_vlanaccess(struct ocelot * ocelot)253 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
254 {
255 	return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
256 }
257 
ocelot_vlant_wait_for_completion(struct ocelot * ocelot)258 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
259 {
260 	u32 val;
261 
262 	return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
263 		ocelot,
264 		val,
265 		(val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
266 		ANA_TABLES_VLANACCESS_CMD_IDLE,
267 		TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
268 }
269 
ocelot_vlant_set_mask(struct ocelot * ocelot,u16 vid,u32 mask)270 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
271 {
272 	/* Select the VID to configure */
273 	ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
274 		     ANA_TABLES_VLANTIDX);
275 	/* Set the vlan port members mask and issue a write command */
276 	ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
277 			     ANA_TABLES_VLANACCESS_CMD_WRITE,
278 		     ANA_TABLES_VLANACCESS);
279 
280 	return ocelot_vlant_wait_for_completion(ocelot);
281 }
282 
ocelot_port_num_untagged_vlans(struct ocelot * ocelot,int port)283 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port)
284 {
285 	struct ocelot_bridge_vlan *vlan;
286 	int num_untagged = 0;
287 
288 	list_for_each_entry(vlan, &ocelot->vlans, list) {
289 		if (!(vlan->portmask & BIT(port)))
290 			continue;
291 
292 		/* Ignore the VLAN added by ocelot_add_vlan_unaware_pvid(),
293 		 * because this is never active in hardware at the same time as
294 		 * the bridge VLANs, which only matter in VLAN-aware mode.
295 		 */
296 		if (vlan->vid >= OCELOT_RSV_VLAN_RANGE_START)
297 			continue;
298 
299 		if (vlan->untagged & BIT(port))
300 			num_untagged++;
301 	}
302 
303 	return num_untagged;
304 }
305 
ocelot_port_num_tagged_vlans(struct ocelot * ocelot,int port)306 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port)
307 {
308 	struct ocelot_bridge_vlan *vlan;
309 	int num_tagged = 0;
310 
311 	list_for_each_entry(vlan, &ocelot->vlans, list) {
312 		if (!(vlan->portmask & BIT(port)))
313 			continue;
314 
315 		if (!(vlan->untagged & BIT(port)))
316 			num_tagged++;
317 	}
318 
319 	return num_tagged;
320 }
321 
322 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly
323  * _one_ egress-untagged VLAN (_the_ native VLAN)
324  */
ocelot_port_uses_native_vlan(struct ocelot * ocelot,int port)325 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port)
326 {
327 	return ocelot_port_num_tagged_vlans(ocelot, port) &&
328 	       ocelot_port_num_untagged_vlans(ocelot, port) == 1;
329 }
330 
331 static struct ocelot_bridge_vlan *
ocelot_port_find_native_vlan(struct ocelot * ocelot,int port)332 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port)
333 {
334 	struct ocelot_bridge_vlan *vlan;
335 
336 	list_for_each_entry(vlan, &ocelot->vlans, list)
337 		if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port))
338 			return vlan;
339 
340 	return NULL;
341 }
342 
343 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable,
344  * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness
345  * state of the port.
346  */
ocelot_port_manage_port_tag(struct ocelot * ocelot,int port)347 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port)
348 {
349 	struct ocelot_port *ocelot_port = ocelot->ports[port];
350 	enum ocelot_port_tag_config tag_cfg;
351 	bool uses_native_vlan = false;
352 
353 	if (ocelot_port->vlan_aware) {
354 		uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port);
355 
356 		if (uses_native_vlan)
357 			tag_cfg = OCELOT_PORT_TAG_NATIVE;
358 		else if (ocelot_port_num_untagged_vlans(ocelot, port))
359 			tag_cfg = OCELOT_PORT_TAG_DISABLED;
360 		else
361 			tag_cfg = OCELOT_PORT_TAG_TRUNK;
362 	} else {
363 		tag_cfg = OCELOT_PORT_TAG_DISABLED;
364 	}
365 
366 	ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg),
367 		       REW_TAG_CFG_TAG_CFG_M,
368 		       REW_TAG_CFG, port);
369 
370 	if (uses_native_vlan) {
371 		struct ocelot_bridge_vlan *native_vlan;
372 
373 		/* Not having a native VLAN is impossible, because
374 		 * ocelot_port_num_untagged_vlans has returned 1.
375 		 * So there is no use in checking for NULL here.
376 		 */
377 		native_vlan = ocelot_port_find_native_vlan(ocelot, port);
378 
379 		ocelot_rmw_gix(ocelot,
380 			       REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid),
381 			       REW_PORT_VLAN_CFG_PORT_VID_M,
382 			       REW_PORT_VLAN_CFG, port);
383 	}
384 }
385 
ocelot_bridge_num_find(struct ocelot * ocelot,const struct net_device * bridge)386 int ocelot_bridge_num_find(struct ocelot *ocelot,
387 			   const struct net_device *bridge)
388 {
389 	int port;
390 
391 	for (port = 0; port < ocelot->num_phys_ports; port++) {
392 		struct ocelot_port *ocelot_port = ocelot->ports[port];
393 
394 		if (ocelot_port && ocelot_port->bridge == bridge)
395 			return ocelot_port->bridge_num;
396 	}
397 
398 	return -1;
399 }
400 EXPORT_SYMBOL_GPL(ocelot_bridge_num_find);
401 
ocelot_vlan_unaware_pvid(struct ocelot * ocelot,const struct net_device * bridge)402 static u16 ocelot_vlan_unaware_pvid(struct ocelot *ocelot,
403 				    const struct net_device *bridge)
404 {
405 	int bridge_num;
406 
407 	/* Standalone ports use VID 0 */
408 	if (!bridge)
409 		return 0;
410 
411 	bridge_num = ocelot_bridge_num_find(ocelot, bridge);
412 	if (WARN_ON(bridge_num < 0))
413 		return 0;
414 
415 	/* VLAN-unaware bridges use a reserved VID going from 4095 downwards */
416 	return VLAN_N_VID - bridge_num - 1;
417 }
418 
419 /* Default vlan to clasify for untagged frames (may be zero) */
ocelot_port_set_pvid(struct ocelot * ocelot,int port,const struct ocelot_bridge_vlan * pvid_vlan)420 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port,
421 				 const struct ocelot_bridge_vlan *pvid_vlan)
422 {
423 	struct ocelot_port *ocelot_port = ocelot->ports[port];
424 	u16 pvid = ocelot_vlan_unaware_pvid(ocelot, ocelot_port->bridge);
425 	u32 val = 0;
426 
427 	ocelot_port->pvid_vlan = pvid_vlan;
428 
429 	if (ocelot_port->vlan_aware && pvid_vlan)
430 		pvid = pvid_vlan->vid;
431 
432 	ocelot_rmw_gix(ocelot,
433 		       ANA_PORT_VLAN_CFG_VLAN_VID(pvid),
434 		       ANA_PORT_VLAN_CFG_VLAN_VID_M,
435 		       ANA_PORT_VLAN_CFG, port);
436 
437 	/* If there's no pvid, we should drop not only untagged traffic (which
438 	 * happens automatically), but also 802.1p traffic which gets
439 	 * classified to VLAN 0, but that is always in our RX filter, so it
440 	 * would get accepted were it not for this setting.
441 	 */
442 	if (!pvid_vlan && ocelot_port->vlan_aware)
443 		val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
444 		      ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
445 
446 	ocelot_rmw_gix(ocelot, val,
447 		       ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
448 		       ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
449 		       ANA_PORT_DROP_CFG, port);
450 }
451 
ocelot_bridge_vlan_find(struct ocelot * ocelot,u16 vid)452 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot,
453 							  u16 vid)
454 {
455 	struct ocelot_bridge_vlan *vlan;
456 
457 	list_for_each_entry(vlan, &ocelot->vlans, list)
458 		if (vlan->vid == vid)
459 			return vlan;
460 
461 	return NULL;
462 }
463 
ocelot_vlan_member_add(struct ocelot * ocelot,int port,u16 vid,bool untagged)464 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid,
465 				  bool untagged)
466 {
467 	struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
468 	unsigned long portmask;
469 	int err;
470 
471 	if (vlan) {
472 		portmask = vlan->portmask | BIT(port);
473 
474 		err = ocelot_vlant_set_mask(ocelot, vid, portmask);
475 		if (err)
476 			return err;
477 
478 		vlan->portmask = portmask;
479 		/* Bridge VLANs can be overwritten with a different
480 		 * egress-tagging setting, so make sure to override an untagged
481 		 * with a tagged VID if that's going on.
482 		 */
483 		if (untagged)
484 			vlan->untagged |= BIT(port);
485 		else
486 			vlan->untagged &= ~BIT(port);
487 
488 		return 0;
489 	}
490 
491 	vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
492 	if (!vlan)
493 		return -ENOMEM;
494 
495 	portmask = BIT(port);
496 
497 	err = ocelot_vlant_set_mask(ocelot, vid, portmask);
498 	if (err) {
499 		kfree(vlan);
500 		return err;
501 	}
502 
503 	vlan->vid = vid;
504 	vlan->portmask = portmask;
505 	if (untagged)
506 		vlan->untagged = BIT(port);
507 	INIT_LIST_HEAD(&vlan->list);
508 	list_add_tail(&vlan->list, &ocelot->vlans);
509 
510 	return 0;
511 }
512 
ocelot_vlan_member_del(struct ocelot * ocelot,int port,u16 vid)513 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid)
514 {
515 	struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
516 	unsigned long portmask;
517 	int err;
518 
519 	if (!vlan)
520 		return 0;
521 
522 	portmask = vlan->portmask & ~BIT(port);
523 
524 	err = ocelot_vlant_set_mask(ocelot, vid, portmask);
525 	if (err)
526 		return err;
527 
528 	vlan->portmask = portmask;
529 	if (vlan->portmask)
530 		return 0;
531 
532 	list_del(&vlan->list);
533 	kfree(vlan);
534 
535 	return 0;
536 }
537 
ocelot_add_vlan_unaware_pvid(struct ocelot * ocelot,int port,const struct net_device * bridge)538 static int ocelot_add_vlan_unaware_pvid(struct ocelot *ocelot, int port,
539 					const struct net_device *bridge)
540 {
541 	u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
542 
543 	return ocelot_vlan_member_add(ocelot, port, vid, true);
544 }
545 
ocelot_del_vlan_unaware_pvid(struct ocelot * ocelot,int port,const struct net_device * bridge)546 static int ocelot_del_vlan_unaware_pvid(struct ocelot *ocelot, int port,
547 					const struct net_device *bridge)
548 {
549 	u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
550 
551 	return ocelot_vlan_member_del(ocelot, port, vid);
552 }
553 
ocelot_port_vlan_filtering(struct ocelot * ocelot,int port,bool vlan_aware,struct netlink_ext_ack * extack)554 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
555 			       bool vlan_aware, struct netlink_ext_ack *extack)
556 {
557 	struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
558 	struct ocelot_port *ocelot_port = ocelot->ports[port];
559 	struct ocelot_vcap_filter *filter;
560 	int err = 0;
561 	u32 val;
562 
563 	list_for_each_entry(filter, &block->rules, list) {
564 		if (filter->ingress_port_mask & BIT(port) &&
565 		    filter->action.vid_replace_ena) {
566 			NL_SET_ERR_MSG_MOD(extack,
567 					   "Cannot change VLAN state with vlan modify rules active");
568 			return -EBUSY;
569 		}
570 	}
571 
572 	err = ocelot_single_vlan_aware_bridge(ocelot, extack);
573 	if (err)
574 		return err;
575 
576 	if (vlan_aware)
577 		err = ocelot_del_vlan_unaware_pvid(ocelot, port,
578 						   ocelot_port->bridge);
579 	else if (ocelot_port->bridge)
580 		err = ocelot_add_vlan_unaware_pvid(ocelot, port,
581 						   ocelot_port->bridge);
582 	if (err)
583 		return err;
584 
585 	ocelot_port->vlan_aware = vlan_aware;
586 
587 	if (vlan_aware)
588 		val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
589 		      ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
590 	else
591 		val = 0;
592 	ocelot_rmw_gix(ocelot, val,
593 		       ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
594 		       ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
595 		       ANA_PORT_VLAN_CFG, port);
596 
597 	ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan);
598 	ocelot_port_manage_port_tag(ocelot, port);
599 
600 	return 0;
601 }
602 EXPORT_SYMBOL(ocelot_port_vlan_filtering);
603 
ocelot_vlan_prepare(struct ocelot * ocelot,int port,u16 vid,bool pvid,bool untagged,struct netlink_ext_ack * extack)604 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
605 			bool untagged, struct netlink_ext_ack *extack)
606 {
607 	if (untagged) {
608 		/* We are adding an egress-tagged VLAN */
609 		if (ocelot_port_uses_native_vlan(ocelot, port)) {
610 			NL_SET_ERR_MSG_MOD(extack,
611 					   "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN");
612 			return -EBUSY;
613 		}
614 	} else {
615 		/* We are adding an egress-tagged VLAN */
616 		if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) {
617 			NL_SET_ERR_MSG_MOD(extack,
618 					   "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs");
619 			return -EBUSY;
620 		}
621 	}
622 
623 	if (vid > OCELOT_RSV_VLAN_RANGE_START) {
624 		NL_SET_ERR_MSG_MOD(extack,
625 				   "VLAN range 4000-4095 reserved for VLAN-unaware bridging");
626 		return -EBUSY;
627 	}
628 
629 	return 0;
630 }
631 EXPORT_SYMBOL(ocelot_vlan_prepare);
632 
ocelot_vlan_add(struct ocelot * ocelot,int port,u16 vid,bool pvid,bool untagged)633 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
634 		    bool untagged)
635 {
636 	int err;
637 
638 	/* Ignore VID 0 added to our RX filter by the 8021q module, since
639 	 * that collides with OCELOT_STANDALONE_PVID and changes it from
640 	 * egress-untagged to egress-tagged.
641 	 */
642 	if (!vid)
643 		return 0;
644 
645 	err = ocelot_vlan_member_add(ocelot, port, vid, untagged);
646 	if (err)
647 		return err;
648 
649 	/* Default ingress vlan classification */
650 	if (pvid)
651 		ocelot_port_set_pvid(ocelot, port,
652 				     ocelot_bridge_vlan_find(ocelot, vid));
653 
654 	/* Untagged egress vlan clasification */
655 	ocelot_port_manage_port_tag(ocelot, port);
656 
657 	return 0;
658 }
659 EXPORT_SYMBOL(ocelot_vlan_add);
660 
ocelot_vlan_del(struct ocelot * ocelot,int port,u16 vid)661 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
662 {
663 	struct ocelot_port *ocelot_port = ocelot->ports[port];
664 	bool del_pvid = false;
665 	int err;
666 
667 	if (!vid)
668 		return 0;
669 
670 	if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid)
671 		del_pvid = true;
672 
673 	err = ocelot_vlan_member_del(ocelot, port, vid);
674 	if (err)
675 		return err;
676 
677 	/* Ingress */
678 	if (del_pvid)
679 		ocelot_port_set_pvid(ocelot, port, NULL);
680 
681 	/* Egress */
682 	ocelot_port_manage_port_tag(ocelot, port);
683 
684 	return 0;
685 }
686 EXPORT_SYMBOL(ocelot_vlan_del);
687 
ocelot_vlan_init(struct ocelot * ocelot)688 static void ocelot_vlan_init(struct ocelot *ocelot)
689 {
690 	unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0);
691 	u16 port, vid;
692 
693 	/* Clear VLAN table, by default all ports are members of all VLANs */
694 	ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
695 		     ANA_TABLES_VLANACCESS);
696 	ocelot_vlant_wait_for_completion(ocelot);
697 
698 	/* Configure the port VLAN memberships */
699 	for (vid = 1; vid < VLAN_N_VID; vid++)
700 		ocelot_vlant_set_mask(ocelot, vid, 0);
701 
702 	/* We need VID 0 to get traffic on standalone ports.
703 	 * It is added automatically if the 8021q module is loaded, but we
704 	 * can't rely on that since it might not be.
705 	 */
706 	ocelot_vlant_set_mask(ocelot, OCELOT_STANDALONE_PVID, all_ports);
707 
708 	/* Set vlan ingress filter mask to all ports but the CPU port by
709 	 * default.
710 	 */
711 	ocelot_write(ocelot, all_ports, ANA_VLANMASK);
712 
713 	for (port = 0; port < ocelot->num_phys_ports; port++) {
714 		ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
715 		ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
716 	}
717 }
718 
ocelot_read_eq_avail(struct ocelot * ocelot,int port)719 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port)
720 {
721 	return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port);
722 }
723 
ocelot_port_flush(struct ocelot * ocelot,int port)724 static int ocelot_port_flush(struct ocelot *ocelot, int port)
725 {
726 	unsigned int pause_ena;
727 	int err, val;
728 
729 	/* Disable dequeuing from the egress queues */
730 	ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS,
731 		       QSYS_PORT_MODE_DEQUEUE_DIS,
732 		       QSYS_PORT_MODE, port);
733 
734 	/* Disable flow control */
735 	ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena);
736 	ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
737 
738 	/* Disable priority flow control */
739 	ocelot_fields_write(ocelot, port,
740 			    QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0);
741 
742 	/* Wait at least the time it takes to receive a frame of maximum length
743 	 * at the port.
744 	 * Worst-case delays for 10 kilobyte jumbo frames are:
745 	 * 8 ms on a 10M port
746 	 * 800 μs on a 100M port
747 	 * 80 μs on a 1G port
748 	 * 32 μs on a 2.5G port
749 	 */
750 	usleep_range(8000, 10000);
751 
752 	/* Disable half duplex backpressure. */
753 	ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE,
754 		       SYS_FRONT_PORT_MODE, port);
755 
756 	/* Flush the queues associated with the port. */
757 	ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA,
758 		       REW_PORT_CFG, port);
759 
760 	/* Enable dequeuing from the egress queues. */
761 	ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE,
762 		       port);
763 
764 	/* Wait until flushing is complete. */
765 	err = read_poll_timeout(ocelot_read_eq_avail, val, !val,
766 				100, 2000000, false, ocelot, port);
767 
768 	/* Clear flushing again. */
769 	ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port);
770 
771 	/* Re-enable flow control */
772 	ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena);
773 
774 	return err;
775 }
776 
ocelot_phylink_mac_link_down(struct ocelot * ocelot,int port,unsigned int link_an_mode,phy_interface_t interface,unsigned long quirks)777 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
778 				  unsigned int link_an_mode,
779 				  phy_interface_t interface,
780 				  unsigned long quirks)
781 {
782 	struct ocelot_port *ocelot_port = ocelot->ports[port];
783 	int err;
784 
785 	ocelot_port->speed = SPEED_UNKNOWN;
786 
787 	ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,
788 			 DEV_MAC_ENA_CFG);
789 
790 	if (ocelot->ops->cut_through_fwd) {
791 		mutex_lock(&ocelot->fwd_domain_lock);
792 		ocelot->ops->cut_through_fwd(ocelot);
793 		mutex_unlock(&ocelot->fwd_domain_lock);
794 	}
795 
796 	ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
797 
798 	err = ocelot_port_flush(ocelot, port);
799 	if (err)
800 		dev_err(ocelot->dev, "failed to flush port %d: %d\n",
801 			port, err);
802 
803 	/* Put the port in reset. */
804 	if (interface != PHY_INTERFACE_MODE_QSGMII ||
805 	    !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP))
806 		ocelot_port_rmwl(ocelot_port,
807 				 DEV_CLOCK_CFG_MAC_TX_RST |
808 				 DEV_CLOCK_CFG_MAC_RX_RST,
809 				 DEV_CLOCK_CFG_MAC_TX_RST |
810 				 DEV_CLOCK_CFG_MAC_RX_RST,
811 				 DEV_CLOCK_CFG);
812 }
813 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down);
814 
ocelot_phylink_mac_link_up(struct ocelot * ocelot,int port,struct phy_device * phydev,unsigned int link_an_mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause,unsigned long quirks)815 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
816 				struct phy_device *phydev,
817 				unsigned int link_an_mode,
818 				phy_interface_t interface,
819 				int speed, int duplex,
820 				bool tx_pause, bool rx_pause,
821 				unsigned long quirks)
822 {
823 	struct ocelot_port *ocelot_port = ocelot->ports[port];
824 	int mac_speed, mode = 0;
825 	u32 mac_fc_cfg;
826 
827 	ocelot_port->speed = speed;
828 
829 	/* The MAC might be integrated in systems where the MAC speed is fixed
830 	 * and it's the PCS who is performing the rate adaptation, so we have
831 	 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG
832 	 * (which is also its default value).
833 	 */
834 	if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) ||
835 	    speed == SPEED_1000) {
836 		mac_speed = OCELOT_SPEED_1000;
837 		mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
838 	} else if (speed == SPEED_2500) {
839 		mac_speed = OCELOT_SPEED_2500;
840 		mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
841 	} else if (speed == SPEED_100) {
842 		mac_speed = OCELOT_SPEED_100;
843 	} else {
844 		mac_speed = OCELOT_SPEED_10;
845 	}
846 
847 	if (duplex == DUPLEX_FULL)
848 		mode |= DEV_MAC_MODE_CFG_FDX_ENA;
849 
850 	ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG);
851 
852 	/* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
853 	 * PORT_RST bits in DEV_CLOCK_CFG.
854 	 */
855 	ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed),
856 			   DEV_CLOCK_CFG);
857 
858 	switch (speed) {
859 	case SPEED_10:
860 		mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10);
861 		break;
862 	case SPEED_100:
863 		mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100);
864 		break;
865 	case SPEED_1000:
866 	case SPEED_2500:
867 		mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000);
868 		break;
869 	default:
870 		dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
871 			port, speed);
872 		return;
873 	}
874 
875 	/* Handle RX pause in all cases, with 2500base-X this is used for rate
876 	 * adaptation.
877 	 */
878 	mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
879 
880 	if (tx_pause)
881 		mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
882 			      SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
883 			      SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
884 			      SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
885 
886 	/* Flow control. Link speed is only used here to evaluate the time
887 	 * specification in incoming pause frames.
888 	 */
889 	ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
890 
891 	ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
892 
893 	/* Don't attempt to send PAUSE frames on the NPI port, it's broken */
894 	if (port != ocelot->npi)
895 		ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA,
896 				    tx_pause);
897 
898 	/* Undo the effects of ocelot_phylink_mac_link_down:
899 	 * enable MAC module
900 	 */
901 	ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
902 			   DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
903 
904 	/* If the port supports cut-through forwarding, update the masks before
905 	 * enabling forwarding on the port.
906 	 */
907 	if (ocelot->ops->cut_through_fwd) {
908 		mutex_lock(&ocelot->fwd_domain_lock);
909 		ocelot->ops->cut_through_fwd(ocelot);
910 		mutex_unlock(&ocelot->fwd_domain_lock);
911 	}
912 
913 	/* Core: Enable port for frame transfer */
914 	ocelot_fields_write(ocelot, port,
915 			    QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
916 }
917 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up);
918 
ocelot_rx_frame_word(struct ocelot * ocelot,u8 grp,bool ifh,u32 * rval)919 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
920 				u32 *rval)
921 {
922 	u32 bytes_valid, val;
923 
924 	val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
925 	if (val == XTR_NOT_READY) {
926 		if (ifh)
927 			return -EIO;
928 
929 		do {
930 			val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
931 		} while (val == XTR_NOT_READY);
932 	}
933 
934 	switch (val) {
935 	case XTR_ABORT:
936 		return -EIO;
937 	case XTR_EOF_0:
938 	case XTR_EOF_1:
939 	case XTR_EOF_2:
940 	case XTR_EOF_3:
941 	case XTR_PRUNED:
942 		bytes_valid = XTR_VALID_BYTES(val);
943 		val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
944 		if (val == XTR_ESCAPE)
945 			*rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
946 		else
947 			*rval = val;
948 
949 		return bytes_valid;
950 	case XTR_ESCAPE:
951 		*rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
952 
953 		return 4;
954 	default:
955 		*rval = val;
956 
957 		return 4;
958 	}
959 }
960 
ocelot_xtr_poll_xfh(struct ocelot * ocelot,int grp,u32 * xfh)961 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh)
962 {
963 	int i, err = 0;
964 
965 	for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
966 		err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]);
967 		if (err != 4)
968 			return (err < 0) ? err : -EIO;
969 	}
970 
971 	return 0;
972 }
973 
ocelot_ptp_rx_timestamp(struct ocelot * ocelot,struct sk_buff * skb,u64 timestamp)974 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
975 			     u64 timestamp)
976 {
977 	struct skb_shared_hwtstamps *shhwtstamps;
978 	u64 tod_in_ns, full_ts_in_ns;
979 	struct timespec64 ts;
980 
981 	ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
982 
983 	tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec);
984 	if ((tod_in_ns & 0xffffffff) < timestamp)
985 		full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |
986 				timestamp;
987 	else
988 		full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |
989 				timestamp;
990 
991 	shhwtstamps = skb_hwtstamps(skb);
992 	memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
993 	shhwtstamps->hwtstamp = full_ts_in_ns;
994 }
995 EXPORT_SYMBOL(ocelot_ptp_rx_timestamp);
996 
ocelot_xtr_poll_frame(struct ocelot * ocelot,int grp,struct sk_buff ** nskb)997 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb)
998 {
999 	u64 timestamp, src_port, len;
1000 	u32 xfh[OCELOT_TAG_LEN / 4];
1001 	struct net_device *dev;
1002 	struct sk_buff *skb;
1003 	int sz, buf_len;
1004 	u32 val, *buf;
1005 	int err;
1006 
1007 	err = ocelot_xtr_poll_xfh(ocelot, grp, xfh);
1008 	if (err)
1009 		return err;
1010 
1011 	ocelot_xfh_get_src_port(xfh, &src_port);
1012 	ocelot_xfh_get_len(xfh, &len);
1013 	ocelot_xfh_get_rew_val(xfh, &timestamp);
1014 
1015 	if (WARN_ON(src_port >= ocelot->num_phys_ports))
1016 		return -EINVAL;
1017 
1018 	dev = ocelot->ops->port_to_netdev(ocelot, src_port);
1019 	if (!dev)
1020 		return -EINVAL;
1021 
1022 	skb = netdev_alloc_skb(dev, len);
1023 	if (unlikely(!skb)) {
1024 		netdev_err(dev, "Unable to allocate sk_buff\n");
1025 		return -ENOMEM;
1026 	}
1027 
1028 	buf_len = len - ETH_FCS_LEN;
1029 	buf = (u32 *)skb_put(skb, buf_len);
1030 
1031 	len = 0;
1032 	do {
1033 		sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1034 		if (sz < 0) {
1035 			err = sz;
1036 			goto out_free_skb;
1037 		}
1038 		*buf++ = val;
1039 		len += sz;
1040 	} while (len < buf_len);
1041 
1042 	/* Read the FCS */
1043 	sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1044 	if (sz < 0) {
1045 		err = sz;
1046 		goto out_free_skb;
1047 	}
1048 
1049 	/* Update the statistics if part of the FCS was read before */
1050 	len -= ETH_FCS_LEN - sz;
1051 
1052 	if (unlikely(dev->features & NETIF_F_RXFCS)) {
1053 		buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
1054 		*buf = val;
1055 	}
1056 
1057 	if (ocelot->ptp)
1058 		ocelot_ptp_rx_timestamp(ocelot, skb, timestamp);
1059 
1060 	/* Everything we see on an interface that is in the HW bridge
1061 	 * has already been forwarded.
1062 	 */
1063 	if (ocelot->ports[src_port]->bridge)
1064 		skb->offload_fwd_mark = 1;
1065 
1066 	skb->protocol = eth_type_trans(skb, dev);
1067 
1068 	*nskb = skb;
1069 
1070 	return 0;
1071 
1072 out_free_skb:
1073 	kfree_skb(skb);
1074 	return err;
1075 }
1076 EXPORT_SYMBOL(ocelot_xtr_poll_frame);
1077 
ocelot_can_inject(struct ocelot * ocelot,int grp)1078 bool ocelot_can_inject(struct ocelot *ocelot, int grp)
1079 {
1080 	u32 val = ocelot_read(ocelot, QS_INJ_STATUS);
1081 
1082 	if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))))
1083 		return false;
1084 	if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))
1085 		return false;
1086 
1087 	return true;
1088 }
1089 EXPORT_SYMBOL(ocelot_can_inject);
1090 
ocelot_ifh_port_set(void * ifh,int port,u32 rew_op,u32 vlan_tag)1091 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag)
1092 {
1093 	ocelot_ifh_set_bypass(ifh, 1);
1094 	ocelot_ifh_set_dest(ifh, BIT_ULL(port));
1095 	ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C);
1096 	if (vlan_tag)
1097 		ocelot_ifh_set_vlan_tci(ifh, vlan_tag);
1098 	if (rew_op)
1099 		ocelot_ifh_set_rew_op(ifh, rew_op);
1100 }
1101 EXPORT_SYMBOL(ocelot_ifh_port_set);
1102 
ocelot_port_inject_frame(struct ocelot * ocelot,int port,int grp,u32 rew_op,struct sk_buff * skb)1103 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
1104 			      u32 rew_op, struct sk_buff *skb)
1105 {
1106 	u32 ifh[OCELOT_TAG_LEN / 4] = {0};
1107 	unsigned int i, count, last;
1108 
1109 	ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1110 			 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
1111 
1112 	ocelot_ifh_port_set(ifh, port, rew_op, skb_vlan_tag_get(skb));
1113 
1114 	for (i = 0; i < OCELOT_TAG_LEN / 4; i++)
1115 		ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp);
1116 
1117 	count = DIV_ROUND_UP(skb->len, 4);
1118 	last = skb->len % 4;
1119 	for (i = 0; i < count; i++)
1120 		ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
1121 
1122 	/* Add padding */
1123 	while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
1124 		ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1125 		i++;
1126 	}
1127 
1128 	/* Indicate EOF and valid bytes in last word */
1129 	ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1130 			 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
1131 			 QS_INJ_CTRL_EOF,
1132 			 QS_INJ_CTRL, grp);
1133 
1134 	/* Add dummy CRC */
1135 	ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1136 	skb_tx_timestamp(skb);
1137 
1138 	skb->dev->stats.tx_packets++;
1139 	skb->dev->stats.tx_bytes += skb->len;
1140 }
1141 EXPORT_SYMBOL(ocelot_port_inject_frame);
1142 
ocelot_drain_cpu_queue(struct ocelot * ocelot,int grp)1143 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
1144 {
1145 	while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
1146 		ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1147 }
1148 EXPORT_SYMBOL(ocelot_drain_cpu_queue);
1149 
ocelot_fdb_add(struct ocelot * ocelot,int port,const unsigned char * addr,u16 vid,const struct net_device * bridge)1150 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr,
1151 		   u16 vid, const struct net_device *bridge)
1152 {
1153 	if (!vid)
1154 		vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1155 
1156 	return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED);
1157 }
1158 EXPORT_SYMBOL(ocelot_fdb_add);
1159 
ocelot_fdb_del(struct ocelot * ocelot,int port,const unsigned char * addr,u16 vid,const struct net_device * bridge)1160 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr,
1161 		   u16 vid, const struct net_device *bridge)
1162 {
1163 	if (!vid)
1164 		vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1165 
1166 	return ocelot_mact_forget(ocelot, addr, vid);
1167 }
1168 EXPORT_SYMBOL(ocelot_fdb_del);
1169 
1170 /* Caller must hold &ocelot->mact_lock */
ocelot_mact_read(struct ocelot * ocelot,int port,int row,int col,struct ocelot_mact_entry * entry)1171 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
1172 			    struct ocelot_mact_entry *entry)
1173 {
1174 	u32 val, dst, macl, mach;
1175 	char mac[ETH_ALEN];
1176 
1177 	/* Set row and column to read from */
1178 	ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
1179 	ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
1180 
1181 	/* Issue a read command */
1182 	ocelot_write(ocelot,
1183 		     ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
1184 		     ANA_TABLES_MACACCESS);
1185 
1186 	if (ocelot_mact_wait_for_completion(ocelot))
1187 		return -ETIMEDOUT;
1188 
1189 	/* Read the entry flags */
1190 	val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
1191 	if (!(val & ANA_TABLES_MACACCESS_VALID))
1192 		return -EINVAL;
1193 
1194 	/* If the entry read has another port configured as its destination,
1195 	 * do not report it.
1196 	 */
1197 	dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
1198 	if (dst != port)
1199 		return -EINVAL;
1200 
1201 	/* Get the entry's MAC address and VLAN id */
1202 	macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
1203 	mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
1204 
1205 	mac[0] = (mach >> 8)  & 0xff;
1206 	mac[1] = (mach >> 0)  & 0xff;
1207 	mac[2] = (macl >> 24) & 0xff;
1208 	mac[3] = (macl >> 16) & 0xff;
1209 	mac[4] = (macl >> 8)  & 0xff;
1210 	mac[5] = (macl >> 0)  & 0xff;
1211 
1212 	entry->vid = (mach >> 16) & 0xfff;
1213 	ether_addr_copy(entry->mac, mac);
1214 
1215 	return 0;
1216 }
1217 
ocelot_mact_flush(struct ocelot * ocelot,int port)1218 int ocelot_mact_flush(struct ocelot *ocelot, int port)
1219 {
1220 	int err;
1221 
1222 	mutex_lock(&ocelot->mact_lock);
1223 
1224 	/* Program ageing filter for a single port */
1225 	ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port),
1226 		     ANA_ANAGEFIL);
1227 
1228 	/* Flushing dynamic FDB entries requires two successive age scans */
1229 	ocelot_write(ocelot,
1230 		     ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1231 		     ANA_TABLES_MACACCESS);
1232 
1233 	err = ocelot_mact_wait_for_completion(ocelot);
1234 	if (err) {
1235 		mutex_unlock(&ocelot->mact_lock);
1236 		return err;
1237 	}
1238 
1239 	/* And second... */
1240 	ocelot_write(ocelot,
1241 		     ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1242 		     ANA_TABLES_MACACCESS);
1243 
1244 	err = ocelot_mact_wait_for_completion(ocelot);
1245 
1246 	/* Restore ageing filter */
1247 	ocelot_write(ocelot, 0, ANA_ANAGEFIL);
1248 
1249 	mutex_unlock(&ocelot->mact_lock);
1250 
1251 	return err;
1252 }
1253 EXPORT_SYMBOL_GPL(ocelot_mact_flush);
1254 
ocelot_fdb_dump(struct ocelot * ocelot,int port,dsa_fdb_dump_cb_t * cb,void * data)1255 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1256 		    dsa_fdb_dump_cb_t *cb, void *data)
1257 {
1258 	int err = 0;
1259 	int i, j;
1260 
1261 	/* We could take the lock just around ocelot_mact_read, but doing so
1262 	 * thousands of times in a row seems rather pointless and inefficient.
1263 	 */
1264 	mutex_lock(&ocelot->mact_lock);
1265 
1266 	/* Loop through all the mac tables entries. */
1267 	for (i = 0; i < ocelot->num_mact_rows; i++) {
1268 		for (j = 0; j < 4; j++) {
1269 			struct ocelot_mact_entry entry;
1270 			bool is_static;
1271 
1272 			err = ocelot_mact_read(ocelot, port, i, j, &entry);
1273 			/* If the entry is invalid (wrong port, invalid...),
1274 			 * skip it.
1275 			 */
1276 			if (err == -EINVAL)
1277 				continue;
1278 			else if (err)
1279 				break;
1280 
1281 			is_static = (entry.type == ENTRYTYPE_LOCKED);
1282 
1283 			/* Hide the reserved VLANs used for
1284 			 * VLAN-unaware bridging.
1285 			 */
1286 			if (entry.vid > OCELOT_RSV_VLAN_RANGE_START)
1287 				entry.vid = 0;
1288 
1289 			err = cb(entry.mac, entry.vid, is_static, data);
1290 			if (err)
1291 				break;
1292 		}
1293 	}
1294 
1295 	mutex_unlock(&ocelot->mact_lock);
1296 
1297 	return err;
1298 }
1299 EXPORT_SYMBOL(ocelot_fdb_dump);
1300 
ocelot_trap_add(struct ocelot * ocelot,int port,unsigned long cookie,bool take_ts,void (* populate)(struct ocelot_vcap_filter * f))1301 int ocelot_trap_add(struct ocelot *ocelot, int port,
1302 		    unsigned long cookie, bool take_ts,
1303 		    void (*populate)(struct ocelot_vcap_filter *f))
1304 {
1305 	struct ocelot_vcap_block *block_vcap_is2;
1306 	struct ocelot_vcap_filter *trap;
1307 	bool new = false;
1308 	int err;
1309 
1310 	block_vcap_is2 = &ocelot->block[VCAP_IS2];
1311 
1312 	trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1313 						   false);
1314 	if (!trap) {
1315 		trap = kzalloc(sizeof(*trap), GFP_KERNEL);
1316 		if (!trap)
1317 			return -ENOMEM;
1318 
1319 		populate(trap);
1320 		trap->prio = 1;
1321 		trap->id.cookie = cookie;
1322 		trap->id.tc_offload = false;
1323 		trap->block_id = VCAP_IS2;
1324 		trap->type = OCELOT_VCAP_FILTER_OFFLOAD;
1325 		trap->lookup = 0;
1326 		trap->action.cpu_copy_ena = true;
1327 		trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY;
1328 		trap->action.port_mask = 0;
1329 		trap->take_ts = take_ts;
1330 		trap->is_trap = true;
1331 		new = true;
1332 	}
1333 
1334 	trap->ingress_port_mask |= BIT(port);
1335 
1336 	if (new)
1337 		err = ocelot_vcap_filter_add(ocelot, trap, NULL);
1338 	else
1339 		err = ocelot_vcap_filter_replace(ocelot, trap);
1340 	if (err) {
1341 		trap->ingress_port_mask &= ~BIT(port);
1342 		if (!trap->ingress_port_mask)
1343 			kfree(trap);
1344 		return err;
1345 	}
1346 
1347 	return 0;
1348 }
1349 
ocelot_trap_del(struct ocelot * ocelot,int port,unsigned long cookie)1350 int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie)
1351 {
1352 	struct ocelot_vcap_block *block_vcap_is2;
1353 	struct ocelot_vcap_filter *trap;
1354 
1355 	block_vcap_is2 = &ocelot->block[VCAP_IS2];
1356 
1357 	trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1358 						   false);
1359 	if (!trap)
1360 		return 0;
1361 
1362 	trap->ingress_port_mask &= ~BIT(port);
1363 	if (!trap->ingress_port_mask)
1364 		return ocelot_vcap_filter_del(ocelot, trap);
1365 
1366 	return ocelot_vcap_filter_replace(ocelot, trap);
1367 }
1368 
ocelot_get_bond_mask(struct ocelot * ocelot,struct net_device * bond)1369 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond)
1370 {
1371 	u32 mask = 0;
1372 	int port;
1373 
1374 	lockdep_assert_held(&ocelot->fwd_domain_lock);
1375 
1376 	for (port = 0; port < ocelot->num_phys_ports; port++) {
1377 		struct ocelot_port *ocelot_port = ocelot->ports[port];
1378 
1379 		if (!ocelot_port)
1380 			continue;
1381 
1382 		if (ocelot_port->bond == bond)
1383 			mask |= BIT(port);
1384 	}
1385 
1386 	return mask;
1387 }
1388 
1389 /* The logical port number of a LAG is equal to the lowest numbered physical
1390  * port ID present in that LAG. It may change if that port ever leaves the LAG.
1391  */
ocelot_bond_get_id(struct ocelot * ocelot,struct net_device * bond)1392 int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond)
1393 {
1394 	int bond_mask = ocelot_get_bond_mask(ocelot, bond);
1395 
1396 	if (!bond_mask)
1397 		return -ENOENT;
1398 
1399 	return __ffs(bond_mask);
1400 }
1401 EXPORT_SYMBOL_GPL(ocelot_bond_get_id);
1402 
1403 /* Returns the mask of user ports assigned to this DSA tag_8021q CPU port.
1404  * Note that when CPU ports are in a LAG, the user ports are assigned to the
1405  * 'primary' CPU port, the one whose physical port number gives the logical
1406  * port number of the LAG.
1407  *
1408  * We leave PGID_SRC poorly configured for the 'secondary' CPU port in the LAG
1409  * (to which no user port is assigned), but it appears that forwarding from
1410  * this secondary CPU port looks at the PGID_SRC associated with the logical
1411  * port ID that it's assigned to, which *is* configured properly.
1412  */
ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot * ocelot,struct ocelot_port * cpu)1413 static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot,
1414 					       struct ocelot_port *cpu)
1415 {
1416 	u32 mask = 0;
1417 	int port;
1418 
1419 	for (port = 0; port < ocelot->num_phys_ports; port++) {
1420 		struct ocelot_port *ocelot_port = ocelot->ports[port];
1421 
1422 		if (!ocelot_port)
1423 			continue;
1424 
1425 		if (ocelot_port->dsa_8021q_cpu == cpu)
1426 			mask |= BIT(port);
1427 	}
1428 
1429 	if (cpu->bond)
1430 		mask &= ~ocelot_get_bond_mask(ocelot, cpu->bond);
1431 
1432 	return mask;
1433 }
1434 
1435 /* Returns the DSA tag_8021q CPU port that the given port is assigned to,
1436  * or the bit mask of CPU ports if said CPU port is in a LAG.
1437  */
ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot * ocelot,int port)1438 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port)
1439 {
1440 	struct ocelot_port *ocelot_port = ocelot->ports[port];
1441 	struct ocelot_port *cpu_port = ocelot_port->dsa_8021q_cpu;
1442 
1443 	if (!cpu_port)
1444 		return 0;
1445 
1446 	if (cpu_port->bond)
1447 		return ocelot_get_bond_mask(ocelot, cpu_port->bond);
1448 
1449 	return BIT(cpu_port->index);
1450 }
1451 EXPORT_SYMBOL_GPL(ocelot_port_assigned_dsa_8021q_cpu_mask);
1452 
ocelot_get_bridge_fwd_mask(struct ocelot * ocelot,int src_port)1453 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port)
1454 {
1455 	struct ocelot_port *ocelot_port = ocelot->ports[src_port];
1456 	const struct net_device *bridge;
1457 	u32 mask = 0;
1458 	int port;
1459 
1460 	if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING)
1461 		return 0;
1462 
1463 	bridge = ocelot_port->bridge;
1464 	if (!bridge)
1465 		return 0;
1466 
1467 	for (port = 0; port < ocelot->num_phys_ports; port++) {
1468 		ocelot_port = ocelot->ports[port];
1469 
1470 		if (!ocelot_port)
1471 			continue;
1472 
1473 		if (ocelot_port->stp_state == BR_STATE_FORWARDING &&
1474 		    ocelot_port->bridge == bridge)
1475 			mask |= BIT(port);
1476 	}
1477 
1478 	return mask;
1479 }
1480 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask);
1481 
ocelot_apply_bridge_fwd_mask(struct ocelot * ocelot,bool joining)1482 static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
1483 {
1484 	int port;
1485 
1486 	lockdep_assert_held(&ocelot->fwd_domain_lock);
1487 
1488 	/* If cut-through forwarding is supported, update the masks before a
1489 	 * port joins the forwarding domain, to avoid potential underruns if it
1490 	 * has the highest speed from the new domain.
1491 	 */
1492 	if (joining && ocelot->ops->cut_through_fwd)
1493 		ocelot->ops->cut_through_fwd(ocelot);
1494 
1495 	/* Apply FWD mask. The loop is needed to add/remove the current port as
1496 	 * a source for the other ports.
1497 	 */
1498 	for (port = 0; port < ocelot->num_phys_ports; port++) {
1499 		struct ocelot_port *ocelot_port = ocelot->ports[port];
1500 		unsigned long mask;
1501 
1502 		if (!ocelot_port) {
1503 			/* Unused ports can't send anywhere */
1504 			mask = 0;
1505 		} else if (ocelot_port->is_dsa_8021q_cpu) {
1506 			/* The DSA tag_8021q CPU ports need to be able to
1507 			 * forward packets to all ports assigned to them.
1508 			 */
1509 			mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot,
1510 								   ocelot_port);
1511 		} else if (ocelot_port->bridge) {
1512 			struct net_device *bond = ocelot_port->bond;
1513 
1514 			mask = ocelot_get_bridge_fwd_mask(ocelot, port);
1515 			mask &= ~BIT(port);
1516 
1517 			mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
1518 									port);
1519 
1520 			if (bond)
1521 				mask &= ~ocelot_get_bond_mask(ocelot, bond);
1522 		} else {
1523 			/* Standalone ports forward only to DSA tag_8021q CPU
1524 			 * ports (if those exist), or to the hardware CPU port
1525 			 * module otherwise.
1526 			 */
1527 			mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
1528 								       port);
1529 		}
1530 
1531 		ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
1532 	}
1533 
1534 	/* If cut-through forwarding is supported and a port is leaving, there
1535 	 * is a chance that cut-through was disabled on the other ports due to
1536 	 * the port which is leaving (it has a higher link speed). We need to
1537 	 * update the cut-through masks of the remaining ports no earlier than
1538 	 * after the port has left, to prevent underruns from happening between
1539 	 * the cut-through update and the forwarding domain update.
1540 	 */
1541 	if (!joining && ocelot->ops->cut_through_fwd)
1542 		ocelot->ops->cut_through_fwd(ocelot);
1543 }
1544 
1545 /* Update PGID_CPU which is the destination port mask used for whitelisting
1546  * unicast addresses filtered towards the host. In the normal and NPI modes,
1547  * this points to the analyzer entry for the CPU port module, while in DSA
1548  * tag_8021q mode, it is a bit mask of all active CPU ports.
1549  * PGID_SRC will take care of forwarding a packet from one user port to
1550  * no more than a single CPU port.
1551  */
ocelot_update_pgid_cpu(struct ocelot * ocelot)1552 static void ocelot_update_pgid_cpu(struct ocelot *ocelot)
1553 {
1554 	int pgid_cpu = 0;
1555 	int port;
1556 
1557 	for (port = 0; port < ocelot->num_phys_ports; port++) {
1558 		struct ocelot_port *ocelot_port = ocelot->ports[port];
1559 
1560 		if (!ocelot_port || !ocelot_port->is_dsa_8021q_cpu)
1561 			continue;
1562 
1563 		pgid_cpu |= BIT(port);
1564 	}
1565 
1566 	if (!pgid_cpu)
1567 		pgid_cpu = BIT(ocelot->num_phys_ports);
1568 
1569 	ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU);
1570 }
1571 
ocelot_port_setup_dsa_8021q_cpu(struct ocelot * ocelot,int cpu)1572 void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu)
1573 {
1574 	struct ocelot_port *cpu_port = ocelot->ports[cpu];
1575 	u16 vid;
1576 
1577 	mutex_lock(&ocelot->fwd_domain_lock);
1578 
1579 	cpu_port->is_dsa_8021q_cpu = true;
1580 
1581 	for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
1582 		ocelot_vlan_member_add(ocelot, cpu, vid, true);
1583 
1584 	ocelot_update_pgid_cpu(ocelot);
1585 
1586 	mutex_unlock(&ocelot->fwd_domain_lock);
1587 }
1588 EXPORT_SYMBOL_GPL(ocelot_port_setup_dsa_8021q_cpu);
1589 
ocelot_port_teardown_dsa_8021q_cpu(struct ocelot * ocelot,int cpu)1590 void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu)
1591 {
1592 	struct ocelot_port *cpu_port = ocelot->ports[cpu];
1593 	u16 vid;
1594 
1595 	mutex_lock(&ocelot->fwd_domain_lock);
1596 
1597 	cpu_port->is_dsa_8021q_cpu = false;
1598 
1599 	for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
1600 		ocelot_vlan_member_del(ocelot, cpu_port->index, vid);
1601 
1602 	ocelot_update_pgid_cpu(ocelot);
1603 
1604 	mutex_unlock(&ocelot->fwd_domain_lock);
1605 }
1606 EXPORT_SYMBOL_GPL(ocelot_port_teardown_dsa_8021q_cpu);
1607 
ocelot_port_assign_dsa_8021q_cpu(struct ocelot * ocelot,int port,int cpu)1608 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port,
1609 				      int cpu)
1610 {
1611 	struct ocelot_port *cpu_port = ocelot->ports[cpu];
1612 
1613 	mutex_lock(&ocelot->fwd_domain_lock);
1614 
1615 	ocelot->ports[port]->dsa_8021q_cpu = cpu_port;
1616 	ocelot_apply_bridge_fwd_mask(ocelot, true);
1617 
1618 	mutex_unlock(&ocelot->fwd_domain_lock);
1619 }
1620 EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu);
1621 
ocelot_port_unassign_dsa_8021q_cpu(struct ocelot * ocelot,int port)1622 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port)
1623 {
1624 	mutex_lock(&ocelot->fwd_domain_lock);
1625 
1626 	ocelot->ports[port]->dsa_8021q_cpu = NULL;
1627 	ocelot_apply_bridge_fwd_mask(ocelot, true);
1628 
1629 	mutex_unlock(&ocelot->fwd_domain_lock);
1630 }
1631 EXPORT_SYMBOL_GPL(ocelot_port_unassign_dsa_8021q_cpu);
1632 
ocelot_bridge_stp_state_set(struct ocelot * ocelot,int port,u8 state)1633 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1634 {
1635 	struct ocelot_port *ocelot_port = ocelot->ports[port];
1636 	u32 learn_ena = 0;
1637 
1638 	mutex_lock(&ocelot->fwd_domain_lock);
1639 
1640 	ocelot_port->stp_state = state;
1641 
1642 	if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) &&
1643 	    ocelot_port->learn_ena)
1644 		learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA;
1645 
1646 	ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA,
1647 		       ANA_PORT_PORT_CFG, port);
1648 
1649 	ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING);
1650 
1651 	mutex_unlock(&ocelot->fwd_domain_lock);
1652 }
1653 EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
1654 
ocelot_set_ageing_time(struct ocelot * ocelot,unsigned int msecs)1655 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
1656 {
1657 	unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
1658 
1659 	/* Setting AGE_PERIOD to zero effectively disables automatic aging,
1660 	 * which is clearly not what our intention is. So avoid that.
1661 	 */
1662 	if (!age_period)
1663 		age_period = 1;
1664 
1665 	ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
1666 }
1667 EXPORT_SYMBOL(ocelot_set_ageing_time);
1668 
ocelot_multicast_get(struct ocelot * ocelot,const unsigned char * addr,u16 vid)1669 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1670 						     const unsigned char *addr,
1671 						     u16 vid)
1672 {
1673 	struct ocelot_multicast *mc;
1674 
1675 	list_for_each_entry(mc, &ocelot->multicast, list) {
1676 		if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1677 			return mc;
1678 	}
1679 
1680 	return NULL;
1681 }
1682 
ocelot_classify_mdb(const unsigned char * addr)1683 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr)
1684 {
1685 	if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e)
1686 		return ENTRYTYPE_MACv4;
1687 	if (addr[0] == 0x33 && addr[1] == 0x33)
1688 		return ENTRYTYPE_MACv6;
1689 	return ENTRYTYPE_LOCKED;
1690 }
1691 
ocelot_pgid_alloc(struct ocelot * ocelot,int index,unsigned long ports)1692 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index,
1693 					     unsigned long ports)
1694 {
1695 	struct ocelot_pgid *pgid;
1696 
1697 	pgid = kzalloc(sizeof(*pgid), GFP_KERNEL);
1698 	if (!pgid)
1699 		return ERR_PTR(-ENOMEM);
1700 
1701 	pgid->ports = ports;
1702 	pgid->index = index;
1703 	refcount_set(&pgid->refcount, 1);
1704 	list_add_tail(&pgid->list, &ocelot->pgids);
1705 
1706 	return pgid;
1707 }
1708 
ocelot_pgid_free(struct ocelot * ocelot,struct ocelot_pgid * pgid)1709 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid)
1710 {
1711 	if (!refcount_dec_and_test(&pgid->refcount))
1712 		return;
1713 
1714 	list_del(&pgid->list);
1715 	kfree(pgid);
1716 }
1717 
ocelot_mdb_get_pgid(struct ocelot * ocelot,const struct ocelot_multicast * mc)1718 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot,
1719 					       const struct ocelot_multicast *mc)
1720 {
1721 	struct ocelot_pgid *pgid;
1722 	int index;
1723 
1724 	/* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
1725 	 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
1726 	 * destination mask table (PGID), the destination set is programmed as
1727 	 * part of the entry MAC address.", and the DEST_IDX is set to 0.
1728 	 */
1729 	if (mc->entry_type == ENTRYTYPE_MACv4 ||
1730 	    mc->entry_type == ENTRYTYPE_MACv6)
1731 		return ocelot_pgid_alloc(ocelot, 0, mc->ports);
1732 
1733 	list_for_each_entry(pgid, &ocelot->pgids, list) {
1734 		/* When searching for a nonreserved multicast PGID, ignore the
1735 		 * dummy PGID of zero that we have for MACv4/MACv6 entries
1736 		 */
1737 		if (pgid->index && pgid->ports == mc->ports) {
1738 			refcount_inc(&pgid->refcount);
1739 			return pgid;
1740 		}
1741 	}
1742 
1743 	/* Search for a free index in the nonreserved multicast PGID area */
1744 	for_each_nonreserved_multicast_dest_pgid(ocelot, index) {
1745 		bool used = false;
1746 
1747 		list_for_each_entry(pgid, &ocelot->pgids, list) {
1748 			if (pgid->index == index) {
1749 				used = true;
1750 				break;
1751 			}
1752 		}
1753 
1754 		if (!used)
1755 			return ocelot_pgid_alloc(ocelot, index, mc->ports);
1756 	}
1757 
1758 	return ERR_PTR(-ENOSPC);
1759 }
1760 
ocelot_encode_ports_to_mdb(unsigned char * addr,struct ocelot_multicast * mc)1761 static void ocelot_encode_ports_to_mdb(unsigned char *addr,
1762 				       struct ocelot_multicast *mc)
1763 {
1764 	ether_addr_copy(addr, mc->addr);
1765 
1766 	if (mc->entry_type == ENTRYTYPE_MACv4) {
1767 		addr[0] = 0;
1768 		addr[1] = mc->ports >> 8;
1769 		addr[2] = mc->ports & 0xff;
1770 	} else if (mc->entry_type == ENTRYTYPE_MACv6) {
1771 		addr[0] = mc->ports >> 8;
1772 		addr[1] = mc->ports & 0xff;
1773 	}
1774 }
1775 
ocelot_port_mdb_add(struct ocelot * ocelot,int port,const struct switchdev_obj_port_mdb * mdb,const struct net_device * bridge)1776 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
1777 			const struct switchdev_obj_port_mdb *mdb,
1778 			const struct net_device *bridge)
1779 {
1780 	unsigned char addr[ETH_ALEN];
1781 	struct ocelot_multicast *mc;
1782 	struct ocelot_pgid *pgid;
1783 	u16 vid = mdb->vid;
1784 
1785 	if (!vid)
1786 		vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1787 
1788 	mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1789 	if (!mc) {
1790 		/* New entry */
1791 		mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1792 		if (!mc)
1793 			return -ENOMEM;
1794 
1795 		mc->entry_type = ocelot_classify_mdb(mdb->addr);
1796 		ether_addr_copy(mc->addr, mdb->addr);
1797 		mc->vid = vid;
1798 
1799 		list_add_tail(&mc->list, &ocelot->multicast);
1800 	} else {
1801 		/* Existing entry. Clean up the current port mask from
1802 		 * hardware now, because we'll be modifying it.
1803 		 */
1804 		ocelot_pgid_free(ocelot, mc->pgid);
1805 		ocelot_encode_ports_to_mdb(addr, mc);
1806 		ocelot_mact_forget(ocelot, addr, vid);
1807 	}
1808 
1809 	mc->ports |= BIT(port);
1810 
1811 	pgid = ocelot_mdb_get_pgid(ocelot, mc);
1812 	if (IS_ERR(pgid)) {
1813 		dev_err(ocelot->dev,
1814 			"Cannot allocate PGID for mdb %pM vid %d\n",
1815 			mc->addr, mc->vid);
1816 		devm_kfree(ocelot->dev, mc);
1817 		return PTR_ERR(pgid);
1818 	}
1819 	mc->pgid = pgid;
1820 
1821 	ocelot_encode_ports_to_mdb(addr, mc);
1822 
1823 	if (mc->entry_type != ENTRYTYPE_MACv4 &&
1824 	    mc->entry_type != ENTRYTYPE_MACv6)
1825 		ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
1826 				 pgid->index);
1827 
1828 	return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
1829 				 mc->entry_type);
1830 }
1831 EXPORT_SYMBOL(ocelot_port_mdb_add);
1832 
ocelot_port_mdb_del(struct ocelot * ocelot,int port,const struct switchdev_obj_port_mdb * mdb,const struct net_device * bridge)1833 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
1834 			const struct switchdev_obj_port_mdb *mdb,
1835 			const struct net_device *bridge)
1836 {
1837 	unsigned char addr[ETH_ALEN];
1838 	struct ocelot_multicast *mc;
1839 	struct ocelot_pgid *pgid;
1840 	u16 vid = mdb->vid;
1841 
1842 	if (!vid)
1843 		vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1844 
1845 	mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1846 	if (!mc)
1847 		return -ENOENT;
1848 
1849 	ocelot_encode_ports_to_mdb(addr, mc);
1850 	ocelot_mact_forget(ocelot, addr, vid);
1851 
1852 	ocelot_pgid_free(ocelot, mc->pgid);
1853 	mc->ports &= ~BIT(port);
1854 	if (!mc->ports) {
1855 		list_del(&mc->list);
1856 		devm_kfree(ocelot->dev, mc);
1857 		return 0;
1858 	}
1859 
1860 	/* We have a PGID with fewer ports now */
1861 	pgid = ocelot_mdb_get_pgid(ocelot, mc);
1862 	if (IS_ERR(pgid))
1863 		return PTR_ERR(pgid);
1864 	mc->pgid = pgid;
1865 
1866 	ocelot_encode_ports_to_mdb(addr, mc);
1867 
1868 	if (mc->entry_type != ENTRYTYPE_MACv4 &&
1869 	    mc->entry_type != ENTRYTYPE_MACv6)
1870 		ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
1871 				 pgid->index);
1872 
1873 	return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
1874 				 mc->entry_type);
1875 }
1876 EXPORT_SYMBOL(ocelot_port_mdb_del);
1877 
ocelot_port_bridge_join(struct ocelot * ocelot,int port,struct net_device * bridge,int bridge_num,struct netlink_ext_ack * extack)1878 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1879 			    struct net_device *bridge, int bridge_num,
1880 			    struct netlink_ext_ack *extack)
1881 {
1882 	struct ocelot_port *ocelot_port = ocelot->ports[port];
1883 	int err;
1884 
1885 	err = ocelot_single_vlan_aware_bridge(ocelot, extack);
1886 	if (err)
1887 		return err;
1888 
1889 	mutex_lock(&ocelot->fwd_domain_lock);
1890 
1891 	ocelot_port->bridge = bridge;
1892 	ocelot_port->bridge_num = bridge_num;
1893 
1894 	ocelot_apply_bridge_fwd_mask(ocelot, true);
1895 
1896 	mutex_unlock(&ocelot->fwd_domain_lock);
1897 
1898 	if (br_vlan_enabled(bridge))
1899 		return 0;
1900 
1901 	return ocelot_add_vlan_unaware_pvid(ocelot, port, bridge);
1902 }
1903 EXPORT_SYMBOL(ocelot_port_bridge_join);
1904 
ocelot_port_bridge_leave(struct ocelot * ocelot,int port,struct net_device * bridge)1905 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1906 			      struct net_device *bridge)
1907 {
1908 	struct ocelot_port *ocelot_port = ocelot->ports[port];
1909 
1910 	mutex_lock(&ocelot->fwd_domain_lock);
1911 
1912 	if (!br_vlan_enabled(bridge))
1913 		ocelot_del_vlan_unaware_pvid(ocelot, port, bridge);
1914 
1915 	ocelot_port->bridge = NULL;
1916 	ocelot_port->bridge_num = -1;
1917 
1918 	ocelot_port_set_pvid(ocelot, port, NULL);
1919 	ocelot_port_manage_port_tag(ocelot, port);
1920 	ocelot_apply_bridge_fwd_mask(ocelot, false);
1921 
1922 	mutex_unlock(&ocelot->fwd_domain_lock);
1923 }
1924 EXPORT_SYMBOL(ocelot_port_bridge_leave);
1925 
ocelot_set_aggr_pgids(struct ocelot * ocelot)1926 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1927 {
1928 	unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0);
1929 	int i, port, lag;
1930 
1931 	/* Reset destination and aggregation PGIDS */
1932 	for_each_unicast_dest_pgid(ocelot, port)
1933 		ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1934 
1935 	for_each_aggr_pgid(ocelot, i)
1936 		ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1937 				 ANA_PGID_PGID, i);
1938 
1939 	/* The visited ports bitmask holds the list of ports offloading any
1940 	 * bonding interface. Initially we mark all these ports as unvisited,
1941 	 * then every time we visit a port in this bitmask, we know that it is
1942 	 * the lowest numbered port, i.e. the one whose logical ID == physical
1943 	 * port ID == LAG ID. So we mark as visited all further ports in the
1944 	 * bitmask that are offloading the same bonding interface. This way,
1945 	 * we set up the aggregation PGIDs only once per bonding interface.
1946 	 */
1947 	for (port = 0; port < ocelot->num_phys_ports; port++) {
1948 		struct ocelot_port *ocelot_port = ocelot->ports[port];
1949 
1950 		if (!ocelot_port || !ocelot_port->bond)
1951 			continue;
1952 
1953 		visited &= ~BIT(port);
1954 	}
1955 
1956 	/* Now, set PGIDs for each active LAG */
1957 	for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1958 		struct net_device *bond = ocelot->ports[lag]->bond;
1959 		int num_active_ports = 0;
1960 		unsigned long bond_mask;
1961 		u8 aggr_idx[16];
1962 
1963 		if (!bond || (visited & BIT(lag)))
1964 			continue;
1965 
1966 		bond_mask = ocelot_get_bond_mask(ocelot, bond);
1967 
1968 		for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1969 			struct ocelot_port *ocelot_port = ocelot->ports[port];
1970 
1971 			// Destination mask
1972 			ocelot_write_rix(ocelot, bond_mask,
1973 					 ANA_PGID_PGID, port);
1974 
1975 			if (ocelot_port->lag_tx_active)
1976 				aggr_idx[num_active_ports++] = port;
1977 		}
1978 
1979 		for_each_aggr_pgid(ocelot, i) {
1980 			u32 ac;
1981 
1982 			ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1983 			ac &= ~bond_mask;
1984 			/* Don't do division by zero if there was no active
1985 			 * port. Just make all aggregation codes zero.
1986 			 */
1987 			if (num_active_ports)
1988 				ac |= BIT(aggr_idx[i % num_active_ports]);
1989 			ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1990 		}
1991 
1992 		/* Mark all ports in the same LAG as visited to avoid applying
1993 		 * the same config again.
1994 		 */
1995 		for (port = lag; port < ocelot->num_phys_ports; port++) {
1996 			struct ocelot_port *ocelot_port = ocelot->ports[port];
1997 
1998 			if (!ocelot_port)
1999 				continue;
2000 
2001 			if (ocelot_port->bond == bond)
2002 				visited |= BIT(port);
2003 		}
2004 	}
2005 }
2006 
2007 /* When offloading a bonding interface, the switch ports configured under the
2008  * same bond must have the same logical port ID, equal to the physical port ID
2009  * of the lowest numbered physical port in that bond. Otherwise, in standalone/
2010  * bridged mode, each port has a logical port ID equal to its physical port ID.
2011  */
ocelot_setup_logical_port_ids(struct ocelot * ocelot)2012 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot)
2013 {
2014 	int port;
2015 
2016 	for (port = 0; port < ocelot->num_phys_ports; port++) {
2017 		struct ocelot_port *ocelot_port = ocelot->ports[port];
2018 		struct net_device *bond;
2019 
2020 		if (!ocelot_port)
2021 			continue;
2022 
2023 		bond = ocelot_port->bond;
2024 		if (bond) {
2025 			int lag = ocelot_bond_get_id(ocelot, bond);
2026 
2027 			ocelot_rmw_gix(ocelot,
2028 				       ANA_PORT_PORT_CFG_PORTID_VAL(lag),
2029 				       ANA_PORT_PORT_CFG_PORTID_VAL_M,
2030 				       ANA_PORT_PORT_CFG, port);
2031 		} else {
2032 			ocelot_rmw_gix(ocelot,
2033 				       ANA_PORT_PORT_CFG_PORTID_VAL(port),
2034 				       ANA_PORT_PORT_CFG_PORTID_VAL_M,
2035 				       ANA_PORT_PORT_CFG, port);
2036 		}
2037 	}
2038 }
2039 
ocelot_migrate_mc(struct ocelot * ocelot,struct ocelot_multicast * mc,unsigned long from_mask,unsigned long to_mask)2040 static int ocelot_migrate_mc(struct ocelot *ocelot, struct ocelot_multicast *mc,
2041 			     unsigned long from_mask, unsigned long to_mask)
2042 {
2043 	unsigned char addr[ETH_ALEN];
2044 	struct ocelot_pgid *pgid;
2045 	u16 vid = mc->vid;
2046 
2047 	dev_dbg(ocelot->dev,
2048 		"Migrating multicast %pM vid %d from port mask 0x%lx to 0x%lx\n",
2049 		mc->addr, mc->vid, from_mask, to_mask);
2050 
2051 	/* First clean up the current port mask from hardware, because
2052 	 * we'll be modifying it.
2053 	 */
2054 	ocelot_pgid_free(ocelot, mc->pgid);
2055 	ocelot_encode_ports_to_mdb(addr, mc);
2056 	ocelot_mact_forget(ocelot, addr, vid);
2057 
2058 	mc->ports &= ~from_mask;
2059 	mc->ports |= to_mask;
2060 
2061 	pgid = ocelot_mdb_get_pgid(ocelot, mc);
2062 	if (IS_ERR(pgid)) {
2063 		dev_err(ocelot->dev,
2064 			"Cannot allocate PGID for mdb %pM vid %d\n",
2065 			mc->addr, mc->vid);
2066 		devm_kfree(ocelot->dev, mc);
2067 		return PTR_ERR(pgid);
2068 	}
2069 	mc->pgid = pgid;
2070 
2071 	ocelot_encode_ports_to_mdb(addr, mc);
2072 
2073 	if (mc->entry_type != ENTRYTYPE_MACv4 &&
2074 	    mc->entry_type != ENTRYTYPE_MACv6)
2075 		ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2076 				 pgid->index);
2077 
2078 	return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2079 				 mc->entry_type);
2080 }
2081 
ocelot_migrate_mdbs(struct ocelot * ocelot,unsigned long from_mask,unsigned long to_mask)2082 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask,
2083 			unsigned long to_mask)
2084 {
2085 	struct ocelot_multicast *mc;
2086 	int err;
2087 
2088 	list_for_each_entry(mc, &ocelot->multicast, list) {
2089 		if (!(mc->ports & from_mask))
2090 			continue;
2091 
2092 		err = ocelot_migrate_mc(ocelot, mc, from_mask, to_mask);
2093 		if (err)
2094 			return err;
2095 	}
2096 
2097 	return 0;
2098 }
2099 EXPORT_SYMBOL_GPL(ocelot_migrate_mdbs);
2100 
2101 /* Documentation for PORTID_VAL says:
2102  *     Logical port number for front port. If port is not a member of a LLAG,
2103  *     then PORTID must be set to the physical port number.
2104  *     If port is a member of a LLAG, then PORTID must be set to the common
2105  *     PORTID_VAL used for all member ports of the LLAG.
2106  *     The value must not exceed the number of physical ports on the device.
2107  *
2108  * This means we have little choice but to migrate FDB entries pointing towards
2109  * a logical port when that changes.
2110  */
ocelot_migrate_lag_fdbs(struct ocelot * ocelot,struct net_device * bond,int lag)2111 static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot,
2112 				    struct net_device *bond,
2113 				    int lag)
2114 {
2115 	struct ocelot_lag_fdb *fdb;
2116 	int err;
2117 
2118 	lockdep_assert_held(&ocelot->fwd_domain_lock);
2119 
2120 	list_for_each_entry(fdb, &ocelot->lag_fdbs, list) {
2121 		if (fdb->bond != bond)
2122 			continue;
2123 
2124 		err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid);
2125 		if (err) {
2126 			dev_err(ocelot->dev,
2127 				"failed to delete LAG %s FDB %pM vid %d: %pe\n",
2128 				bond->name, fdb->addr, fdb->vid, ERR_PTR(err));
2129 		}
2130 
2131 		err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid,
2132 					ENTRYTYPE_LOCKED);
2133 		if (err) {
2134 			dev_err(ocelot->dev,
2135 				"failed to migrate LAG %s FDB %pM vid %d: %pe\n",
2136 				bond->name, fdb->addr, fdb->vid, ERR_PTR(err));
2137 		}
2138 	}
2139 }
2140 
ocelot_port_lag_join(struct ocelot * ocelot,int port,struct net_device * bond,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)2141 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
2142 			 struct net_device *bond,
2143 			 struct netdev_lag_upper_info *info,
2144 			 struct netlink_ext_ack *extack)
2145 {
2146 	if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2147 		NL_SET_ERR_MSG_MOD(extack,
2148 				   "Can only offload LAG using hash TX type");
2149 		return -EOPNOTSUPP;
2150 	}
2151 
2152 	mutex_lock(&ocelot->fwd_domain_lock);
2153 
2154 	ocelot->ports[port]->bond = bond;
2155 
2156 	ocelot_setup_logical_port_ids(ocelot);
2157 	ocelot_apply_bridge_fwd_mask(ocelot, true);
2158 	ocelot_set_aggr_pgids(ocelot);
2159 
2160 	mutex_unlock(&ocelot->fwd_domain_lock);
2161 
2162 	return 0;
2163 }
2164 EXPORT_SYMBOL(ocelot_port_lag_join);
2165 
ocelot_port_lag_leave(struct ocelot * ocelot,int port,struct net_device * bond)2166 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
2167 			   struct net_device *bond)
2168 {
2169 	int old_lag_id, new_lag_id;
2170 
2171 	mutex_lock(&ocelot->fwd_domain_lock);
2172 
2173 	old_lag_id = ocelot_bond_get_id(ocelot, bond);
2174 
2175 	ocelot->ports[port]->bond = NULL;
2176 
2177 	ocelot_setup_logical_port_ids(ocelot);
2178 	ocelot_apply_bridge_fwd_mask(ocelot, false);
2179 	ocelot_set_aggr_pgids(ocelot);
2180 
2181 	new_lag_id = ocelot_bond_get_id(ocelot, bond);
2182 
2183 	if (new_lag_id >= 0 && old_lag_id != new_lag_id)
2184 		ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id);
2185 
2186 	mutex_unlock(&ocelot->fwd_domain_lock);
2187 }
2188 EXPORT_SYMBOL(ocelot_port_lag_leave);
2189 
ocelot_port_lag_change(struct ocelot * ocelot,int port,bool lag_tx_active)2190 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active)
2191 {
2192 	struct ocelot_port *ocelot_port = ocelot->ports[port];
2193 
2194 	mutex_lock(&ocelot->fwd_domain_lock);
2195 
2196 	ocelot_port->lag_tx_active = lag_tx_active;
2197 
2198 	/* Rebalance the LAGs */
2199 	ocelot_set_aggr_pgids(ocelot);
2200 
2201 	mutex_unlock(&ocelot->fwd_domain_lock);
2202 }
2203 EXPORT_SYMBOL(ocelot_port_lag_change);
2204 
ocelot_lag_fdb_add(struct ocelot * ocelot,struct net_device * bond,const unsigned char * addr,u16 vid,const struct net_device * bridge)2205 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond,
2206 		       const unsigned char *addr, u16 vid,
2207 		       const struct net_device *bridge)
2208 {
2209 	struct ocelot_lag_fdb *fdb;
2210 	int lag, err;
2211 
2212 	fdb = kzalloc(sizeof(*fdb), GFP_KERNEL);
2213 	if (!fdb)
2214 		return -ENOMEM;
2215 
2216 	mutex_lock(&ocelot->fwd_domain_lock);
2217 
2218 	if (!vid)
2219 		vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2220 
2221 	ether_addr_copy(fdb->addr, addr);
2222 	fdb->vid = vid;
2223 	fdb->bond = bond;
2224 
2225 	lag = ocelot_bond_get_id(ocelot, bond);
2226 
2227 	err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED);
2228 	if (err) {
2229 		mutex_unlock(&ocelot->fwd_domain_lock);
2230 		kfree(fdb);
2231 		return err;
2232 	}
2233 
2234 	list_add_tail(&fdb->list, &ocelot->lag_fdbs);
2235 	mutex_unlock(&ocelot->fwd_domain_lock);
2236 
2237 	return 0;
2238 }
2239 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_add);
2240 
ocelot_lag_fdb_del(struct ocelot * ocelot,struct net_device * bond,const unsigned char * addr,u16 vid,const struct net_device * bridge)2241 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond,
2242 		       const unsigned char *addr, u16 vid,
2243 		       const struct net_device *bridge)
2244 {
2245 	struct ocelot_lag_fdb *fdb, *tmp;
2246 
2247 	mutex_lock(&ocelot->fwd_domain_lock);
2248 
2249 	if (!vid)
2250 		vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2251 
2252 	list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) {
2253 		if (!ether_addr_equal(fdb->addr, addr) || fdb->vid != vid ||
2254 		    fdb->bond != bond)
2255 			continue;
2256 
2257 		ocelot_mact_forget(ocelot, addr, vid);
2258 		list_del(&fdb->list);
2259 		mutex_unlock(&ocelot->fwd_domain_lock);
2260 		kfree(fdb);
2261 
2262 		return 0;
2263 	}
2264 
2265 	mutex_unlock(&ocelot->fwd_domain_lock);
2266 
2267 	return -ENOENT;
2268 }
2269 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_del);
2270 
2271 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
2272  * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
2273  * In the special case that it's the NPI port that we're configuring, the
2274  * length of the tag and optional prefix needs to be accounted for privately,
2275  * in order to be able to sustain communication at the requested @sdu.
2276  */
ocelot_port_set_maxlen(struct ocelot * ocelot,int port,size_t sdu)2277 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
2278 {
2279 	struct ocelot_port *ocelot_port = ocelot->ports[port];
2280 	int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
2281 	int pause_start, pause_stop;
2282 	int atop, atop_tot;
2283 
2284 	if (port == ocelot->npi) {
2285 		maxlen += OCELOT_TAG_LEN;
2286 
2287 		if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2288 			maxlen += OCELOT_SHORT_PREFIX_LEN;
2289 		else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2290 			maxlen += OCELOT_LONG_PREFIX_LEN;
2291 	}
2292 
2293 	ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
2294 
2295 	/* Set Pause watermark hysteresis */
2296 	pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
2297 	pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
2298 	ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
2299 			    pause_start);
2300 	ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
2301 			    pause_stop);
2302 
2303 	/* Tail dropping watermarks */
2304 	atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) /
2305 		   OCELOT_BUFFER_CELL_SZ;
2306 	atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
2307 	ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
2308 	ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
2309 }
2310 EXPORT_SYMBOL(ocelot_port_set_maxlen);
2311 
ocelot_get_max_mtu(struct ocelot * ocelot,int port)2312 int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
2313 {
2314 	int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
2315 
2316 	if (port == ocelot->npi) {
2317 		max_mtu -= OCELOT_TAG_LEN;
2318 
2319 		if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2320 			max_mtu -= OCELOT_SHORT_PREFIX_LEN;
2321 		else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2322 			max_mtu -= OCELOT_LONG_PREFIX_LEN;
2323 	}
2324 
2325 	return max_mtu;
2326 }
2327 EXPORT_SYMBOL(ocelot_get_max_mtu);
2328 
ocelot_port_set_learning(struct ocelot * ocelot,int port,bool enabled)2329 static void ocelot_port_set_learning(struct ocelot *ocelot, int port,
2330 				     bool enabled)
2331 {
2332 	struct ocelot_port *ocelot_port = ocelot->ports[port];
2333 	u32 val = 0;
2334 
2335 	if (enabled)
2336 		val = ANA_PORT_PORT_CFG_LEARN_ENA;
2337 
2338 	ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA,
2339 		       ANA_PORT_PORT_CFG, port);
2340 
2341 	ocelot_port->learn_ena = enabled;
2342 }
2343 
ocelot_port_set_ucast_flood(struct ocelot * ocelot,int port,bool enabled)2344 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port,
2345 					bool enabled)
2346 {
2347 	u32 val = 0;
2348 
2349 	if (enabled)
2350 		val = BIT(port);
2351 
2352 	ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC);
2353 }
2354 
ocelot_port_set_mcast_flood(struct ocelot * ocelot,int port,bool enabled)2355 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port,
2356 					bool enabled)
2357 {
2358 	u32 val = 0;
2359 
2360 	if (enabled)
2361 		val = BIT(port);
2362 
2363 	ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC);
2364 	ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV4);
2365 	ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV6);
2366 }
2367 
ocelot_port_set_bcast_flood(struct ocelot * ocelot,int port,bool enabled)2368 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port,
2369 					bool enabled)
2370 {
2371 	u32 val = 0;
2372 
2373 	if (enabled)
2374 		val = BIT(port);
2375 
2376 	ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC);
2377 }
2378 
ocelot_port_pre_bridge_flags(struct ocelot * ocelot,int port,struct switchdev_brport_flags flags)2379 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
2380 				 struct switchdev_brport_flags flags)
2381 {
2382 	if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
2383 			   BR_BCAST_FLOOD))
2384 		return -EINVAL;
2385 
2386 	return 0;
2387 }
2388 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags);
2389 
ocelot_port_bridge_flags(struct ocelot * ocelot,int port,struct switchdev_brport_flags flags)2390 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
2391 			      struct switchdev_brport_flags flags)
2392 {
2393 	if (flags.mask & BR_LEARNING)
2394 		ocelot_port_set_learning(ocelot, port,
2395 					 !!(flags.val & BR_LEARNING));
2396 
2397 	if (flags.mask & BR_FLOOD)
2398 		ocelot_port_set_ucast_flood(ocelot, port,
2399 					    !!(flags.val & BR_FLOOD));
2400 
2401 	if (flags.mask & BR_MCAST_FLOOD)
2402 		ocelot_port_set_mcast_flood(ocelot, port,
2403 					    !!(flags.val & BR_MCAST_FLOOD));
2404 
2405 	if (flags.mask & BR_BCAST_FLOOD)
2406 		ocelot_port_set_bcast_flood(ocelot, port,
2407 					    !!(flags.val & BR_BCAST_FLOOD));
2408 }
2409 EXPORT_SYMBOL(ocelot_port_bridge_flags);
2410 
ocelot_port_get_default_prio(struct ocelot * ocelot,int port)2411 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port)
2412 {
2413 	int val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
2414 
2415 	return ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val);
2416 }
2417 EXPORT_SYMBOL_GPL(ocelot_port_get_default_prio);
2418 
ocelot_port_set_default_prio(struct ocelot * ocelot,int port,u8 prio)2419 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio)
2420 {
2421 	if (prio >= OCELOT_NUM_TC)
2422 		return -ERANGE;
2423 
2424 	ocelot_rmw_gix(ocelot,
2425 		       ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(prio),
2426 		       ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M,
2427 		       ANA_PORT_QOS_CFG,
2428 		       port);
2429 
2430 	return 0;
2431 }
2432 EXPORT_SYMBOL_GPL(ocelot_port_set_default_prio);
2433 
ocelot_port_get_dscp_prio(struct ocelot * ocelot,int port,u8 dscp)2434 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp)
2435 {
2436 	int qos_cfg = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
2437 	int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2438 
2439 	/* Return error if DSCP prioritization isn't enabled */
2440 	if (!(qos_cfg & ANA_PORT_QOS_CFG_QOS_DSCP_ENA))
2441 		return -EOPNOTSUPP;
2442 
2443 	if (qos_cfg & ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA) {
2444 		dscp = ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(dscp_cfg);
2445 		/* Re-read ANA_DSCP_CFG for the translated DSCP */
2446 		dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2447 	}
2448 
2449 	/* If the DSCP value is not trusted, the QoS classification falls back
2450 	 * to VLAN PCP or port-based default.
2451 	 */
2452 	if (!(dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA))
2453 		return -EOPNOTSUPP;
2454 
2455 	return ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg);
2456 }
2457 EXPORT_SYMBOL_GPL(ocelot_port_get_dscp_prio);
2458 
ocelot_port_add_dscp_prio(struct ocelot * ocelot,int port,u8 dscp,u8 prio)2459 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
2460 {
2461 	int mask, val;
2462 
2463 	if (prio >= OCELOT_NUM_TC)
2464 		return -ERANGE;
2465 
2466 	/* There is at least one app table priority (this one), so we need to
2467 	 * make sure DSCP prioritization is enabled on the port.
2468 	 * Also make sure DSCP translation is disabled
2469 	 * (dcbnl doesn't support it).
2470 	 */
2471 	mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA |
2472 	       ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA;
2473 
2474 	ocelot_rmw_gix(ocelot, ANA_PORT_QOS_CFG_QOS_DSCP_ENA, mask,
2475 		       ANA_PORT_QOS_CFG, port);
2476 
2477 	/* Trust this DSCP value and map it to the given QoS class */
2478 	val = ANA_DSCP_CFG_DSCP_TRUST_ENA | ANA_DSCP_CFG_QOS_DSCP_VAL(prio);
2479 
2480 	ocelot_write_rix(ocelot, val, ANA_DSCP_CFG, dscp);
2481 
2482 	return 0;
2483 }
2484 EXPORT_SYMBOL_GPL(ocelot_port_add_dscp_prio);
2485 
ocelot_port_del_dscp_prio(struct ocelot * ocelot,int port,u8 dscp,u8 prio)2486 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
2487 {
2488 	int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2489 	int mask, i;
2490 
2491 	/* During a "dcb app replace" command, the new app table entry will be
2492 	 * added first, then the old one will be deleted. But the hardware only
2493 	 * supports one QoS class per DSCP value (duh), so if we blindly delete
2494 	 * the app table entry for this DSCP value, we end up deleting the
2495 	 * entry with the new priority. Avoid that by checking whether user
2496 	 * space wants to delete the priority which is currently configured, or
2497 	 * something else which is no longer current.
2498 	 */
2499 	if (ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg) != prio)
2500 		return 0;
2501 
2502 	/* Untrust this DSCP value */
2503 	ocelot_write_rix(ocelot, 0, ANA_DSCP_CFG, dscp);
2504 
2505 	for (i = 0; i < 64; i++) {
2506 		int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, i);
2507 
2508 		/* There are still app table entries on the port, so we need to
2509 		 * keep DSCP enabled, nothing to do.
2510 		 */
2511 		if (dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA)
2512 			return 0;
2513 	}
2514 
2515 	/* Disable DSCP QoS classification if there isn't any trusted
2516 	 * DSCP value left.
2517 	 */
2518 	mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA |
2519 	       ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA;
2520 
2521 	ocelot_rmw_gix(ocelot, 0, mask, ANA_PORT_QOS_CFG, port);
2522 
2523 	return 0;
2524 }
2525 EXPORT_SYMBOL_GPL(ocelot_port_del_dscp_prio);
2526 
ocelot_mirror_get(struct ocelot * ocelot,int to,struct netlink_ext_ack * extack)2527 struct ocelot_mirror *ocelot_mirror_get(struct ocelot *ocelot, int to,
2528 					struct netlink_ext_ack *extack)
2529 {
2530 	struct ocelot_mirror *m = ocelot->mirror;
2531 
2532 	if (m) {
2533 		if (m->to != to) {
2534 			NL_SET_ERR_MSG_MOD(extack,
2535 					   "Mirroring already configured towards different egress port");
2536 			return ERR_PTR(-EBUSY);
2537 		}
2538 
2539 		refcount_inc(&m->refcount);
2540 		return m;
2541 	}
2542 
2543 	m = kzalloc(sizeof(*m), GFP_KERNEL);
2544 	if (!m)
2545 		return ERR_PTR(-ENOMEM);
2546 
2547 	m->to = to;
2548 	refcount_set(&m->refcount, 1);
2549 	ocelot->mirror = m;
2550 
2551 	/* Program the mirror port to hardware */
2552 	ocelot_write(ocelot, BIT(to), ANA_MIRRORPORTS);
2553 
2554 	return m;
2555 }
2556 
ocelot_mirror_put(struct ocelot * ocelot)2557 void ocelot_mirror_put(struct ocelot *ocelot)
2558 {
2559 	struct ocelot_mirror *m = ocelot->mirror;
2560 
2561 	if (!refcount_dec_and_test(&m->refcount))
2562 		return;
2563 
2564 	ocelot_write(ocelot, 0, ANA_MIRRORPORTS);
2565 	ocelot->mirror = NULL;
2566 	kfree(m);
2567 }
2568 
ocelot_port_mirror_add(struct ocelot * ocelot,int from,int to,bool ingress,struct netlink_ext_ack * extack)2569 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to,
2570 			   bool ingress, struct netlink_ext_ack *extack)
2571 {
2572 	struct ocelot_mirror *m = ocelot_mirror_get(ocelot, to, extack);
2573 
2574 	if (IS_ERR(m))
2575 		return PTR_ERR(m);
2576 
2577 	if (ingress) {
2578 		ocelot_rmw_gix(ocelot, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2579 			       ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2580 			       ANA_PORT_PORT_CFG, from);
2581 	} else {
2582 		ocelot_rmw(ocelot, BIT(from), BIT(from),
2583 			   ANA_EMIRRORPORTS);
2584 	}
2585 
2586 	return 0;
2587 }
2588 EXPORT_SYMBOL_GPL(ocelot_port_mirror_add);
2589 
ocelot_port_mirror_del(struct ocelot * ocelot,int from,bool ingress)2590 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress)
2591 {
2592 	if (ingress) {
2593 		ocelot_rmw_gix(ocelot, 0, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2594 			       ANA_PORT_PORT_CFG, from);
2595 	} else {
2596 		ocelot_rmw(ocelot, 0, BIT(from), ANA_EMIRRORPORTS);
2597 	}
2598 
2599 	ocelot_mirror_put(ocelot);
2600 }
2601 EXPORT_SYMBOL_GPL(ocelot_port_mirror_del);
2602 
ocelot_init_port(struct ocelot * ocelot,int port)2603 void ocelot_init_port(struct ocelot *ocelot, int port)
2604 {
2605 	struct ocelot_port *ocelot_port = ocelot->ports[port];
2606 
2607 	skb_queue_head_init(&ocelot_port->tx_skbs);
2608 
2609 	/* Basic L2 initialization */
2610 
2611 	/* Set MAC IFG Gaps
2612 	 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
2613 	 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
2614 	 */
2615 	ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
2616 			   DEV_MAC_IFG_CFG);
2617 
2618 	/* Load seed (0) and set MAC HDX late collision  */
2619 	ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
2620 			   DEV_MAC_HDX_CFG_SEED_LOAD,
2621 			   DEV_MAC_HDX_CFG);
2622 	mdelay(1);
2623 	ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
2624 			   DEV_MAC_HDX_CFG);
2625 
2626 	/* Set Max Length and maximum tags allowed */
2627 	ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
2628 	ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
2629 			   DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
2630 			   DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
2631 			   DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
2632 			   DEV_MAC_TAGS_CFG);
2633 
2634 	/* Set SMAC of Pause frame (00:00:00:00:00:00) */
2635 	ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
2636 	ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
2637 
2638 	/* Enable transmission of pause frames */
2639 	ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
2640 
2641 	/* Drop frames with multicast source address */
2642 	ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2643 		       ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2644 		       ANA_PORT_DROP_CFG, port);
2645 
2646 	/* Set default VLAN and tag type to 8021Q. */
2647 	ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
2648 		       REW_PORT_VLAN_CFG_PORT_TPID_M,
2649 		       REW_PORT_VLAN_CFG, port);
2650 
2651 	/* Disable source address learning for standalone mode */
2652 	ocelot_port_set_learning(ocelot, port, false);
2653 
2654 	/* Set the port's initial logical port ID value, enable receiving
2655 	 * frames on it, and configure the MAC address learning type to
2656 	 * automatic.
2657 	 */
2658 	ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
2659 			 ANA_PORT_PORT_CFG_RECV_ENA |
2660 			 ANA_PORT_PORT_CFG_PORTID_VAL(port),
2661 			 ANA_PORT_PORT_CFG, port);
2662 
2663 	/* Enable vcap lookups */
2664 	ocelot_vcap_enable(ocelot, port);
2665 }
2666 EXPORT_SYMBOL(ocelot_init_port);
2667 
2668 /* Configure and enable the CPU port module, which is a set of queues
2669  * accessible through register MMIO, frame DMA or Ethernet (in case
2670  * NPI mode is used).
2671  */
ocelot_cpu_port_init(struct ocelot * ocelot)2672 static void ocelot_cpu_port_init(struct ocelot *ocelot)
2673 {
2674 	int cpu = ocelot->num_phys_ports;
2675 
2676 	/* The unicast destination PGID for the CPU port module is unused */
2677 	ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
2678 	/* Instead set up a multicast destination PGID for traffic copied to
2679 	 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
2680 	 * addresses will be copied to the CPU via this PGID.
2681 	 */
2682 	ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
2683 	ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
2684 			 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
2685 			 ANA_PORT_PORT_CFG, cpu);
2686 
2687 	/* Enable CPU port module */
2688 	ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
2689 	/* CPU port Injection/Extraction configuration */
2690 	ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
2691 			    OCELOT_TAG_PREFIX_NONE);
2692 	ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
2693 			    OCELOT_TAG_PREFIX_NONE);
2694 
2695 	/* Configure the CPU port to be VLAN aware */
2696 	ocelot_write_gix(ocelot,
2697 			 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_STANDALONE_PVID) |
2698 			 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
2699 			 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
2700 			 ANA_PORT_VLAN_CFG, cpu);
2701 }
2702 
ocelot_detect_features(struct ocelot * ocelot)2703 static void ocelot_detect_features(struct ocelot *ocelot)
2704 {
2705 	int mmgt, eq_ctrl;
2706 
2707 	/* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds
2708 	 * the number of 240-byte free memory words (aka 4-cell chunks) and not
2709 	 * 192 bytes as the documentation incorrectly says.
2710 	 */
2711 	mmgt = ocelot_read(ocelot, SYS_MMGT);
2712 	ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt);
2713 
2714 	eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL);
2715 	ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl);
2716 }
2717 
ocelot_init(struct ocelot * ocelot)2718 int ocelot_init(struct ocelot *ocelot)
2719 {
2720 	int i, ret;
2721 	u32 port;
2722 
2723 	if (ocelot->ops->reset) {
2724 		ret = ocelot->ops->reset(ocelot);
2725 		if (ret) {
2726 			dev_err(ocelot->dev, "Switch reset failed\n");
2727 			return ret;
2728 		}
2729 	}
2730 
2731 	mutex_init(&ocelot->ptp_lock);
2732 	mutex_init(&ocelot->mact_lock);
2733 	mutex_init(&ocelot->fwd_domain_lock);
2734 	mutex_init(&ocelot->tas_lock);
2735 	spin_lock_init(&ocelot->ptp_clock_lock);
2736 	spin_lock_init(&ocelot->ts_id_lock);
2737 
2738 	ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
2739 	if (!ocelot->owq)
2740 		return -ENOMEM;
2741 
2742 	ret = ocelot_stats_init(ocelot);
2743 	if (ret) {
2744 		destroy_workqueue(ocelot->owq);
2745 		return ret;
2746 	}
2747 
2748 	INIT_LIST_HEAD(&ocelot->multicast);
2749 	INIT_LIST_HEAD(&ocelot->pgids);
2750 	INIT_LIST_HEAD(&ocelot->vlans);
2751 	INIT_LIST_HEAD(&ocelot->lag_fdbs);
2752 	ocelot_detect_features(ocelot);
2753 	ocelot_mact_init(ocelot);
2754 	ocelot_vlan_init(ocelot);
2755 	ocelot_vcap_init(ocelot);
2756 	ocelot_cpu_port_init(ocelot);
2757 
2758 	if (ocelot->ops->psfp_init)
2759 		ocelot->ops->psfp_init(ocelot);
2760 
2761 	for (port = 0; port < ocelot->num_phys_ports; port++) {
2762 		/* Clear all counters (5 groups) */
2763 		ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
2764 				     SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
2765 			     SYS_STAT_CFG);
2766 	}
2767 
2768 	/* Only use S-Tag */
2769 	ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
2770 
2771 	/* Aggregation mode */
2772 	ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
2773 			     ANA_AGGR_CFG_AC_DMAC_ENA |
2774 			     ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
2775 			     ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA |
2776 			     ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA |
2777 			     ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA,
2778 			     ANA_AGGR_CFG);
2779 
2780 	/* Set MAC age time to default value. The entry is aged after
2781 	 * 2*AGE_PERIOD
2782 	 */
2783 	ocelot_write(ocelot,
2784 		     ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
2785 		     ANA_AUTOAGE);
2786 
2787 	/* Disable learning for frames discarded by VLAN ingress filtering */
2788 	regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
2789 
2790 	/* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
2791 	ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
2792 		     SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
2793 
2794 	/* Setup flooding PGIDs */
2795 	for (i = 0; i < ocelot->num_flooding_pgids; i++)
2796 		ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
2797 				 ANA_FLOODING_FLD_BROADCAST(PGID_BC) |
2798 				 ANA_FLOODING_FLD_UNICAST(PGID_UC),
2799 				 ANA_FLOODING, i);
2800 	ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
2801 		     ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
2802 		     ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
2803 		     ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
2804 		     ANA_FLOODING_IPMC);
2805 
2806 	for (port = 0; port < ocelot->num_phys_ports; port++) {
2807 		/* Transmit the frame to the local port. */
2808 		ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2809 		/* Do not forward BPDU frames to the front ports. */
2810 		ocelot_write_gix(ocelot,
2811 				 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
2812 				 ANA_PORT_CPU_FWD_BPDU_CFG,
2813 				 port);
2814 		/* Ensure bridging is disabled */
2815 		ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
2816 	}
2817 
2818 	for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
2819 		u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
2820 
2821 		ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
2822 	}
2823 
2824 	ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE);
2825 
2826 	/* Allow broadcast and unknown L2 multicast to the CPU. */
2827 	ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2828 		       ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2829 		       ANA_PGID_PGID, PGID_MC);
2830 	ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2831 		       ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2832 		       ANA_PGID_PGID, PGID_BC);
2833 	ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
2834 	ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
2835 
2836 	/* Allow manual injection via DEVCPU_QS registers, and byte swap these
2837 	 * registers endianness.
2838 	 */
2839 	ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
2840 			 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
2841 	ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
2842 			 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
2843 	ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
2844 		     ANA_CPUQ_CFG_CPUQ_LRN(2) |
2845 		     ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
2846 		     ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
2847 		     ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
2848 		     ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
2849 		     ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
2850 		     ANA_CPUQ_CFG_CPUQ_IGMP(6) |
2851 		     ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
2852 	for (i = 0; i < 16; i++)
2853 		ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
2854 				 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
2855 				 ANA_CPUQ_8021_CFG, i);
2856 
2857 	return 0;
2858 }
2859 EXPORT_SYMBOL(ocelot_init);
2860 
ocelot_deinit(struct ocelot * ocelot)2861 void ocelot_deinit(struct ocelot *ocelot)
2862 {
2863 	ocelot_stats_deinit(ocelot);
2864 	destroy_workqueue(ocelot->owq);
2865 }
2866 EXPORT_SYMBOL(ocelot_deinit);
2867 
ocelot_deinit_port(struct ocelot * ocelot,int port)2868 void ocelot_deinit_port(struct ocelot *ocelot, int port)
2869 {
2870 	struct ocelot_port *ocelot_port = ocelot->ports[port];
2871 
2872 	skb_queue_purge(&ocelot_port->tx_skbs);
2873 }
2874 EXPORT_SYMBOL(ocelot_deinit_port);
2875 
2876 MODULE_LICENSE("Dual MIT/GPL");
2877