1 /*
2  * Copyright 2013 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "priv.h"
25 
26 #include <subdev/bios.h>
27 #include <subdev/bios/boost.h>
28 #include <subdev/bios/cstep.h>
29 #include <subdev/bios/perf.h>
30 #include <subdev/bios/vpstate.h>
31 #include <subdev/fb.h>
32 #include <subdev/therm.h>
33 #include <subdev/volt.h>
34 
35 #include <core/option.h>
36 
37 /******************************************************************************
38  * misc
39  *****************************************************************************/
40 static u32
nvkm_clk_adjust(struct nvkm_clk * clk,bool adjust,u8 pstate,u8 domain,u32 input)41 nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust,
42 		u8 pstate, u8 domain, u32 input)
43 {
44 	struct nvkm_bios *bios = clk->subdev.device->bios;
45 	struct nvbios_boostE boostE;
46 	u8  ver, hdr, cnt, len;
47 	u32 data;
48 
49 	data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);
50 	if (data) {
51 		struct nvbios_boostS boostS;
52 		u8  idx = 0, sver, shdr;
53 		u32 subd;
54 
55 		input = max(boostE.min, input);
56 		input = min(boostE.max, input);
57 		do {
58 			sver = ver;
59 			shdr = hdr;
60 			subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr,
61 					      cnt, len, &boostS);
62 			if (subd && boostS.domain == domain) {
63 				if (adjust)
64 					input = input * boostS.percent / 100;
65 				input = max(boostS.min, input);
66 				input = min(boostS.max, input);
67 				break;
68 			}
69 		} while (subd);
70 	}
71 
72 	return input;
73 }
74 
75 /******************************************************************************
76  * C-States
77  *****************************************************************************/
78 static bool
nvkm_cstate_valid(struct nvkm_clk * clk,struct nvkm_cstate * cstate,u32 max_volt,int temp)79 nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate,
80 		  u32 max_volt, int temp)
81 {
82 	const struct nvkm_domain *domain = clk->domains;
83 	struct nvkm_volt *volt = clk->subdev.device->volt;
84 	int voltage;
85 
86 	while (domain && domain->name != nv_clk_src_max) {
87 		if (domain->flags & NVKM_CLK_DOM_FLAG_VPSTATE) {
88 			u32 freq = cstate->domain[domain->name];
89 			switch (clk->boost_mode) {
90 			case NVKM_CLK_BOOST_NONE:
91 				if (clk->base_khz && freq > clk->base_khz)
92 					return false;
93 				fallthrough;
94 			case NVKM_CLK_BOOST_BIOS:
95 				if (clk->boost_khz && freq > clk->boost_khz)
96 					return false;
97 			}
98 		}
99 		domain++;
100 	}
101 
102 	if (!volt)
103 		return true;
104 
105 	voltage = nvkm_volt_map(volt, cstate->voltage, temp);
106 	if (voltage < 0)
107 		return false;
108 	return voltage <= min(max_volt, volt->max_uv);
109 }
110 
111 static struct nvkm_cstate *
nvkm_cstate_find_best(struct nvkm_clk * clk,struct nvkm_pstate * pstate,struct nvkm_cstate * cstate)112 nvkm_cstate_find_best(struct nvkm_clk *clk, struct nvkm_pstate *pstate,
113 		      struct nvkm_cstate *cstate)
114 {
115 	struct nvkm_device *device = clk->subdev.device;
116 	struct nvkm_volt *volt = device->volt;
117 	int max_volt;
118 
119 	if (!pstate || !cstate)
120 		return NULL;
121 
122 	if (!volt)
123 		return cstate;
124 
125 	max_volt = volt->max_uv;
126 	if (volt->max0_id != 0xff)
127 		max_volt = min(max_volt,
128 			       nvkm_volt_map(volt, volt->max0_id, clk->temp));
129 	if (volt->max1_id != 0xff)
130 		max_volt = min(max_volt,
131 			       nvkm_volt_map(volt, volt->max1_id, clk->temp));
132 	if (volt->max2_id != 0xff)
133 		max_volt = min(max_volt,
134 			       nvkm_volt_map(volt, volt->max2_id, clk->temp));
135 
136 	list_for_each_entry_from_reverse(cstate, &pstate->list, head) {
137 		if (nvkm_cstate_valid(clk, cstate, max_volt, clk->temp))
138 			return cstate;
139 	}
140 
141 	return NULL;
142 }
143 
144 static struct nvkm_cstate *
nvkm_cstate_get(struct nvkm_clk * clk,struct nvkm_pstate * pstate,int cstatei)145 nvkm_cstate_get(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
146 {
147 	struct nvkm_cstate *cstate;
148 	if (cstatei == NVKM_CLK_CSTATE_HIGHEST)
149 		return list_last_entry(&pstate->list, typeof(*cstate), head);
150 	else {
151 		list_for_each_entry(cstate, &pstate->list, head) {
152 			if (cstate->id == cstatei)
153 				return cstate;
154 		}
155 	}
156 	return NULL;
157 }
158 
159 static int
nvkm_cstate_prog(struct nvkm_clk * clk,struct nvkm_pstate * pstate,int cstatei)160 nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
161 {
162 	struct nvkm_subdev *subdev = &clk->subdev;
163 	struct nvkm_device *device = subdev->device;
164 	struct nvkm_therm *therm = device->therm;
165 	struct nvkm_volt *volt = device->volt;
166 	struct nvkm_cstate *cstate;
167 	int ret;
168 
169 	if (!list_empty(&pstate->list)) {
170 		cstate = nvkm_cstate_get(clk, pstate, cstatei);
171 		cstate = nvkm_cstate_find_best(clk, pstate, cstate);
172 		if (!cstate)
173 			return -EINVAL;
174 	} else {
175 		cstate = &pstate->base;
176 	}
177 
178 	if (therm) {
179 		ret = nvkm_therm_cstate(therm, pstate->fanspeed, +1);
180 		if (ret && ret != -ENODEV) {
181 			nvkm_error(subdev, "failed to raise fan speed: %d\n", ret);
182 			return ret;
183 		}
184 	}
185 
186 	if (volt) {
187 		ret = nvkm_volt_set_id(volt, cstate->voltage,
188 				       pstate->base.voltage, clk->temp, +1);
189 		if (ret && ret != -ENODEV) {
190 			nvkm_error(subdev, "failed to raise voltage: %d\n", ret);
191 			return ret;
192 		}
193 	}
194 
195 	ret = clk->func->calc(clk, cstate);
196 	if (ret == 0) {
197 		ret = clk->func->prog(clk);
198 		clk->func->tidy(clk);
199 	}
200 
201 	if (volt) {
202 		ret = nvkm_volt_set_id(volt, cstate->voltage,
203 				       pstate->base.voltage, clk->temp, -1);
204 		if (ret && ret != -ENODEV)
205 			nvkm_error(subdev, "failed to lower voltage: %d\n", ret);
206 	}
207 
208 	if (therm) {
209 		ret = nvkm_therm_cstate(therm, pstate->fanspeed, -1);
210 		if (ret && ret != -ENODEV)
211 			nvkm_error(subdev, "failed to lower fan speed: %d\n", ret);
212 	}
213 
214 	return ret;
215 }
216 
217 static void
nvkm_cstate_del(struct nvkm_cstate * cstate)218 nvkm_cstate_del(struct nvkm_cstate *cstate)
219 {
220 	list_del(&cstate->head);
221 	kfree(cstate);
222 }
223 
224 static int
nvkm_cstate_new(struct nvkm_clk * clk,int idx,struct nvkm_pstate * pstate)225 nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate)
226 {
227 	struct nvkm_bios *bios = clk->subdev.device->bios;
228 	struct nvkm_volt *volt = clk->subdev.device->volt;
229 	const struct nvkm_domain *domain = clk->domains;
230 	struct nvkm_cstate *cstate = NULL;
231 	struct nvbios_cstepX cstepX;
232 	u8  ver, hdr;
233 	u32 data;
234 
235 	data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX);
236 	if (!data)
237 		return -ENOENT;
238 
239 	if (volt && nvkm_volt_map_min(volt, cstepX.voltage) > volt->max_uv)
240 		return -EINVAL;
241 
242 	cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
243 	if (!cstate)
244 		return -ENOMEM;
245 
246 	*cstate = pstate->base;
247 	cstate->voltage = cstepX.voltage;
248 	cstate->id = idx;
249 
250 	while (domain && domain->name != nv_clk_src_max) {
251 		if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
252 			u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate,
253 						   domain->bios, cstepX.freq);
254 			cstate->domain[domain->name] = freq;
255 		}
256 		domain++;
257 	}
258 
259 	list_add(&cstate->head, &pstate->list);
260 	return 0;
261 }
262 
263 /******************************************************************************
264  * P-States
265  *****************************************************************************/
266 static int
nvkm_pstate_prog(struct nvkm_clk * clk,int pstatei)267 nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
268 {
269 	struct nvkm_subdev *subdev = &clk->subdev;
270 	struct nvkm_fb *fb = subdev->device->fb;
271 	struct nvkm_pci *pci = subdev->device->pci;
272 	struct nvkm_pstate *pstate;
273 	int ret, idx = 0;
274 
275 	list_for_each_entry(pstate, &clk->states, head) {
276 		if (idx++ == pstatei)
277 			break;
278 	}
279 
280 	nvkm_debug(subdev, "setting performance state %d\n", pstatei);
281 	clk->pstate = pstatei;
282 
283 	nvkm_pcie_set_link(pci, pstate->pcie_speed, pstate->pcie_width);
284 
285 	if (fb && fb->ram && fb->ram->func->calc) {
286 		struct nvkm_ram *ram = fb->ram;
287 		int khz = pstate->base.domain[nv_clk_src_mem];
288 		do {
289 			ret = ram->func->calc(ram, khz);
290 			if (ret == 0)
291 				ret = ram->func->prog(ram);
292 		} while (ret > 0);
293 		ram->func->tidy(ram);
294 	}
295 
296 	return nvkm_cstate_prog(clk, pstate, NVKM_CLK_CSTATE_HIGHEST);
297 }
298 
299 static void
nvkm_pstate_work(struct work_struct * work)300 nvkm_pstate_work(struct work_struct *work)
301 {
302 	struct nvkm_clk *clk = container_of(work, typeof(*clk), work);
303 	struct nvkm_subdev *subdev = &clk->subdev;
304 	int pstate;
305 
306 	if (!atomic_xchg(&clk->waiting, 0))
307 		return;
308 	clk->pwrsrc = power_supply_is_system_supplied();
309 
310 	nvkm_trace(subdev, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d°C D %d\n",
311 		   clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
312 		   clk->astate, clk->temp, clk->dstate);
313 
314 	pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc;
315 	if (clk->state_nr && pstate != -1) {
316 		pstate = (pstate < 0) ? clk->astate : pstate;
317 		pstate = min(pstate, clk->state_nr - 1);
318 		pstate = max(pstate, clk->dstate);
319 	} else {
320 		pstate = clk->pstate = -1;
321 	}
322 
323 	nvkm_trace(subdev, "-> %d\n", pstate);
324 	if (pstate != clk->pstate) {
325 		int ret = nvkm_pstate_prog(clk, pstate);
326 		if (ret) {
327 			nvkm_error(subdev, "error setting pstate %d: %d\n",
328 				   pstate, ret);
329 		}
330 	}
331 
332 	wake_up_all(&clk->wait);
333 	nvkm_notify_get(&clk->pwrsrc_ntfy);
334 }
335 
336 static int
nvkm_pstate_calc(struct nvkm_clk * clk,bool wait)337 nvkm_pstate_calc(struct nvkm_clk *clk, bool wait)
338 {
339 	atomic_set(&clk->waiting, 1);
340 	schedule_work(&clk->work);
341 	if (wait)
342 		wait_event(clk->wait, !atomic_read(&clk->waiting));
343 	return 0;
344 }
345 
346 static void
nvkm_pstate_info(struct nvkm_clk * clk,struct nvkm_pstate * pstate)347 nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate)
348 {
349 	const struct nvkm_domain *clock = clk->domains - 1;
350 	struct nvkm_cstate *cstate;
351 	struct nvkm_subdev *subdev = &clk->subdev;
352 	char info[3][32] = { "", "", "" };
353 	char name[4] = "--";
354 	int i = -1;
355 
356 	if (pstate->pstate != 0xff)
357 		snprintf(name, sizeof(name), "%02x", pstate->pstate);
358 
359 	while ((++clock)->name != nv_clk_src_max) {
360 		u32 lo = pstate->base.domain[clock->name];
361 		u32 hi = lo;
362 		if (hi == 0)
363 			continue;
364 
365 		nvkm_debug(subdev, "%02x: %10d KHz\n", clock->name, lo);
366 		list_for_each_entry(cstate, &pstate->list, head) {
367 			u32 freq = cstate->domain[clock->name];
368 			lo = min(lo, freq);
369 			hi = max(hi, freq);
370 			nvkm_debug(subdev, "%10d KHz\n", freq);
371 		}
372 
373 		if (clock->mname && ++i < ARRAY_SIZE(info)) {
374 			lo /= clock->mdiv;
375 			hi /= clock->mdiv;
376 			if (lo == hi) {
377 				snprintf(info[i], sizeof(info[i]), "%s %d MHz",
378 					 clock->mname, lo);
379 			} else {
380 				snprintf(info[i], sizeof(info[i]),
381 					 "%s %d-%d MHz", clock->mname, lo, hi);
382 			}
383 		}
384 	}
385 
386 	nvkm_debug(subdev, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
387 }
388 
389 static void
nvkm_pstate_del(struct nvkm_pstate * pstate)390 nvkm_pstate_del(struct nvkm_pstate *pstate)
391 {
392 	struct nvkm_cstate *cstate, *temp;
393 
394 	list_for_each_entry_safe(cstate, temp, &pstate->list, head) {
395 		nvkm_cstate_del(cstate);
396 	}
397 
398 	list_del(&pstate->head);
399 	kfree(pstate);
400 }
401 
402 static int
nvkm_pstate_new(struct nvkm_clk * clk,int idx)403 nvkm_pstate_new(struct nvkm_clk *clk, int idx)
404 {
405 	struct nvkm_bios *bios = clk->subdev.device->bios;
406 	const struct nvkm_domain *domain = clk->domains - 1;
407 	struct nvkm_pstate *pstate;
408 	struct nvkm_cstate *cstate;
409 	struct nvbios_cstepE cstepE;
410 	struct nvbios_perfE perfE;
411 	u8  ver, hdr, cnt, len;
412 	u32 data;
413 
414 	data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE);
415 	if (!data)
416 		return -EINVAL;
417 	if (perfE.pstate == 0xff)
418 		return 0;
419 
420 	pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
421 	cstate = &pstate->base;
422 	if (!pstate)
423 		return -ENOMEM;
424 
425 	INIT_LIST_HEAD(&pstate->list);
426 
427 	pstate->pstate = perfE.pstate;
428 	pstate->fanspeed = perfE.fanspeed;
429 	pstate->pcie_speed = perfE.pcie_speed;
430 	pstate->pcie_width = perfE.pcie_width;
431 	cstate->voltage = perfE.voltage;
432 	cstate->domain[nv_clk_src_core] = perfE.core;
433 	cstate->domain[nv_clk_src_shader] = perfE.shader;
434 	cstate->domain[nv_clk_src_mem] = perfE.memory;
435 	cstate->domain[nv_clk_src_vdec] = perfE.vdec;
436 	cstate->domain[nv_clk_src_dom6] = perfE.disp;
437 
438 	while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) {
439 		struct nvbios_perfS perfS;
440 		u8  sver = ver, shdr = hdr;
441 		u32 perfSe = nvbios_perfSp(bios, data, domain->bios,
442 					  &sver, &shdr, cnt, len, &perfS);
443 		if (perfSe == 0 || sver != 0x40)
444 			continue;
445 
446 		if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
447 			perfS.v40.freq = nvkm_clk_adjust(clk, false,
448 							 pstate->pstate,
449 							 domain->bios,
450 							 perfS.v40.freq);
451 		}
452 
453 		cstate->domain[domain->name] = perfS.v40.freq;
454 	}
455 
456 	data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE);
457 	if (data) {
458 		int idx = cstepE.index;
459 		do {
460 			nvkm_cstate_new(clk, idx, pstate);
461 		} while(idx--);
462 	}
463 
464 	nvkm_pstate_info(clk, pstate);
465 	list_add_tail(&pstate->head, &clk->states);
466 	clk->state_nr++;
467 	return 0;
468 }
469 
470 /******************************************************************************
471  * Adjustment triggers
472  *****************************************************************************/
473 static int
nvkm_clk_ustate_update(struct nvkm_clk * clk,int req)474 nvkm_clk_ustate_update(struct nvkm_clk *clk, int req)
475 {
476 	struct nvkm_pstate *pstate;
477 	int i = 0;
478 
479 	if (!clk->allow_reclock)
480 		return -ENOSYS;
481 
482 	if (req != -1 && req != -2) {
483 		list_for_each_entry(pstate, &clk->states, head) {
484 			if (pstate->pstate == req)
485 				break;
486 			i++;
487 		}
488 
489 		if (pstate->pstate != req)
490 			return -EINVAL;
491 		req = i;
492 	}
493 
494 	return req + 2;
495 }
496 
497 static int
nvkm_clk_nstate(struct nvkm_clk * clk,const char * mode,int arglen)498 nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen)
499 {
500 	int ret = 1;
501 
502 	if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen))
503 		return -2;
504 
505 	if (strncasecmpz(mode, "disabled", arglen)) {
506 		char save = mode[arglen];
507 		long v;
508 
509 		((char *)mode)[arglen] = '\0';
510 		if (!kstrtol(mode, 0, &v)) {
511 			ret = nvkm_clk_ustate_update(clk, v);
512 			if (ret < 0)
513 				ret = 1;
514 		}
515 		((char *)mode)[arglen] = save;
516 	}
517 
518 	return ret - 2;
519 }
520 
521 int
nvkm_clk_ustate(struct nvkm_clk * clk,int req,int pwr)522 nvkm_clk_ustate(struct nvkm_clk *clk, int req, int pwr)
523 {
524 	int ret = nvkm_clk_ustate_update(clk, req);
525 	if (ret >= 0) {
526 		if (ret -= 2, pwr) clk->ustate_ac = ret;
527 		else		   clk->ustate_dc = ret;
528 		return nvkm_pstate_calc(clk, true);
529 	}
530 	return ret;
531 }
532 
533 int
nvkm_clk_astate(struct nvkm_clk * clk,int req,int rel,bool wait)534 nvkm_clk_astate(struct nvkm_clk *clk, int req, int rel, bool wait)
535 {
536 	if (!rel) clk->astate  = req;
537 	if ( rel) clk->astate += rel;
538 	clk->astate = min(clk->astate, clk->state_nr - 1);
539 	clk->astate = max(clk->astate, 0);
540 	return nvkm_pstate_calc(clk, wait);
541 }
542 
543 int
nvkm_clk_tstate(struct nvkm_clk * clk,u8 temp)544 nvkm_clk_tstate(struct nvkm_clk *clk, u8 temp)
545 {
546 	if (clk->temp == temp)
547 		return 0;
548 	clk->temp = temp;
549 	return nvkm_pstate_calc(clk, false);
550 }
551 
552 int
nvkm_clk_dstate(struct nvkm_clk * clk,int req,int rel)553 nvkm_clk_dstate(struct nvkm_clk *clk, int req, int rel)
554 {
555 	if (!rel) clk->dstate  = req;
556 	if ( rel) clk->dstate += rel;
557 	clk->dstate = min(clk->dstate, clk->state_nr - 1);
558 	clk->dstate = max(clk->dstate, 0);
559 	return nvkm_pstate_calc(clk, true);
560 }
561 
562 static int
nvkm_clk_pwrsrc(struct nvkm_notify * notify)563 nvkm_clk_pwrsrc(struct nvkm_notify *notify)
564 {
565 	struct nvkm_clk *clk =
566 		container_of(notify, typeof(*clk), pwrsrc_ntfy);
567 	nvkm_pstate_calc(clk, false);
568 	return NVKM_NOTIFY_DROP;
569 }
570 
571 /******************************************************************************
572  * subdev base class implementation
573  *****************************************************************************/
574 
575 int
nvkm_clk_read(struct nvkm_clk * clk,enum nv_clk_src src)576 nvkm_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
577 {
578 	return clk->func->read(clk, src);
579 }
580 
581 static int
nvkm_clk_fini(struct nvkm_subdev * subdev,bool suspend)582 nvkm_clk_fini(struct nvkm_subdev *subdev, bool suspend)
583 {
584 	struct nvkm_clk *clk = nvkm_clk(subdev);
585 	nvkm_notify_put(&clk->pwrsrc_ntfy);
586 	flush_work(&clk->work);
587 	if (clk->func->fini)
588 		clk->func->fini(clk);
589 	return 0;
590 }
591 
592 static int
nvkm_clk_init(struct nvkm_subdev * subdev)593 nvkm_clk_init(struct nvkm_subdev *subdev)
594 {
595 	struct nvkm_clk *clk = nvkm_clk(subdev);
596 	const struct nvkm_domain *clock = clk->domains;
597 	int ret;
598 
599 	memset(&clk->bstate, 0x00, sizeof(clk->bstate));
600 	INIT_LIST_HEAD(&clk->bstate.list);
601 	clk->bstate.pstate = 0xff;
602 
603 	while (clock->name != nv_clk_src_max) {
604 		ret = nvkm_clk_read(clk, clock->name);
605 		if (ret < 0) {
606 			nvkm_error(subdev, "%02x freq unknown\n", clock->name);
607 			return ret;
608 		}
609 		clk->bstate.base.domain[clock->name] = ret;
610 		clock++;
611 	}
612 
613 	nvkm_pstate_info(clk, &clk->bstate);
614 
615 	if (clk->func->init)
616 		return clk->func->init(clk);
617 
618 	clk->astate = clk->state_nr - 1;
619 	clk->dstate = 0;
620 	clk->pstate = -1;
621 	clk->temp = 90; /* reasonable default value */
622 	nvkm_pstate_calc(clk, true);
623 	return 0;
624 }
625 
626 static void *
nvkm_clk_dtor(struct nvkm_subdev * subdev)627 nvkm_clk_dtor(struct nvkm_subdev *subdev)
628 {
629 	struct nvkm_clk *clk = nvkm_clk(subdev);
630 	struct nvkm_pstate *pstate, *temp;
631 
632 	nvkm_notify_fini(&clk->pwrsrc_ntfy);
633 
634 	/* Early return if the pstates have been provided statically */
635 	if (clk->func->pstates)
636 		return clk;
637 
638 	list_for_each_entry_safe(pstate, temp, &clk->states, head) {
639 		nvkm_pstate_del(pstate);
640 	}
641 
642 	return clk;
643 }
644 
645 static const struct nvkm_subdev_func
646 nvkm_clk = {
647 	.dtor = nvkm_clk_dtor,
648 	.init = nvkm_clk_init,
649 	.fini = nvkm_clk_fini,
650 };
651 
652 int
nvkm_clk_ctor(const struct nvkm_clk_func * func,struct nvkm_device * device,enum nvkm_subdev_type type,int inst,bool allow_reclock,struct nvkm_clk * clk)653 nvkm_clk_ctor(const struct nvkm_clk_func *func, struct nvkm_device *device,
654 	      enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk *clk)
655 {
656 	struct nvkm_subdev *subdev = &clk->subdev;
657 	struct nvkm_bios *bios = device->bios;
658 	int ret, idx, arglen;
659 	const char *mode;
660 	struct nvbios_vpstate_header h;
661 
662 	nvkm_subdev_ctor(&nvkm_clk, device, type, inst, subdev);
663 
664 	if (bios && !nvbios_vpstate_parse(bios, &h)) {
665 		struct nvbios_vpstate_entry base, boost;
666 		if (!nvbios_vpstate_entry(bios, &h, h.boost_id, &boost))
667 			clk->boost_khz = boost.clock_mhz * 1000;
668 		if (!nvbios_vpstate_entry(bios, &h, h.base_id, &base))
669 			clk->base_khz = base.clock_mhz * 1000;
670 	}
671 
672 	clk->func = func;
673 	INIT_LIST_HEAD(&clk->states);
674 	clk->domains = func->domains;
675 	clk->ustate_ac = -1;
676 	clk->ustate_dc = -1;
677 	clk->allow_reclock = allow_reclock;
678 
679 	INIT_WORK(&clk->work, nvkm_pstate_work);
680 	init_waitqueue_head(&clk->wait);
681 	atomic_set(&clk->waiting, 0);
682 
683 	/* If no pstates are provided, try and fetch them from the BIOS */
684 	if (!func->pstates) {
685 		idx = 0;
686 		do {
687 			ret = nvkm_pstate_new(clk, idx++);
688 		} while (ret == 0);
689 	} else {
690 		for (idx = 0; idx < func->nr_pstates; idx++)
691 			list_add_tail(&func->pstates[idx].head, &clk->states);
692 		clk->state_nr = func->nr_pstates;
693 	}
694 
695 	ret = nvkm_notify_init(NULL, &device->event, nvkm_clk_pwrsrc, true,
696 			       NULL, 0, 0, &clk->pwrsrc_ntfy);
697 	if (ret)
698 		return ret;
699 
700 	mode = nvkm_stropt(device->cfgopt, "NvClkMode", &arglen);
701 	if (mode) {
702 		clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen);
703 		clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen);
704 	}
705 
706 	mode = nvkm_stropt(device->cfgopt, "NvClkModeAC", &arglen);
707 	if (mode)
708 		clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen);
709 
710 	mode = nvkm_stropt(device->cfgopt, "NvClkModeDC", &arglen);
711 	if (mode)
712 		clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen);
713 
714 	clk->boost_mode = nvkm_longopt(device->cfgopt, "NvBoost",
715 				       NVKM_CLK_BOOST_NONE);
716 	return 0;
717 }
718 
719 int
nvkm_clk_new_(const struct nvkm_clk_func * func,struct nvkm_device * device,enum nvkm_subdev_type type,int inst,bool allow_reclock,struct nvkm_clk ** pclk)720 nvkm_clk_new_(const struct nvkm_clk_func *func, struct nvkm_device *device,
721 	      enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk **pclk)
722 {
723 	if (!(*pclk = kzalloc(sizeof(**pclk), GFP_KERNEL)))
724 		return -ENOMEM;
725 	return nvkm_clk_ctor(func, device, type, inst, allow_reclock, *pclk);
726 }
727