1 /*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include "drmP.h"
26 #include "nouveau_drv.h"
27 #include "nouveau_mm.h"
28
29 static int types[0x80] = {
30 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
31 1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0,
32 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0,
33 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
34 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0,
35 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
36 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2,
37 1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0
38 };
39
40 bool
nv50_vram_flags_valid(struct drm_device * dev,u32 tile_flags)41 nv50_vram_flags_valid(struct drm_device *dev, u32 tile_flags)
42 {
43 int type = (tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) >> 8;
44
45 if (likely(type < ARRAY_SIZE(types) && types[type]))
46 return true;
47 return false;
48 }
49
50 void
nv50_vram_del(struct drm_device * dev,struct nouveau_mem ** pmem)51 nv50_vram_del(struct drm_device *dev, struct nouveau_mem **pmem)
52 {
53 struct drm_nouveau_private *dev_priv = dev->dev_private;
54 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
55 struct ttm_mem_type_manager *man = &bdev->man[TTM_PL_VRAM];
56 struct nouveau_mm *mm = man->priv;
57 struct nouveau_mm_node *this;
58 struct nouveau_mem *mem;
59
60 mem = *pmem;
61 *pmem = NULL;
62 if (unlikely(mem == NULL))
63 return;
64
65 mutex_lock(&mm->mutex);
66 while (!list_empty(&mem->regions)) {
67 this = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
68
69 list_del(&this->rl_entry);
70 nouveau_mm_put(mm, this);
71 }
72
73 if (mem->tag) {
74 drm_mm_put_block(mem->tag);
75 mem->tag = NULL;
76 }
77 mutex_unlock(&mm->mutex);
78
79 kfree(mem);
80 }
81
82 int
nv50_vram_new(struct drm_device * dev,u64 size,u32 align,u32 size_nc,u32 memtype,struct nouveau_mem ** pmem)83 nv50_vram_new(struct drm_device *dev, u64 size, u32 align, u32 size_nc,
84 u32 memtype, struct nouveau_mem **pmem)
85 {
86 struct drm_nouveau_private *dev_priv = dev->dev_private;
87 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
88 struct ttm_mem_type_manager *man = &bdev->man[TTM_PL_VRAM];
89 struct nouveau_mm *mm = man->priv;
90 struct nouveau_mm_node *r;
91 struct nouveau_mem *mem;
92 int comp = (memtype & 0x300) >> 8;
93 int type = (memtype & 0x07f);
94 int ret;
95
96 if (!types[type])
97 return -EINVAL;
98 size >>= 12;
99 align >>= 12;
100 size_nc >>= 12;
101
102 mem = kzalloc(sizeof(*mem), GFP_KERNEL);
103 if (!mem)
104 return -ENOMEM;
105
106 mutex_lock(&mm->mutex);
107 if (comp) {
108 if (align == 16) {
109 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
110 int n = (size >> 4) * comp;
111
112 mem->tag = drm_mm_search_free(&pfb->tag_heap, n, 0, 0);
113 if (mem->tag)
114 mem->tag = drm_mm_get_block(mem->tag, n, 0);
115 }
116
117 if (unlikely(!mem->tag))
118 comp = 0;
119 }
120
121 INIT_LIST_HEAD(&mem->regions);
122 mem->dev = dev_priv->dev;
123 mem->memtype = (comp << 7) | type;
124 mem->size = size;
125
126 do {
127 ret = nouveau_mm_get(mm, types[type], size, size_nc, align, &r);
128 if (ret) {
129 mutex_unlock(&mm->mutex);
130 nv50_vram_del(dev, &mem);
131 return ret;
132 }
133
134 list_add_tail(&r->rl_entry, &mem->regions);
135 size -= r->length;
136 } while (size);
137 mutex_unlock(&mm->mutex);
138
139 r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
140 mem->offset = (u64)r->offset << 12;
141 *pmem = mem;
142 return 0;
143 }
144
145 static u32
nv50_vram_rblock(struct drm_device * dev)146 nv50_vram_rblock(struct drm_device *dev)
147 {
148 struct drm_nouveau_private *dev_priv = dev->dev_private;
149 int i, parts, colbits, rowbitsa, rowbitsb, banks;
150 u64 rowsize, predicted;
151 u32 r0, r4, rt, ru, rblock_size;
152
153 r0 = nv_rd32(dev, 0x100200);
154 r4 = nv_rd32(dev, 0x100204);
155 rt = nv_rd32(dev, 0x100250);
156 ru = nv_rd32(dev, 0x001540);
157 NV_DEBUG(dev, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);
158
159 for (i = 0, parts = 0; i < 8; i++) {
160 if (ru & (0x00010000 << i))
161 parts++;
162 }
163
164 colbits = (r4 & 0x0000f000) >> 12;
165 rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
166 rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
167 banks = ((r4 & 0x01000000) ? 8 : 4);
168
169 rowsize = parts * banks * (1 << colbits) * 8;
170 predicted = rowsize << rowbitsa;
171 if (r0 & 0x00000004)
172 predicted += rowsize << rowbitsb;
173
174 if (predicted != dev_priv->vram_size) {
175 NV_WARN(dev, "memory controller reports %dMiB VRAM\n",
176 (u32)(dev_priv->vram_size >> 20));
177 NV_WARN(dev, "we calculated %dMiB VRAM\n",
178 (u32)(predicted >> 20));
179 }
180
181 rblock_size = rowsize;
182 if (rt & 1)
183 rblock_size *= 3;
184
185 NV_DEBUG(dev, "rblock %d bytes\n", rblock_size);
186 return rblock_size;
187 }
188
189 int
nv50_vram_init(struct drm_device * dev)190 nv50_vram_init(struct drm_device *dev)
191 {
192 struct drm_nouveau_private *dev_priv = dev->dev_private;
193
194 dev_priv->vram_size = nv_rd32(dev, 0x10020c);
195 dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
196 dev_priv->vram_size &= 0xffffffff00ULL;
197
198 switch (dev_priv->chipset) {
199 case 0xaa:
200 case 0xac:
201 case 0xaf:
202 dev_priv->vram_sys_base = (u64)nv_rd32(dev, 0x100e10) << 12;
203 dev_priv->vram_rblock_size = 4096;
204 break;
205 default:
206 dev_priv->vram_rblock_size = nv50_vram_rblock(dev);
207 break;
208 }
209
210 return 0;
211 }
212