1 /*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
28 #include "nv50_display.h"
29 #include "nouveau_crtc.h"
30 #include "nouveau_encoder.h"
31 #include "nouveau_connector.h"
32 #include "nouveau_fb.h"
33 #include "nouveau_fbcon.h"
34 #include "nouveau_ramht.h"
35 #include "drm_crtc_helper.h"
36
37 static void nv50_display_isr(struct drm_device *);
38 static void nv50_display_bh(unsigned long);
39
40 static inline int
nv50_sor_nr(struct drm_device * dev)41 nv50_sor_nr(struct drm_device *dev)
42 {
43 struct drm_nouveau_private *dev_priv = dev->dev_private;
44
45 if (dev_priv->chipset < 0x90 ||
46 dev_priv->chipset == 0x92 ||
47 dev_priv->chipset == 0xa0)
48 return 2;
49
50 return 4;
51 }
52
53 u32
nv50_display_active_crtcs(struct drm_device * dev)54 nv50_display_active_crtcs(struct drm_device *dev)
55 {
56 struct drm_nouveau_private *dev_priv = dev->dev_private;
57 u32 mask = 0;
58 int i;
59
60 if (dev_priv->chipset < 0x90 ||
61 dev_priv->chipset == 0x92 ||
62 dev_priv->chipset == 0xa0) {
63 for (i = 0; i < 2; i++)
64 mask |= nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
65 } else {
66 for (i = 0; i < 4; i++)
67 mask |= nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
68 }
69
70 for (i = 0; i < 3; i++)
71 mask |= nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
72
73 return mask & 3;
74 }
75
76 static int
evo_icmd(struct drm_device * dev,int ch,u32 mthd,u32 data)77 evo_icmd(struct drm_device *dev, int ch, u32 mthd, u32 data)
78 {
79 int ret = 0;
80 nv_mask(dev, 0x610300 + (ch * 0x08), 0x00000001, 0x00000001);
81 nv_wr32(dev, 0x610304 + (ch * 0x08), data);
82 nv_wr32(dev, 0x610300 + (ch * 0x08), 0x80000001 | mthd);
83 if (!nv_wait(dev, 0x610300 + (ch * 0x08), 0x80000000, 0x00000000))
84 ret = -EBUSY;
85 if (ret || (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO))
86 NV_INFO(dev, "EvoPIO: %d 0x%04x 0x%08x\n", ch, mthd, data);
87 nv_mask(dev, 0x610300 + (ch * 0x08), 0x00000001, 0x00000000);
88 return ret;
89 }
90
91 int
nv50_display_early_init(struct drm_device * dev)92 nv50_display_early_init(struct drm_device *dev)
93 {
94 u32 ctrl = nv_rd32(dev, 0x610200);
95 int i;
96
97 /* check if master evo channel is already active, a good a sign as any
98 * that the display engine is in a weird state (hibernate/kexec), if
99 * it is, do our best to reset the display engine...
100 */
101 if ((ctrl & 0x00000003) == 0x00000003) {
102 NV_INFO(dev, "PDISP: EVO(0) 0x%08x, resetting...\n", ctrl);
103
104 /* deactivate both heads first, PDISP will disappear forever
105 * (well, until you power cycle) on some boards as soon as
106 * PMC_ENABLE is hit unless they are..
107 */
108 for (i = 0; i < 2; i++) {
109 evo_icmd(dev, 0, 0x0880 + (i * 0x400), 0x05000000);
110 evo_icmd(dev, 0, 0x089c + (i * 0x400), 0);
111 evo_icmd(dev, 0, 0x0840 + (i * 0x400), 0);
112 evo_icmd(dev, 0, 0x0844 + (i * 0x400), 0);
113 evo_icmd(dev, 0, 0x085c + (i * 0x400), 0);
114 evo_icmd(dev, 0, 0x0874 + (i * 0x400), 0);
115 }
116 evo_icmd(dev, 0, 0x0080, 0);
117
118 /* reset PDISP */
119 nv_mask(dev, 0x000200, 0x40000000, 0x00000000);
120 nv_mask(dev, 0x000200, 0x40000000, 0x40000000);
121 }
122
123 return 0;
124 }
125
126 void
nv50_display_late_takedown(struct drm_device * dev)127 nv50_display_late_takedown(struct drm_device *dev)
128 {
129 }
130
131 int
nv50_display_sync(struct drm_device * dev)132 nv50_display_sync(struct drm_device *dev)
133 {
134 struct drm_nouveau_private *dev_priv = dev->dev_private;
135 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
136 struct nv50_display *disp = nv50_display(dev);
137 struct nouveau_channel *evo = disp->master;
138 u64 start;
139 int ret;
140
141 ret = RING_SPACE(evo, 6);
142 if (ret == 0) {
143 BEGIN_RING(evo, 0, 0x0084, 1);
144 OUT_RING (evo, 0x80000000);
145 BEGIN_RING(evo, 0, 0x0080, 1);
146 OUT_RING (evo, 0);
147 BEGIN_RING(evo, 0, 0x0084, 1);
148 OUT_RING (evo, 0x00000000);
149
150 nv_wo32(disp->ntfy, 0x000, 0x00000000);
151 FIRE_RING (evo);
152
153 start = ptimer->read(dev);
154 do {
155 if (nv_ro32(disp->ntfy, 0x000))
156 return 0;
157 } while (ptimer->read(dev) - start < 2000000000ULL);
158 }
159
160 return -EBUSY;
161 }
162
163 int
nv50_display_init(struct drm_device * dev)164 nv50_display_init(struct drm_device *dev)
165 {
166 struct nouveau_channel *evo;
167 int ret, i;
168 u32 val;
169
170 NV_DEBUG_KMS(dev, "\n");
171
172 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
173
174 /*
175 * I think the 0x006101XX range is some kind of main control area
176 * that enables things.
177 */
178 /* CRTC? */
179 for (i = 0; i < 2; i++) {
180 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
181 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
182 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
183 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
184 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
185 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
186 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
187 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
188 }
189
190 /* DAC */
191 for (i = 0; i < 3; i++) {
192 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
193 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
194 }
195
196 /* SOR */
197 for (i = 0; i < nv50_sor_nr(dev); i++) {
198 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
199 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
200 }
201
202 /* EXT */
203 for (i = 0; i < 3; i++) {
204 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
205 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
206 }
207
208 for (i = 0; i < 3; i++) {
209 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
210 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
211 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
212 }
213
214 /* The precise purpose is unknown, i suspect it has something to do
215 * with text mode.
216 */
217 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
218 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
219 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
220 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
221 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
222 NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
223 nv_rd32(dev, 0x6194e8));
224 return -EBUSY;
225 }
226 }
227
228 for (i = 0; i < 2; i++) {
229 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
230 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
231 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
232 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
233 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
234 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
235 return -EBUSY;
236 }
237
238 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
239 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
240 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
241 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
242 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
243 NV_ERROR(dev, "timeout: "
244 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
245 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
246 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
247 return -EBUSY;
248 }
249 }
250
251 nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
252 nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
253 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
254 nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
255 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1,
256 NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
257 NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
258 NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
259
260 ret = nv50_evo_init(dev);
261 if (ret)
262 return ret;
263 evo = nv50_display(dev)->master;
264
265 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
266
267 ret = RING_SPACE(evo, 3);
268 if (ret)
269 return ret;
270 BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
271 OUT_RING (evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
272 OUT_RING (evo, NvEvoSync);
273
274 return nv50_display_sync(dev);
275 }
276
277 void
nv50_display_fini(struct drm_device * dev)278 nv50_display_fini(struct drm_device *dev)
279 {
280 struct nv50_display *disp = nv50_display(dev);
281 struct nouveau_channel *evo = disp->master;
282 struct drm_crtc *drm_crtc;
283 int ret, i;
284
285 NV_DEBUG_KMS(dev, "\n");
286
287 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
288 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
289
290 nv50_crtc_blank(crtc, true);
291 }
292
293 ret = RING_SPACE(evo, 2);
294 if (ret == 0) {
295 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
296 OUT_RING(evo, 0);
297 }
298 FIRE_RING(evo);
299
300 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
301 * cleaning up?
302 */
303 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
304 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
305 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
306
307 if (!crtc->base.enabled)
308 continue;
309
310 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
311 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
312 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
313 "0x%08x\n", mask, mask);
314 NV_ERROR(dev, "0x610024 = 0x%08x\n",
315 nv_rd32(dev, NV50_PDISPLAY_INTR_1));
316 }
317 }
318
319 for (i = 0; i < 2; i++) {
320 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0);
321 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
322 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
323 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
324 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
325 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
326 }
327 }
328
329 nv50_evo_fini(dev);
330
331 for (i = 0; i < 3; i++) {
332 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
333 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
334 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
335 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
336 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
337 }
338 }
339
340 /* disable interrupts. */
341 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
342 }
343
344 int
nv50_display_create(struct drm_device * dev)345 nv50_display_create(struct drm_device *dev)
346 {
347 struct drm_nouveau_private *dev_priv = dev->dev_private;
348 struct dcb_table *dcb = &dev_priv->vbios.dcb;
349 struct drm_connector *connector, *ct;
350 struct nv50_display *priv;
351 int ret, i;
352
353 NV_DEBUG_KMS(dev, "\n");
354
355 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
356 if (!priv)
357 return -ENOMEM;
358 dev_priv->engine.display.priv = priv;
359
360 /* Create CRTC objects */
361 for (i = 0; i < 2; i++)
362 nv50_crtc_create(dev, i);
363
364 /* We setup the encoders from the BIOS table */
365 for (i = 0 ; i < dcb->entries; i++) {
366 struct dcb_entry *entry = &dcb->entry[i];
367
368 if (entry->location != DCB_LOC_ON_CHIP) {
369 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
370 entry->type, ffs(entry->or) - 1);
371 continue;
372 }
373
374 connector = nouveau_connector_create(dev, entry->connector);
375 if (IS_ERR(connector))
376 continue;
377
378 switch (entry->type) {
379 case OUTPUT_TMDS:
380 case OUTPUT_LVDS:
381 case OUTPUT_DP:
382 nv50_sor_create(connector, entry);
383 break;
384 case OUTPUT_ANALOG:
385 nv50_dac_create(connector, entry);
386 break;
387 default:
388 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
389 continue;
390 }
391 }
392
393 list_for_each_entry_safe(connector, ct,
394 &dev->mode_config.connector_list, head) {
395 if (!connector->encoder_ids[0]) {
396 NV_WARN(dev, "%s has no encoders, removing\n",
397 drm_get_connector_name(connector));
398 connector->funcs->destroy(connector);
399 }
400 }
401
402 tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev);
403 nouveau_irq_register(dev, 26, nv50_display_isr);
404
405 ret = nv50_evo_create(dev);
406 if (ret) {
407 nv50_display_destroy(dev);
408 return ret;
409 }
410
411 return 0;
412 }
413
414 void
nv50_display_destroy(struct drm_device * dev)415 nv50_display_destroy(struct drm_device *dev)
416 {
417 struct nv50_display *disp = nv50_display(dev);
418
419 NV_DEBUG_KMS(dev, "\n");
420
421 nv50_evo_destroy(dev);
422 nouveau_irq_unregister(dev, 26);
423 kfree(disp);
424 }
425
426 void
nv50_display_flip_stop(struct drm_crtc * crtc)427 nv50_display_flip_stop(struct drm_crtc *crtc)
428 {
429 struct nv50_display *disp = nv50_display(crtc->dev);
430 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
431 struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
432 struct nouveau_channel *evo = dispc->sync;
433 int ret;
434
435 ret = RING_SPACE(evo, 8);
436 if (ret) {
437 WARN_ON(1);
438 return;
439 }
440
441 BEGIN_RING(evo, 0, 0x0084, 1);
442 OUT_RING (evo, 0x00000000);
443 BEGIN_RING(evo, 0, 0x0094, 1);
444 OUT_RING (evo, 0x00000000);
445 BEGIN_RING(evo, 0, 0x00c0, 1);
446 OUT_RING (evo, 0x00000000);
447 BEGIN_RING(evo, 0, 0x0080, 1);
448 OUT_RING (evo, 0x00000000);
449 FIRE_RING (evo);
450 }
451
452 int
nv50_display_flip_next(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct nouveau_channel * chan)453 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
454 struct nouveau_channel *chan)
455 {
456 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
457 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
458 struct nv50_display *disp = nv50_display(crtc->dev);
459 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
460 struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
461 struct nouveau_channel *evo = dispc->sync;
462 int ret;
463
464 ret = RING_SPACE(evo, chan ? 25 : 27);
465 if (unlikely(ret))
466 return ret;
467
468 /* synchronise with the rendering channel, if necessary */
469 if (likely(chan)) {
470 ret = RING_SPACE(chan, 10);
471 if (ret) {
472 WIND_RING(evo);
473 return ret;
474 }
475
476 if (dev_priv->chipset < 0xc0) {
477 BEGIN_RING(chan, 0, 0x0060, 2);
478 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
479 OUT_RING (chan, dispc->sem.offset);
480 BEGIN_RING(chan, 0, 0x006c, 1);
481 OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
482 BEGIN_RING(chan, 0, 0x0064, 2);
483 OUT_RING (chan, dispc->sem.offset ^ 0x10);
484 OUT_RING (chan, 0x74b1e000);
485 BEGIN_RING(chan, 0, 0x0060, 1);
486 if (dev_priv->chipset < 0x84)
487 OUT_RING (chan, NvSema);
488 else
489 OUT_RING (chan, chan->vram_handle);
490 } else {
491 u64 offset = chan->dispc_vma[nv_crtc->index].offset;
492 offset += dispc->sem.offset;
493 BEGIN_NVC0(chan, 2, 0, 0x0010, 4);
494 OUT_RING (chan, upper_32_bits(offset));
495 OUT_RING (chan, lower_32_bits(offset));
496 OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
497 OUT_RING (chan, 0x1002);
498 BEGIN_NVC0(chan, 2, 0, 0x0010, 4);
499 OUT_RING (chan, upper_32_bits(offset));
500 OUT_RING (chan, lower_32_bits(offset ^ 0x10));
501 OUT_RING (chan, 0x74b1e000);
502 OUT_RING (chan, 0x1001);
503 }
504 FIRE_RING (chan);
505 } else {
506 nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4,
507 0xf00d0000 | dispc->sem.value);
508 }
509
510 /* queue the flip on the crtc's "display sync" channel */
511 BEGIN_RING(evo, 0, 0x0100, 1);
512 OUT_RING (evo, 0xfffe0000);
513 if (chan) {
514 BEGIN_RING(evo, 0, 0x0084, 1);
515 OUT_RING (evo, 0x00000100);
516 } else {
517 BEGIN_RING(evo, 0, 0x0084, 1);
518 OUT_RING (evo, 0x00000010);
519 /* allows gamma somehow, PDISP will bitch at you if
520 * you don't wait for vblank before changing this..
521 */
522 BEGIN_RING(evo, 0, 0x00e0, 1);
523 OUT_RING (evo, 0x40000000);
524 }
525 BEGIN_RING(evo, 0, 0x0088, 4);
526 OUT_RING (evo, dispc->sem.offset);
527 OUT_RING (evo, 0xf00d0000 | dispc->sem.value);
528 OUT_RING (evo, 0x74b1e000);
529 OUT_RING (evo, NvEvoSync);
530 BEGIN_RING(evo, 0, 0x00a0, 2);
531 OUT_RING (evo, 0x00000000);
532 OUT_RING (evo, 0x00000000);
533 BEGIN_RING(evo, 0, 0x00c0, 1);
534 OUT_RING (evo, nv_fb->r_dma);
535 BEGIN_RING(evo, 0, 0x0110, 2);
536 OUT_RING (evo, 0x00000000);
537 OUT_RING (evo, 0x00000000);
538 BEGIN_RING(evo, 0, 0x0800, 5);
539 OUT_RING (evo, nv_fb->nvbo->bo.offset >> 8);
540 OUT_RING (evo, 0);
541 OUT_RING (evo, (fb->height << 16) | fb->width);
542 OUT_RING (evo, nv_fb->r_pitch);
543 OUT_RING (evo, nv_fb->r_format);
544 BEGIN_RING(evo, 0, 0x0080, 1);
545 OUT_RING (evo, 0x00000000);
546 FIRE_RING (evo);
547
548 dispc->sem.offset ^= 0x10;
549 dispc->sem.value++;
550 return 0;
551 }
552
553 static u16
nv50_display_script_select(struct drm_device * dev,struct dcb_entry * dcb,u32 mc,int pxclk)554 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
555 u32 mc, int pxclk)
556 {
557 struct drm_nouveau_private *dev_priv = dev->dev_private;
558 struct nouveau_connector *nv_connector = NULL;
559 struct drm_encoder *encoder;
560 struct nvbios *bios = &dev_priv->vbios;
561 u32 script = 0, or;
562
563 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
564 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
565
566 if (nv_encoder->dcb != dcb)
567 continue;
568
569 nv_connector = nouveau_encoder_connector_get(nv_encoder);
570 break;
571 }
572
573 or = ffs(dcb->or) - 1;
574 switch (dcb->type) {
575 case OUTPUT_LVDS:
576 script = (mc >> 8) & 0xf;
577 if (bios->fp_no_ddc) {
578 if (bios->fp.dual_link)
579 script |= 0x0100;
580 if (bios->fp.if_is_24bit)
581 script |= 0x0200;
582 } else {
583 /* determine number of lvds links */
584 if (nv_connector && nv_connector->edid &&
585 nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
586 /* http://www.spwg.org */
587 if (((u8 *)nv_connector->edid)[121] == 2)
588 script |= 0x0100;
589 } else
590 if (pxclk >= bios->fp.duallink_transition_clk) {
591 script |= 0x0100;
592 }
593
594 /* determine panel depth */
595 if (script & 0x0100) {
596 if (bios->fp.strapless_is_24bit & 2)
597 script |= 0x0200;
598 } else {
599 if (bios->fp.strapless_is_24bit & 1)
600 script |= 0x0200;
601 }
602
603 if (nv_connector && nv_connector->edid &&
604 (nv_connector->edid->revision >= 4) &&
605 (nv_connector->edid->input & 0x70) >= 0x20)
606 script |= 0x0200;
607 }
608
609 if (nouveau_uscript_lvds >= 0) {
610 NV_INFO(dev, "override script 0x%04x with 0x%04x "
611 "for output LVDS-%d\n", script,
612 nouveau_uscript_lvds, or);
613 script = nouveau_uscript_lvds;
614 }
615 break;
616 case OUTPUT_TMDS:
617 script = (mc >> 8) & 0xf;
618 if (pxclk >= 165000)
619 script |= 0x0100;
620
621 if (nouveau_uscript_tmds >= 0) {
622 NV_INFO(dev, "override script 0x%04x with 0x%04x "
623 "for output TMDS-%d\n", script,
624 nouveau_uscript_tmds, or);
625 script = nouveau_uscript_tmds;
626 }
627 break;
628 case OUTPUT_DP:
629 script = (mc >> 8) & 0xf;
630 break;
631 case OUTPUT_ANALOG:
632 script = 0xff;
633 break;
634 default:
635 NV_ERROR(dev, "modeset on unsupported output type!\n");
636 break;
637 }
638
639 return script;
640 }
641
642 static void
nv50_display_vblank_crtc_handler(struct drm_device * dev,int crtc)643 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
644 {
645 struct drm_nouveau_private *dev_priv = dev->dev_private;
646 struct nouveau_channel *chan, *tmp;
647
648 list_for_each_entry_safe(chan, tmp, &dev_priv->vbl_waiting,
649 nvsw.vbl_wait) {
650 if (chan->nvsw.vblsem_head != crtc)
651 continue;
652
653 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
654 chan->nvsw.vblsem_rval);
655 list_del(&chan->nvsw.vbl_wait);
656 drm_vblank_put(dev, crtc);
657 }
658
659 drm_handle_vblank(dev, crtc);
660 }
661
662 static void
nv50_display_vblank_handler(struct drm_device * dev,uint32_t intr)663 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
664 {
665 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
666 nv50_display_vblank_crtc_handler(dev, 0);
667
668 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
669 nv50_display_vblank_crtc_handler(dev, 1);
670
671 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_VBLANK_CRTC);
672 }
673
674 static void
nv50_display_unk10_handler(struct drm_device * dev)675 nv50_display_unk10_handler(struct drm_device *dev)
676 {
677 struct drm_nouveau_private *dev_priv = dev->dev_private;
678 struct nv50_display *disp = nv50_display(dev);
679 u32 unk30 = nv_rd32(dev, 0x610030), mc;
680 int i, crtc, or = 0, type = OUTPUT_ANY;
681
682 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
683 disp->irq.dcb = NULL;
684
685 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
686
687 /* Determine which CRTC we're dealing with, only 1 ever will be
688 * signalled at the same time with the current nouveau code.
689 */
690 crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
691 if (crtc < 0)
692 goto ack;
693
694 /* Nothing needs to be done for the encoder */
695 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
696 if (crtc < 0)
697 goto ack;
698
699 /* Find which encoder was connected to the CRTC */
700 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
701 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
702 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
703 if (!(mc & (1 << crtc)))
704 continue;
705
706 switch ((mc & 0x00000f00) >> 8) {
707 case 0: type = OUTPUT_ANALOG; break;
708 case 1: type = OUTPUT_TV; break;
709 default:
710 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
711 goto ack;
712 }
713
714 or = i;
715 }
716
717 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
718 if (dev_priv->chipset < 0x90 ||
719 dev_priv->chipset == 0x92 ||
720 dev_priv->chipset == 0xa0)
721 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
722 else
723 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
724
725 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
726 if (!(mc & (1 << crtc)))
727 continue;
728
729 switch ((mc & 0x00000f00) >> 8) {
730 case 0: type = OUTPUT_LVDS; break;
731 case 1: type = OUTPUT_TMDS; break;
732 case 2: type = OUTPUT_TMDS; break;
733 case 5: type = OUTPUT_TMDS; break;
734 case 8: type = OUTPUT_DP; break;
735 case 9: type = OUTPUT_DP; break;
736 default:
737 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
738 goto ack;
739 }
740
741 or = i;
742 }
743
744 /* There was no encoder to disable */
745 if (type == OUTPUT_ANY)
746 goto ack;
747
748 /* Disable the encoder */
749 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
750 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
751
752 if (dcb->type == type && (dcb->or & (1 << or))) {
753 nouveau_bios_run_display_table(dev, 0, -1, dcb, -1);
754 disp->irq.dcb = dcb;
755 goto ack;
756 }
757 }
758
759 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
760 ack:
761 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
762 nv_wr32(dev, 0x610030, 0x80000000);
763 }
764
765 static void
nv50_display_unk20_handler(struct drm_device * dev)766 nv50_display_unk20_handler(struct drm_device *dev)
767 {
768 struct drm_nouveau_private *dev_priv = dev->dev_private;
769 struct nv50_display *disp = nv50_display(dev);
770 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0;
771 struct dcb_entry *dcb;
772 int i, crtc, or = 0, type = OUTPUT_ANY;
773
774 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
775 dcb = disp->irq.dcb;
776 if (dcb) {
777 nouveau_bios_run_display_table(dev, 0, -2, dcb, -1);
778 disp->irq.dcb = NULL;
779 }
780
781 /* CRTC clock change requested? */
782 crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
783 if (crtc >= 0) {
784 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
785 pclk &= 0x003fffff;
786 if (pclk)
787 nv50_crtc_set_clock(dev, crtc, pclk);
788
789 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
790 tmp &= ~0x000000f;
791 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
792 }
793
794 /* Nothing needs to be done for the encoder */
795 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
796 if (crtc < 0)
797 goto ack;
798 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
799
800 /* Find which encoder is connected to the CRTC */
801 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
802 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
803 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
804 if (!(mc & (1 << crtc)))
805 continue;
806
807 switch ((mc & 0x00000f00) >> 8) {
808 case 0: type = OUTPUT_ANALOG; break;
809 case 1: type = OUTPUT_TV; break;
810 default:
811 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
812 goto ack;
813 }
814
815 or = i;
816 }
817
818 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
819 if (dev_priv->chipset < 0x90 ||
820 dev_priv->chipset == 0x92 ||
821 dev_priv->chipset == 0xa0)
822 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
823 else
824 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
825
826 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
827 if (!(mc & (1 << crtc)))
828 continue;
829
830 switch ((mc & 0x00000f00) >> 8) {
831 case 0: type = OUTPUT_LVDS; break;
832 case 1: type = OUTPUT_TMDS; break;
833 case 2: type = OUTPUT_TMDS; break;
834 case 5: type = OUTPUT_TMDS; break;
835 case 8: type = OUTPUT_DP; break;
836 case 9: type = OUTPUT_DP; break;
837 default:
838 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
839 goto ack;
840 }
841
842 or = i;
843 }
844
845 if (type == OUTPUT_ANY)
846 goto ack;
847
848 /* Enable the encoder */
849 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
850 dcb = &dev_priv->vbios.dcb.entry[i];
851 if (dcb->type == type && (dcb->or & (1 << or)))
852 break;
853 }
854
855 if (i == dev_priv->vbios.dcb.entries) {
856 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
857 goto ack;
858 }
859
860 script = nv50_display_script_select(dev, dcb, mc, pclk);
861 nouveau_bios_run_display_table(dev, script, pclk, dcb, -1);
862
863 if (type == OUTPUT_DP) {
864 int link = !(dcb->dpconf.sor.link & 1);
865 if ((mc & 0x000f0000) == 0x00020000)
866 nv50_sor_dp_calc_tu(dev, or, link, pclk, 18);
867 else
868 nv50_sor_dp_calc_tu(dev, or, link, pclk, 24);
869 }
870
871 if (dcb->type != OUTPUT_ANALOG) {
872 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
873 tmp &= ~0x00000f0f;
874 if (script & 0x0100)
875 tmp |= 0x00000101;
876 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
877 } else {
878 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
879 }
880
881 disp->irq.dcb = dcb;
882 disp->irq.pclk = pclk;
883 disp->irq.script = script;
884
885 ack:
886 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
887 nv_wr32(dev, 0x610030, 0x80000000);
888 }
889
890 /* If programming a TMDS output on a SOR that can also be configured for
891 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
892 *
893 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
894 * the VBIOS scripts on at least one board I have only switch it off on
895 * link 0, causing a blank display if the output has previously been
896 * programmed for DisplayPort.
897 */
898 static void
nv50_display_unk40_dp_set_tmds(struct drm_device * dev,struct dcb_entry * dcb)899 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
900 {
901 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
902 struct drm_encoder *encoder;
903 u32 tmp;
904
905 if (dcb->type != OUTPUT_TMDS)
906 return;
907
908 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
909 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
910
911 if (nv_encoder->dcb->type == OUTPUT_DP &&
912 nv_encoder->dcb->or & (1 << or)) {
913 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
914 tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
915 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
916 break;
917 }
918 }
919 }
920
921 static void
nv50_display_unk40_handler(struct drm_device * dev)922 nv50_display_unk40_handler(struct drm_device *dev)
923 {
924 struct nv50_display *disp = nv50_display(dev);
925 struct dcb_entry *dcb = disp->irq.dcb;
926 u16 script = disp->irq.script;
927 u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk;
928
929 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
930 disp->irq.dcb = NULL;
931 if (!dcb)
932 goto ack;
933
934 nouveau_bios_run_display_table(dev, script, -pclk, dcb, -1);
935 nv50_display_unk40_dp_set_tmds(dev, dcb);
936
937 ack:
938 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
939 nv_wr32(dev, 0x610030, 0x80000000);
940 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
941 }
942
943 static void
nv50_display_bh(unsigned long data)944 nv50_display_bh(unsigned long data)
945 {
946 struct drm_device *dev = (struct drm_device *)data;
947
948 for (;;) {
949 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
950 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
951
952 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
953
954 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
955 nv50_display_unk10_handler(dev);
956 else
957 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
958 nv50_display_unk20_handler(dev);
959 else
960 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
961 nv50_display_unk40_handler(dev);
962 else
963 break;
964 }
965
966 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
967 }
968
969 static void
nv50_display_error_handler(struct drm_device * dev)970 nv50_display_error_handler(struct drm_device *dev)
971 {
972 u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
973 u32 addr, data;
974 int chid;
975
976 for (chid = 0; chid < 5; chid++) {
977 if (!(channels & (1 << chid)))
978 continue;
979
980 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
981 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid));
982 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid));
983 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x "
984 "(0x%04x 0x%02x)\n", chid,
985 addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
986
987 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
988 }
989 }
990
991 static void
nv50_display_isr(struct drm_device * dev)992 nv50_display_isr(struct drm_device *dev)
993 {
994 struct nv50_display *disp = nv50_display(dev);
995 uint32_t delayed = 0;
996
997 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
998 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
999 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
1000 uint32_t clock;
1001
1002 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
1003
1004 if (!intr0 && !(intr1 & ~delayed))
1005 break;
1006
1007 if (intr0 & 0x001f0000) {
1008 nv50_display_error_handler(dev);
1009 intr0 &= ~0x001f0000;
1010 }
1011
1012 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1013 nv50_display_vblank_handler(dev, intr1);
1014 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1015 }
1016
1017 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1018 NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1019 NV50_PDISPLAY_INTR_1_CLK_UNK40));
1020 if (clock) {
1021 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1022 tasklet_schedule(&disp->tasklet);
1023 delayed |= clock;
1024 intr1 &= ~clock;
1025 }
1026
1027 if (intr0) {
1028 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1029 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1030 }
1031
1032 if (intr1) {
1033 NV_ERROR(dev,
1034 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1035 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1036 }
1037 }
1038 }
1039