1 /* 2 * arch/arm/plat-spear/include/plat/clock.h 3 * 4 * Clock framework definitions for SPEAr platform 5 * 6 * Copyright (C) 2009 ST Microelectronics 7 * Viresh Kumar<viresh.kumar@st.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #ifndef __PLAT_CLOCK_H 15 #define __PLAT_CLOCK_H 16 17 #include <linux/list.h> 18 #include <linux/clkdev.h> 19 #include <linux/types.h> 20 21 /* clk structure flags */ 22 #define ALWAYS_ENABLED (1 << 0) /* clock always enabled */ 23 #define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */ 24 #define ENABLED_ON_INIT (1 << 2) /* clocks enabled at init */ 25 26 /** 27 * struct clkops - clock operations 28 * @enable: pointer to clock enable function 29 * @disable: pointer to clock disable function 30 */ 31 struct clkops { 32 int (*enable) (struct clk *); 33 void (*disable) (struct clk *); 34 }; 35 36 /** 37 * struct pclk_info - parents info 38 * @pclk: pointer to parent clk 39 * @pclk_val: value to be written for selecting this parent 40 */ 41 struct pclk_info { 42 struct clk *pclk; 43 u8 pclk_val; 44 }; 45 46 /** 47 * struct pclk_sel - parents selection configuration 48 * @pclk_info: pointer to array of parent clock info 49 * @pclk_count: number of parents 50 * @pclk_sel_reg: register for selecting a parent 51 * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also) 52 */ 53 struct pclk_sel { 54 struct pclk_info *pclk_info; 55 u8 pclk_count; 56 void __iomem *pclk_sel_reg; 57 unsigned int pclk_sel_mask; 58 }; 59 60 /** 61 * struct rate_config - clk rate configurations 62 * @tbls: array of device specific clk rate tables, in ascending order of rates 63 * @count: size of tbls array 64 * @default_index: default setting when originally disabled 65 */ 66 struct rate_config { 67 void *tbls; 68 u8 count; 69 u8 default_index; 70 }; 71 72 /** 73 * struct clk - clock structure 74 * @usage_count: num of users who enabled this clock 75 * @flags: flags for clock properties 76 * @rate: programmed clock rate in Hz 77 * @en_reg: clk enable/disable reg 78 * @en_reg_bit: clk enable/disable bit 79 * @ops: clk enable/disable ops - generic_clkops selected if NULL 80 * @recalc: pointer to clock rate recalculate function 81 * @set_rate: pointer to clock set rate function 82 * @calc_rate: pointer to clock get rate function for index 83 * @rate_config: rate configuration information, used by set_rate 84 * @div_factor: division factor to parent clock. 85 * @pclk: current parent clk 86 * @pclk_sel: pointer to parent selection structure 87 * @pclk_sel_shift: register shift for selecting parent of this clock 88 * @children: list for childrens or this clock 89 * @sibling: node for list of clocks having same parents 90 * @private_data: clock specific private data 91 * @node: list to maintain clocks linearly 92 * @cl: clocklook up associated with this clock 93 * @dent: object for debugfs 94 */ 95 struct clk { 96 unsigned int usage_count; 97 unsigned int flags; 98 unsigned long rate; 99 void __iomem *en_reg; 100 u8 en_reg_bit; 101 const struct clkops *ops; 102 int (*recalc) (struct clk *); 103 int (*set_rate) (struct clk *, unsigned long rate); 104 unsigned long (*calc_rate)(struct clk *, int index); 105 struct rate_config rate_config; 106 unsigned int div_factor; 107 108 struct clk *pclk; 109 struct pclk_sel *pclk_sel; 110 unsigned int pclk_sel_shift; 111 112 struct list_head children; 113 struct list_head sibling; 114 void *private_data; 115 #ifdef CONFIG_DEBUG_FS 116 struct list_head node; 117 struct clk_lookup *cl; 118 struct dentry *dent; 119 #endif 120 }; 121 122 /* pll configuration structure */ 123 struct pll_clk_masks { 124 u32 mode_mask; 125 u32 mode_shift; 126 127 u32 norm_fdbk_m_mask; 128 u32 norm_fdbk_m_shift; 129 u32 dith_fdbk_m_mask; 130 u32 dith_fdbk_m_shift; 131 u32 div_p_mask; 132 u32 div_p_shift; 133 u32 div_n_mask; 134 u32 div_n_shift; 135 }; 136 137 struct pll_clk_config { 138 void __iomem *mode_reg; 139 void __iomem *cfg_reg; 140 struct pll_clk_masks *masks; 141 }; 142 143 /* pll clk rate config structure */ 144 struct pll_rate_tbl { 145 u8 mode; 146 u16 m; 147 u8 n; 148 u8 p; 149 }; 150 151 /* ahb and apb bus configuration structure */ 152 struct bus_clk_masks { 153 u32 mask; 154 u32 shift; 155 }; 156 157 struct bus_clk_config { 158 void __iomem *reg; 159 struct bus_clk_masks *masks; 160 }; 161 162 /* ahb and apb clk bus rate config structure */ 163 struct bus_rate_tbl { 164 u8 div; 165 }; 166 167 /* Aux clk configuration structure: applicable to UART and FIRDA */ 168 struct aux_clk_masks { 169 u32 eq_sel_mask; 170 u32 eq_sel_shift; 171 u32 eq1_mask; 172 u32 eq2_mask; 173 u32 xscale_sel_mask; 174 u32 xscale_sel_shift; 175 u32 yscale_sel_mask; 176 u32 yscale_sel_shift; 177 }; 178 179 struct aux_clk_config { 180 void __iomem *synth_reg; 181 struct aux_clk_masks *masks; 182 }; 183 184 /* aux clk rate config structure */ 185 struct aux_rate_tbl { 186 u16 xscale; 187 u16 yscale; 188 u8 eq; 189 }; 190 191 /* GPT clk configuration structure */ 192 struct gpt_clk_masks { 193 u32 mscale_sel_mask; 194 u32 mscale_sel_shift; 195 u32 nscale_sel_mask; 196 u32 nscale_sel_shift; 197 }; 198 199 struct gpt_clk_config { 200 void __iomem *synth_reg; 201 struct gpt_clk_masks *masks; 202 }; 203 204 /* gpt clk rate config structure */ 205 struct gpt_rate_tbl { 206 u16 mscale; 207 u16 nscale; 208 }; 209 210 /* clcd clk configuration structure */ 211 struct clcd_synth_masks { 212 u32 div_factor_mask; 213 u32 div_factor_shift; 214 }; 215 216 struct clcd_clk_config { 217 void __iomem *synth_reg; 218 struct clcd_synth_masks *masks; 219 }; 220 221 /* clcd clk rate config structure */ 222 struct clcd_rate_tbl { 223 u16 div; 224 }; 225 226 /* platform specific clock functions */ 227 void __init clk_init(void); 228 void clk_register(struct clk_lookup *cl); 229 void recalc_root_clocks(void); 230 231 /* clock recalc & set rate functions */ 232 int follow_parent(struct clk *clk); 233 unsigned long pll_calc_rate(struct clk *clk, int index); 234 int pll_clk_recalc(struct clk *clk); 235 int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate); 236 unsigned long bus_calc_rate(struct clk *clk, int index); 237 int bus_clk_recalc(struct clk *clk); 238 int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate); 239 unsigned long gpt_calc_rate(struct clk *clk, int index); 240 int gpt_clk_recalc(struct clk *clk); 241 int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate); 242 unsigned long aux_calc_rate(struct clk *clk, int index); 243 int aux_clk_recalc(struct clk *clk); 244 int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate); 245 unsigned long clcd_calc_rate(struct clk *clk, int index); 246 int clcd_clk_recalc(struct clk *clk); 247 int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate); 248 249 #endif /* __PLAT_CLOCK_H */ 250