1 /*
2  * Copyright 2005 Stephane Marchesin.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #ifndef __NOUVEAU_DRM_H__
26 #define __NOUVEAU_DRM_H__
27 
28 #define DRM_NOUVEAU_EVENT_NVIF                                       0x80000000
29 
30 #include "drm.h"
31 
32 #if defined(__cplusplus)
33 extern "C" {
34 #endif
35 
36 #define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
37 #define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
38 #define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
39 #define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)
40 #define NOUVEAU_GEM_DOMAIN_COHERENT  (1 << 4)
41 
42 #define NOUVEAU_GEM_TILE_COMP        0x00030000 /* nv50-only */
43 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
44 #define NOUVEAU_GEM_TILE_16BPP       0x00000001
45 #define NOUVEAU_GEM_TILE_32BPP       0x00000002
46 #define NOUVEAU_GEM_TILE_ZETA        0x00000004
47 #define NOUVEAU_GEM_TILE_NONCONTIG   0x00000008
48 
49 struct drm_nouveau_gem_info {
50 	__u32 handle;
51 	__u32 domain;
52 	__u64 size;
53 	__u64 offset;
54 	__u64 map_handle;
55 	__u32 tile_mode;
56 	__u32 tile_flags;
57 };
58 
59 struct drm_nouveau_gem_new {
60 	struct drm_nouveau_gem_info info;
61 	__u32 channel_hint;
62 	__u32 align;
63 };
64 
65 #define NOUVEAU_GEM_MAX_BUFFERS 1024
66 struct drm_nouveau_gem_pushbuf_bo_presumed {
67 	__u32 valid;
68 	__u32 domain;
69 	__u64 offset;
70 };
71 
72 struct drm_nouveau_gem_pushbuf_bo {
73 	__u64 user_priv;
74 	__u32 handle;
75 	__u32 read_domains;
76 	__u32 write_domains;
77 	__u32 valid_domains;
78 	struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
79 };
80 
81 #define NOUVEAU_GEM_RELOC_LOW  (1 << 0)
82 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
83 #define NOUVEAU_GEM_RELOC_OR   (1 << 2)
84 #define NOUVEAU_GEM_MAX_RELOCS 1024
85 struct drm_nouveau_gem_pushbuf_reloc {
86 	__u32 reloc_bo_index;
87 	__u32 reloc_bo_offset;
88 	__u32 bo_index;
89 	__u32 flags;
90 	__u32 data;
91 	__u32 vor;
92 	__u32 tor;
93 };
94 
95 #define NOUVEAU_GEM_MAX_PUSH 512
96 struct drm_nouveau_gem_pushbuf_push {
97 	__u32 bo_index;
98 	__u32 pad;
99 	__u64 offset;
100 	__u64 length;
101 };
102 
103 struct drm_nouveau_gem_pushbuf {
104 	__u32 channel;
105 	__u32 nr_buffers;
106 	__u64 buffers;
107 	__u32 nr_relocs;
108 	__u32 nr_push;
109 	__u64 relocs;
110 	__u64 push;
111 	__u32 suffix0;
112 	__u32 suffix1;
113 #define NOUVEAU_GEM_PUSHBUF_SYNC                                    (1ULL << 0)
114 	__u64 vram_available;
115 	__u64 gart_available;
116 };
117 
118 #define NOUVEAU_GEM_CPU_PREP_NOWAIT                                  0x00000001
119 #define NOUVEAU_GEM_CPU_PREP_WRITE                                   0x00000004
120 struct drm_nouveau_gem_cpu_prep {
121 	__u32 handle;
122 	__u32 flags;
123 };
124 
125 struct drm_nouveau_gem_cpu_fini {
126 	__u32 handle;
127 };
128 
129 #define DRM_NOUVEAU_GETPARAM           0x00 /* deprecated */
130 #define DRM_NOUVEAU_SETPARAM           0x01 /* deprecated */
131 #define DRM_NOUVEAU_CHANNEL_ALLOC      0x02 /* deprecated */
132 #define DRM_NOUVEAU_CHANNEL_FREE       0x03 /* deprecated */
133 #define DRM_NOUVEAU_GROBJ_ALLOC        0x04 /* deprecated */
134 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x05 /* deprecated */
135 #define DRM_NOUVEAU_GPUOBJ_FREE        0x06 /* deprecated */
136 #define DRM_NOUVEAU_NVIF               0x07
137 #define DRM_NOUVEAU_SVM_INIT           0x08
138 #define DRM_NOUVEAU_SVM_BIND           0x09
139 #define DRM_NOUVEAU_GEM_NEW            0x40
140 #define DRM_NOUVEAU_GEM_PUSHBUF        0x41
141 #define DRM_NOUVEAU_GEM_CPU_PREP       0x42
142 #define DRM_NOUVEAU_GEM_CPU_FINI       0x43
143 #define DRM_NOUVEAU_GEM_INFO           0x44
144 
145 struct drm_nouveau_svm_init {
146 	__u64 unmanaged_addr;
147 	__u64 unmanaged_size;
148 };
149 
150 struct drm_nouveau_svm_bind {
151 	__u64 header;
152 	__u64 va_start;
153 	__u64 va_end;
154 	__u64 npages;
155 	__u64 stride;
156 	__u64 result;
157 	__u64 reserved0;
158 	__u64 reserved1;
159 };
160 
161 #define NOUVEAU_SVM_BIND_COMMAND_SHIFT          0
162 #define NOUVEAU_SVM_BIND_COMMAND_BITS           8
163 #define NOUVEAU_SVM_BIND_COMMAND_MASK           ((1 << 8) - 1)
164 #define NOUVEAU_SVM_BIND_PRIORITY_SHIFT         8
165 #define NOUVEAU_SVM_BIND_PRIORITY_BITS          8
166 #define NOUVEAU_SVM_BIND_PRIORITY_MASK          ((1 << 8) - 1)
167 #define NOUVEAU_SVM_BIND_TARGET_SHIFT           16
168 #define NOUVEAU_SVM_BIND_TARGET_BITS            32
169 #define NOUVEAU_SVM_BIND_TARGET_MASK            0xffffffff
170 
171 /*
172  * Below is use to validate ioctl argument, userspace can also use it to make
173  * sure that no bit are set beyond known fields for a given kernel version.
174  */
175 #define NOUVEAU_SVM_BIND_VALID_BITS     48
176 #define NOUVEAU_SVM_BIND_VALID_MASK     ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
177 
178 
179 /*
180  * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory.
181  * result: number of page successfuly migrate to the target memory.
182  */
183 #define NOUVEAU_SVM_BIND_COMMAND__MIGRATE               0
184 
185 /*
186  * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory.
187  */
188 #define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM               (1UL << 31)
189 
190 
191 #define DRM_IOCTL_NOUVEAU_SVM_INIT           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
192 #define DRM_IOCTL_NOUVEAU_SVM_BIND           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
193 
194 #define DRM_IOCTL_NOUVEAU_GEM_NEW            DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
195 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF        DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
196 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
197 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
198 #define DRM_IOCTL_NOUVEAU_GEM_INFO           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
199 
200 #if defined(__cplusplus)
201 }
202 #endif
203 
204 #endif /* __NOUVEAU_DRM_H__ */
205