1 /*
2 * Defines, structures, APIs for edac_core module
3 *
4 * (C) 2007 Linux Networx (http://lnxi.com)
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
8 * Written by Thayne Harbaugh
9 * Based on work by Dan Hollis <goemon at anime dot net> and others.
10 * http://www.anime.net/~goemon/linux-ecc/
11 *
12 * NMI handling support added by
13 * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
14 *
15 * Refactored for multi-source files:
16 * Doug Thompson <norsk5@xmission.com>
17 *
18 */
19
20 #ifndef _EDAC_CORE_H_
21 #define _EDAC_CORE_H_
22
23 #include <linux/kernel.h>
24 #include <linux/types.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
27 #include <linux/smp.h>
28 #include <linux/pci.h>
29 #include <linux/time.h>
30 #include <linux/nmi.h>
31 #include <linux/rcupdate.h>
32 #include <linux/completion.h>
33 #include <linux/kobject.h>
34 #include <linux/platform_device.h>
35 #include <linux/workqueue.h>
36 #include <linux/edac.h>
37
38 #define EDAC_DEVICE_NAME_LEN 31
39 #define EDAC_ATTRIB_VALUE_LEN 15
40
41 #if PAGE_SHIFT < 20
42 #define PAGES_TO_MiB(pages) ((pages) >> (20 - PAGE_SHIFT))
43 #define MiB_TO_PAGES(mb) ((mb) << (20 - PAGE_SHIFT))
44 #else /* PAGE_SHIFT > 20 */
45 #define PAGES_TO_MiB(pages) ((pages) << (PAGE_SHIFT - 20))
46 #define MiB_TO_PAGES(mb) ((mb) >> (PAGE_SHIFT - 20))
47 #endif
48
49 #define edac_printk(level, prefix, fmt, arg...) \
50 printk(level "EDAC " prefix ": " fmt, ##arg)
51
52 #define edac_mc_printk(mci, level, fmt, arg...) \
53 printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
54
55 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
56 printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
57
58 #define edac_device_printk(ctl, level, fmt, arg...) \
59 printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
60
61 #define edac_pci_printk(ctl, level, fmt, arg...) \
62 printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
63
64 /* prefixes for edac_printk() and edac_mc_printk() */
65 #define EDAC_MC "MC"
66 #define EDAC_PCI "PCI"
67 #define EDAC_DEBUG "DEBUG"
68
69 extern const char *edac_mem_types[];
70
71 #ifdef CONFIG_EDAC_DEBUG
72 extern int edac_debug_level;
73
74 #define edac_debug_printk(level, fmt, arg...) \
75 do { \
76 if (level <= edac_debug_level) \
77 edac_printk(KERN_DEBUG, EDAC_DEBUG, \
78 "%s: " fmt, __func__, ##arg); \
79 } while (0)
80
81 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
82 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
83 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
84 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
85 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
86
87 #else /* !CONFIG_EDAC_DEBUG */
88
89 #define debugf0( ... )
90 #define debugf1( ... )
91 #define debugf2( ... )
92 #define debugf3( ... )
93 #define debugf4( ... )
94
95 #endif /* !CONFIG_EDAC_DEBUG */
96
97 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
98 PCI_DEVICE_ID_ ## vend ## _ ## dev
99
100 #define edac_dev_name(dev) (dev)->dev_name
101
102 /*
103 * The following are the structures to provide for a generic
104 * or abstract 'edac_device'. This set of structures and the
105 * code that implements the APIs for the same, provide for
106 * registering EDAC type devices which are NOT standard memory.
107 *
108 * CPU caches (L1 and L2)
109 * DMA engines
110 * Core CPU swithces
111 * Fabric switch units
112 * PCIe interface controllers
113 * other EDAC/ECC type devices that can be monitored for
114 * errors, etc.
115 *
116 * It allows for a 2 level set of hiearchry. For example:
117 *
118 * cache could be composed of L1, L2 and L3 levels of cache.
119 * Each CPU core would have its own L1 cache, while sharing
120 * L2 and maybe L3 caches.
121 *
122 * View them arranged, via the sysfs presentation:
123 * /sys/devices/system/edac/..
124 *
125 * mc/ <existing memory device directory>
126 * cpu/cpu0/.. <L1 and L2 block directory>
127 * /L1-cache/ce_count
128 * /ue_count
129 * /L2-cache/ce_count
130 * /ue_count
131 * cpu/cpu1/.. <L1 and L2 block directory>
132 * /L1-cache/ce_count
133 * /ue_count
134 * /L2-cache/ce_count
135 * /ue_count
136 * ...
137 *
138 * the L1 and L2 directories would be "edac_device_block's"
139 */
140
141 struct edac_device_counter {
142 u32 ue_count;
143 u32 ce_count;
144 };
145
146 /* forward reference */
147 struct edac_device_ctl_info;
148 struct edac_device_block;
149
150 /* edac_dev_sysfs_attribute structure
151 * used for driver sysfs attributes in mem_ctl_info
152 * for extra controls and attributes:
153 * like high level error Injection controls
154 */
155 struct edac_dev_sysfs_attribute {
156 struct attribute attr;
157 ssize_t (*show)(struct edac_device_ctl_info *, char *);
158 ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
159 };
160
161 /* edac_dev_sysfs_block_attribute structure
162 *
163 * used in leaf 'block' nodes for adding controls/attributes
164 *
165 * each block in each instance of the containing control structure
166 * can have an array of the following. The show and store functions
167 * will be filled in with the show/store function in the
168 * low level driver.
169 *
170 * The 'value' field will be the actual value field used for
171 * counting
172 */
173 struct edac_dev_sysfs_block_attribute {
174 struct attribute attr;
175 ssize_t (*show)(struct kobject *, struct attribute *, char *);
176 ssize_t (*store)(struct kobject *, struct attribute *,
177 const char *, size_t);
178 struct edac_device_block *block;
179
180 unsigned int value;
181 };
182
183 /* device block control structure */
184 struct edac_device_block {
185 struct edac_device_instance *instance; /* Up Pointer */
186 char name[EDAC_DEVICE_NAME_LEN + 1];
187
188 struct edac_device_counter counters; /* basic UE and CE counters */
189
190 int nr_attribs; /* how many attributes */
191
192 /* this block's attributes, could be NULL */
193 struct edac_dev_sysfs_block_attribute *block_attributes;
194
195 /* edac sysfs device control */
196 struct kobject kobj;
197 };
198
199 /* device instance control structure */
200 struct edac_device_instance {
201 struct edac_device_ctl_info *ctl; /* Up pointer */
202 char name[EDAC_DEVICE_NAME_LEN + 4];
203
204 struct edac_device_counter counters; /* instance counters */
205
206 u32 nr_blocks; /* how many blocks */
207 struct edac_device_block *blocks; /* block array */
208
209 /* edac sysfs device control */
210 struct kobject kobj;
211 };
212
213
214 /*
215 * Abstract edac_device control info structure
216 *
217 */
218 struct edac_device_ctl_info {
219 /* for global list of edac_device_ctl_info structs */
220 struct list_head link;
221
222 struct module *owner; /* Module owner of this control struct */
223
224 int dev_idx;
225
226 /* Per instance controls for this edac_device */
227 int log_ue; /* boolean for logging UEs */
228 int log_ce; /* boolean for logging CEs */
229 int panic_on_ue; /* boolean for panic'ing on an UE */
230 unsigned poll_msec; /* number of milliseconds to poll interval */
231 unsigned long delay; /* number of jiffies for poll_msec */
232
233 /* Additional top controller level attributes, but specified
234 * by the low level driver.
235 *
236 * Set by the low level driver to provide attributes at the
237 * controller level, same level as 'ue_count' and 'ce_count' above.
238 * An array of structures, NULL terminated
239 *
240 * If attributes are desired, then set to array of attributes
241 * If no attributes are desired, leave NULL
242 */
243 struct edac_dev_sysfs_attribute *sysfs_attributes;
244
245 /* pointer to main 'edac' subsys in sysfs */
246 struct bus_type *edac_subsys;
247
248 /* the internal state of this controller instance */
249 int op_state;
250 /* work struct for this instance */
251 struct delayed_work work;
252
253 /* pointer to edac polling checking routine:
254 * If NOT NULL: points to polling check routine
255 * If NULL: Then assumes INTERRUPT operation, where
256 * MC driver will receive events
257 */
258 void (*edac_check) (struct edac_device_ctl_info * edac_dev);
259
260 struct device *dev; /* pointer to device structure */
261
262 const char *mod_name; /* module name */
263 const char *ctl_name; /* edac controller name */
264 const char *dev_name; /* pci/platform/etc... name */
265
266 void *pvt_info; /* pointer to 'private driver' info */
267
268 unsigned long start_time; /* edac_device load start time (jiffies) */
269
270 struct completion removal_complete;
271
272 /* sysfs top name under 'edac' directory
273 * and instance name:
274 * cpu/cpu0/...
275 * cpu/cpu1/...
276 * cpu/cpu2/...
277 * ...
278 */
279 char name[EDAC_DEVICE_NAME_LEN + 1];
280
281 /* Number of instances supported on this control structure
282 * and the array of those instances
283 */
284 u32 nr_instances;
285 struct edac_device_instance *instances;
286
287 /* Event counters for the this whole EDAC Device */
288 struct edac_device_counter counters;
289
290 /* edac sysfs device control for the 'name'
291 * device this structure controls
292 */
293 struct kobject kobj;
294 };
295
296 /* To get from the instance's wq to the beginning of the ctl structure */
297 #define to_edac_mem_ctl_work(w) \
298 container_of(w, struct mem_ctl_info, work)
299
300 #define to_edac_device_ctl_work(w) \
301 container_of(w,struct edac_device_ctl_info,work)
302
303 /*
304 * The alloc() and free() functions for the 'edac_device' control info
305 * structure. A MC driver will allocate one of these for each edac_device
306 * it is going to control/register with the EDAC CORE.
307 */
308 extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
309 unsigned sizeof_private,
310 char *edac_device_name, unsigned nr_instances,
311 char *edac_block_name, unsigned nr_blocks,
312 unsigned offset_value,
313 struct edac_dev_sysfs_block_attribute *block_attributes,
314 unsigned nr_attribs,
315 int device_index);
316
317 /* The offset value can be:
318 * -1 indicating no offset value
319 * 0 for zero-based block numbers
320 * 1 for 1-based block number
321 * other for other-based block number
322 */
323 #define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1)
324
325 extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
326
327 #ifdef CONFIG_PCI
328
329 struct edac_pci_counter {
330 atomic_t pe_count;
331 atomic_t npe_count;
332 };
333
334 /*
335 * Abstract edac_pci control info structure
336 *
337 */
338 struct edac_pci_ctl_info {
339 /* for global list of edac_pci_ctl_info structs */
340 struct list_head link;
341
342 int pci_idx;
343
344 struct bus_type *edac_subsys; /* pointer to subsystem */
345
346 /* the internal state of this controller instance */
347 int op_state;
348 /* work struct for this instance */
349 struct delayed_work work;
350
351 /* pointer to edac polling checking routine:
352 * If NOT NULL: points to polling check routine
353 * If NULL: Then assumes INTERRUPT operation, where
354 * MC driver will receive events
355 */
356 void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
357
358 struct device *dev; /* pointer to device structure */
359
360 const char *mod_name; /* module name */
361 const char *ctl_name; /* edac controller name */
362 const char *dev_name; /* pci/platform/etc... name */
363
364 void *pvt_info; /* pointer to 'private driver' info */
365
366 unsigned long start_time; /* edac_pci load start time (jiffies) */
367
368 struct completion complete;
369
370 /* sysfs top name under 'edac' directory
371 * and instance name:
372 * cpu/cpu0/...
373 * cpu/cpu1/...
374 * cpu/cpu2/...
375 * ...
376 */
377 char name[EDAC_DEVICE_NAME_LEN + 1];
378
379 /* Event counters for the this whole EDAC Device */
380 struct edac_pci_counter counters;
381
382 /* edac sysfs device control for the 'name'
383 * device this structure controls
384 */
385 struct kobject kobj;
386 struct completion kobj_complete;
387 };
388
389 #define to_edac_pci_ctl_work(w) \
390 container_of(w, struct edac_pci_ctl_info,work)
391
392 /* write all or some bits in a byte-register*/
pci_write_bits8(struct pci_dev * pdev,int offset,u8 value,u8 mask)393 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
394 u8 mask)
395 {
396 if (mask != 0xff) {
397 u8 buf;
398
399 pci_read_config_byte(pdev, offset, &buf);
400 value &= mask;
401 buf &= ~mask;
402 value |= buf;
403 }
404
405 pci_write_config_byte(pdev, offset, value);
406 }
407
408 /* write all or some bits in a word-register*/
pci_write_bits16(struct pci_dev * pdev,int offset,u16 value,u16 mask)409 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
410 u16 value, u16 mask)
411 {
412 if (mask != 0xffff) {
413 u16 buf;
414
415 pci_read_config_word(pdev, offset, &buf);
416 value &= mask;
417 buf &= ~mask;
418 value |= buf;
419 }
420
421 pci_write_config_word(pdev, offset, value);
422 }
423
424 /*
425 * pci_write_bits32
426 *
427 * edac local routine to do pci_write_config_dword, but adds
428 * a mask parameter. If mask is all ones, ignore the mask.
429 * Otherwise utilize the mask to isolate specified bits
430 *
431 * write all or some bits in a dword-register
432 */
pci_write_bits32(struct pci_dev * pdev,int offset,u32 value,u32 mask)433 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
434 u32 value, u32 mask)
435 {
436 if (mask != 0xffffffff) {
437 u32 buf;
438
439 pci_read_config_dword(pdev, offset, &buf);
440 value &= mask;
441 buf &= ~mask;
442 value |= buf;
443 }
444
445 pci_write_config_dword(pdev, offset, value);
446 }
447
448 #endif /* CONFIG_PCI */
449
450 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
451 unsigned nr_chans, int edac_index);
452 extern int edac_mc_add_mc(struct mem_ctl_info *mci);
453 extern void edac_mc_free(struct mem_ctl_info *mci);
454 extern struct mem_ctl_info *edac_mc_find(int idx);
455 extern struct mem_ctl_info *find_mci_by_dev(struct device *dev);
456 extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
457 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
458 unsigned long page);
459
460 /*
461 * The no info errors are used when error overflows are reported.
462 * There are a limited number of error logging registers that can
463 * be exausted. When all registers are exhausted and an additional
464 * error occurs then an error overflow register records that an
465 * error occurred and the type of error, but doesn't have any
466 * further information. The ce/ue versions make for cleaner
467 * reporting logic and function interface - reduces conditional
468 * statement clutter and extra function arguments.
469 */
470 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
471 unsigned long page_frame_number,
472 unsigned long offset_in_page,
473 unsigned long syndrome, int row, int channel,
474 const char *msg);
475 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
476 const char *msg);
477 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
478 unsigned long page_frame_number,
479 unsigned long offset_in_page, int row,
480 const char *msg);
481 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
482 const char *msg);
483 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
484 unsigned int channel0, unsigned int channel1,
485 char *msg);
486 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
487 unsigned int channel, char *msg);
488
489 /*
490 * edac_device APIs
491 */
492 extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
493 extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
494 extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
495 int inst_nr, int block_nr, const char *msg);
496 extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
497 int inst_nr, int block_nr, const char *msg);
498 extern int edac_device_alloc_index(void);
499
500 /*
501 * edac_pci APIs
502 */
503 extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
504 const char *edac_pci_name);
505
506 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
507
508 extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
509 unsigned long value);
510
511 extern int edac_pci_alloc_index(void);
512 extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
513 extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
514
515 extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
516 struct device *dev,
517 const char *mod_name);
518
519 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
520 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
521 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
522
523 /*
524 * edac misc APIs
525 */
526 extern char *edac_op_state_to_string(int op_state);
527
528 #endif /* _EDAC_CORE_H_ */
529