1 /*
2 * Copyright (C) 2007 Ben Skeggs.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27 #include "drmP.h"
28 #include "drm.h"
29 #include "nouveau_drv.h"
30 #include "nouveau_dma.h"
31 #include "nouveau_ramht.h"
32
33 void
nouveau_dma_init(struct nouveau_channel * chan)34 nouveau_dma_init(struct nouveau_channel *chan)
35 {
36 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
37 struct nouveau_bo *pushbuf = chan->pushbuf_bo;
38
39 if (dev_priv->card_type >= NV_50) {
40 const int ib_size = pushbuf->bo.mem.size / 2;
41
42 chan->dma.ib_base = (pushbuf->bo.mem.size - ib_size) >> 2;
43 chan->dma.ib_max = (ib_size / 8) - 1;
44 chan->dma.ib_put = 0;
45 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
46
47 chan->dma.max = (pushbuf->bo.mem.size - ib_size) >> 2;
48 } else {
49 chan->dma.max = (pushbuf->bo.mem.size >> 2) - 2;
50 }
51
52 chan->dma.put = 0;
53 chan->dma.cur = chan->dma.put;
54 chan->dma.free = chan->dma.max - chan->dma.cur;
55 }
56
57 void
OUT_RINGp(struct nouveau_channel * chan,const void * data,unsigned nr_dwords)58 OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
59 {
60 bool is_iomem;
61 u32 *mem = ttm_kmap_obj_virtual(&chan->pushbuf_bo->kmap, &is_iomem);
62 mem = &mem[chan->dma.cur];
63 if (is_iomem)
64 memcpy_toio((void __force __iomem *)mem, data, nr_dwords * 4);
65 else
66 memcpy(mem, data, nr_dwords * 4);
67 chan->dma.cur += nr_dwords;
68 }
69
70 /* Fetch and adjust GPU GET pointer
71 *
72 * Returns:
73 * value >= 0, the adjusted GET pointer
74 * -EINVAL if GET pointer currently outside main push buffer
75 * -EBUSY if timeout exceeded
76 */
77 static inline int
READ_GET(struct nouveau_channel * chan,uint64_t * prev_get,int * timeout)78 READ_GET(struct nouveau_channel *chan, uint64_t *prev_get, int *timeout)
79 {
80 uint64_t val;
81
82 val = nvchan_rd32(chan, chan->user_get);
83 if (chan->user_get_hi)
84 val |= (uint64_t)nvchan_rd32(chan, chan->user_get_hi) << 32;
85
86 /* reset counter as long as GET is still advancing, this is
87 * to avoid misdetecting a GPU lockup if the GPU happens to
88 * just be processing an operation that takes a long time
89 */
90 if (val != *prev_get) {
91 *prev_get = val;
92 *timeout = 0;
93 }
94
95 if ((++*timeout & 0xff) == 0) {
96 DRM_UDELAY(1);
97 if (*timeout > 100000)
98 return -EBUSY;
99 }
100
101 if (val < chan->pushbuf_base ||
102 val > chan->pushbuf_base + (chan->dma.max << 2))
103 return -EINVAL;
104
105 return (val - chan->pushbuf_base) >> 2;
106 }
107
108 void
nv50_dma_push(struct nouveau_channel * chan,struct nouveau_bo * bo,int delta,int length)109 nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
110 int delta, int length)
111 {
112 struct nouveau_bo *pb = chan->pushbuf_bo;
113 struct nouveau_vma *vma;
114 int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base;
115 u64 offset;
116
117 vma = nouveau_bo_vma_find(bo, chan->vm);
118 BUG_ON(!vma);
119 offset = vma->offset + delta;
120
121 BUG_ON(chan->dma.ib_free < 1);
122 nouveau_bo_wr32(pb, ip++, lower_32_bits(offset));
123 nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8);
124
125 chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
126
127 DRM_MEMORYBARRIER();
128 /* Flush writes. */
129 nouveau_bo_rd32(pb, 0);
130
131 nvchan_wr32(chan, 0x8c, chan->dma.ib_put);
132 chan->dma.ib_free--;
133 }
134
135 static int
nv50_dma_push_wait(struct nouveau_channel * chan,int count)136 nv50_dma_push_wait(struct nouveau_channel *chan, int count)
137 {
138 uint32_t cnt = 0, prev_get = 0;
139
140 while (chan->dma.ib_free < count) {
141 uint32_t get = nvchan_rd32(chan, 0x88);
142 if (get != prev_get) {
143 prev_get = get;
144 cnt = 0;
145 }
146
147 if ((++cnt & 0xff) == 0) {
148 DRM_UDELAY(1);
149 if (cnt > 100000)
150 return -EBUSY;
151 }
152
153 chan->dma.ib_free = get - chan->dma.ib_put;
154 if (chan->dma.ib_free <= 0)
155 chan->dma.ib_free += chan->dma.ib_max;
156 }
157
158 return 0;
159 }
160
161 static int
nv50_dma_wait(struct nouveau_channel * chan,int slots,int count)162 nv50_dma_wait(struct nouveau_channel *chan, int slots, int count)
163 {
164 uint64_t prev_get = 0;
165 int ret, cnt = 0;
166
167 ret = nv50_dma_push_wait(chan, slots + 1);
168 if (unlikely(ret))
169 return ret;
170
171 while (chan->dma.free < count) {
172 int get = READ_GET(chan, &prev_get, &cnt);
173 if (unlikely(get < 0)) {
174 if (get == -EINVAL)
175 continue;
176
177 return get;
178 }
179
180 if (get <= chan->dma.cur) {
181 chan->dma.free = chan->dma.max - chan->dma.cur;
182 if (chan->dma.free >= count)
183 break;
184
185 FIRE_RING(chan);
186 do {
187 get = READ_GET(chan, &prev_get, &cnt);
188 if (unlikely(get < 0)) {
189 if (get == -EINVAL)
190 continue;
191 return get;
192 }
193 } while (get == 0);
194 chan->dma.cur = 0;
195 chan->dma.put = 0;
196 }
197
198 chan->dma.free = get - chan->dma.cur - 1;
199 }
200
201 return 0;
202 }
203
204 int
nouveau_dma_wait(struct nouveau_channel * chan,int slots,int size)205 nouveau_dma_wait(struct nouveau_channel *chan, int slots, int size)
206 {
207 uint64_t prev_get = 0;
208 int cnt = 0, get;
209
210 if (chan->dma.ib_max)
211 return nv50_dma_wait(chan, slots, size);
212
213 while (chan->dma.free < size) {
214 get = READ_GET(chan, &prev_get, &cnt);
215 if (unlikely(get == -EBUSY))
216 return -EBUSY;
217
218 /* loop until we have a usable GET pointer. the value
219 * we read from the GPU may be outside the main ring if
220 * PFIFO is processing a buffer called from the main ring,
221 * discard these values until something sensible is seen.
222 *
223 * the other case we discard GET is while the GPU is fetching
224 * from the SKIPS area, so the code below doesn't have to deal
225 * with some fun corner cases.
226 */
227 if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS)
228 continue;
229
230 if (get <= chan->dma.cur) {
231 /* engine is fetching behind us, or is completely
232 * idle (GET == PUT) so we have free space up until
233 * the end of the push buffer
234 *
235 * we can only hit that path once per call due to
236 * looping back to the beginning of the push buffer,
237 * we'll hit the fetching-ahead-of-us path from that
238 * point on.
239 *
240 * the *one* exception to that rule is if we read
241 * GET==PUT, in which case the below conditional will
242 * always succeed and break us out of the wait loop.
243 */
244 chan->dma.free = chan->dma.max - chan->dma.cur;
245 if (chan->dma.free >= size)
246 break;
247
248 /* not enough space left at the end of the push buffer,
249 * instruct the GPU to jump back to the start right
250 * after processing the currently pending commands.
251 */
252 OUT_RING(chan, chan->pushbuf_base | 0x20000000);
253
254 /* wait for GET to depart from the skips area.
255 * prevents writing GET==PUT and causing a race
256 * condition that causes us to think the GPU is
257 * idle when it's not.
258 */
259 do {
260 get = READ_GET(chan, &prev_get, &cnt);
261 if (unlikely(get == -EBUSY))
262 return -EBUSY;
263 if (unlikely(get == -EINVAL))
264 continue;
265 } while (get <= NOUVEAU_DMA_SKIPS);
266 WRITE_PUT(NOUVEAU_DMA_SKIPS);
267
268 /* we're now submitting commands at the start of
269 * the push buffer.
270 */
271 chan->dma.cur =
272 chan->dma.put = NOUVEAU_DMA_SKIPS;
273 }
274
275 /* engine fetching ahead of us, we have space up until the
276 * current GET pointer. the "- 1" is to ensure there's
277 * space left to emit a jump back to the beginning of the
278 * push buffer if we require it. we can never get GET == PUT
279 * here, so this is safe.
280 */
281 chan->dma.free = get - chan->dma.cur - 1;
282 }
283
284 return 0;
285 }
286
287