1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2004-2008 Cavium Networks
7  */
8 #ifndef __ASM_OCTEON_OCTEON_H
9 #define __ASM_OCTEON_OCTEON_H
10 
11 #include "cvmx.h"
12 
13 extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
14 						uint64_t alignment,
15 						uint64_t min_addr,
16 						uint64_t max_addr,
17 						int do_locking);
18 extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
19 				  int do_locking);
20 extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
21 					uint64_t min_addr, uint64_t max_addr,
22 					int do_locking);
23 extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
24 					char *name);
25 extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
26 					      uint64_t max_addr, uint64_t align,
27 					      char *name);
28 extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
29 						char *name);
30 extern int octeon_bootmem_free_named(char *name);
31 extern void octeon_bootmem_lock(void);
32 extern void octeon_bootmem_unlock(void);
33 
34 extern int octeon_is_simulation(void);
35 extern int octeon_is_pci_host(void);
36 extern int octeon_usb_is_ref_clk(void);
37 extern uint64_t octeon_get_clock_rate(void);
38 extern u64 octeon_get_io_clock_rate(void);
39 extern const char *octeon_board_type_string(void);
40 extern const char *octeon_get_pci_interrupts(void);
41 extern int octeon_get_southbridge_interrupt(void);
42 extern int octeon_get_boot_coremask(void);
43 extern int octeon_get_boot_num_arguments(void);
44 extern const char *octeon_get_boot_argument(int arg);
45 extern void octeon_hal_setup_reserved32(void);
46 extern void octeon_user_io_init(void);
47 struct octeon_cop2_state;
48 extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
49 extern void octeon_crypto_disable(struct octeon_cop2_state *state,
50 				  unsigned long flags);
51 extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
52 
53 extern void octeon_init_cvmcount(void);
54 extern void octeon_setup_delays(void);
55 
56 #define OCTEON_ARGV_MAX_ARGS	64
57 #define OCTOEN_SERIAL_LEN	20
58 
59 struct octeon_boot_descriptor {
60 	/* Start of block referenced by assembly code - do not change! */
61 	uint32_t desc_version;
62 	uint32_t desc_size;
63 	uint64_t stack_top;
64 	uint64_t heap_base;
65 	uint64_t heap_end;
66 	/* Only used by bootloader */
67 	uint64_t entry_point;
68 	uint64_t desc_vaddr;
69 	/* End of This block referenced by assembly code - do not change! */
70 	uint32_t exception_base_addr;
71 	uint32_t stack_size;
72 	uint32_t heap_size;
73 	/* Argc count for application. */
74 	uint32_t argc;
75 	uint32_t argv[OCTEON_ARGV_MAX_ARGS];
76 
77 #define  BOOT_FLAG_INIT_CORE		(1 << 0)
78 #define  OCTEON_BL_FLAG_DEBUG		(1 << 1)
79 #define  OCTEON_BL_FLAG_NO_MAGIC	(1 << 2)
80 	/* If set, use uart1 for console */
81 #define  OCTEON_BL_FLAG_CONSOLE_UART1	(1 << 3)
82 	/* If set, use PCI console */
83 #define  OCTEON_BL_FLAG_CONSOLE_PCI	(1 << 4)
84 	/* Call exit on break on serial port */
85 #define  OCTEON_BL_FLAG_BREAK		(1 << 5)
86 
87 	uint32_t flags;
88 	uint32_t core_mask;
89 	/* DRAM size in megabyes. */
90 	uint32_t dram_size;
91 	/* physical address of free memory descriptor block. */
92 	uint32_t phy_mem_desc_addr;
93 	/* used to pass flags from app to debugger. */
94 	uint32_t debugger_flags_base_addr;
95 	/* CPU clock speed, in hz. */
96 	uint32_t eclock_hz;
97 	/* DRAM clock speed, in hz. */
98 	uint32_t dclock_hz;
99 	/* SPI4 clock in hz. */
100 	uint32_t spi_clock_hz;
101 	uint16_t board_type;
102 	uint8_t board_rev_major;
103 	uint8_t board_rev_minor;
104 	uint16_t chip_type;
105 	uint8_t chip_rev_major;
106 	uint8_t chip_rev_minor;
107 	char board_serial_number[OCTOEN_SERIAL_LEN];
108 	uint8_t mac_addr_base[6];
109 	uint8_t mac_addr_count;
110 	uint64_t cvmx_desc_vaddr;
111 };
112 
113 union octeon_cvmemctl {
114 	uint64_t u64;
115 	struct {
116 		/* RO 1 = BIST fail, 0 = BIST pass */
117 		uint64_t tlbbist:1;
118 		/* RO 1 = BIST fail, 0 = BIST pass */
119 		uint64_t l1cbist:1;
120 		/* RO 1 = BIST fail, 0 = BIST pass */
121 		uint64_t l1dbist:1;
122 		/* RO 1 = BIST fail, 0 = BIST pass */
123 		uint64_t dcmbist:1;
124 		/* RO 1 = BIST fail, 0 = BIST pass */
125 		uint64_t ptgbist:1;
126 		/* RO 1 = BIST fail, 0 = BIST pass */
127 		uint64_t wbfbist:1;
128 		/* Reserved */
129 		uint64_t reserved:22;
130 		/* R/W If set, marked write-buffer entries time out
131 		 * the same as as other entries; if clear, marked
132 		 * write-buffer entries use the maximum timeout. */
133 		uint64_t dismarkwblongto:1;
134 		/* R/W If set, a merged store does not clear the
135 		 * write-buffer entry timeout state. */
136 		uint64_t dismrgclrwbto:1;
137 		/* R/W Two bits that are the MSBs of the resultant
138 		 * CVMSEG LM word location for an IOBDMA. The other 8
139 		 * bits come from the SCRADDR field of the IOBDMA. */
140 		uint64_t iobdmascrmsb:2;
141 		/* R/W If set, SYNCWS and SYNCS only order marked
142 		 * stores; if clear, SYNCWS and SYNCS only order
143 		 * unmarked stores. SYNCWSMARKED has no effect when
144 		 * DISSYNCWS is set. */
145 		uint64_t syncwsmarked:1;
146 		/* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
147 		 * SYNC. */
148 		uint64_t dissyncws:1;
149 		/* R/W If set, no stall happens on write buffer
150 		 * full. */
151 		uint64_t diswbfst:1;
152 		/* R/W If set (and SX set), supervisor-level
153 		 * loads/stores can use XKPHYS addresses with
154 		 * VA<48>==0 */
155 		uint64_t xkmemenas:1;
156 		/* R/W If set (and UX set), user-level loads/stores
157 		 * can use XKPHYS addresses with VA<48>==0 */
158 		uint64_t xkmemenau:1;
159 		/* R/W If set (and SX set), supervisor-level
160 		 * loads/stores can use XKPHYS addresses with
161 		 * VA<48>==1 */
162 		uint64_t xkioenas:1;
163 		/* R/W If set (and UX set), user-level loads/stores
164 		 * can use XKPHYS addresses with VA<48>==1 */
165 		uint64_t xkioenau:1;
166 		/* R/W If set, all stores act as SYNCW (NOMERGE must
167 		 * be set when this is set) RW, reset to 0. */
168 		uint64_t allsyncw:1;
169 		/* R/W If set, no stores merge, and all stores reach
170 		 * the coherent bus in order. */
171 		uint64_t nomerge:1;
172 		/* R/W Selects the bit in the counter used for DID
173 		 * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
174 		 * 214. Actual time-out is between 1x and 2x this
175 		 * interval. For example, with DIDTTO=3, expiration
176 		 * interval is between 16K and 32K. */
177 		uint64_t didtto:2;
178 		/* R/W If set, the (mem) CSR clock never turns off. */
179 		uint64_t csrckalwys:1;
180 		/* R/W If set, mclk never turns off. */
181 		uint64_t mclkalwys:1;
182 		/* R/W Selects the bit in the counter used for write
183 		 * buffer flush time-outs (WBFLT+11) is the bit
184 		 * position in an internal counter used to determine
185 		 * expiration. The write buffer expires between 1x and
186 		 * 2x this interval. For example, with WBFLT = 0, a
187 		 * write buffer expires between 2K and 4K cycles after
188 		 * the write buffer entry is allocated. */
189 		uint64_t wbfltime:3;
190 		/* R/W If set, do not put Istream in the L2 cache. */
191 		uint64_t istrnol2:1;
192 		/* R/W The write buffer threshold. */
193 		uint64_t wbthresh:4;
194 		/* Reserved */
195 		uint64_t reserved2:2;
196 		/* R/W If set, CVMSEG is available for loads/stores in
197 		 * kernel/debug mode. */
198 		uint64_t cvmsegenak:1;
199 		/* R/W If set, CVMSEG is available for loads/stores in
200 		 * supervisor mode. */
201 		uint64_t cvmsegenas:1;
202 		/* R/W If set, CVMSEG is available for loads/stores in
203 		 * user mode. */
204 		uint64_t cvmsegenau:1;
205 		/* R/W Size of local memory in cache blocks, 54 (6912
206 		 * bytes) is max legal value. */
207 		uint64_t lmemsz:6;
208 	} s;
209 };
210 
211 struct octeon_cf_data {
212 	unsigned long	base_region_bias;
213 	unsigned int	base_region;	/* The chip select region used by CF */
214 	int		is16bit;	/* 0 - 8bit, !0 - 16bit */
215 	int		dma_engine;	/* -1 for no DMA */
216 };
217 
218 struct octeon_i2c_data {
219 	unsigned int	sys_freq;
220 	unsigned int	i2c_freq;
221 };
222 
223 extern void octeon_write_lcd(const char *s);
224 extern void octeon_check_cpu_bist(void);
225 extern int octeon_get_boot_debug_flag(void);
226 extern int octeon_get_boot_uart(void);
227 
228 struct uart_port;
229 extern unsigned int octeon_serial_in(struct uart_port *, int);
230 extern void octeon_serial_out(struct uart_port *, int, int);
231 
232 /**
233  * Write a 32bit value to the Octeon NPI register space
234  *
235  * @address: Address to write to
236  * @val:     Value to write
237  */
octeon_npi_write32(uint64_t address,uint32_t val)238 static inline void octeon_npi_write32(uint64_t address, uint32_t val)
239 {
240 	cvmx_write64_uint32(address ^ 4, val);
241 	cvmx_read64_uint32(address ^ 4);
242 }
243 
244 
245 /**
246  * Read a 32bit value from the Octeon NPI register space
247  *
248  * @address: Address to read
249  * Returns The result
250  */
octeon_npi_read32(uint64_t address)251 static inline uint32_t octeon_npi_read32(uint64_t address)
252 {
253 	return cvmx_read64_uint32(address ^ 4);
254 }
255 
256 extern struct cvmx_bootinfo *octeon_bootinfo;
257 
258 extern uint64_t octeon_bootloader_entry_addr;
259 
260 extern void (*octeon_irq_setup_secondary)(void);
261 
262 #endif /* __ASM_OCTEON_OCTEON_H */
263