1 /*
2 * linux/arch/arm/plat-nomadik/timer.c
3 *
4 * Copyright (C) 2008 STMicroelectronics
5 * Copyright (C) 2010 Alessandro Rubini
6 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2, as
10 * published by the Free Software Foundation.
11 */
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/io.h>
16 #include <linux/clockchips.h>
17 #include <linux/clk.h>
18 #include <linux/jiffies.h>
19 #include <linux/err.h>
20 #include <asm/mach/time.h>
21 #include <asm/sched_clock.h>
22
23 /*
24 * The MTU device hosts four different counters, with 4 set of
25 * registers. These are register names.
26 */
27
28 #define MTU_IMSC 0x00 /* Interrupt mask set/clear */
29 #define MTU_RIS 0x04 /* Raw interrupt status */
30 #define MTU_MIS 0x08 /* Masked interrupt status */
31 #define MTU_ICR 0x0C /* Interrupt clear register */
32
33 /* per-timer registers take 0..3 as argument */
34 #define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
35 #define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
36 #define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
37 #define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
38
39 /* bits for the control register */
40 #define MTU_CRn_ENA 0x80
41 #define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
42 #define MTU_CRn_PRESCALE_MASK 0x0c
43 #define MTU_CRn_PRESCALE_1 0x00
44 #define MTU_CRn_PRESCALE_16 0x04
45 #define MTU_CRn_PRESCALE_256 0x08
46 #define MTU_CRn_32BITS 0x02
47 #define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
48
49 /* Other registers are usual amba/primecell registers, currently not used */
50 #define MTU_ITCR 0xff0
51 #define MTU_ITOP 0xff4
52
53 #define MTU_PERIPH_ID0 0xfe0
54 #define MTU_PERIPH_ID1 0xfe4
55 #define MTU_PERIPH_ID2 0xfe8
56 #define MTU_PERIPH_ID3 0xfeC
57
58 #define MTU_PCELL0 0xff0
59 #define MTU_PCELL1 0xff4
60 #define MTU_PCELL2 0xff8
61 #define MTU_PCELL3 0xffC
62
63 static void __iomem *mtu_base;
64 static bool clkevt_periodic;
65 static u32 clk_prescale;
66 static u32 nmdk_cycle; /* write-once */
67
68 #ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
69 /*
70 * Override the global weak sched_clock symbol with this
71 * local implementation which uses the clocksource to get some
72 * better resolution when scheduling the kernel.
73 */
nomadik_read_sched_clock(void)74 static u32 notrace nomadik_read_sched_clock(void)
75 {
76 if (unlikely(!mtu_base))
77 return 0;
78
79 return -readl(mtu_base + MTU_VAL(0));
80 }
81 #endif
82
83 /* Clockevent device: use one-shot mode */
nmdk_clkevt_next(unsigned long evt,struct clock_event_device * ev)84 static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
85 {
86 writel(1 << 1, mtu_base + MTU_IMSC);
87 writel(evt, mtu_base + MTU_LR(1));
88 /* Load highest value, enable device, enable interrupts */
89 writel(MTU_CRn_ONESHOT | clk_prescale |
90 MTU_CRn_32BITS | MTU_CRn_ENA,
91 mtu_base + MTU_CR(1));
92
93 return 0;
94 }
95
nmdk_clkevt_reset(void)96 void nmdk_clkevt_reset(void)
97 {
98 if (clkevt_periodic) {
99 /* Timer: configure load and background-load, and fire it up */
100 writel(nmdk_cycle, mtu_base + MTU_LR(1));
101 writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
102
103 writel(MTU_CRn_PERIODIC | clk_prescale |
104 MTU_CRn_32BITS | MTU_CRn_ENA,
105 mtu_base + MTU_CR(1));
106 writel(1 << 1, mtu_base + MTU_IMSC);
107 } else {
108 /* Generate an interrupt to start the clockevent again */
109 (void) nmdk_clkevt_next(nmdk_cycle, NULL);
110 }
111 }
112
nmdk_clkevt_mode(enum clock_event_mode mode,struct clock_event_device * dev)113 static void nmdk_clkevt_mode(enum clock_event_mode mode,
114 struct clock_event_device *dev)
115 {
116 switch (mode) {
117 case CLOCK_EVT_MODE_PERIODIC:
118 clkevt_periodic = true;
119 nmdk_clkevt_reset();
120 break;
121 case CLOCK_EVT_MODE_ONESHOT:
122 clkevt_periodic = false;
123 break;
124 case CLOCK_EVT_MODE_SHUTDOWN:
125 case CLOCK_EVT_MODE_UNUSED:
126 writel(0, mtu_base + MTU_IMSC);
127 /* disable timer */
128 writel(0, mtu_base + MTU_CR(1));
129 /* load some high default value */
130 writel(0xffffffff, mtu_base + MTU_LR(1));
131 break;
132 case CLOCK_EVT_MODE_RESUME:
133 break;
134 }
135 }
136
137 static struct clock_event_device nmdk_clkevt = {
138 .name = "mtu_1",
139 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
140 .rating = 200,
141 .set_mode = nmdk_clkevt_mode,
142 .set_next_event = nmdk_clkevt_next,
143 };
144
145 /*
146 * IRQ Handler for timer 1 of the MTU block.
147 */
nmdk_timer_interrupt(int irq,void * dev_id)148 static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
149 {
150 struct clock_event_device *evdev = dev_id;
151
152 writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
153 evdev->event_handler(evdev);
154 return IRQ_HANDLED;
155 }
156
157 static struct irqaction nmdk_timer_irq = {
158 .name = "Nomadik Timer Tick",
159 .flags = IRQF_DISABLED | IRQF_TIMER,
160 .handler = nmdk_timer_interrupt,
161 .dev_id = &nmdk_clkevt,
162 };
163
nmdk_clksrc_reset(void)164 void nmdk_clksrc_reset(void)
165 {
166 /* Disable */
167 writel(0, mtu_base + MTU_CR(0));
168
169 /* ClockSource: configure load and background-load, and fire it up */
170 writel(nmdk_cycle, mtu_base + MTU_LR(0));
171 writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
172
173 writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
174 mtu_base + MTU_CR(0));
175 }
176
nmdk_timer_init(void __iomem * base)177 void __init nmdk_timer_init(void __iomem *base)
178 {
179 unsigned long rate;
180 struct clk *clk0;
181
182 mtu_base = base;
183 clk0 = clk_get_sys("mtu0", NULL);
184 BUG_ON(IS_ERR(clk0));
185 BUG_ON(clk_prepare(clk0) < 0);
186 BUG_ON(clk_enable(clk0) < 0);
187
188 /*
189 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
190 * for ux500.
191 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
192 * At 32 MHz, the timer (with 32 bit counter) can be programmed
193 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
194 * with 16 gives too low timer resolution.
195 */
196 rate = clk_get_rate(clk0);
197 if (rate > 32000000) {
198 rate /= 16;
199 clk_prescale = MTU_CRn_PRESCALE_16;
200 } else {
201 clk_prescale = MTU_CRn_PRESCALE_1;
202 }
203
204 nmdk_cycle = (rate + HZ/2) / HZ;
205
206
207 /* Timer 0 is the free running clocksource */
208 nmdk_clksrc_reset();
209
210 if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
211 rate, 200, 32, clocksource_mmio_readl_down))
212 pr_err("timer: failed to initialize clock source %s\n",
213 "mtu_0");
214
215 #ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
216 setup_sched_clock(nomadik_read_sched_clock, 32, rate);
217 #endif
218
219 /* Timer 1 is used for events, register irq and clockevents */
220 setup_irq(IRQ_MTU0, &nmdk_timer_irq);
221 nmdk_clkevt.cpumask = cpumask_of(0);
222 clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
223 }
224