1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
53 #include <linux/cpuidle.h>
54
55 #include <asm/acpi.h>
56 #include <asm/desc.h>
57 #include <asm/nmi.h>
58 #include <asm/irq.h>
59 #include <asm/idle.h>
60 #include <asm/trampoline.h>
61 #include <asm/cpu.h>
62 #include <asm/numa.h>
63 #include <asm/pgtable.h>
64 #include <asm/tlbflush.h>
65 #include <asm/mtrr.h>
66 #include <asm/mwait.h>
67 #include <asm/apic.h>
68 #include <asm/io_apic.h>
69 #include <asm/i387.h>
70 #include <asm/fpu-internal.h>
71 #include <asm/setup.h>
72 #include <asm/uv/uv.h>
73 #include <linux/mc146818rtc.h>
74
75 #include <asm/smpboot_hooks.h>
76 #include <asm/i8259.h>
77
78 /* State of each CPU */
79 DEFINE_PER_CPU(int, cpu_state) = { 0 };
80
81 /* Store all idle threads, this can be reused instead of creating
82 * a new thread. Also avoids complicated thread destroy functionality
83 * for idle threads.
84 */
85 #ifdef CONFIG_HOTPLUG_CPU
86 /*
87 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
88 * removed after init for !CONFIG_HOTPLUG_CPU.
89 */
90 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
91 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
92 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
93
94 /*
95 * We need this for trampoline_base protection from concurrent accesses when
96 * off- and onlining cores wildly.
97 */
98 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
99
cpu_hotplug_driver_lock(void)100 void cpu_hotplug_driver_lock(void)
101 {
102 mutex_lock(&x86_cpu_hotplug_driver_mutex);
103 }
104
cpu_hotplug_driver_unlock(void)105 void cpu_hotplug_driver_unlock(void)
106 {
107 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
108 }
109
arch_cpu_probe(const char * buf,size_t count)110 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
arch_cpu_release(const char * buf,size_t count)111 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
112 #else
113 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
114 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
115 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
116 #endif
117
118 /* Number of siblings per CPU package */
119 int smp_num_siblings = 1;
120 EXPORT_SYMBOL(smp_num_siblings);
121
122 /* Last level cache ID of each logical CPU */
123 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
124
125 /* representing HT siblings of each logical CPU */
126 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
127 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
128
129 /* representing HT and core siblings of each logical CPU */
130 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
131 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
132
133 DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
134
135 /* Per CPU bogomips and other parameters */
136 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
137 EXPORT_PER_CPU_SYMBOL(cpu_info);
138
139 atomic_t init_deasserted;
140
141 /*
142 * Report back to the Boot Processor.
143 * Running on AP.
144 */
smp_callin(void)145 static void __cpuinit smp_callin(void)
146 {
147 int cpuid, phys_id;
148 unsigned long timeout;
149
150 /*
151 * If waken up by an INIT in an 82489DX configuration
152 * we may get here before an INIT-deassert IPI reaches
153 * our local APIC. We have to wait for the IPI or we'll
154 * lock up on an APIC access.
155 */
156 if (apic->wait_for_init_deassert)
157 apic->wait_for_init_deassert(&init_deasserted);
158
159 /*
160 * (This works even if the APIC is not enabled.)
161 */
162 phys_id = read_apic_id();
163 cpuid = smp_processor_id();
164 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
165 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
166 phys_id, cpuid);
167 }
168 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
169
170 /*
171 * STARTUP IPIs are fragile beasts as they might sometimes
172 * trigger some glue motherboard logic. Complete APIC bus
173 * silence for 1 second, this overestimates the time the
174 * boot CPU is spending to send the up to 2 STARTUP IPIs
175 * by a factor of two. This should be enough.
176 */
177
178 /*
179 * Waiting 2s total for startup (udelay is not yet working)
180 */
181 timeout = jiffies + 2*HZ;
182 while (time_before(jiffies, timeout)) {
183 /*
184 * Has the boot CPU finished it's STARTUP sequence?
185 */
186 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
187 break;
188 cpu_relax();
189 }
190
191 if (!time_before(jiffies, timeout)) {
192 panic("%s: CPU%d started up but did not get a callout!\n",
193 __func__, cpuid);
194 }
195
196 /*
197 * the boot CPU has finished the init stage and is spinning
198 * on callin_map until we finish. We are free to set up this
199 * CPU, first the APIC. (this is probably redundant on most
200 * boards)
201 */
202
203 pr_debug("CALLIN, before setup_local_APIC().\n");
204 if (apic->smp_callin_clear_local_apic)
205 apic->smp_callin_clear_local_apic();
206 setup_local_APIC();
207 end_local_APIC_setup();
208
209 /*
210 * Need to setup vector mappings before we enable interrupts.
211 */
212 setup_vector_irq(smp_processor_id());
213
214 /*
215 * Save our processor parameters. Note: this information
216 * is needed for clock calibration.
217 */
218 smp_store_cpu_info(cpuid);
219
220 /*
221 * Get our bogomips.
222 * Update loops_per_jiffy in cpu_data. Previous call to
223 * smp_store_cpu_info() stored a value that is close but not as
224 * accurate as the value just calculated.
225 */
226 calibrate_delay();
227 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
228 pr_debug("Stack at about %p\n", &cpuid);
229
230 /*
231 * This must be done before setting cpu_online_mask
232 * or calling notify_cpu_starting.
233 */
234 set_cpu_sibling_map(raw_smp_processor_id());
235 wmb();
236
237 notify_cpu_starting(cpuid);
238
239 /*
240 * Allow the master to continue.
241 */
242 cpumask_set_cpu(cpuid, cpu_callin_mask);
243 }
244
245 /*
246 * Activate a secondary processor.
247 */
start_secondary(void * unused)248 notrace static void __cpuinit start_secondary(void *unused)
249 {
250 /*
251 * Don't put *anything* before cpu_init(), SMP booting is too
252 * fragile that we want to limit the things done here to the
253 * most necessary things.
254 */
255 cpu_init();
256 x86_cpuinit.early_percpu_clock_init();
257 preempt_disable();
258 smp_callin();
259
260 #ifdef CONFIG_X86_32
261 /* switch away from the initial page table */
262 load_cr3(swapper_pg_dir);
263 __flush_tlb_all();
264 #endif
265
266 /* otherwise gcc will move up smp_processor_id before the cpu_init */
267 barrier();
268 /*
269 * Check TSC synchronization with the BP:
270 */
271 check_tsc_sync_target();
272
273 /*
274 * We need to hold call_lock, so there is no inconsistency
275 * between the time smp_call_function() determines number of
276 * IPI recipients, and the time when the determination is made
277 * for which cpus receive the IPI. Holding this
278 * lock helps us to not include this cpu in a currently in progress
279 * smp_call_function().
280 *
281 * We need to hold vector_lock so there the set of online cpus
282 * does not change while we are assigning vectors to cpus. Holding
283 * this lock ensures we don't half assign or remove an irq from a cpu.
284 */
285 ipi_call_lock();
286 lock_vector_lock();
287 set_cpu_online(smp_processor_id(), true);
288 unlock_vector_lock();
289 ipi_call_unlock();
290 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
291 x86_platform.nmi_init();
292
293 /* enable local interrupts */
294 local_irq_enable();
295
296 /* to prevent fake stack check failure in clock setup */
297 boot_init_stack_canary();
298
299 x86_cpuinit.setup_percpu_clockev();
300
301 wmb();
302 cpu_idle();
303 }
304
305 /*
306 * The bootstrap kernel entry code has set these up. Save them for
307 * a given CPU
308 */
309
smp_store_cpu_info(int id)310 void __cpuinit smp_store_cpu_info(int id)
311 {
312 struct cpuinfo_x86 *c = &cpu_data(id);
313
314 *c = boot_cpu_data;
315 c->cpu_index = id;
316 if (id != 0)
317 identify_secondary_cpu(c);
318 }
319
link_thread_siblings(int cpu1,int cpu2)320 static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
321 {
322 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
323 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
324 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
325 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
326 cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2));
327 cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1));
328 }
329
330
set_cpu_sibling_map(int cpu)331 void __cpuinit set_cpu_sibling_map(int cpu)
332 {
333 int i;
334 struct cpuinfo_x86 *c = &cpu_data(cpu);
335
336 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
337
338 if (smp_num_siblings > 1) {
339 for_each_cpu(i, cpu_sibling_setup_mask) {
340 struct cpuinfo_x86 *o = &cpu_data(i);
341
342 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
343 if (c->phys_proc_id == o->phys_proc_id &&
344 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) &&
345 c->compute_unit_id == o->compute_unit_id)
346 link_thread_siblings(cpu, i);
347 } else if (c->phys_proc_id == o->phys_proc_id &&
348 c->cpu_core_id == o->cpu_core_id) {
349 link_thread_siblings(cpu, i);
350 }
351 }
352 } else {
353 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
354 }
355
356 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
357
358 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) {
359 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
360 c->booted_cores = 1;
361 return;
362 }
363
364 for_each_cpu(i, cpu_sibling_setup_mask) {
365 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
366 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
367 cpumask_set_cpu(i, cpu_llc_shared_mask(cpu));
368 cpumask_set_cpu(cpu, cpu_llc_shared_mask(i));
369 }
370 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
371 cpumask_set_cpu(i, cpu_core_mask(cpu));
372 cpumask_set_cpu(cpu, cpu_core_mask(i));
373 /*
374 * Does this new cpu bringup a new core?
375 */
376 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
377 /*
378 * for each core in package, increment
379 * the booted_cores for this new cpu
380 */
381 if (cpumask_first(cpu_sibling_mask(i)) == i)
382 c->booted_cores++;
383 /*
384 * increment the core count for all
385 * the other cpus in this package
386 */
387 if (i != cpu)
388 cpu_data(i).booted_cores++;
389 } else if (i != cpu && !c->booted_cores)
390 c->booted_cores = cpu_data(i).booted_cores;
391 }
392 }
393 }
394
395 /* maps the cpu to the sched domain representing multi-core */
cpu_coregroup_mask(int cpu)396 const struct cpumask *cpu_coregroup_mask(int cpu)
397 {
398 struct cpuinfo_x86 *c = &cpu_data(cpu);
399 /*
400 * For perf, we return last level cache shared map.
401 * And for power savings, we return cpu_core_map
402 */
403 if ((sched_mc_power_savings || sched_smt_power_savings) &&
404 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
405 return cpu_core_mask(cpu);
406 else
407 return cpu_llc_shared_mask(cpu);
408 }
409
impress_friends(void)410 static void impress_friends(void)
411 {
412 int cpu;
413 unsigned long bogosum = 0;
414 /*
415 * Allow the user to impress friends.
416 */
417 pr_debug("Before bogomips.\n");
418 for_each_possible_cpu(cpu)
419 if (cpumask_test_cpu(cpu, cpu_callout_mask))
420 bogosum += cpu_data(cpu).loops_per_jiffy;
421 printk(KERN_INFO
422 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
423 num_online_cpus(),
424 bogosum/(500000/HZ),
425 (bogosum/(5000/HZ))%100);
426
427 pr_debug("Before bogocount - setting activated=1.\n");
428 }
429
__inquire_remote_apic(int apicid)430 void __inquire_remote_apic(int apicid)
431 {
432 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
433 const char * const names[] = { "ID", "VERSION", "SPIV" };
434 int timeout;
435 u32 status;
436
437 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
438
439 for (i = 0; i < ARRAY_SIZE(regs); i++) {
440 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
441
442 /*
443 * Wait for idle.
444 */
445 status = safe_apic_wait_icr_idle();
446 if (status)
447 printk(KERN_CONT
448 "a previous APIC delivery may have failed\n");
449
450 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
451
452 timeout = 0;
453 do {
454 udelay(100);
455 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
456 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
457
458 switch (status) {
459 case APIC_ICR_RR_VALID:
460 status = apic_read(APIC_RRR);
461 printk(KERN_CONT "%08x\n", status);
462 break;
463 default:
464 printk(KERN_CONT "failed\n");
465 }
466 }
467 }
468
469 /*
470 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
471 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
472 * won't ... remember to clear down the APIC, etc later.
473 */
474 int __cpuinit
wakeup_secondary_cpu_via_nmi(int logical_apicid,unsigned long start_eip)475 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
476 {
477 unsigned long send_status, accept_status = 0;
478 int maxlvt;
479
480 /* Target chip */
481 /* Boot on the stack */
482 /* Kick the second */
483 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
484
485 pr_debug("Waiting for send to finish...\n");
486 send_status = safe_apic_wait_icr_idle();
487
488 /*
489 * Give the other CPU some time to accept the IPI.
490 */
491 udelay(200);
492 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
493 maxlvt = lapic_get_maxlvt();
494 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
495 apic_write(APIC_ESR, 0);
496 accept_status = (apic_read(APIC_ESR) & 0xEF);
497 }
498 pr_debug("NMI sent.\n");
499
500 if (send_status)
501 printk(KERN_ERR "APIC never delivered???\n");
502 if (accept_status)
503 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
504
505 return (send_status | accept_status);
506 }
507
508 static int __cpuinit
wakeup_secondary_cpu_via_init(int phys_apicid,unsigned long start_eip)509 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
510 {
511 unsigned long send_status, accept_status = 0;
512 int maxlvt, num_starts, j;
513
514 maxlvt = lapic_get_maxlvt();
515
516 /*
517 * Be paranoid about clearing APIC errors.
518 */
519 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
520 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
521 apic_write(APIC_ESR, 0);
522 apic_read(APIC_ESR);
523 }
524
525 pr_debug("Asserting INIT.\n");
526
527 /*
528 * Turn INIT on target chip
529 */
530 /*
531 * Send IPI
532 */
533 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
534 phys_apicid);
535
536 pr_debug("Waiting for send to finish...\n");
537 send_status = safe_apic_wait_icr_idle();
538
539 mdelay(10);
540
541 pr_debug("Deasserting INIT.\n");
542
543 /* Target chip */
544 /* Send IPI */
545 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
546
547 pr_debug("Waiting for send to finish...\n");
548 send_status = safe_apic_wait_icr_idle();
549
550 mb();
551 atomic_set(&init_deasserted, 1);
552
553 /*
554 * Should we send STARTUP IPIs ?
555 *
556 * Determine this based on the APIC version.
557 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
558 */
559 if (APIC_INTEGRATED(apic_version[phys_apicid]))
560 num_starts = 2;
561 else
562 num_starts = 0;
563
564 /*
565 * Paravirt / VMI wants a startup IPI hook here to set up the
566 * target processor state.
567 */
568 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
569 stack_start);
570
571 /*
572 * Run STARTUP IPI loop.
573 */
574 pr_debug("#startup loops: %d.\n", num_starts);
575
576 for (j = 1; j <= num_starts; j++) {
577 pr_debug("Sending STARTUP #%d.\n", j);
578 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
579 apic_write(APIC_ESR, 0);
580 apic_read(APIC_ESR);
581 pr_debug("After apic_write.\n");
582
583 /*
584 * STARTUP IPI
585 */
586
587 /* Target chip */
588 /* Boot on the stack */
589 /* Kick the second */
590 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
591 phys_apicid);
592
593 /*
594 * Give the other CPU some time to accept the IPI.
595 */
596 udelay(300);
597
598 pr_debug("Startup point 1.\n");
599
600 pr_debug("Waiting for send to finish...\n");
601 send_status = safe_apic_wait_icr_idle();
602
603 /*
604 * Give the other CPU some time to accept the IPI.
605 */
606 udelay(200);
607 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
608 apic_write(APIC_ESR, 0);
609 accept_status = (apic_read(APIC_ESR) & 0xEF);
610 if (send_status || accept_status)
611 break;
612 }
613 pr_debug("After Startup.\n");
614
615 if (send_status)
616 printk(KERN_ERR "APIC never delivered???\n");
617 if (accept_status)
618 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
619
620 return (send_status | accept_status);
621 }
622
623 struct create_idle {
624 struct work_struct work;
625 struct task_struct *idle;
626 struct completion done;
627 int cpu;
628 };
629
do_fork_idle(struct work_struct * work)630 static void __cpuinit do_fork_idle(struct work_struct *work)
631 {
632 struct create_idle *c_idle =
633 container_of(work, struct create_idle, work);
634
635 c_idle->idle = fork_idle(c_idle->cpu);
636 complete(&c_idle->done);
637 }
638
639 /* reduce the number of lines printed when booting a large cpu count system */
announce_cpu(int cpu,int apicid)640 static void __cpuinit announce_cpu(int cpu, int apicid)
641 {
642 static int current_node = -1;
643 int node = early_cpu_to_node(cpu);
644
645 if (system_state == SYSTEM_BOOTING) {
646 if (node != current_node) {
647 if (current_node > (-1))
648 pr_cont(" Ok.\n");
649 current_node = node;
650 pr_info("Booting Node %3d, Processors ", node);
651 }
652 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
653 return;
654 } else
655 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
656 node, cpu, apicid);
657 }
658
659 /*
660 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
661 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
662 * Returns zero if CPU booted OK, else error code from
663 * ->wakeup_secondary_cpu.
664 */
do_boot_cpu(int apicid,int cpu)665 static int __cpuinit do_boot_cpu(int apicid, int cpu)
666 {
667 unsigned long boot_error = 0;
668 unsigned long start_ip;
669 int timeout;
670 struct create_idle c_idle = {
671 .cpu = cpu,
672 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
673 };
674
675 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
676
677 alternatives_smp_switch(1);
678
679 c_idle.idle = get_idle_for_cpu(cpu);
680
681 /*
682 * We can't use kernel_thread since we must avoid to
683 * reschedule the child.
684 */
685 if (c_idle.idle) {
686 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
687 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
688 init_idle(c_idle.idle, cpu);
689 goto do_rest;
690 }
691
692 schedule_work(&c_idle.work);
693 wait_for_completion(&c_idle.done);
694
695 if (IS_ERR(c_idle.idle)) {
696 printk("failed fork for CPU %d\n", cpu);
697 destroy_work_on_stack(&c_idle.work);
698 return PTR_ERR(c_idle.idle);
699 }
700
701 set_idle_for_cpu(cpu, c_idle.idle);
702 do_rest:
703 per_cpu(current_task, cpu) = c_idle.idle;
704 #ifdef CONFIG_X86_32
705 /* Stack for startup_32 can be just as for start_secondary onwards */
706 irq_ctx_init(cpu);
707 #else
708 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
709 initial_gs = per_cpu_offset(cpu);
710 per_cpu(kernel_stack, cpu) =
711 (unsigned long)task_stack_page(c_idle.idle) -
712 KERNEL_STACK_OFFSET + THREAD_SIZE;
713 #endif
714 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
715 initial_code = (unsigned long)start_secondary;
716 stack_start = c_idle.idle->thread.sp;
717
718 /* start_ip had better be page-aligned! */
719 start_ip = trampoline_address();
720
721 /* So we see what's up */
722 announce_cpu(cpu, apicid);
723
724 /*
725 * This grunge runs the startup process for
726 * the targeted processor.
727 */
728
729 atomic_set(&init_deasserted, 0);
730
731 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
732
733 pr_debug("Setting warm reset code and vector.\n");
734
735 smpboot_setup_warm_reset_vector(start_ip);
736 /*
737 * Be paranoid about clearing APIC errors.
738 */
739 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
740 apic_write(APIC_ESR, 0);
741 apic_read(APIC_ESR);
742 }
743 }
744
745 /*
746 * Kick the secondary CPU. Use the method in the APIC driver
747 * if it's defined - or use an INIT boot APIC message otherwise:
748 */
749 if (apic->wakeup_secondary_cpu)
750 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
751 else
752 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
753
754 if (!boot_error) {
755 /*
756 * allow APs to start initializing.
757 */
758 pr_debug("Before Callout %d.\n", cpu);
759 cpumask_set_cpu(cpu, cpu_callout_mask);
760 pr_debug("After Callout %d.\n", cpu);
761
762 /*
763 * Wait 5s total for a response
764 */
765 for (timeout = 0; timeout < 50000; timeout++) {
766 if (cpumask_test_cpu(cpu, cpu_callin_mask))
767 break; /* It has booted */
768 udelay(100);
769 /*
770 * Allow other tasks to run while we wait for the
771 * AP to come online. This also gives a chance
772 * for the MTRR work(triggered by the AP coming online)
773 * to be completed in the stop machine context.
774 */
775 schedule();
776 }
777
778 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
779 print_cpu_msr(&cpu_data(cpu));
780 pr_debug("CPU%d: has booted.\n", cpu);
781 } else {
782 boot_error = 1;
783 if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status)
784 == 0xA5A5A5A5)
785 /* trampoline started but...? */
786 pr_err("CPU%d: Stuck ??\n", cpu);
787 else
788 /* trampoline code not run */
789 pr_err("CPU%d: Not responding.\n", cpu);
790 if (apic->inquire_remote_apic)
791 apic->inquire_remote_apic(apicid);
792 }
793 }
794
795 if (boot_error) {
796 /* Try to put things back the way they were before ... */
797 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
798
799 /* was set by do_boot_cpu() */
800 cpumask_clear_cpu(cpu, cpu_callout_mask);
801
802 /* was set by cpu_init() */
803 cpumask_clear_cpu(cpu, cpu_initialized_mask);
804
805 set_cpu_present(cpu, false);
806 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
807 }
808
809 /* mark "stuck" area as not stuck */
810 *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0;
811
812 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
813 /*
814 * Cleanup possible dangling ends...
815 */
816 smpboot_restore_warm_reset_vector();
817 }
818
819 destroy_work_on_stack(&c_idle.work);
820 return boot_error;
821 }
822
native_cpu_up(unsigned int cpu)823 int __cpuinit native_cpu_up(unsigned int cpu)
824 {
825 int apicid = apic->cpu_present_to_apicid(cpu);
826 unsigned long flags;
827 int err;
828
829 WARN_ON(irqs_disabled());
830
831 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
832
833 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
834 !physid_isset(apicid, phys_cpu_present_map) ||
835 !apic->apic_id_valid(apicid)) {
836 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
837 return -EINVAL;
838 }
839
840 /*
841 * Already booted CPU?
842 */
843 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
844 pr_debug("do_boot_cpu %d Already started\n", cpu);
845 return -ENOSYS;
846 }
847
848 /*
849 * Save current MTRR state in case it was changed since early boot
850 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
851 */
852 mtrr_save_state();
853
854 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
855
856 /* the FPU context is blank, nobody can own it */
857 __cpu_disable_lazy_restore(cpu);
858
859 err = do_boot_cpu(apicid, cpu);
860 if (err) {
861 pr_debug("do_boot_cpu failed %d\n", err);
862 return -EIO;
863 }
864
865 /*
866 * Check TSC synchronization with the AP (keep irqs disabled
867 * while doing so):
868 */
869 local_irq_save(flags);
870 check_tsc_sync_source(cpu);
871 local_irq_restore(flags);
872
873 while (!cpu_online(cpu)) {
874 cpu_relax();
875 touch_nmi_watchdog();
876 }
877
878 return 0;
879 }
880
881 /**
882 * arch_disable_smp_support() - disables SMP support for x86 at runtime
883 */
arch_disable_smp_support(void)884 void arch_disable_smp_support(void)
885 {
886 disable_ioapic_support();
887 }
888
889 /*
890 * Fall back to non SMP mode after errors.
891 *
892 * RED-PEN audit/test this more. I bet there is more state messed up here.
893 */
disable_smp(void)894 static __init void disable_smp(void)
895 {
896 init_cpu_present(cpumask_of(0));
897 init_cpu_possible(cpumask_of(0));
898 smpboot_clear_io_apic_irqs();
899
900 if (smp_found_config)
901 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
902 else
903 physid_set_mask_of_physid(0, &phys_cpu_present_map);
904 cpumask_set_cpu(0, cpu_sibling_mask(0));
905 cpumask_set_cpu(0, cpu_core_mask(0));
906 }
907
908 /*
909 * Various sanity checks.
910 */
smp_sanity_check(unsigned max_cpus)911 static int __init smp_sanity_check(unsigned max_cpus)
912 {
913 preempt_disable();
914
915 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
916 if (def_to_bigsmp && nr_cpu_ids > 8) {
917 unsigned int cpu;
918 unsigned nr;
919
920 printk(KERN_WARNING
921 "More than 8 CPUs detected - skipping them.\n"
922 "Use CONFIG_X86_BIGSMP.\n");
923
924 nr = 0;
925 for_each_present_cpu(cpu) {
926 if (nr >= 8)
927 set_cpu_present(cpu, false);
928 nr++;
929 }
930
931 nr = 0;
932 for_each_possible_cpu(cpu) {
933 if (nr >= 8)
934 set_cpu_possible(cpu, false);
935 nr++;
936 }
937
938 nr_cpu_ids = 8;
939 }
940 #endif
941
942 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
943 printk(KERN_WARNING
944 "weird, boot CPU (#%d) not listed by the BIOS.\n",
945 hard_smp_processor_id());
946
947 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
948 }
949
950 /*
951 * If we couldn't find an SMP configuration at boot time,
952 * get out of here now!
953 */
954 if (!smp_found_config && !acpi_lapic) {
955 preempt_enable();
956 printk(KERN_NOTICE "SMP motherboard not detected.\n");
957 disable_smp();
958 if (APIC_init_uniprocessor())
959 printk(KERN_NOTICE "Local APIC not detected."
960 " Using dummy APIC emulation.\n");
961 return -1;
962 }
963
964 /*
965 * Should not be necessary because the MP table should list the boot
966 * CPU too, but we do it for the sake of robustness anyway.
967 */
968 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
969 printk(KERN_NOTICE
970 "weird, boot CPU (#%d) not listed by the BIOS.\n",
971 boot_cpu_physical_apicid);
972 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
973 }
974 preempt_enable();
975
976 /*
977 * If we couldn't find a local APIC, then get out of here now!
978 */
979 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
980 !cpu_has_apic) {
981 if (!disable_apic) {
982 pr_err("BIOS bug, local APIC #%d not detected!...\n",
983 boot_cpu_physical_apicid);
984 pr_err("... forcing use of dummy APIC emulation."
985 "(tell your hw vendor)\n");
986 }
987 smpboot_clear_io_apic();
988 disable_ioapic_support();
989 return -1;
990 }
991
992 verify_local_APIC();
993
994 /*
995 * If SMP should be disabled, then really disable it!
996 */
997 if (!max_cpus) {
998 printk(KERN_INFO "SMP mode deactivated.\n");
999 smpboot_clear_io_apic();
1000
1001 connect_bsp_APIC();
1002 setup_local_APIC();
1003 bsp_end_local_APIC_setup();
1004 return -1;
1005 }
1006
1007 return 0;
1008 }
1009
smp_cpu_index_default(void)1010 static void __init smp_cpu_index_default(void)
1011 {
1012 int i;
1013 struct cpuinfo_x86 *c;
1014
1015 for_each_possible_cpu(i) {
1016 c = &cpu_data(i);
1017 /* mark all to hotplug */
1018 c->cpu_index = nr_cpu_ids;
1019 }
1020 }
1021
1022 /*
1023 * Prepare for SMP bootup. The MP table or ACPI has been read
1024 * earlier. Just do some sanity checking here and enable APIC mode.
1025 */
native_smp_prepare_cpus(unsigned int max_cpus)1026 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1027 {
1028 unsigned int i;
1029
1030 preempt_disable();
1031 smp_cpu_index_default();
1032
1033 /*
1034 * Setup boot CPU information
1035 */
1036 smp_store_cpu_info(0); /* Final full version of the data */
1037 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1038 mb();
1039
1040 current_thread_info()->cpu = 0; /* needed? */
1041 for_each_possible_cpu(i) {
1042 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1043 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1044 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1045 }
1046 set_cpu_sibling_map(0);
1047
1048
1049 if (smp_sanity_check(max_cpus) < 0) {
1050 printk(KERN_INFO "SMP disabled\n");
1051 disable_smp();
1052 goto out;
1053 }
1054
1055 default_setup_apic_routing();
1056
1057 preempt_disable();
1058 if (read_apic_id() != boot_cpu_physical_apicid) {
1059 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1060 read_apic_id(), boot_cpu_physical_apicid);
1061 /* Or can we switch back to PIC here? */
1062 }
1063 preempt_enable();
1064
1065 connect_bsp_APIC();
1066
1067 /*
1068 * Switch from PIC to APIC mode.
1069 */
1070 setup_local_APIC();
1071
1072 /*
1073 * Enable IO APIC before setting up error vector
1074 */
1075 if (!skip_ioapic_setup && nr_ioapics)
1076 enable_IO_APIC();
1077
1078 bsp_end_local_APIC_setup();
1079
1080 if (apic->setup_portio_remap)
1081 apic->setup_portio_remap();
1082
1083 smpboot_setup_io_apic();
1084 /*
1085 * Set up local APIC timer on boot CPU.
1086 */
1087
1088 printk(KERN_INFO "CPU%d: ", 0);
1089 print_cpu_info(&cpu_data(0));
1090 x86_init.timers.setup_percpu_clockev();
1091
1092 if (is_uv_system())
1093 uv_system_init();
1094
1095 set_mtrr_aps_delayed_init();
1096 out:
1097 preempt_enable();
1098 }
1099
arch_disable_nonboot_cpus_begin(void)1100 void arch_disable_nonboot_cpus_begin(void)
1101 {
1102 /*
1103 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1104 * In the suspend path, we will be back in the SMP mode shortly anyways.
1105 */
1106 skip_smp_alternatives = true;
1107 }
1108
arch_disable_nonboot_cpus_end(void)1109 void arch_disable_nonboot_cpus_end(void)
1110 {
1111 skip_smp_alternatives = false;
1112 }
1113
arch_enable_nonboot_cpus_begin(void)1114 void arch_enable_nonboot_cpus_begin(void)
1115 {
1116 set_mtrr_aps_delayed_init();
1117 }
1118
arch_enable_nonboot_cpus_end(void)1119 void arch_enable_nonboot_cpus_end(void)
1120 {
1121 mtrr_aps_init();
1122 }
1123
1124 /*
1125 * Early setup to make printk work.
1126 */
native_smp_prepare_boot_cpu(void)1127 void __init native_smp_prepare_boot_cpu(void)
1128 {
1129 int me = smp_processor_id();
1130 switch_to_new_gdt(me);
1131 /* already set me in cpu_online_mask in boot_cpu_init() */
1132 cpumask_set_cpu(me, cpu_callout_mask);
1133 per_cpu(cpu_state, me) = CPU_ONLINE;
1134 }
1135
native_smp_cpus_done(unsigned int max_cpus)1136 void __init native_smp_cpus_done(unsigned int max_cpus)
1137 {
1138 pr_debug("Boot done.\n");
1139
1140 nmi_selftest();
1141 impress_friends();
1142 #ifdef CONFIG_X86_IO_APIC
1143 setup_ioapic_dest();
1144 #endif
1145 mtrr_aps_init();
1146 }
1147
1148 static int __initdata setup_possible_cpus = -1;
_setup_possible_cpus(char * str)1149 static int __init _setup_possible_cpus(char *str)
1150 {
1151 get_option(&str, &setup_possible_cpus);
1152 return 0;
1153 }
1154 early_param("possible_cpus", _setup_possible_cpus);
1155
1156
1157 /*
1158 * cpu_possible_mask should be static, it cannot change as cpu's
1159 * are onlined, or offlined. The reason is per-cpu data-structures
1160 * are allocated by some modules at init time, and dont expect to
1161 * do this dynamically on cpu arrival/departure.
1162 * cpu_present_mask on the other hand can change dynamically.
1163 * In case when cpu_hotplug is not compiled, then we resort to current
1164 * behaviour, which is cpu_possible == cpu_present.
1165 * - Ashok Raj
1166 *
1167 * Three ways to find out the number of additional hotplug CPUs:
1168 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1169 * - The user can overwrite it with possible_cpus=NUM
1170 * - Otherwise don't reserve additional CPUs.
1171 * We do this because additional CPUs waste a lot of memory.
1172 * -AK
1173 */
prefill_possible_map(void)1174 __init void prefill_possible_map(void)
1175 {
1176 int i, possible;
1177
1178 /* no processor from mptable or madt */
1179 if (!num_processors)
1180 num_processors = 1;
1181
1182 i = setup_max_cpus ?: 1;
1183 if (setup_possible_cpus == -1) {
1184 possible = num_processors;
1185 #ifdef CONFIG_HOTPLUG_CPU
1186 if (setup_max_cpus)
1187 possible += disabled_cpus;
1188 #else
1189 if (possible > i)
1190 possible = i;
1191 #endif
1192 } else
1193 possible = setup_possible_cpus;
1194
1195 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1196
1197 /* nr_cpu_ids could be reduced via nr_cpus= */
1198 if (possible > nr_cpu_ids) {
1199 printk(KERN_WARNING
1200 "%d Processors exceeds NR_CPUS limit of %d\n",
1201 possible, nr_cpu_ids);
1202 possible = nr_cpu_ids;
1203 }
1204
1205 #ifdef CONFIG_HOTPLUG_CPU
1206 if (!setup_max_cpus)
1207 #endif
1208 if (possible > i) {
1209 printk(KERN_WARNING
1210 "%d Processors exceeds max_cpus limit of %u\n",
1211 possible, setup_max_cpus);
1212 possible = i;
1213 }
1214
1215 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1216 possible, max_t(int, possible - num_processors, 0));
1217
1218 for (i = 0; i < possible; i++)
1219 set_cpu_possible(i, true);
1220 for (; i < NR_CPUS; i++)
1221 set_cpu_possible(i, false);
1222
1223 nr_cpu_ids = possible;
1224 }
1225
1226 #ifdef CONFIG_HOTPLUG_CPU
1227
remove_siblinginfo(int cpu)1228 static void remove_siblinginfo(int cpu)
1229 {
1230 int sibling;
1231 struct cpuinfo_x86 *c = &cpu_data(cpu);
1232
1233 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1234 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1235 /*/
1236 * last thread sibling in this cpu core going down
1237 */
1238 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1239 cpu_data(sibling).booted_cores--;
1240 }
1241
1242 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1243 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1244 cpumask_clear(cpu_sibling_mask(cpu));
1245 cpumask_clear(cpu_core_mask(cpu));
1246 c->phys_proc_id = 0;
1247 c->cpu_core_id = 0;
1248 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1249 }
1250
remove_cpu_from_maps(int cpu)1251 static void __ref remove_cpu_from_maps(int cpu)
1252 {
1253 set_cpu_online(cpu, false);
1254 cpumask_clear_cpu(cpu, cpu_callout_mask);
1255 cpumask_clear_cpu(cpu, cpu_callin_mask);
1256 /* was set by cpu_init() */
1257 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1258 numa_remove_cpu(cpu);
1259 }
1260
cpu_disable_common(void)1261 void cpu_disable_common(void)
1262 {
1263 int cpu = smp_processor_id();
1264
1265 remove_siblinginfo(cpu);
1266
1267 /* It's now safe to remove this processor from the online map */
1268 lock_vector_lock();
1269 remove_cpu_from_maps(cpu);
1270 unlock_vector_lock();
1271 fixup_irqs();
1272 }
1273
native_cpu_disable(void)1274 int native_cpu_disable(void)
1275 {
1276 int cpu = smp_processor_id();
1277
1278 /*
1279 * Perhaps use cpufreq to drop frequency, but that could go
1280 * into generic code.
1281 *
1282 * We won't take down the boot processor on i386 due to some
1283 * interrupts only being able to be serviced by the BSP.
1284 * Especially so if we're not using an IOAPIC -zwane
1285 */
1286 if (cpu == 0)
1287 return -EBUSY;
1288
1289 clear_local_APIC();
1290
1291 cpu_disable_common();
1292 return 0;
1293 }
1294
native_cpu_die(unsigned int cpu)1295 void native_cpu_die(unsigned int cpu)
1296 {
1297 /* We don't do anything here: idle task is faking death itself. */
1298 unsigned int i;
1299
1300 for (i = 0; i < 10; i++) {
1301 /* They ack this in play_dead by setting CPU_DEAD */
1302 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1303 if (system_state == SYSTEM_RUNNING)
1304 pr_info("CPU %u is now offline\n", cpu);
1305
1306 if (1 == num_online_cpus())
1307 alternatives_smp_switch(0);
1308 return;
1309 }
1310 msleep(100);
1311 }
1312 pr_err("CPU %u didn't die...\n", cpu);
1313 }
1314
play_dead_common(void)1315 void play_dead_common(void)
1316 {
1317 idle_task_exit();
1318 reset_lazy_tlbstate();
1319 amd_e400_remove_cpu(raw_smp_processor_id());
1320
1321 mb();
1322 /* Ack it */
1323 __this_cpu_write(cpu_state, CPU_DEAD);
1324
1325 /*
1326 * With physical CPU hotplug, we should halt the cpu
1327 */
1328 local_irq_disable();
1329 }
1330
1331 /*
1332 * We need to flush the caches before going to sleep, lest we have
1333 * dirty data in our caches when we come back up.
1334 */
mwait_play_dead(void)1335 static inline void mwait_play_dead(void)
1336 {
1337 unsigned int eax, ebx, ecx, edx;
1338 unsigned int highest_cstate = 0;
1339 unsigned int highest_subcstate = 0;
1340 int i;
1341 void *mwait_ptr;
1342 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1343
1344 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c)))
1345 return;
1346 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1347 return;
1348 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1349 return;
1350
1351 eax = CPUID_MWAIT_LEAF;
1352 ecx = 0;
1353 native_cpuid(&eax, &ebx, &ecx, &edx);
1354
1355 /*
1356 * eax will be 0 if EDX enumeration is not valid.
1357 * Initialized below to cstate, sub_cstate value when EDX is valid.
1358 */
1359 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1360 eax = 0;
1361 } else {
1362 edx >>= MWAIT_SUBSTATE_SIZE;
1363 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1364 if (edx & MWAIT_SUBSTATE_MASK) {
1365 highest_cstate = i;
1366 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1367 }
1368 }
1369 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1370 (highest_subcstate - 1);
1371 }
1372
1373 /*
1374 * This should be a memory location in a cache line which is
1375 * unlikely to be touched by other processors. The actual
1376 * content is immaterial as it is not actually modified in any way.
1377 */
1378 mwait_ptr = ¤t_thread_info()->flags;
1379
1380 wbinvd();
1381
1382 while (1) {
1383 /*
1384 * The CLFLUSH is a workaround for erratum AAI65 for
1385 * the Xeon 7400 series. It's not clear it is actually
1386 * needed, but it should be harmless in either case.
1387 * The WBINVD is insufficient due to the spurious-wakeup
1388 * case where we return around the loop.
1389 */
1390 clflush(mwait_ptr);
1391 __monitor(mwait_ptr, 0, 0);
1392 mb();
1393 __mwait(eax, 0);
1394 }
1395 }
1396
hlt_play_dead(void)1397 static inline void hlt_play_dead(void)
1398 {
1399 if (__this_cpu_read(cpu_info.x86) >= 4)
1400 wbinvd();
1401
1402 while (1) {
1403 native_halt();
1404 }
1405 }
1406
native_play_dead(void)1407 void native_play_dead(void)
1408 {
1409 play_dead_common();
1410 tboot_shutdown(TB_SHUTDOWN_WFS);
1411
1412 mwait_play_dead(); /* Only returns on failure */
1413 if (cpuidle_play_dead())
1414 hlt_play_dead();
1415 }
1416
1417 #else /* ... !CONFIG_HOTPLUG_CPU */
native_cpu_disable(void)1418 int native_cpu_disable(void)
1419 {
1420 return -ENOSYS;
1421 }
1422
native_cpu_die(unsigned int cpu)1423 void native_cpu_die(unsigned int cpu)
1424 {
1425 /* We said "no" in __cpu_disable */
1426 BUG();
1427 }
1428
native_play_dead(void)1429 void native_play_dead(void)
1430 {
1431 BUG();
1432 }
1433
1434 #endif
1435