1 /*
2 * Copyright (C) 2000-2001 Deep Blue Solutions
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/clockchips.h>
26 #include <linux/clk.h>
27
28 #include <asm/mach/time.h>
29 #include <mach/mxs.h>
30 #include <mach/common.h>
31
32 /*
33 * There are 2 versions of the timrot on Freescale MXS-based SoCs.
34 * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
35 * extends the counter to 32 bits.
36 *
37 * The implementation uses two timers, one for clock_event and
38 * another for clocksource. MX28 uses timrot 0 and 1, while MX23
39 * uses 0 and 2.
40 */
41
42 #define MX23_TIMROT_VERSION_OFFSET 0x0a0
43 #define MX28_TIMROT_VERSION_OFFSET 0x120
44 #define BP_TIMROT_MAJOR_VERSION 24
45 #define BV_TIMROT_VERSION_1 0x01
46 #define BV_TIMROT_VERSION_2 0x02
47 #define timrot_is_v1() (timrot_major_version == BV_TIMROT_VERSION_1)
48
49 /*
50 * There are 4 registers for each timrotv2 instance, and 2 registers
51 * for each timrotv1. So address step 0x40 in macros below strides
52 * one instance of timrotv2 while two instances of timrotv1.
53 *
54 * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
55 * on MX28 while timrot2 on MX23.
56 */
57 /* common between v1 and v2 */
58 #define HW_TIMROT_ROTCTRL 0x00
59 #define HW_TIMROT_TIMCTRLn(n) (0x20 + (n) * 0x40)
60 /* v1 only */
61 #define HW_TIMROT_TIMCOUNTn(n) (0x30 + (n) * 0x40)
62 /* v2 only */
63 #define HW_TIMROT_RUNNING_COUNTn(n) (0x30 + (n) * 0x40)
64 #define HW_TIMROT_FIXED_COUNTn(n) (0x40 + (n) * 0x40)
65
66 #define BM_TIMROT_TIMCTRLn_RELOAD (1 << 6)
67 #define BM_TIMROT_TIMCTRLn_UPDATE (1 << 7)
68 #define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
69 #define BM_TIMROT_TIMCTRLn_IRQ (1 << 15)
70 #define BP_TIMROT_TIMCTRLn_SELECT 0
71 #define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
72 #define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
73
74 static struct clock_event_device mxs_clockevent_device;
75 static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
76
77 static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR);
78 static u32 timrot_major_version;
79
timrot_irq_disable(void)80 static inline void timrot_irq_disable(void)
81 {
82 __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
83 mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
84 }
85
timrot_irq_enable(void)86 static inline void timrot_irq_enable(void)
87 {
88 __mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
89 mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
90 }
91
timrot_irq_acknowledge(void)92 static void timrot_irq_acknowledge(void)
93 {
94 __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
95 mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
96 }
97
timrotv1_get_cycles(struct clocksource * cs)98 static cycle_t timrotv1_get_cycles(struct clocksource *cs)
99 {
100 return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
101 & 0xffff0000) >> 16);
102 }
103
timrotv2_get_cycles(struct clocksource * cs)104 static cycle_t timrotv2_get_cycles(struct clocksource *cs)
105 {
106 return ~__raw_readl(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
107 }
108
timrotv1_set_next_event(unsigned long evt,struct clock_event_device * dev)109 static int timrotv1_set_next_event(unsigned long evt,
110 struct clock_event_device *dev)
111 {
112 /* timrot decrements the count */
113 __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
114
115 return 0;
116 }
117
timrotv2_set_next_event(unsigned long evt,struct clock_event_device * dev)118 static int timrotv2_set_next_event(unsigned long evt,
119 struct clock_event_device *dev)
120 {
121 /* timrot decrements the count */
122 __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
123
124 return 0;
125 }
126
mxs_timer_interrupt(int irq,void * dev_id)127 static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
128 {
129 struct clock_event_device *evt = dev_id;
130
131 timrot_irq_acknowledge();
132 evt->event_handler(evt);
133
134 return IRQ_HANDLED;
135 }
136
137 static struct irqaction mxs_timer_irq = {
138 .name = "MXS Timer Tick",
139 .dev_id = &mxs_clockevent_device,
140 .flags = IRQF_TIMER | IRQF_IRQPOLL,
141 .handler = mxs_timer_interrupt,
142 };
143
144 #ifdef DEBUG
145 static const char *clock_event_mode_label[] const = {
146 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
147 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
148 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
149 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED"
150 };
151 #endif /* DEBUG */
152
mxs_set_mode(enum clock_event_mode mode,struct clock_event_device * evt)153 static void mxs_set_mode(enum clock_event_mode mode,
154 struct clock_event_device *evt)
155 {
156 /* Disable interrupt in timer module */
157 timrot_irq_disable();
158
159 if (mode != mxs_clockevent_mode) {
160 /* Set event time into the furthest future */
161 if (timrot_is_v1())
162 __raw_writel(0xffff,
163 mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
164 else
165 __raw_writel(0xffffffff,
166 mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
167
168 /* Clear pending interrupt */
169 timrot_irq_acknowledge();
170 }
171
172 #ifdef DEBUG
173 pr_info("%s: changing mode from %s to %s\n", __func__,
174 clock_event_mode_label[mxs_clockevent_mode],
175 clock_event_mode_label[mode]);
176 #endif /* DEBUG */
177
178 /* Remember timer mode */
179 mxs_clockevent_mode = mode;
180
181 switch (mode) {
182 case CLOCK_EVT_MODE_PERIODIC:
183 pr_err("%s: Periodic mode is not implemented\n", __func__);
184 break;
185 case CLOCK_EVT_MODE_ONESHOT:
186 timrot_irq_enable();
187 break;
188 case CLOCK_EVT_MODE_SHUTDOWN:
189 case CLOCK_EVT_MODE_UNUSED:
190 case CLOCK_EVT_MODE_RESUME:
191 /* Left event sources disabled, no more interrupts appear */
192 break;
193 }
194 }
195
196 static struct clock_event_device mxs_clockevent_device = {
197 .name = "mxs_timrot",
198 .features = CLOCK_EVT_FEAT_ONESHOT,
199 .shift = 32,
200 .set_mode = mxs_set_mode,
201 .set_next_event = timrotv2_set_next_event,
202 .rating = 200,
203 };
204
mxs_clockevent_init(struct clk * timer_clk)205 static int __init mxs_clockevent_init(struct clk *timer_clk)
206 {
207 unsigned int c = clk_get_rate(timer_clk);
208
209 mxs_clockevent_device.mult =
210 div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift);
211 mxs_clockevent_device.cpumask = cpumask_of(0);
212 if (timrot_is_v1()) {
213 mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
214 mxs_clockevent_device.max_delta_ns =
215 clockevent_delta2ns(0xfffe, &mxs_clockevent_device);
216 mxs_clockevent_device.min_delta_ns =
217 clockevent_delta2ns(0xf, &mxs_clockevent_device);
218 } else {
219 mxs_clockevent_device.max_delta_ns =
220 clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device);
221 mxs_clockevent_device.min_delta_ns =
222 clockevent_delta2ns(0xf, &mxs_clockevent_device);
223 }
224
225 clockevents_register_device(&mxs_clockevent_device);
226
227 return 0;
228 }
229
230 static struct clocksource clocksource_mxs = {
231 .name = "mxs_timer",
232 .rating = 200,
233 .read = timrotv2_get_cycles,
234 .mask = CLOCKSOURCE_MASK(32),
235 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
236 };
237
mxs_clocksource_init(struct clk * timer_clk)238 static int __init mxs_clocksource_init(struct clk *timer_clk)
239 {
240 unsigned int c = clk_get_rate(timer_clk);
241
242 if (timrot_is_v1()) {
243 clocksource_mxs.read = timrotv1_get_cycles;
244 clocksource_mxs.mask = CLOCKSOURCE_MASK(16);
245 }
246
247 clocksource_register_hz(&clocksource_mxs, c);
248
249 return 0;
250 }
251
mxs_timer_init(struct clk * timer_clk,int irq)252 void __init mxs_timer_init(struct clk *timer_clk, int irq)
253 {
254 clk_enable(timer_clk);
255
256 /*
257 * Initialize timers to a known state
258 */
259 mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
260
261 /* get timrot version */
262 timrot_major_version = __raw_readl(mxs_timrot_base +
263 (cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
264 MX28_TIMROT_VERSION_OFFSET));
265 timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
266
267 /* one for clock_event */
268 __raw_writel((timrot_is_v1() ?
269 BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
270 BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
271 BM_TIMROT_TIMCTRLn_UPDATE |
272 BM_TIMROT_TIMCTRLn_IRQ_EN,
273 mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
274
275 /* another for clocksource */
276 __raw_writel((timrot_is_v1() ?
277 BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
278 BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
279 BM_TIMROT_TIMCTRLn_RELOAD,
280 mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
281
282 /* set clocksource timer fixed count to the maximum */
283 if (timrot_is_v1())
284 __raw_writel(0xffff,
285 mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
286 else
287 __raw_writel(0xffffffff,
288 mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
289
290 /* init and register the timer to the framework */
291 mxs_clocksource_init(timer_clk);
292 mxs_clockevent_init(timer_clk);
293
294 /* Make irqs happen */
295 setup_irq(irq, &mxs_timer_irq);
296 }
297