1 /*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18 #include <asm/sizes.h>
19 #include <mach/mx23.h>
20 #include <mach/mx28.h>
21 #include <mach/devices-common.h>
22 #include <linux/dma-mapping.h>
23
24 #ifdef CONFIG_SOC_IMX23
25 const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst = {
26 .devid = "imx23-gpmi-nand",
27 .res = {
28 /* GPMI */
29 DEFINE_RES_MEM_NAMED(MX23_GPMI_BASE_ADDR, SZ_8K,
30 GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
31 DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_ATTENTION,
32 GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
33 /* BCH */
34 DEFINE_RES_MEM_NAMED(MX23_BCH_BASE_ADDR, SZ_8K,
35 GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
36 DEFINE_RES_IRQ_NAMED(MX23_INT_BCH,
37 GPMI_NAND_BCH_INTERRUPT_RES_NAME),
38 /* DMA */
39 DEFINE_RES_NAMED(MX23_DMA_GPMI0,
40 MX23_DMA_GPMI3 - MX23_DMA_GPMI0 + 1,
41 GPMI_NAND_DMA_CHANNELS_RES_NAME,
42 IORESOURCE_DMA),
43 DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_DMA,
44 GPMI_NAND_DMA_INTERRUPT_RES_NAME),
45 },
46 };
47 #endif
48
49 #ifdef CONFIG_SOC_IMX28
50 const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst = {
51 .devid = "imx28-gpmi-nand",
52 .res = {
53 /* GPMI */
54 DEFINE_RES_MEM_NAMED(MX28_GPMI_BASE_ADDR, SZ_8K,
55 GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
56 DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI,
57 GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
58 /* BCH */
59 DEFINE_RES_MEM_NAMED(MX28_BCH_BASE_ADDR, SZ_8K,
60 GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
61 DEFINE_RES_IRQ_NAMED(MX28_INT_BCH,
62 GPMI_NAND_BCH_INTERRUPT_RES_NAME),
63 /* DMA */
64 DEFINE_RES_NAMED(MX28_DMA_GPMI0,
65 MX28_DMA_GPMI7 - MX28_DMA_GPMI0 + 1,
66 GPMI_NAND_DMA_CHANNELS_RES_NAME,
67 IORESOURCE_DMA),
68 DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI_DMA,
69 GPMI_NAND_DMA_INTERRUPT_RES_NAME),
70 },
71 };
72 #endif
73
74 struct platform_device *__init
mxs_add_gpmi_nand(const struct gpmi_nand_platform_data * pdata,const struct mxs_gpmi_nand_data * data)75 mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata,
76 const struct mxs_gpmi_nand_data *data)
77 {
78 return mxs_add_platform_device_dmamask(data->devid, -1,
79 data->res, GPMI_NAND_RES_SIZE,
80 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
81 }
82