1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Marvell 88E6xxx Switch Global (1) Registers support
4  *
5  * Copyright (c) 2008 Marvell Semiconductor
6  *
7  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9  */
10 
11 #include <linux/bitfield.h>
12 
13 #include "chip.h"
14 #include "global1.h"
15 
mv88e6xxx_g1_read(struct mv88e6xxx_chip * chip,int reg,u16 * val)16 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
17 {
18 	int addr = chip->info->global1_addr;
19 
20 	return mv88e6xxx_read(chip, addr, reg, val);
21 }
22 
mv88e6xxx_g1_write(struct mv88e6xxx_chip * chip,int reg,u16 val)23 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
24 {
25 	int addr = chip->info->global1_addr;
26 
27 	return mv88e6xxx_write(chip, addr, reg, val);
28 }
29 
mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip * chip,int reg,int bit,int val)30 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
31 			  bit, int val)
32 {
33 	return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg,
34 				  bit, val);
35 }
36 
mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip * chip,int reg,u16 mask,u16 val)37 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
38 			   u16 mask, u16 val)
39 {
40 	return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg,
41 				   mask, val);
42 }
43 
44 /* Offset 0x00: Switch Global Status Register */
45 
mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip * chip)46 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
47 {
48 	return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
49 				      MV88E6185_G1_STS_PPU_STATE_MASK,
50 				      MV88E6185_G1_STS_PPU_STATE_DISABLED);
51 }
52 
mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip * chip)53 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
54 {
55 	return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
56 				      MV88E6185_G1_STS_PPU_STATE_MASK,
57 				      MV88E6185_G1_STS_PPU_STATE_POLLING);
58 }
59 
mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip * chip)60 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
61 {
62 	int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE);
63 
64 	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
65 }
66 
mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip * chip)67 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
68 {
69 	int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY);
70 
71 	/* Wait up to 1 second for the switch to be ready. The InitReady bit 11
72 	 * is set to a one when all units inside the device (ATU, VTU, etc.)
73 	 * have finished their initialization and are ready to accept frames.
74 	 */
75 	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
76 }
77 
78 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
79  * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
80  * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
81  */
mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip * chip,u8 * addr)82 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
83 {
84 	u16 reg;
85 	int err;
86 
87 	reg = (addr[0] << 8) | addr[1];
88 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
89 	if (err)
90 		return err;
91 
92 	reg = (addr[2] << 8) | addr[3];
93 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
94 	if (err)
95 		return err;
96 
97 	reg = (addr[4] << 8) | addr[5];
98 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
99 	if (err)
100 		return err;
101 
102 	return 0;
103 }
104 
105 /* Offset 0x04: Switch Global Control Register */
106 
mv88e6185_g1_reset(struct mv88e6xxx_chip * chip)107 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
108 {
109 	u16 val;
110 	int err;
111 
112 	/* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
113 	 * the PPU, including re-doing PHY detection and initialization
114 	 */
115 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
116 	if (err)
117 		return err;
118 
119 	val |= MV88E6XXX_G1_CTL1_SW_RESET;
120 	val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
121 
122 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
123 	if (err)
124 		return err;
125 
126 	err = mv88e6xxx_g1_wait_init_ready(chip);
127 	if (err)
128 		return err;
129 
130 	return mv88e6185_g1_wait_ppu_polling(chip);
131 }
132 
mv88e6250_g1_reset(struct mv88e6xxx_chip * chip)133 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip)
134 {
135 	u16 val;
136 	int err;
137 
138 	/* Set the SWReset bit 15 */
139 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
140 	if (err)
141 		return err;
142 
143 	val |= MV88E6XXX_G1_CTL1_SW_RESET;
144 
145 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
146 	if (err)
147 		return err;
148 
149 	return mv88e6xxx_g1_wait_init_ready(chip);
150 }
151 
mv88e6352_g1_reset(struct mv88e6xxx_chip * chip)152 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
153 {
154 	int err;
155 
156 	err = mv88e6250_g1_reset(chip);
157 	if (err)
158 		return err;
159 
160 	return mv88e6352_g1_wait_ppu_polling(chip);
161 }
162 
mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip * chip)163 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
164 {
165 	u16 val;
166 	int err;
167 
168 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
169 	if (err)
170 		return err;
171 
172 	val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
173 
174 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
175 	if (err)
176 		return err;
177 
178 	return mv88e6185_g1_wait_ppu_polling(chip);
179 }
180 
mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip * chip)181 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
182 {
183 	u16 val;
184 	int err;
185 
186 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
187 	if (err)
188 		return err;
189 
190 	val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
191 
192 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
193 	if (err)
194 		return err;
195 
196 	return mv88e6185_g1_wait_ppu_disabled(chip);
197 }
198 
mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip * chip,int mtu)199 int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu)
200 {
201 	u16 val;
202 	int err;
203 
204 	mtu += ETH_HLEN + ETH_FCS_LEN;
205 
206 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
207 	if (err)
208 		return err;
209 
210 	val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632;
211 
212 	if (mtu > 1518)
213 		val |= MV88E6185_G1_CTL1_MAX_FRAME_1632;
214 
215 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
216 }
217 
218 /* Offset 0x10: IP-PRI Mapping Register 0
219  * Offset 0x11: IP-PRI Mapping Register 1
220  * Offset 0x12: IP-PRI Mapping Register 2
221  * Offset 0x13: IP-PRI Mapping Register 3
222  * Offset 0x14: IP-PRI Mapping Register 4
223  * Offset 0x15: IP-PRI Mapping Register 5
224  * Offset 0x16: IP-PRI Mapping Register 6
225  * Offset 0x17: IP-PRI Mapping Register 7
226  */
227 
mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip * chip)228 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip)
229 {
230 	int err;
231 
232 	/* Reset the IP TOS/DiffServ/Traffic priorities to defaults */
233 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
234 	if (err)
235 		return err;
236 
237 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
238 	if (err)
239 		return err;
240 
241 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
242 	if (err)
243 		return err;
244 
245 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
246 	if (err)
247 		return err;
248 
249 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
250 	if (err)
251 		return err;
252 
253 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
254 	if (err)
255 		return err;
256 
257 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
258 	if (err)
259 		return err;
260 
261 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
262 	if (err)
263 		return err;
264 
265 	return 0;
266 }
267 
268 /* Offset 0x18: IEEE-PRI Register */
269 
mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip * chip)270 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
271 {
272 	/* Reset the IEEE Tag priorities to defaults */
273 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
274 }
275 
mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip * chip)276 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
277 {
278 	/* Reset the IEEE Tag priorities to defaults */
279 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50);
280 }
281 
282 /* Offset 0x1a: Monitor Control */
283 /* Offset 0x1a: Monitor & MGMT Control on some devices */
284 
mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)285 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
286 				 enum mv88e6xxx_egress_direction direction,
287 				 int port)
288 {
289 	u16 reg;
290 	int err;
291 
292 	err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, &reg);
293 	if (err)
294 		return err;
295 
296 	switch (direction) {
297 	case MV88E6XXX_EGRESS_DIR_INGRESS:
298 		reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK;
299 		reg |= port <<
300 		       __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);
301 		break;
302 	case MV88E6XXX_EGRESS_DIR_EGRESS:
303 		reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK;
304 		reg |= port <<
305 		       __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
306 		break;
307 	default:
308 		return -EINVAL;
309 	}
310 
311 	return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
312 }
313 
314 /* Older generations also call this the ARP destination. It has been
315  * generalized in more modern devices such that more than ARP can
316  * egress it
317  */
mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip * chip,int port)318 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
319 {
320 	u16 reg;
321 	int err;
322 
323 	err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, &reg);
324 	if (err)
325 		return err;
326 
327 	reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
328 	reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
329 
330 	return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
331 }
332 
mv88e6390_g1_monitor_write(struct mv88e6xxx_chip * chip,u16 pointer,u8 data)333 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
334 				      u16 pointer, u8 data)
335 {
336 	u16 reg;
337 
338 	reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
339 
340 	return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
341 }
342 
mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)343 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
344 				 enum mv88e6xxx_egress_direction direction,
345 				 int port)
346 {
347 	u16 ptr;
348 
349 	switch (direction) {
350 	case MV88E6XXX_EGRESS_DIR_INGRESS:
351 		ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
352 		break;
353 	case MV88E6XXX_EGRESS_DIR_EGRESS:
354 		ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
355 		break;
356 	default:
357 		return -EINVAL;
358 	}
359 
360 	return mv88e6390_g1_monitor_write(chip, ptr, port);
361 }
362 
mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip * chip,int port)363 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
364 {
365 	u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
366 
367 	/* Use the default high priority for management frames sent to
368 	 * the CPU.
369 	 */
370 	port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
371 
372 	return mv88e6390_g1_monitor_write(chip, ptr, port);
373 }
374 
mv88e6390_g1_set_ptp_cpu_port(struct mv88e6xxx_chip * chip,int port)375 int mv88e6390_g1_set_ptp_cpu_port(struct mv88e6xxx_chip *chip, int port)
376 {
377 	u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_PTP_CPU_DEST;
378 
379 	/* Use the default high priority for PTP frames sent to
380 	 * the CPU.
381 	 */
382 	port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
383 
384 	return mv88e6390_g1_monitor_write(chip, ptr, port);
385 }
386 
mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip * chip)387 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
388 {
389 	u16 ptr;
390 	int err;
391 
392 	/* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */
393 	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO;
394 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
395 	if (err)
396 		return err;
397 
398 	/* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */
399 	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI;
400 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
401 	if (err)
402 		return err;
403 
404 	/* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */
405 	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO;
406 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
407 	if (err)
408 		return err;
409 
410 	/* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */
411 	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI;
412 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
413 	if (err)
414 		return err;
415 
416 	return 0;
417 }
418 
419 /* Offset 0x1c: Global Control 2 */
420 
mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip * chip,u16 mask,u16 val)421 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask,
422 				  u16 val)
423 {
424 	u16 reg;
425 	int err;
426 
427 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, &reg);
428 	if (err)
429 		return err;
430 
431 	reg &= ~mask;
432 	reg |= val & mask;
433 
434 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg);
435 }
436 
mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip * chip,int port)437 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
438 {
439 	const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK;
440 
441 	return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
442 }
443 
mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip * chip)444 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
445 {
446 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
447 				      MV88E6085_G1_CTL2_RM_ENABLE, 0);
448 }
449 
mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip * chip)450 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
451 {
452 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
453 				      MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
454 }
455 
mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip * chip)456 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
457 {
458 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
459 				      MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
460 }
461 
mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip * chip)462 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
463 {
464 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK,
465 				      MV88E6390_G1_CTL2_HIST_MODE_RX |
466 				      MV88E6390_G1_CTL2_HIST_MODE_TX);
467 }
468 
mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip * chip,int index)469 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index)
470 {
471 	return mv88e6xxx_g1_ctl2_mask(chip,
472 				      MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK,
473 				      index);
474 }
475 
476 /* Offset 0x1d: Statistics Operation 2 */
477 
mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip * chip)478 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
479 {
480 	int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY);
481 
482 	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0);
483 }
484 
mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip * chip)485 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
486 {
487 	u16 val;
488 	int err;
489 
490 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
491 	if (err)
492 		return err;
493 
494 	val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
495 
496 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
497 
498 	return err;
499 }
500 
mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip * chip,int port)501 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
502 {
503 	int err;
504 
505 	/* Snapshot the hardware statistics counters for this port. */
506 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
507 				 MV88E6XXX_G1_STATS_OP_BUSY |
508 				 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
509 				 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port);
510 	if (err)
511 		return err;
512 
513 	/* Wait for the snapshotting to complete. */
514 	return mv88e6xxx_g1_stats_wait(chip);
515 }
516 
mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip * chip,int port)517 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
518 {
519 	port = (port + 1) << 5;
520 
521 	return mv88e6xxx_g1_stats_snapshot(chip, port);
522 }
523 
mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip * chip,int port)524 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
525 {
526 	int err;
527 
528 	port = (port + 1) << 5;
529 
530 	/* Snapshot the hardware statistics counters for this port. */
531 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
532 				 MV88E6XXX_G1_STATS_OP_BUSY |
533 				 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
534 	if (err)
535 		return err;
536 
537 	/* Wait for the snapshotting to complete. */
538 	return mv88e6xxx_g1_stats_wait(chip);
539 }
540 
mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip * chip,int stat,u32 * val)541 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
542 {
543 	u32 value;
544 	u16 reg;
545 	int err;
546 
547 	*val = 0;
548 
549 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
550 				 MV88E6XXX_G1_STATS_OP_BUSY |
551 				 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
552 	if (err)
553 		return;
554 
555 	err = mv88e6xxx_g1_stats_wait(chip);
556 	if (err)
557 		return;
558 
559 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, &reg);
560 	if (err)
561 		return;
562 
563 	value = reg << 16;
564 
565 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, &reg);
566 	if (err)
567 		return;
568 
569 	*val = value | reg;
570 }
571 
mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip * chip)572 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
573 {
574 	int err;
575 	u16 val;
576 
577 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
578 	if (err)
579 		return err;
580 
581 	/* Keep the histogram mode bits */
582 	val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
583 	val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL;
584 
585 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
586 	if (err)
587 		return err;
588 
589 	/* Wait for the flush to complete. */
590 	return mv88e6xxx_g1_stats_wait(chip);
591 }
592