1 /*
2 * arch/arm/mach-mv78xx0/pcie.c
3 *
4 * PCIe functions for Marvell MV78xx0 SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/mbus.h>
14 #include <video/vga.h>
15 #include <asm/irq.h>
16 #include <asm/mach/pci.h>
17 #include <plat/pcie.h>
18 #include "mv78xx0.h"
19 #include "common.h"
20
21 #define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4)
22 #define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane)))
23 #define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4)
24 #define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane)))
25
26 struct pcie_port {
27 u8 maj;
28 u8 min;
29 u8 root_bus_nr;
30 void __iomem *base;
31 spinlock_t conf_lock;
32 char mem_space_name[20];
33 struct resource res;
34 };
35
36 static struct pcie_port pcie_port[8];
37 static int num_pcie_ports;
38 static struct resource pcie_io_space;
39
mv78xx0_pcie_id(u32 * dev,u32 * rev)40 void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
41 {
42 *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
43 *rev = orion_pcie_rev(PCIE00_VIRT_BASE);
44 }
45
46 u32 pcie_port_size[8] = {
47 0,
48 0x30000000,
49 0x10000000,
50 0x10000000,
51 0x08000000,
52 0x08000000,
53 0x08000000,
54 0x04000000,
55 };
56
mv78xx0_pcie_preinit(void)57 static void __init mv78xx0_pcie_preinit(void)
58 {
59 int i;
60 u32 size_each;
61 u32 start;
62
63 pcie_io_space.name = "PCIe I/O Space";
64 pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
65 pcie_io_space.end =
66 MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
67 pcie_io_space.flags = IORESOURCE_MEM;
68 if (request_resource(&iomem_resource, &pcie_io_space))
69 panic("can't allocate PCIe I/O space");
70
71 if (num_pcie_ports > 7)
72 panic("invalid number of PCIe ports");
73
74 size_each = pcie_port_size[num_pcie_ports];
75
76 start = MV78XX0_PCIE_MEM_PHYS_BASE;
77 for (i = 0; i < num_pcie_ports; i++) {
78 struct pcie_port *pp = pcie_port + i;
79
80 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
81 "PCIe %d.%d MEM", pp->maj, pp->min);
82 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
83 pp->res.name = pp->mem_space_name;
84 pp->res.flags = IORESOURCE_MEM;
85 pp->res.start = start;
86 pp->res.end = start + size_each - 1;
87 start += size_each;
88
89 if (request_resource(&iomem_resource, &pp->res))
90 panic("can't allocate PCIe MEM sub-space");
91
92 mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),
93 MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),
94 pp->res.start, resource_size(&pp->res));
95 mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),
96 MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),
97 i * SZ_64K, SZ_64K, 0);
98 }
99 }
100
mv78xx0_pcie_setup(int nr,struct pci_sys_data * sys)101 static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
102 {
103 struct pcie_port *pp;
104 struct resource realio;
105
106 if (nr >= num_pcie_ports)
107 return 0;
108
109 pp = &pcie_port[nr];
110 sys->private_data = pp;
111 pp->root_bus_nr = sys->busnr;
112
113 /*
114 * Generic PCIe unit setup.
115 */
116 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
117 orion_pcie_setup(pp->base);
118
119 realio.start = nr * SZ_64K;
120 realio.end = realio.start + SZ_64K - 1;
121 pci_remap_iospace(&realio, MV78XX0_PCIE_IO_PHYS_BASE(nr));
122
123 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
124
125 return 1;
126 }
127
pcie_valid_config(struct pcie_port * pp,int bus,int dev)128 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
129 {
130 /*
131 * Don't go out when trying to access nonexisting devices
132 * on the local bus.
133 */
134 if (bus == pp->root_bus_nr && dev > 1)
135 return 0;
136
137 return 1;
138 }
139
pcie_rd_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)140 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
141 int size, u32 *val)
142 {
143 struct pci_sys_data *sys = bus->sysdata;
144 struct pcie_port *pp = sys->private_data;
145 unsigned long flags;
146 int ret;
147
148 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
149 *val = 0xffffffff;
150 return PCIBIOS_DEVICE_NOT_FOUND;
151 }
152
153 spin_lock_irqsave(&pp->conf_lock, flags);
154 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
155 spin_unlock_irqrestore(&pp->conf_lock, flags);
156
157 return ret;
158 }
159
pcie_wr_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 val)160 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
161 int where, int size, u32 val)
162 {
163 struct pci_sys_data *sys = bus->sysdata;
164 struct pcie_port *pp = sys->private_data;
165 unsigned long flags;
166 int ret;
167
168 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
169 return PCIBIOS_DEVICE_NOT_FOUND;
170
171 spin_lock_irqsave(&pp->conf_lock, flags);
172 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
173 spin_unlock_irqrestore(&pp->conf_lock, flags);
174
175 return ret;
176 }
177
178 static struct pci_ops pcie_ops = {
179 .read = pcie_rd_conf,
180 .write = pcie_wr_conf,
181 };
182
183 /*
184 * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
185 * is operating as a root complex this needs to be switched to
186 * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
187 * the device. Decoding setup is handled by the orion code.
188 */
rc_pci_fixup(struct pci_dev * dev)189 static void rc_pci_fixup(struct pci_dev *dev)
190 {
191 if (dev->bus->parent == NULL && dev->devfn == 0) {
192 int i;
193
194 dev->class &= 0xff;
195 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
196 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
197 dev->resource[i].start = 0;
198 dev->resource[i].end = 0;
199 dev->resource[i].flags = 0;
200 }
201 }
202 }
203 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
204
mv78xx0_pcie_scan_bus(int nr,struct pci_host_bridge * bridge)205 static int __init mv78xx0_pcie_scan_bus(int nr, struct pci_host_bridge *bridge)
206 {
207 struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
208
209 if (nr >= num_pcie_ports) {
210 BUG();
211 return -EINVAL;
212 }
213
214 list_splice_init(&sys->resources, &bridge->windows);
215 bridge->dev.parent = NULL;
216 bridge->sysdata = sys;
217 bridge->busnr = sys->busnr;
218 bridge->ops = &pcie_ops;
219
220 return pci_scan_root_bus_bridge(bridge);
221 }
222
mv78xx0_pcie_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)223 static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot,
224 u8 pin)
225 {
226 struct pci_sys_data *sys = dev->bus->sysdata;
227 struct pcie_port *pp = sys->private_data;
228
229 return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;
230 }
231
232 static struct hw_pci mv78xx0_pci __initdata = {
233 .nr_controllers = 8,
234 .preinit = mv78xx0_pcie_preinit,
235 .setup = mv78xx0_pcie_setup,
236 .scan = mv78xx0_pcie_scan_bus,
237 .map_irq = mv78xx0_pcie_map_irq,
238 };
239
add_pcie_port(int maj,int min,void __iomem * base)240 static void __init add_pcie_port(int maj, int min, void __iomem *base)
241 {
242 printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
243
244 if (orion_pcie_link_up(base)) {
245 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
246
247 printk("link up\n");
248
249 pp->maj = maj;
250 pp->min = min;
251 pp->root_bus_nr = -1;
252 pp->base = base;
253 spin_lock_init(&pp->conf_lock);
254 memset(&pp->res, 0, sizeof(pp->res));
255 } else {
256 printk("link down, ignoring\n");
257 }
258 }
259
mv78xx0_pcie_init(int init_port0,int init_port1)260 void __init mv78xx0_pcie_init(int init_port0, int init_port1)
261 {
262 vga_base = MV78XX0_PCIE_MEM_PHYS_BASE;
263
264 if (init_port0) {
265 add_pcie_port(0, 0, PCIE00_VIRT_BASE);
266 if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
267 add_pcie_port(0, 1, PCIE01_VIRT_BASE);
268 add_pcie_port(0, 2, PCIE02_VIRT_BASE);
269 add_pcie_port(0, 3, PCIE03_VIRT_BASE);
270 }
271 }
272
273 if (init_port1) {
274 add_pcie_port(1, 0, PCIE10_VIRT_BASE);
275 if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) {
276 add_pcie_port(1, 1, PCIE11_VIRT_BASE);
277 add_pcie_port(1, 2, PCIE12_VIRT_BASE);
278 add_pcie_port(1, 3, PCIE13_VIRT_BASE);
279 }
280 }
281
282 pci_common_init(&mv78xx0_pci);
283 }
284