1 /*
2 * MUSB OTG driver host support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/errno.h>
42 #include <linux/init.h>
43 #include <linux/list.h>
44 #include <linux/dma-mapping.h>
45
46 #include "musb_core.h"
47 #include "musb_host.h"
48
49
50 /* MUSB HOST status 22-mar-2006
51 *
52 * - There's still lots of partial code duplication for fault paths, so
53 * they aren't handled as consistently as they need to be.
54 *
55 * - PIO mostly behaved when last tested.
56 * + including ep0, with all usbtest cases 9, 10
57 * + usbtest 14 (ep0out) doesn't seem to run at all
58 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
59 * configurations, but otherwise double buffering passes basic tests.
60 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
61 *
62 * - DMA (CPPI) ... partially behaves, not currently recommended
63 * + about 1/15 the speed of typical EHCI implementations (PCI)
64 * + RX, all too often reqpkt seems to misbehave after tx
65 * + TX, no known issues (other than evident silicon issue)
66 *
67 * - DMA (Mentor/OMAP) ...has at least toggle update problems
68 *
69 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
70 * starvation ... nothing yet for TX, interrupt, or bulk.
71 *
72 * - Not tested with HNP, but some SRP paths seem to behave.
73 *
74 * NOTE 24-August-2006:
75 *
76 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
77 * extra endpoint for periodic use enabling hub + keybd + mouse. That
78 * mostly works, except that with "usbnet" it's easy to trigger cases
79 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
80 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
81 * although ARP RX wins. (That test was done with a full speed link.)
82 */
83
84
85 /*
86 * NOTE on endpoint usage:
87 *
88 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
89 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
90 * (Yes, bulk _could_ use more of the endpoints than that, and would even
91 * benefit from it.)
92 *
93 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
94 * So far that scheduling is both dumb and optimistic: the endpoint will be
95 * "claimed" until its software queue is no longer refilled. No multiplexing
96 * of transfers between endpoints, or anything clever.
97 */
98
99
100 static void musb_ep_program(struct musb *musb, u8 epnum,
101 struct urb *urb, int is_out,
102 u8 *buf, u32 offset, u32 len);
103
104 /*
105 * Clear TX fifo. Needed to avoid BABBLE errors.
106 */
musb_h_tx_flush_fifo(struct musb_hw_ep * ep)107 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
108 {
109 void __iomem *epio = ep->regs;
110 u16 csr;
111 u16 lastcsr = 0;
112 int retries = 1000;
113
114 csr = musb_readw(epio, MUSB_TXCSR);
115 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
116 if (csr != lastcsr)
117 DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
118 lastcsr = csr;
119 csr |= MUSB_TXCSR_FLUSHFIFO;
120 musb_writew(epio, MUSB_TXCSR, csr);
121 csr = musb_readw(epio, MUSB_TXCSR);
122 if (WARN(retries-- < 1,
123 "Could not flush host TX%d fifo: csr: %04x\n",
124 ep->epnum, csr))
125 return;
126 mdelay(1);
127 }
128 }
129
musb_h_ep0_flush_fifo(struct musb_hw_ep * ep)130 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
131 {
132 void __iomem *epio = ep->regs;
133 u16 csr;
134 int retries = 5;
135
136 /* scrub any data left in the fifo */
137 do {
138 csr = musb_readw(epio, MUSB_TXCSR);
139 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
140 break;
141 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
142 csr = musb_readw(epio, MUSB_TXCSR);
143 udelay(10);
144 } while (--retries);
145
146 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
147 ep->epnum, csr);
148
149 /* and reset for the next transfer */
150 musb_writew(epio, MUSB_TXCSR, 0);
151 }
152
153 /*
154 * Start transmit. Caller is responsible for locking shared resources.
155 * musb must be locked.
156 */
musb_h_tx_start(struct musb_hw_ep * ep)157 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
158 {
159 u16 txcsr;
160
161 /* NOTE: no locks here; caller should lock and select EP */
162 if (ep->epnum) {
163 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
164 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
165 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
166 } else {
167 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
168 musb_writew(ep->regs, MUSB_CSR0, txcsr);
169 }
170
171 }
172
musb_h_tx_dma_start(struct musb_hw_ep * ep)173 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
174 {
175 u16 txcsr;
176
177 /* NOTE: no locks here; caller should lock and select EP */
178 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
179 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
180 if (is_cppi_enabled())
181 txcsr |= MUSB_TXCSR_DMAMODE;
182 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
183 }
184
musb_ep_set_qh(struct musb_hw_ep * ep,int is_in,struct musb_qh * qh)185 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
186 {
187 if (is_in != 0 || ep->is_shared_fifo)
188 ep->in_qh = qh;
189 if (is_in == 0 || ep->is_shared_fifo)
190 ep->out_qh = qh;
191 }
192
musb_ep_get_qh(struct musb_hw_ep * ep,int is_in)193 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
194 {
195 return is_in ? ep->in_qh : ep->out_qh;
196 }
197
198 /*
199 * Start the URB at the front of an endpoint's queue
200 * end must be claimed from the caller.
201 *
202 * Context: controller locked, irqs blocked
203 */
204 static void
musb_start_urb(struct musb * musb,int is_in,struct musb_qh * qh)205 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
206 {
207 u16 frame;
208 u32 len;
209 void __iomem *mbase = musb->mregs;
210 struct urb *urb = next_urb(qh);
211 void *buf = urb->transfer_buffer;
212 u32 offset = 0;
213 struct musb_hw_ep *hw_ep = qh->hw_ep;
214 unsigned pipe = urb->pipe;
215 u8 address = usb_pipedevice(pipe);
216 int epnum = hw_ep->epnum;
217
218 /* initialize software qh state */
219 qh->offset = 0;
220 qh->segsize = 0;
221
222 /* gather right source of data */
223 switch (qh->type) {
224 case USB_ENDPOINT_XFER_CONTROL:
225 /* control transfers always start with SETUP */
226 is_in = 0;
227 musb->ep0_stage = MUSB_EP0_START;
228 buf = urb->setup_packet;
229 len = 8;
230 break;
231 case USB_ENDPOINT_XFER_ISOC:
232 qh->iso_idx = 0;
233 qh->frame = 0;
234 offset = urb->iso_frame_desc[0].offset;
235 len = urb->iso_frame_desc[0].length;
236 break;
237 default: /* bulk, interrupt */
238 /* actual_length may be nonzero on retry paths */
239 buf = urb->transfer_buffer + urb->actual_length;
240 len = urb->transfer_buffer_length - urb->actual_length;
241 }
242
243 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
244 qh, urb, address, qh->epnum,
245 is_in ? "in" : "out",
246 ({char *s; switch (qh->type) {
247 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
248 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
249 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
250 default: s = "-intr"; break;
251 }; s; }),
252 epnum, buf + offset, len);
253
254 /* Configure endpoint */
255 musb_ep_set_qh(hw_ep, is_in, qh);
256 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
257
258 /* transmit may have more work: start it when it is time */
259 if (is_in)
260 return;
261
262 /* determine if the time is right for a periodic transfer */
263 switch (qh->type) {
264 case USB_ENDPOINT_XFER_ISOC:
265 case USB_ENDPOINT_XFER_INT:
266 DBG(3, "check whether there's still time for periodic Tx\n");
267 frame = musb_readw(mbase, MUSB_FRAME);
268 /* FIXME this doesn't implement that scheduling policy ...
269 * or handle framecounter wrapping
270 */
271 if ((urb->transfer_flags & URB_ISO_ASAP)
272 || (frame >= urb->start_frame)) {
273 /* REVISIT the SOF irq handler shouldn't duplicate
274 * this code; and we don't init urb->start_frame...
275 */
276 qh->frame = 0;
277 goto start;
278 } else {
279 qh->frame = urb->start_frame;
280 /* enable SOF interrupt so we can count down */
281 DBG(1, "SOF for %d\n", epnum);
282 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
283 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
284 #endif
285 }
286 break;
287 default:
288 start:
289 DBG(4, "Start TX%d %s\n", epnum,
290 hw_ep->tx_channel ? "dma" : "pio");
291
292 if (!hw_ep->tx_channel)
293 musb_h_tx_start(hw_ep);
294 else if (is_cppi_enabled() || tusb_dma_omap())
295 musb_h_tx_dma_start(hw_ep);
296 }
297 }
298
299 /* Context: caller owns controller lock, IRQs are blocked */
musb_giveback(struct musb * musb,struct urb * urb,int status)300 static void musb_giveback(struct musb *musb, struct urb *urb, int status)
301 __releases(musb->lock)
302 __acquires(musb->lock)
303 {
304 DBG(({ int level; switch (status) {
305 case 0:
306 level = 4;
307 break;
308 /* common/boring faults */
309 case -EREMOTEIO:
310 case -ESHUTDOWN:
311 case -ECONNRESET:
312 case -EPIPE:
313 level = 3;
314 break;
315 default:
316 level = 2;
317 break;
318 }; level; }),
319 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
320 urb, urb->complete, status,
321 usb_pipedevice(urb->pipe),
322 usb_pipeendpoint(urb->pipe),
323 usb_pipein(urb->pipe) ? "in" : "out",
324 urb->actual_length, urb->transfer_buffer_length
325 );
326
327 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
328 spin_unlock(&musb->lock);
329 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
330 spin_lock(&musb->lock);
331 }
332
333 /* For bulk/interrupt endpoints only */
musb_save_toggle(struct musb_qh * qh,int is_in,struct urb * urb)334 static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
335 struct urb *urb)
336 {
337 void __iomem *epio = qh->hw_ep->regs;
338 u16 csr;
339
340 /*
341 * FIXME: the current Mentor DMA code seems to have
342 * problems getting toggle correct.
343 */
344
345 if (is_in)
346 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
347 else
348 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
349
350 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
351 }
352
353 /*
354 * Advance this hardware endpoint's queue, completing the specified URB and
355 * advancing to either the next URB queued to that qh, or else invalidating
356 * that qh and advancing to the next qh scheduled after the current one.
357 *
358 * Context: caller owns controller lock, IRQs are blocked
359 */
musb_advance_schedule(struct musb * musb,struct urb * urb,struct musb_hw_ep * hw_ep,int is_in)360 static void musb_advance_schedule(struct musb *musb, struct urb *urb,
361 struct musb_hw_ep *hw_ep, int is_in)
362 {
363 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
364 struct musb_hw_ep *ep = qh->hw_ep;
365 int ready = qh->is_ready;
366 int status;
367
368 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
369
370 /* save toggle eagerly, for paranoia */
371 switch (qh->type) {
372 case USB_ENDPOINT_XFER_BULK:
373 case USB_ENDPOINT_XFER_INT:
374 musb_save_toggle(qh, is_in, urb);
375 break;
376 case USB_ENDPOINT_XFER_ISOC:
377 if (status == 0 && urb->error_count)
378 status = -EXDEV;
379 break;
380 }
381
382 qh->is_ready = 0;
383 musb_giveback(musb, urb, status);
384 qh->is_ready = ready;
385
386 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
387 * invalidate qh as soon as list_empty(&hep->urb_list)
388 */
389 if (list_empty(&qh->hep->urb_list)) {
390 struct list_head *head;
391
392 if (is_in)
393 ep->rx_reinit = 1;
394 else
395 ep->tx_reinit = 1;
396
397 /* Clobber old pointers to this qh */
398 musb_ep_set_qh(ep, is_in, NULL);
399 qh->hep->hcpriv = NULL;
400
401 switch (qh->type) {
402
403 case USB_ENDPOINT_XFER_CONTROL:
404 case USB_ENDPOINT_XFER_BULK:
405 /* fifo policy for these lists, except that NAKing
406 * should rotate a qh to the end (for fairness).
407 */
408 if (qh->mux == 1) {
409 head = qh->ring.prev;
410 list_del(&qh->ring);
411 kfree(qh);
412 qh = first_qh(head);
413 break;
414 }
415
416 case USB_ENDPOINT_XFER_ISOC:
417 case USB_ENDPOINT_XFER_INT:
418 /* this is where periodic bandwidth should be
419 * de-allocated if it's tracked and allocated;
420 * and where we'd update the schedule tree...
421 */
422 kfree(qh);
423 qh = NULL;
424 break;
425 }
426 }
427
428 if (qh != NULL && qh->is_ready) {
429 DBG(4, "... next ep%d %cX urb %p\n",
430 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
431 musb_start_urb(musb, is_in, qh);
432 }
433 }
434
musb_h_flush_rxfifo(struct musb_hw_ep * hw_ep,u16 csr)435 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
436 {
437 /* we don't want fifo to fill itself again;
438 * ignore dma (various models),
439 * leave toggle alone (may not have been saved yet)
440 */
441 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
442 csr &= ~(MUSB_RXCSR_H_REQPKT
443 | MUSB_RXCSR_H_AUTOREQ
444 | MUSB_RXCSR_AUTOCLEAR);
445
446 /* write 2x to allow double buffering */
447 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
448 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
449
450 /* flush writebuffer */
451 return musb_readw(hw_ep->regs, MUSB_RXCSR);
452 }
453
454 /*
455 * PIO RX for a packet (or part of it).
456 */
457 static bool
musb_host_packet_rx(struct musb * musb,struct urb * urb,u8 epnum,u8 iso_err)458 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
459 {
460 u16 rx_count;
461 u8 *buf;
462 u16 csr;
463 bool done = false;
464 u32 length;
465 int do_flush = 0;
466 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
467 void __iomem *epio = hw_ep->regs;
468 struct musb_qh *qh = hw_ep->in_qh;
469 int pipe = urb->pipe;
470 void *buffer = urb->transfer_buffer;
471
472 /* musb_ep_select(mbase, epnum); */
473 rx_count = musb_readw(epio, MUSB_RXCOUNT);
474 DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
475 urb->transfer_buffer, qh->offset,
476 urb->transfer_buffer_length);
477
478 /* unload FIFO */
479 if (usb_pipeisoc(pipe)) {
480 int status = 0;
481 struct usb_iso_packet_descriptor *d;
482
483 if (iso_err) {
484 status = -EILSEQ;
485 urb->error_count++;
486 }
487
488 d = urb->iso_frame_desc + qh->iso_idx;
489 buf = buffer + d->offset;
490 length = d->length;
491 if (rx_count > length) {
492 if (status == 0) {
493 status = -EOVERFLOW;
494 urb->error_count++;
495 }
496 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
497 do_flush = 1;
498 } else
499 length = rx_count;
500 urb->actual_length += length;
501 d->actual_length = length;
502
503 d->status = status;
504
505 /* see if we are done */
506 done = (++qh->iso_idx >= urb->number_of_packets);
507 } else {
508 /* non-isoch */
509 buf = buffer + qh->offset;
510 length = urb->transfer_buffer_length - qh->offset;
511 if (rx_count > length) {
512 if (urb->status == -EINPROGRESS)
513 urb->status = -EOVERFLOW;
514 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
515 do_flush = 1;
516 } else
517 length = rx_count;
518 urb->actual_length += length;
519 qh->offset += length;
520
521 /* see if we are done */
522 done = (urb->actual_length == urb->transfer_buffer_length)
523 || (rx_count < qh->maxpacket)
524 || (urb->status != -EINPROGRESS);
525 if (done
526 && (urb->status == -EINPROGRESS)
527 && (urb->transfer_flags & URB_SHORT_NOT_OK)
528 && (urb->actual_length
529 < urb->transfer_buffer_length))
530 urb->status = -EREMOTEIO;
531 }
532
533 musb_read_fifo(hw_ep, length, buf);
534
535 csr = musb_readw(epio, MUSB_RXCSR);
536 csr |= MUSB_RXCSR_H_WZC_BITS;
537 if (unlikely(do_flush))
538 musb_h_flush_rxfifo(hw_ep, csr);
539 else {
540 /* REVISIT this assumes AUTOCLEAR is never set */
541 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
542 if (!done)
543 csr |= MUSB_RXCSR_H_REQPKT;
544 musb_writew(epio, MUSB_RXCSR, csr);
545 }
546
547 return done;
548 }
549
550 /* we don't always need to reinit a given side of an endpoint...
551 * when we do, use tx/rx reinit routine and then construct a new CSR
552 * to address data toggle, NYET, and DMA or PIO.
553 *
554 * it's possible that driver bugs (especially for DMA) or aborting a
555 * transfer might have left the endpoint busier than it should be.
556 * the busy/not-empty tests are basically paranoia.
557 */
558 static void
musb_rx_reinit(struct musb * musb,struct musb_qh * qh,struct musb_hw_ep * ep)559 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
560 {
561 u16 csr;
562
563 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
564 * That always uses tx_reinit since ep0 repurposes TX register
565 * offsets; the initial SETUP packet is also a kind of OUT.
566 */
567
568 /* if programmed for Tx, put it in RX mode */
569 if (ep->is_shared_fifo) {
570 csr = musb_readw(ep->regs, MUSB_TXCSR);
571 if (csr & MUSB_TXCSR_MODE) {
572 musb_h_tx_flush_fifo(ep);
573 csr = musb_readw(ep->regs, MUSB_TXCSR);
574 musb_writew(ep->regs, MUSB_TXCSR,
575 csr | MUSB_TXCSR_FRCDATATOG);
576 }
577
578 /*
579 * Clear the MODE bit (and everything else) to enable Rx.
580 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
581 */
582 if (csr & MUSB_TXCSR_DMAMODE)
583 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
584 musb_writew(ep->regs, MUSB_TXCSR, 0);
585
586 /* scrub all previous state, clearing toggle */
587 } else {
588 csr = musb_readw(ep->regs, MUSB_RXCSR);
589 if (csr & MUSB_RXCSR_RXPKTRDY)
590 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
591 musb_readw(ep->regs, MUSB_RXCOUNT));
592
593 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
594 }
595
596 /* target addr and (for multipoint) hub addr/port */
597 if (musb->is_multipoint) {
598 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
599 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
600 musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
601
602 } else
603 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
604
605 /* protocol/endpoint, interval/NAKlimit, i/o size */
606 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
607 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
608 /* NOTE: bulk combining rewrites high bits of maxpacket */
609 /* Set RXMAXP with the FIFO size of the endpoint
610 * to disable double buffer mode.
611 */
612 if (musb->double_buffer_not_ok)
613 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
614 else
615 musb_writew(ep->regs, MUSB_RXMAXP,
616 qh->maxpacket | ((qh->hb_mult - 1) << 11));
617
618 ep->rx_reinit = 0;
619 }
620
musb_tx_dma_program(struct dma_controller * dma,struct musb_hw_ep * hw_ep,struct musb_qh * qh,struct urb * urb,u32 offset,u32 length)621 static bool musb_tx_dma_program(struct dma_controller *dma,
622 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
623 struct urb *urb, u32 offset, u32 length)
624 {
625 struct dma_channel *channel = hw_ep->tx_channel;
626 void __iomem *epio = hw_ep->regs;
627 u16 pkt_size = qh->maxpacket;
628 u16 csr;
629 u8 mode;
630
631 #ifdef CONFIG_USB_INVENTRA_DMA
632 if (length > channel->max_len)
633 length = channel->max_len;
634
635 csr = musb_readw(epio, MUSB_TXCSR);
636 if (length > pkt_size) {
637 mode = 1;
638 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
639 /* autoset shouldn't be set in high bandwidth */
640 if (qh->hb_mult == 1)
641 csr |= MUSB_TXCSR_AUTOSET;
642 } else {
643 mode = 0;
644 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
645 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
646 }
647 channel->desired_mode = mode;
648 musb_writew(epio, MUSB_TXCSR, csr);
649 #else
650 if (!is_cppi_enabled() && !tusb_dma_omap())
651 return false;
652
653 channel->actual_len = 0;
654
655 /*
656 * TX uses "RNDIS" mode automatically but needs help
657 * to identify the zero-length-final-packet case.
658 */
659 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
660 #endif
661
662 qh->segsize = length;
663
664 /*
665 * Ensure the data reaches to main memory before starting
666 * DMA transfer
667 */
668 wmb();
669
670 if (!dma->channel_program(channel, pkt_size, mode,
671 urb->transfer_dma + offset, length)) {
672 dma->channel_release(channel);
673 hw_ep->tx_channel = NULL;
674
675 csr = musb_readw(epio, MUSB_TXCSR);
676 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
677 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
678 return false;
679 }
680 return true;
681 }
682
683 /*
684 * Program an HDRC endpoint as per the given URB
685 * Context: irqs blocked, controller lock held
686 */
musb_ep_program(struct musb * musb,u8 epnum,struct urb * urb,int is_out,u8 * buf,u32 offset,u32 len)687 static void musb_ep_program(struct musb *musb, u8 epnum,
688 struct urb *urb, int is_out,
689 u8 *buf, u32 offset, u32 len)
690 {
691 struct dma_controller *dma_controller;
692 struct dma_channel *dma_channel;
693 u8 dma_ok;
694 void __iomem *mbase = musb->mregs;
695 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
696 void __iomem *epio = hw_ep->regs;
697 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
698 u16 packet_sz = qh->maxpacket;
699
700 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
701 "h_addr%02x h_port%02x bytes %d\n",
702 is_out ? "-->" : "<--",
703 epnum, urb, urb->dev->speed,
704 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
705 qh->h_addr_reg, qh->h_port_reg,
706 len);
707
708 musb_ep_select(mbase, epnum);
709
710 /* candidate for DMA? */
711 dma_controller = musb->dma_controller;
712 if (is_dma_capable() && epnum && dma_controller) {
713 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
714 if (!dma_channel) {
715 dma_channel = dma_controller->channel_alloc(
716 dma_controller, hw_ep, is_out);
717 if (is_out)
718 hw_ep->tx_channel = dma_channel;
719 else
720 hw_ep->rx_channel = dma_channel;
721 }
722 } else
723 dma_channel = NULL;
724
725 /* make sure we clear DMAEnab, autoSet bits from previous run */
726
727 /* OUT/transmit/EP0 or IN/receive? */
728 if (is_out) {
729 u16 csr;
730 u16 int_txe;
731 u16 load_count;
732
733 csr = musb_readw(epio, MUSB_TXCSR);
734
735 /* disable interrupt in case we flush */
736 int_txe = musb_readw(mbase, MUSB_INTRTXE);
737 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
738
739 /* general endpoint setup */
740 if (epnum) {
741 /* flush all old state, set default */
742 musb_h_tx_flush_fifo(hw_ep);
743
744 /*
745 * We must not clear the DMAMODE bit before or in
746 * the same cycle with the DMAENAB bit, so we clear
747 * the latter first...
748 */
749 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
750 | MUSB_TXCSR_AUTOSET
751 | MUSB_TXCSR_DMAENAB
752 | MUSB_TXCSR_FRCDATATOG
753 | MUSB_TXCSR_H_RXSTALL
754 | MUSB_TXCSR_H_ERROR
755 | MUSB_TXCSR_TXPKTRDY
756 );
757 csr |= MUSB_TXCSR_MODE;
758
759 if (usb_gettoggle(urb->dev, qh->epnum, 1))
760 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
761 | MUSB_TXCSR_H_DATATOGGLE;
762 else
763 csr |= MUSB_TXCSR_CLRDATATOG;
764
765 musb_writew(epio, MUSB_TXCSR, csr);
766 /* REVISIT may need to clear FLUSHFIFO ... */
767 csr &= ~MUSB_TXCSR_DMAMODE;
768 musb_writew(epio, MUSB_TXCSR, csr);
769 csr = musb_readw(epio, MUSB_TXCSR);
770 } else {
771 /* endpoint 0: just flush */
772 musb_h_ep0_flush_fifo(hw_ep);
773 }
774
775 /* target addr and (for multipoint) hub addr/port */
776 if (musb->is_multipoint) {
777 musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
778 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
779 musb_write_txhubport(mbase, epnum, qh->h_port_reg);
780 /* FIXME if !epnum, do the same for RX ... */
781 } else
782 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
783
784 /* protocol/endpoint/interval/NAKlimit */
785 if (epnum) {
786 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
787 if (musb->double_buffer_not_ok)
788 musb_writew(epio, MUSB_TXMAXP,
789 hw_ep->max_packet_sz_tx);
790 else
791 musb_writew(epio, MUSB_TXMAXP,
792 qh->maxpacket |
793 ((qh->hb_mult - 1) << 11));
794 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
795 } else {
796 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
797 if (musb->is_multipoint)
798 musb_writeb(epio, MUSB_TYPE0,
799 qh->type_reg);
800 }
801
802 if (can_bulk_split(musb, qh->type))
803 load_count = min((u32) hw_ep->max_packet_sz_tx,
804 len);
805 else
806 load_count = min((u32) packet_sz, len);
807
808 if (dma_channel && musb_tx_dma_program(dma_controller,
809 hw_ep, qh, urb, offset, len))
810 load_count = 0;
811
812 if (load_count) {
813 /* PIO to load FIFO */
814 qh->segsize = load_count;
815 musb_write_fifo(hw_ep, load_count, buf);
816 }
817
818 /* re-enable interrupt */
819 musb_writew(mbase, MUSB_INTRTXE, int_txe);
820
821 /* IN/receive */
822 } else {
823 u16 csr;
824
825 if (hw_ep->rx_reinit) {
826 musb_rx_reinit(musb, qh, hw_ep);
827
828 /* init new state: toggle and NYET, maybe DMA later */
829 if (usb_gettoggle(urb->dev, qh->epnum, 0))
830 csr = MUSB_RXCSR_H_WR_DATATOGGLE
831 | MUSB_RXCSR_H_DATATOGGLE;
832 else
833 csr = 0;
834 if (qh->type == USB_ENDPOINT_XFER_INT)
835 csr |= MUSB_RXCSR_DISNYET;
836
837 } else {
838 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
839
840 if (csr & (MUSB_RXCSR_RXPKTRDY
841 | MUSB_RXCSR_DMAENAB
842 | MUSB_RXCSR_H_REQPKT))
843 ERR("broken !rx_reinit, ep%d csr %04x\n",
844 hw_ep->epnum, csr);
845
846 /* scrub any stale state, leaving toggle alone */
847 csr &= MUSB_RXCSR_DISNYET;
848 }
849
850 /* kick things off */
851
852 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
853 /* candidate for DMA */
854 if (dma_channel) {
855 dma_channel->actual_len = 0L;
856 qh->segsize = len;
857
858 /* AUTOREQ is in a DMA register */
859 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
860 csr = musb_readw(hw_ep->regs,
861 MUSB_RXCSR);
862
863 /* unless caller treats short rx transfers as
864 * errors, we dare not queue multiple transfers.
865 */
866 dma_ok = dma_controller->channel_program(
867 dma_channel, packet_sz,
868 !(urb->transfer_flags
869 & URB_SHORT_NOT_OK),
870 urb->transfer_dma + offset,
871 qh->segsize);
872 if (!dma_ok) {
873 dma_controller->channel_release(
874 dma_channel);
875 hw_ep->rx_channel = NULL;
876 dma_channel = NULL;
877 } else
878 csr |= MUSB_RXCSR_DMAENAB;
879 }
880 }
881
882 csr |= MUSB_RXCSR_H_REQPKT;
883 DBG(7, "RXCSR%d := %04x\n", epnum, csr);
884 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
885 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
886 }
887 }
888
889
890 /*
891 * Service the default endpoint (ep0) as host.
892 * Return true until it's time to start the status stage.
893 */
musb_h_ep0_continue(struct musb * musb,u16 len,struct urb * urb)894 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
895 {
896 bool more = false;
897 u8 *fifo_dest = NULL;
898 u16 fifo_count = 0;
899 struct musb_hw_ep *hw_ep = musb->control_ep;
900 struct musb_qh *qh = hw_ep->in_qh;
901 struct usb_ctrlrequest *request;
902
903 switch (musb->ep0_stage) {
904 case MUSB_EP0_IN:
905 fifo_dest = urb->transfer_buffer + urb->actual_length;
906 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
907 urb->actual_length);
908 if (fifo_count < len)
909 urb->status = -EOVERFLOW;
910
911 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
912
913 urb->actual_length += fifo_count;
914 if (len < qh->maxpacket) {
915 /* always terminate on short read; it's
916 * rarely reported as an error.
917 */
918 } else if (urb->actual_length <
919 urb->transfer_buffer_length)
920 more = true;
921 break;
922 case MUSB_EP0_START:
923 request = (struct usb_ctrlrequest *) urb->setup_packet;
924
925 if (!request->wLength) {
926 DBG(4, "start no-DATA\n");
927 break;
928 } else if (request->bRequestType & USB_DIR_IN) {
929 DBG(4, "start IN-DATA\n");
930 musb->ep0_stage = MUSB_EP0_IN;
931 more = true;
932 break;
933 } else {
934 DBG(4, "start OUT-DATA\n");
935 musb->ep0_stage = MUSB_EP0_OUT;
936 more = true;
937 }
938 /* FALLTHROUGH */
939 case MUSB_EP0_OUT:
940 fifo_count = min_t(size_t, qh->maxpacket,
941 urb->transfer_buffer_length -
942 urb->actual_length);
943 if (fifo_count) {
944 fifo_dest = (u8 *) (urb->transfer_buffer
945 + urb->actual_length);
946 DBG(3, "Sending %d byte%s to ep0 fifo %p\n",
947 fifo_count,
948 (fifo_count == 1) ? "" : "s",
949 fifo_dest);
950 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
951
952 urb->actual_length += fifo_count;
953 more = true;
954 }
955 break;
956 default:
957 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
958 break;
959 }
960
961 return more;
962 }
963
964 /*
965 * Handle default endpoint interrupt as host. Only called in IRQ time
966 * from musb_interrupt().
967 *
968 * called with controller irqlocked
969 */
musb_h_ep0_irq(struct musb * musb)970 irqreturn_t musb_h_ep0_irq(struct musb *musb)
971 {
972 struct urb *urb;
973 u16 csr, len;
974 int status = 0;
975 void __iomem *mbase = musb->mregs;
976 struct musb_hw_ep *hw_ep = musb->control_ep;
977 void __iomem *epio = hw_ep->regs;
978 struct musb_qh *qh = hw_ep->in_qh;
979 bool complete = false;
980 irqreturn_t retval = IRQ_NONE;
981
982 /* ep0 only has one queue, "in" */
983 urb = next_urb(qh);
984
985 musb_ep_select(mbase, 0);
986 csr = musb_readw(epio, MUSB_CSR0);
987 len = (csr & MUSB_CSR0_RXPKTRDY)
988 ? musb_readb(epio, MUSB_COUNT0)
989 : 0;
990
991 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
992 csr, qh, len, urb, musb->ep0_stage);
993
994 /* if we just did status stage, we are done */
995 if (MUSB_EP0_STATUS == musb->ep0_stage) {
996 retval = IRQ_HANDLED;
997 complete = true;
998 }
999
1000 /* prepare status */
1001 if (csr & MUSB_CSR0_H_RXSTALL) {
1002 DBG(6, "STALLING ENDPOINT\n");
1003 status = -EPIPE;
1004
1005 } else if (csr & MUSB_CSR0_H_ERROR) {
1006 DBG(2, "no response, csr0 %04x\n", csr);
1007 status = -EPROTO;
1008
1009 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1010 DBG(2, "control NAK timeout\n");
1011
1012 /* NOTE: this code path would be a good place to PAUSE a
1013 * control transfer, if another one is queued, so that
1014 * ep0 is more likely to stay busy. That's already done
1015 * for bulk RX transfers.
1016 *
1017 * if (qh->ring.next != &musb->control), then
1018 * we have a candidate... NAKing is *NOT* an error
1019 */
1020 musb_writew(epio, MUSB_CSR0, 0);
1021 retval = IRQ_HANDLED;
1022 }
1023
1024 if (status) {
1025 DBG(6, "aborting\n");
1026 retval = IRQ_HANDLED;
1027 if (urb)
1028 urb->status = status;
1029 complete = true;
1030
1031 /* use the proper sequence to abort the transfer */
1032 if (csr & MUSB_CSR0_H_REQPKT) {
1033 csr &= ~MUSB_CSR0_H_REQPKT;
1034 musb_writew(epio, MUSB_CSR0, csr);
1035 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1036 musb_writew(epio, MUSB_CSR0, csr);
1037 } else {
1038 musb_h_ep0_flush_fifo(hw_ep);
1039 }
1040
1041 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1042
1043 /* clear it */
1044 musb_writew(epio, MUSB_CSR0, 0);
1045 }
1046
1047 if (unlikely(!urb)) {
1048 /* stop endpoint since we have no place for its data, this
1049 * SHOULD NEVER HAPPEN! */
1050 ERR("no URB for end 0\n");
1051
1052 musb_h_ep0_flush_fifo(hw_ep);
1053 goto done;
1054 }
1055
1056 if (!complete) {
1057 /* call common logic and prepare response */
1058 if (musb_h_ep0_continue(musb, len, urb)) {
1059 /* more packets required */
1060 csr = (MUSB_EP0_IN == musb->ep0_stage)
1061 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1062 } else {
1063 /* data transfer complete; perform status phase */
1064 if (usb_pipeout(urb->pipe)
1065 || !urb->transfer_buffer_length)
1066 csr = MUSB_CSR0_H_STATUSPKT
1067 | MUSB_CSR0_H_REQPKT;
1068 else
1069 csr = MUSB_CSR0_H_STATUSPKT
1070 | MUSB_CSR0_TXPKTRDY;
1071
1072 /* flag status stage */
1073 musb->ep0_stage = MUSB_EP0_STATUS;
1074
1075 DBG(5, "ep0 STATUS, csr %04x\n", csr);
1076
1077 }
1078 musb_writew(epio, MUSB_CSR0, csr);
1079 retval = IRQ_HANDLED;
1080 } else
1081 musb->ep0_stage = MUSB_EP0_IDLE;
1082
1083 /* call completion handler if done */
1084 if (complete)
1085 musb_advance_schedule(musb, urb, hw_ep, 1);
1086 done:
1087 return retval;
1088 }
1089
1090
1091 #ifdef CONFIG_USB_INVENTRA_DMA
1092
1093 /* Host side TX (OUT) using Mentor DMA works as follows:
1094 submit_urb ->
1095 - if queue was empty, Program Endpoint
1096 - ... which starts DMA to fifo in mode 1 or 0
1097
1098 DMA Isr (transfer complete) -> TxAvail()
1099 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1100 only in musb_cleanup_urb)
1101 - TxPktRdy has to be set in mode 0 or for
1102 short packets in mode 1.
1103 */
1104
1105 #endif
1106
1107 /* Service a Tx-Available or dma completion irq for the endpoint */
musb_host_tx(struct musb * musb,u8 epnum)1108 void musb_host_tx(struct musb *musb, u8 epnum)
1109 {
1110 int pipe;
1111 bool done = false;
1112 u16 tx_csr;
1113 size_t length = 0;
1114 size_t offset = 0;
1115 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1116 void __iomem *epio = hw_ep->regs;
1117 struct musb_qh *qh = hw_ep->out_qh;
1118 struct urb *urb = next_urb(qh);
1119 u32 status = 0;
1120 void __iomem *mbase = musb->mregs;
1121 struct dma_channel *dma;
1122 bool transfer_pending = false;
1123
1124 musb_ep_select(mbase, epnum);
1125 tx_csr = musb_readw(epio, MUSB_TXCSR);
1126
1127 /* with CPPI, DMA sometimes triggers "extra" irqs */
1128 if (!urb) {
1129 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1130 return;
1131 }
1132
1133 pipe = urb->pipe;
1134 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1135 DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1136 dma ? ", dma" : "");
1137
1138 /* check for errors */
1139 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1140 /* dma was disabled, fifo flushed */
1141 DBG(3, "TX end %d stall\n", epnum);
1142
1143 /* stall; record URB status */
1144 status = -EPIPE;
1145
1146 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1147 /* (NON-ISO) dma was disabled, fifo flushed */
1148 DBG(3, "TX 3strikes on ep=%d\n", epnum);
1149
1150 status = -ETIMEDOUT;
1151
1152 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1153 DBG(6, "TX end=%d device not responding\n", epnum);
1154
1155 /* NOTE: this code path would be a good place to PAUSE a
1156 * transfer, if there's some other (nonperiodic) tx urb
1157 * that could use this fifo. (dma complicates it...)
1158 * That's already done for bulk RX transfers.
1159 *
1160 * if (bulk && qh->ring.next != &musb->out_bulk), then
1161 * we have a candidate... NAKing is *NOT* an error
1162 */
1163 musb_ep_select(mbase, epnum);
1164 musb_writew(epio, MUSB_TXCSR,
1165 MUSB_TXCSR_H_WZC_BITS
1166 | MUSB_TXCSR_TXPKTRDY);
1167 return;
1168 }
1169
1170 if (status) {
1171 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1172 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1173 (void) musb->dma_controller->channel_abort(dma);
1174 }
1175
1176 /* do the proper sequence to abort the transfer in the
1177 * usb core; the dma engine should already be stopped.
1178 */
1179 musb_h_tx_flush_fifo(hw_ep);
1180 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1181 | MUSB_TXCSR_DMAENAB
1182 | MUSB_TXCSR_H_ERROR
1183 | MUSB_TXCSR_H_RXSTALL
1184 | MUSB_TXCSR_H_NAKTIMEOUT
1185 );
1186
1187 musb_ep_select(mbase, epnum);
1188 musb_writew(epio, MUSB_TXCSR, tx_csr);
1189 /* REVISIT may need to clear FLUSHFIFO ... */
1190 musb_writew(epio, MUSB_TXCSR, tx_csr);
1191 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1192
1193 done = true;
1194 }
1195
1196 /* second cppi case */
1197 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1198 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1199 return;
1200 }
1201
1202 if (is_dma_capable() && dma && !status) {
1203 /*
1204 * DMA has completed. But if we're using DMA mode 1 (multi
1205 * packet DMA), we need a terminal TXPKTRDY interrupt before
1206 * we can consider this transfer completed, lest we trash
1207 * its last packet when writing the next URB's data. So we
1208 * switch back to mode 0 to get that interrupt; we'll come
1209 * back here once it happens.
1210 */
1211 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1212 /*
1213 * We shouldn't clear DMAMODE with DMAENAB set; so
1214 * clear them in a safe order. That should be OK
1215 * once TXPKTRDY has been set (and I've never seen
1216 * it being 0 at this moment -- DMA interrupt latency
1217 * is significant) but if it hasn't been then we have
1218 * no choice but to stop being polite and ignore the
1219 * programmer's guide... :-)
1220 *
1221 * Note that we must write TXCSR with TXPKTRDY cleared
1222 * in order not to re-trigger the packet send (this bit
1223 * can't be cleared by CPU), and there's another caveat:
1224 * TXPKTRDY may be set shortly and then cleared in the
1225 * double-buffered FIFO mode, so we do an extra TXCSR
1226 * read for debouncing...
1227 */
1228 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1229 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1230 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1231 MUSB_TXCSR_TXPKTRDY);
1232 musb_writew(epio, MUSB_TXCSR,
1233 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1234 }
1235 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1236 MUSB_TXCSR_TXPKTRDY);
1237 musb_writew(epio, MUSB_TXCSR,
1238 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1239
1240 /*
1241 * There is no guarantee that we'll get an interrupt
1242 * after clearing DMAMODE as we might have done this
1243 * too late (after TXPKTRDY was cleared by controller).
1244 * Re-read TXCSR as we have spoiled its previous value.
1245 */
1246 tx_csr = musb_readw(epio, MUSB_TXCSR);
1247 }
1248
1249 /*
1250 * We may get here from a DMA completion or TXPKTRDY interrupt.
1251 * In any case, we must check the FIFO status here and bail out
1252 * only if the FIFO still has data -- that should prevent the
1253 * "missed" TXPKTRDY interrupts and deal with double-buffered
1254 * FIFO mode too...
1255 */
1256 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1257 DBG(2, "DMA complete but packet still in FIFO, "
1258 "CSR %04x\n", tx_csr);
1259 return;
1260 }
1261 }
1262
1263 if (!status || dma || usb_pipeisoc(pipe)) {
1264 if (dma)
1265 length = dma->actual_len;
1266 else
1267 length = qh->segsize;
1268 qh->offset += length;
1269
1270 if (usb_pipeisoc(pipe)) {
1271 struct usb_iso_packet_descriptor *d;
1272
1273 d = urb->iso_frame_desc + qh->iso_idx;
1274 d->actual_length = length;
1275 d->status = status;
1276 if (++qh->iso_idx >= urb->number_of_packets) {
1277 done = true;
1278 } else {
1279 d++;
1280 offset = d->offset;
1281 length = d->length;
1282 }
1283 } else if (dma && urb->transfer_buffer_length == qh->offset) {
1284 done = true;
1285 } else {
1286 /* see if we need to send more data, or ZLP */
1287 if (qh->segsize < qh->maxpacket)
1288 done = true;
1289 else if (qh->offset == urb->transfer_buffer_length
1290 && !(urb->transfer_flags
1291 & URB_ZERO_PACKET))
1292 done = true;
1293 if (!done) {
1294 offset = qh->offset;
1295 length = urb->transfer_buffer_length - offset;
1296 transfer_pending = true;
1297 }
1298 }
1299 }
1300
1301 /* urb->status != -EINPROGRESS means request has been faulted,
1302 * so we must abort this transfer after cleanup
1303 */
1304 if (urb->status != -EINPROGRESS) {
1305 done = true;
1306 if (status == 0)
1307 status = urb->status;
1308 }
1309
1310 if (done) {
1311 /* set status */
1312 urb->status = status;
1313 urb->actual_length = qh->offset;
1314 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1315 return;
1316 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
1317 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
1318 offset, length)) {
1319 if (is_cppi_enabled() || tusb_dma_omap())
1320 musb_h_tx_dma_start(hw_ep);
1321 return;
1322 }
1323 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1324 DBG(1, "not complete, but DMA enabled?\n");
1325 return;
1326 }
1327
1328 /*
1329 * PIO: start next packet in this URB.
1330 *
1331 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1332 * (and presumably, FIFO is not half-full) we should write *two*
1333 * packets before updating TXCSR; other docs disagree...
1334 */
1335 if (length > qh->maxpacket)
1336 length = qh->maxpacket;
1337 /* Unmap the buffer so that CPU can use it */
1338 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
1339 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1340 qh->segsize = length;
1341
1342 musb_ep_select(mbase, epnum);
1343 musb_writew(epio, MUSB_TXCSR,
1344 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1345 }
1346
1347
1348 #ifdef CONFIG_USB_INVENTRA_DMA
1349
1350 /* Host side RX (IN) using Mentor DMA works as follows:
1351 submit_urb ->
1352 - if queue was empty, ProgramEndpoint
1353 - first IN token is sent out (by setting ReqPkt)
1354 LinuxIsr -> RxReady()
1355 /\ => first packet is received
1356 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1357 | -> DMA Isr (transfer complete) -> RxReady()
1358 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1359 | - if urb not complete, send next IN token (ReqPkt)
1360 | | else complete urb.
1361 | |
1362 ---------------------------
1363 *
1364 * Nuances of mode 1:
1365 * For short packets, no ack (+RxPktRdy) is sent automatically
1366 * (even if AutoClear is ON)
1367 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1368 * automatically => major problem, as collecting the next packet becomes
1369 * difficult. Hence mode 1 is not used.
1370 *
1371 * REVISIT
1372 * All we care about at this driver level is that
1373 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1374 * (b) termination conditions are: short RX, or buffer full;
1375 * (c) fault modes include
1376 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1377 * (and that endpoint's dma queue stops immediately)
1378 * - overflow (full, PLUS more bytes in the terminal packet)
1379 *
1380 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1381 * thus be a great candidate for using mode 1 ... for all but the
1382 * last packet of one URB's transfer.
1383 */
1384
1385 #endif
1386
1387 /* Schedule next QH from musb->in_bulk and move the current qh to
1388 * the end; avoids starvation for other endpoints.
1389 */
musb_bulk_rx_nak_timeout(struct musb * musb,struct musb_hw_ep * ep)1390 static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
1391 {
1392 struct dma_channel *dma;
1393 struct urb *urb;
1394 void __iomem *mbase = musb->mregs;
1395 void __iomem *epio = ep->regs;
1396 struct musb_qh *cur_qh, *next_qh;
1397 u16 rx_csr;
1398
1399 musb_ep_select(mbase, ep->epnum);
1400 dma = is_dma_capable() ? ep->rx_channel : NULL;
1401
1402 /* clear nak timeout bit */
1403 rx_csr = musb_readw(epio, MUSB_RXCSR);
1404 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1405 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1406 musb_writew(epio, MUSB_RXCSR, rx_csr);
1407
1408 cur_qh = first_qh(&musb->in_bulk);
1409 if (cur_qh) {
1410 urb = next_urb(cur_qh);
1411 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1412 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1413 musb->dma_controller->channel_abort(dma);
1414 urb->actual_length += dma->actual_len;
1415 dma->actual_len = 0L;
1416 }
1417 musb_save_toggle(cur_qh, 1, urb);
1418
1419 /* move cur_qh to end of queue */
1420 list_move_tail(&cur_qh->ring, &musb->in_bulk);
1421
1422 /* get the next qh from musb->in_bulk */
1423 next_qh = first_qh(&musb->in_bulk);
1424
1425 /* set rx_reinit and schedule the next qh */
1426 ep->rx_reinit = 1;
1427 musb_start_urb(musb, 1, next_qh);
1428 }
1429 }
1430
1431 /*
1432 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1433 * and high-bandwidth IN transfer cases.
1434 */
musb_host_rx(struct musb * musb,u8 epnum)1435 void musb_host_rx(struct musb *musb, u8 epnum)
1436 {
1437 struct urb *urb;
1438 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1439 void __iomem *epio = hw_ep->regs;
1440 struct musb_qh *qh = hw_ep->in_qh;
1441 size_t xfer_len;
1442 void __iomem *mbase = musb->mregs;
1443 int pipe;
1444 u16 rx_csr, val;
1445 bool iso_err = false;
1446 bool done = false;
1447 u32 status;
1448 struct dma_channel *dma;
1449
1450 musb_ep_select(mbase, epnum);
1451
1452 urb = next_urb(qh);
1453 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1454 status = 0;
1455 xfer_len = 0;
1456
1457 rx_csr = musb_readw(epio, MUSB_RXCSR);
1458 val = rx_csr;
1459
1460 if (unlikely(!urb)) {
1461 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1462 * usbtest #11 (unlinks) triggers it regularly, sometimes
1463 * with fifo full. (Only with DMA??)
1464 */
1465 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1466 musb_readw(epio, MUSB_RXCOUNT));
1467 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1468 return;
1469 }
1470
1471 pipe = urb->pipe;
1472
1473 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1474 epnum, rx_csr, urb->actual_length,
1475 dma ? dma->actual_len : 0);
1476
1477 /* check for errors, concurrent stall & unlink is not really
1478 * handled yet! */
1479 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1480 DBG(3, "RX end %d STALL\n", epnum);
1481
1482 /* stall; record URB status */
1483 status = -EPIPE;
1484
1485 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1486 DBG(3, "end %d RX proto error\n", epnum);
1487
1488 status = -EPROTO;
1489 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1490
1491 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1492
1493 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1494 DBG(6, "RX end %d NAK timeout\n", epnum);
1495
1496 /* NOTE: NAKing is *NOT* an error, so we want to
1497 * continue. Except ... if there's a request for
1498 * another QH, use that instead of starving it.
1499 *
1500 * Devices like Ethernet and serial adapters keep
1501 * reads posted at all times, which will starve
1502 * other devices without this logic.
1503 */
1504 if (usb_pipebulk(urb->pipe)
1505 && qh->mux == 1
1506 && !list_is_singular(&musb->in_bulk)) {
1507 musb_bulk_rx_nak_timeout(musb, hw_ep);
1508 return;
1509 }
1510 musb_ep_select(mbase, epnum);
1511 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1512 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1513 musb_writew(epio, MUSB_RXCSR, rx_csr);
1514
1515 goto finish;
1516 } else {
1517 DBG(4, "RX end %d ISO data error\n", epnum);
1518 /* packet error reported later */
1519 iso_err = true;
1520 }
1521 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1522 DBG(3, "end %d high bandwidth incomplete ISO packet RX\n",
1523 epnum);
1524 status = -EPROTO;
1525 }
1526
1527 /* faults abort the transfer */
1528 if (status) {
1529 /* clean up dma and collect transfer count */
1530 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1531 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1532 (void) musb->dma_controller->channel_abort(dma);
1533 xfer_len = dma->actual_len;
1534 }
1535 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1536 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1537 done = true;
1538 goto finish;
1539 }
1540
1541 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1542 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1543 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1544 goto finish;
1545 }
1546
1547 /* thorough shutdown for now ... given more precise fault handling
1548 * and better queueing support, we might keep a DMA pipeline going
1549 * while processing this irq for earlier completions.
1550 */
1551
1552 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1553
1554 #ifndef CONFIG_USB_INVENTRA_DMA
1555 if (rx_csr & MUSB_RXCSR_H_REQPKT) {
1556 /* REVISIT this happened for a while on some short reads...
1557 * the cleanup still needs investigation... looks bad...
1558 * and also duplicates dma cleanup code above ... plus,
1559 * shouldn't this be the "half full" double buffer case?
1560 */
1561 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1562 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1563 (void) musb->dma_controller->channel_abort(dma);
1564 xfer_len = dma->actual_len;
1565 done = true;
1566 }
1567
1568 DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1569 xfer_len, dma ? ", dma" : "");
1570 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1571
1572 musb_ep_select(mbase, epnum);
1573 musb_writew(epio, MUSB_RXCSR,
1574 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1575 }
1576 #endif
1577 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1578 xfer_len = dma->actual_len;
1579
1580 val &= ~(MUSB_RXCSR_DMAENAB
1581 | MUSB_RXCSR_H_AUTOREQ
1582 | MUSB_RXCSR_AUTOCLEAR
1583 | MUSB_RXCSR_RXPKTRDY);
1584 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1585
1586 #ifdef CONFIG_USB_INVENTRA_DMA
1587 if (usb_pipeisoc(pipe)) {
1588 struct usb_iso_packet_descriptor *d;
1589
1590 d = urb->iso_frame_desc + qh->iso_idx;
1591 d->actual_length = xfer_len;
1592
1593 /* even if there was an error, we did the dma
1594 * for iso_frame_desc->length
1595 */
1596 if (d->status != EILSEQ && d->status != -EOVERFLOW)
1597 d->status = 0;
1598
1599 if (++qh->iso_idx >= urb->number_of_packets)
1600 done = true;
1601 else
1602 done = false;
1603
1604 } else {
1605 /* done if urb buffer is full or short packet is recd */
1606 done = (urb->actual_length + xfer_len >=
1607 urb->transfer_buffer_length
1608 || dma->actual_len < qh->maxpacket);
1609 }
1610
1611 /* send IN token for next packet, without AUTOREQ */
1612 if (!done) {
1613 val |= MUSB_RXCSR_H_REQPKT;
1614 musb_writew(epio, MUSB_RXCSR,
1615 MUSB_RXCSR_H_WZC_BITS | val);
1616 }
1617
1618 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1619 done ? "off" : "reset",
1620 musb_readw(epio, MUSB_RXCSR),
1621 musb_readw(epio, MUSB_RXCOUNT));
1622 #else
1623 done = true;
1624 #endif
1625 } else if (urb->status == -EINPROGRESS) {
1626 /* if no errors, be sure a packet is ready for unloading */
1627 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1628 status = -EPROTO;
1629 ERR("Rx interrupt with no errors or packet!\n");
1630
1631 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1632
1633 /* SCRUB (RX) */
1634 /* do the proper sequence to abort the transfer */
1635 musb_ep_select(mbase, epnum);
1636 val &= ~MUSB_RXCSR_H_REQPKT;
1637 musb_writew(epio, MUSB_RXCSR, val);
1638 goto finish;
1639 }
1640
1641 /* we are expecting IN packets */
1642 #ifdef CONFIG_USB_INVENTRA_DMA
1643 if (dma) {
1644 struct dma_controller *c;
1645 u16 rx_count;
1646 int ret, length;
1647 dma_addr_t buf;
1648
1649 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1650
1651 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
1652 epnum, rx_count,
1653 urb->transfer_dma
1654 + urb->actual_length,
1655 qh->offset,
1656 urb->transfer_buffer_length);
1657
1658 c = musb->dma_controller;
1659
1660 if (usb_pipeisoc(pipe)) {
1661 int d_status = 0;
1662 struct usb_iso_packet_descriptor *d;
1663
1664 d = urb->iso_frame_desc + qh->iso_idx;
1665
1666 if (iso_err) {
1667 d_status = -EILSEQ;
1668 urb->error_count++;
1669 }
1670 if (rx_count > d->length) {
1671 if (d_status == 0) {
1672 d_status = -EOVERFLOW;
1673 urb->error_count++;
1674 }
1675 DBG(2, "** OVERFLOW %d into %d\n",\
1676 rx_count, d->length);
1677
1678 length = d->length;
1679 } else
1680 length = rx_count;
1681 d->status = d_status;
1682 buf = urb->transfer_dma + d->offset;
1683 } else {
1684 length = rx_count;
1685 buf = urb->transfer_dma +
1686 urb->actual_length;
1687 }
1688
1689 dma->desired_mode = 0;
1690 #ifdef USE_MODE1
1691 /* because of the issue below, mode 1 will
1692 * only rarely behave with correct semantics.
1693 */
1694 if ((urb->transfer_flags &
1695 URB_SHORT_NOT_OK)
1696 && (urb->transfer_buffer_length -
1697 urb->actual_length)
1698 > qh->maxpacket)
1699 dma->desired_mode = 1;
1700 if (rx_count < hw_ep->max_packet_sz_rx) {
1701 length = rx_count;
1702 dma->desired_mode = 0;
1703 } else {
1704 length = urb->transfer_buffer_length;
1705 }
1706 #endif
1707
1708 /* Disadvantage of using mode 1:
1709 * It's basically usable only for mass storage class; essentially all
1710 * other protocols also terminate transfers on short packets.
1711 *
1712 * Details:
1713 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1714 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1715 * to use the extra IN token to grab the last packet using mode 0, then
1716 * the problem is that you cannot be sure when the device will send the
1717 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1718 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1719 * transfer, while sometimes it is recd just a little late so that if you
1720 * try to configure for mode 0 soon after the mode 1 transfer is
1721 * completed, you will find rxcount 0. Okay, so you might think why not
1722 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1723 */
1724
1725 val = musb_readw(epio, MUSB_RXCSR);
1726 val &= ~MUSB_RXCSR_H_REQPKT;
1727
1728 if (dma->desired_mode == 0)
1729 val &= ~MUSB_RXCSR_H_AUTOREQ;
1730 else
1731 val |= MUSB_RXCSR_H_AUTOREQ;
1732 val |= MUSB_RXCSR_DMAENAB;
1733
1734 /* autoclear shouldn't be set in high bandwidth */
1735 if (qh->hb_mult == 1)
1736 val |= MUSB_RXCSR_AUTOCLEAR;
1737
1738 musb_writew(epio, MUSB_RXCSR,
1739 MUSB_RXCSR_H_WZC_BITS | val);
1740
1741 /* REVISIT if when actual_length != 0,
1742 * transfer_buffer_length needs to be
1743 * adjusted first...
1744 */
1745 ret = c->channel_program(
1746 dma, qh->maxpacket,
1747 dma->desired_mode, buf, length);
1748
1749 if (!ret) {
1750 c->channel_release(dma);
1751 hw_ep->rx_channel = NULL;
1752 dma = NULL;
1753 /* REVISIT reset CSR */
1754 }
1755 }
1756 #endif /* Mentor DMA */
1757
1758 if (!dma) {
1759 /* Unmap the buffer so that CPU can use it */
1760 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
1761 done = musb_host_packet_rx(musb, urb,
1762 epnum, iso_err);
1763 DBG(6, "read %spacket\n", done ? "last " : "");
1764 }
1765 }
1766
1767 finish:
1768 urb->actual_length += xfer_len;
1769 qh->offset += xfer_len;
1770 if (done) {
1771 if (urb->status == -EINPROGRESS)
1772 urb->status = status;
1773 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
1774 }
1775 }
1776
1777 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1778 * the software schedule associates multiple such nodes with a given
1779 * host side hardware endpoint + direction; scheduling may activate
1780 * that hardware endpoint.
1781 */
musb_schedule(struct musb * musb,struct musb_qh * qh,int is_in)1782 static int musb_schedule(
1783 struct musb *musb,
1784 struct musb_qh *qh,
1785 int is_in)
1786 {
1787 int idle;
1788 int best_diff;
1789 int best_end, epnum;
1790 struct musb_hw_ep *hw_ep = NULL;
1791 struct list_head *head = NULL;
1792 u8 toggle;
1793 u8 txtype;
1794 struct urb *urb = next_urb(qh);
1795
1796 /* use fixed hardware for control and bulk */
1797 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
1798 head = &musb->control;
1799 hw_ep = musb->control_ep;
1800 goto success;
1801 }
1802
1803 /* else, periodic transfers get muxed to other endpoints */
1804
1805 /*
1806 * We know this qh hasn't been scheduled, so all we need to do
1807 * is choose which hardware endpoint to put it on ...
1808 *
1809 * REVISIT what we really want here is a regular schedule tree
1810 * like e.g. OHCI uses.
1811 */
1812 best_diff = 4096;
1813 best_end = -1;
1814
1815 for (epnum = 1, hw_ep = musb->endpoints + 1;
1816 epnum < musb->nr_endpoints;
1817 epnum++, hw_ep++) {
1818 int diff;
1819
1820 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
1821 continue;
1822
1823 if (hw_ep == musb->bulk_ep)
1824 continue;
1825
1826 if (is_in)
1827 diff = hw_ep->max_packet_sz_rx;
1828 else
1829 diff = hw_ep->max_packet_sz_tx;
1830 diff -= (qh->maxpacket * qh->hb_mult);
1831
1832 if (diff >= 0 && best_diff > diff) {
1833
1834 /*
1835 * Mentor controller has a bug in that if we schedule
1836 * a BULK Tx transfer on an endpoint that had earlier
1837 * handled ISOC then the BULK transfer has to start on
1838 * a zero toggle. If the BULK transfer starts on a 1
1839 * toggle then this transfer will fail as the mentor
1840 * controller starts the Bulk transfer on a 0 toggle
1841 * irrespective of the programming of the toggle bits
1842 * in the TXCSR register. Check for this condition
1843 * while allocating the EP for a Tx Bulk transfer. If
1844 * so skip this EP.
1845 */
1846 hw_ep = musb->endpoints + epnum;
1847 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
1848 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
1849 >> 4) & 0x3;
1850 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
1851 toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
1852 continue;
1853
1854 best_diff = diff;
1855 best_end = epnum;
1856 }
1857 }
1858 /* use bulk reserved ep1 if no other ep is free */
1859 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
1860 hw_ep = musb->bulk_ep;
1861 if (is_in)
1862 head = &musb->in_bulk;
1863 else
1864 head = &musb->out_bulk;
1865
1866 /* Enable bulk RX NAK timeout scheme when bulk requests are
1867 * multiplexed. This scheme doen't work in high speed to full
1868 * speed scenario as NAK interrupts are not coming from a
1869 * full speed device connected to a high speed device.
1870 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
1871 * 4 (8 frame or 8ms) for FS device.
1872 */
1873 if (is_in && qh->dev)
1874 qh->intv_reg =
1875 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
1876 goto success;
1877 } else if (best_end < 0) {
1878 return -ENOSPC;
1879 }
1880
1881 idle = 1;
1882 qh->mux = 0;
1883 hw_ep = musb->endpoints + best_end;
1884 DBG(4, "qh %p periodic slot %d\n", qh, best_end);
1885 success:
1886 if (head) {
1887 idle = list_empty(head);
1888 list_add_tail(&qh->ring, head);
1889 qh->mux = 1;
1890 }
1891 qh->hw_ep = hw_ep;
1892 qh->hep->hcpriv = qh;
1893 if (idle)
1894 musb_start_urb(musb, is_in, qh);
1895 return 0;
1896 }
1897
musb_urb_enqueue(struct usb_hcd * hcd,struct urb * urb,gfp_t mem_flags)1898 static int musb_urb_enqueue(
1899 struct usb_hcd *hcd,
1900 struct urb *urb,
1901 gfp_t mem_flags)
1902 {
1903 unsigned long flags;
1904 struct musb *musb = hcd_to_musb(hcd);
1905 struct usb_host_endpoint *hep = urb->ep;
1906 struct musb_qh *qh;
1907 struct usb_endpoint_descriptor *epd = &hep->desc;
1908 int ret;
1909 unsigned type_reg;
1910 unsigned interval;
1911
1912 /* host role must be active */
1913 if (!is_host_active(musb) || !musb->is_active)
1914 return -ENODEV;
1915
1916 spin_lock_irqsave(&musb->lock, flags);
1917 ret = usb_hcd_link_urb_to_ep(hcd, urb);
1918 qh = ret ? NULL : hep->hcpriv;
1919 if (qh)
1920 urb->hcpriv = qh;
1921 spin_unlock_irqrestore(&musb->lock, flags);
1922
1923 /* DMA mapping was already done, if needed, and this urb is on
1924 * hep->urb_list now ... so we're done, unless hep wasn't yet
1925 * scheduled onto a live qh.
1926 *
1927 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
1928 * disabled, testing for empty qh->ring and avoiding qh setup costs
1929 * except for the first urb queued after a config change.
1930 */
1931 if (qh || ret)
1932 return ret;
1933
1934 /* Allocate and initialize qh, minimizing the work done each time
1935 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
1936 *
1937 * REVISIT consider a dedicated qh kmem_cache, so it's harder
1938 * for bugs in other kernel code to break this driver...
1939 */
1940 qh = kzalloc(sizeof *qh, mem_flags);
1941 if (!qh) {
1942 spin_lock_irqsave(&musb->lock, flags);
1943 usb_hcd_unlink_urb_from_ep(hcd, urb);
1944 spin_unlock_irqrestore(&musb->lock, flags);
1945 return -ENOMEM;
1946 }
1947
1948 qh->hep = hep;
1949 qh->dev = urb->dev;
1950 INIT_LIST_HEAD(&qh->ring);
1951 qh->is_ready = 1;
1952
1953 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize);
1954 qh->type = usb_endpoint_type(epd);
1955
1956 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
1957 * Some musb cores don't support high bandwidth ISO transfers; and
1958 * we don't (yet!) support high bandwidth interrupt transfers.
1959 */
1960 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
1961 if (qh->hb_mult > 1) {
1962 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
1963
1964 if (ok)
1965 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
1966 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
1967 if (!ok) {
1968 ret = -EMSGSIZE;
1969 goto done;
1970 }
1971 qh->maxpacket &= 0x7ff;
1972 }
1973
1974 qh->epnum = usb_endpoint_num(epd);
1975
1976 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
1977 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
1978
1979 /* precompute rxtype/txtype/type0 register */
1980 type_reg = (qh->type << 4) | qh->epnum;
1981 switch (urb->dev->speed) {
1982 case USB_SPEED_LOW:
1983 type_reg |= 0xc0;
1984 break;
1985 case USB_SPEED_FULL:
1986 type_reg |= 0x80;
1987 break;
1988 default:
1989 type_reg |= 0x40;
1990 }
1991 qh->type_reg = type_reg;
1992
1993 /* Precompute RXINTERVAL/TXINTERVAL register */
1994 switch (qh->type) {
1995 case USB_ENDPOINT_XFER_INT:
1996 /*
1997 * Full/low speeds use the linear encoding,
1998 * high speed uses the logarithmic encoding.
1999 */
2000 if (urb->dev->speed <= USB_SPEED_FULL) {
2001 interval = max_t(u8, epd->bInterval, 1);
2002 break;
2003 }
2004 /* FALLTHROUGH */
2005 case USB_ENDPOINT_XFER_ISOC:
2006 /* ISO always uses logarithmic encoding */
2007 interval = min_t(u8, epd->bInterval, 16);
2008 break;
2009 default:
2010 /* REVISIT we actually want to use NAK limits, hinting to the
2011 * transfer scheduling logic to try some other qh, e.g. try
2012 * for 2 msec first:
2013 *
2014 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
2015 *
2016 * The downside of disabling this is that transfer scheduling
2017 * gets VERY unfair for nonperiodic transfers; a misbehaving
2018 * peripheral could make that hurt. That's perfectly normal
2019 * for reads from network or serial adapters ... so we have
2020 * partial NAKlimit support for bulk RX.
2021 *
2022 * The upside of disabling it is simpler transfer scheduling.
2023 */
2024 interval = 0;
2025 }
2026 qh->intv_reg = interval;
2027
2028 /* precompute addressing for external hub/tt ports */
2029 if (musb->is_multipoint) {
2030 struct usb_device *parent = urb->dev->parent;
2031
2032 if (parent != hcd->self.root_hub) {
2033 qh->h_addr_reg = (u8) parent->devnum;
2034
2035 /* set up tt info if needed */
2036 if (urb->dev->tt) {
2037 qh->h_port_reg = (u8) urb->dev->ttport;
2038 if (urb->dev->tt->hub)
2039 qh->h_addr_reg =
2040 (u8) urb->dev->tt->hub->devnum;
2041 if (urb->dev->tt->multi)
2042 qh->h_addr_reg |= 0x80;
2043 }
2044 }
2045 }
2046
2047 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2048 * until we get real dma queues (with an entry for each urb/buffer),
2049 * we only have work to do in the former case.
2050 */
2051 spin_lock_irqsave(&musb->lock, flags);
2052 if (hep->hcpriv) {
2053 /* some concurrent activity submitted another urb to hep...
2054 * odd, rare, error prone, but legal.
2055 */
2056 kfree(qh);
2057 qh = NULL;
2058 ret = 0;
2059 } else
2060 ret = musb_schedule(musb, qh,
2061 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2062
2063 if (ret == 0) {
2064 urb->hcpriv = qh;
2065 /* FIXME set urb->start_frame for iso/intr, it's tested in
2066 * musb_start_urb(), but otherwise only konicawc cares ...
2067 */
2068 }
2069 spin_unlock_irqrestore(&musb->lock, flags);
2070
2071 done:
2072 if (ret != 0) {
2073 spin_lock_irqsave(&musb->lock, flags);
2074 usb_hcd_unlink_urb_from_ep(hcd, urb);
2075 spin_unlock_irqrestore(&musb->lock, flags);
2076 kfree(qh);
2077 }
2078 return ret;
2079 }
2080
2081
2082 /*
2083 * abort a transfer that's at the head of a hardware queue.
2084 * called with controller locked, irqs blocked
2085 * that hardware queue advances to the next transfer, unless prevented
2086 */
musb_cleanup_urb(struct urb * urb,struct musb_qh * qh)2087 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2088 {
2089 struct musb_hw_ep *ep = qh->hw_ep;
2090 void __iomem *epio = ep->regs;
2091 unsigned hw_end = ep->epnum;
2092 void __iomem *regs = ep->musb->mregs;
2093 int is_in = usb_pipein(urb->pipe);
2094 int status = 0;
2095 u16 csr;
2096
2097 musb_ep_select(regs, hw_end);
2098
2099 if (is_dma_capable()) {
2100 struct dma_channel *dma;
2101
2102 dma = is_in ? ep->rx_channel : ep->tx_channel;
2103 if (dma) {
2104 status = ep->musb->dma_controller->channel_abort(dma);
2105 DBG(status ? 1 : 3,
2106 "abort %cX%d DMA for urb %p --> %d\n",
2107 is_in ? 'R' : 'T', ep->epnum,
2108 urb, status);
2109 urb->actual_length += dma->actual_len;
2110 }
2111 }
2112
2113 /* turn off DMA requests, discard state, stop polling ... */
2114 if (is_in) {
2115 /* giveback saves bulk toggle */
2116 csr = musb_h_flush_rxfifo(ep, 0);
2117
2118 /* REVISIT we still get an irq; should likely clear the
2119 * endpoint's irq status here to avoid bogus irqs.
2120 * clearing that status is platform-specific...
2121 */
2122 } else if (ep->epnum) {
2123 musb_h_tx_flush_fifo(ep);
2124 csr = musb_readw(epio, MUSB_TXCSR);
2125 csr &= ~(MUSB_TXCSR_AUTOSET
2126 | MUSB_TXCSR_DMAENAB
2127 | MUSB_TXCSR_H_RXSTALL
2128 | MUSB_TXCSR_H_NAKTIMEOUT
2129 | MUSB_TXCSR_H_ERROR
2130 | MUSB_TXCSR_TXPKTRDY);
2131 musb_writew(epio, MUSB_TXCSR, csr);
2132 /* REVISIT may need to clear FLUSHFIFO ... */
2133 musb_writew(epio, MUSB_TXCSR, csr);
2134 /* flush cpu writebuffer */
2135 csr = musb_readw(epio, MUSB_TXCSR);
2136 } else {
2137 musb_h_ep0_flush_fifo(ep);
2138 }
2139 if (status == 0)
2140 musb_advance_schedule(ep->musb, urb, ep, is_in);
2141 return status;
2142 }
2143
musb_urb_dequeue(struct usb_hcd * hcd,struct urb * urb,int status)2144 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2145 {
2146 struct musb *musb = hcd_to_musb(hcd);
2147 struct musb_qh *qh;
2148 unsigned long flags;
2149 int is_in = usb_pipein(urb->pipe);
2150 int ret;
2151
2152 DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
2153 usb_pipedevice(urb->pipe),
2154 usb_pipeendpoint(urb->pipe),
2155 is_in ? "in" : "out");
2156
2157 spin_lock_irqsave(&musb->lock, flags);
2158 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2159 if (ret)
2160 goto done;
2161
2162 qh = urb->hcpriv;
2163 if (!qh)
2164 goto done;
2165
2166 /*
2167 * Any URB not actively programmed into endpoint hardware can be
2168 * immediately given back; that's any URB not at the head of an
2169 * endpoint queue, unless someday we get real DMA queues. And even
2170 * if it's at the head, it might not be known to the hardware...
2171 *
2172 * Otherwise abort current transfer, pending DMA, etc.; urb->status
2173 * has already been updated. This is a synchronous abort; it'd be
2174 * OK to hold off until after some IRQ, though.
2175 *
2176 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
2177 */
2178 if (!qh->is_ready
2179 || urb->urb_list.prev != &qh->hep->urb_list
2180 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2181 int ready = qh->is_ready;
2182
2183 qh->is_ready = 0;
2184 musb_giveback(musb, urb, 0);
2185 qh->is_ready = ready;
2186
2187 /* If nothing else (usually musb_giveback) is using it
2188 * and its URB list has emptied, recycle this qh.
2189 */
2190 if (ready && list_empty(&qh->hep->urb_list)) {
2191 qh->hep->hcpriv = NULL;
2192 list_del(&qh->ring);
2193 kfree(qh);
2194 }
2195 } else
2196 ret = musb_cleanup_urb(urb, qh);
2197 done:
2198 spin_unlock_irqrestore(&musb->lock, flags);
2199 return ret;
2200 }
2201
2202 /* disable an endpoint */
2203 static void
musb_h_disable(struct usb_hcd * hcd,struct usb_host_endpoint * hep)2204 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2205 {
2206 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2207 unsigned long flags;
2208 struct musb *musb = hcd_to_musb(hcd);
2209 struct musb_qh *qh;
2210 struct urb *urb;
2211
2212 spin_lock_irqsave(&musb->lock, flags);
2213
2214 qh = hep->hcpriv;
2215 if (qh == NULL)
2216 goto exit;
2217
2218 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2219
2220 /* Kick the first URB off the hardware, if needed */
2221 qh->is_ready = 0;
2222 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2223 urb = next_urb(qh);
2224
2225 /* make software (then hardware) stop ASAP */
2226 if (!urb->unlinked)
2227 urb->status = -ESHUTDOWN;
2228
2229 /* cleanup */
2230 musb_cleanup_urb(urb, qh);
2231
2232 /* Then nuke all the others ... and advance the
2233 * queue on hw_ep (e.g. bulk ring) when we're done.
2234 */
2235 while (!list_empty(&hep->urb_list)) {
2236 urb = next_urb(qh);
2237 urb->status = -ESHUTDOWN;
2238 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2239 }
2240 } else {
2241 /* Just empty the queue; the hardware is busy with
2242 * other transfers, and since !qh->is_ready nothing
2243 * will activate any of these as it advances.
2244 */
2245 while (!list_empty(&hep->urb_list))
2246 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2247
2248 hep->hcpriv = NULL;
2249 list_del(&qh->ring);
2250 kfree(qh);
2251 }
2252 exit:
2253 spin_unlock_irqrestore(&musb->lock, flags);
2254 }
2255
musb_h_get_frame_number(struct usb_hcd * hcd)2256 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2257 {
2258 struct musb *musb = hcd_to_musb(hcd);
2259
2260 return musb_readw(musb->mregs, MUSB_FRAME);
2261 }
2262
musb_h_start(struct usb_hcd * hcd)2263 static int musb_h_start(struct usb_hcd *hcd)
2264 {
2265 struct musb *musb = hcd_to_musb(hcd);
2266
2267 /* NOTE: musb_start() is called when the hub driver turns
2268 * on port power, or when (OTG) peripheral starts.
2269 */
2270 hcd->state = HC_STATE_RUNNING;
2271 musb->port1_status = 0;
2272 return 0;
2273 }
2274
musb_h_stop(struct usb_hcd * hcd)2275 static void musb_h_stop(struct usb_hcd *hcd)
2276 {
2277 musb_stop(hcd_to_musb(hcd));
2278 hcd->state = HC_STATE_HALT;
2279 }
2280
musb_bus_suspend(struct usb_hcd * hcd)2281 static int musb_bus_suspend(struct usb_hcd *hcd)
2282 {
2283 struct musb *musb = hcd_to_musb(hcd);
2284 u8 devctl;
2285
2286 if (!is_host_active(musb))
2287 return 0;
2288
2289 switch (musb->xceiv->state) {
2290 case OTG_STATE_A_SUSPEND:
2291 return 0;
2292 case OTG_STATE_A_WAIT_VRISE:
2293 /* ID could be grounded even if there's no device
2294 * on the other end of the cable. NOTE that the
2295 * A_WAIT_VRISE timers are messy with MUSB...
2296 */
2297 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2298 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2299 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2300 break;
2301 default:
2302 break;
2303 }
2304
2305 if (musb->is_active) {
2306 WARNING("trying to suspend as %s while active\n",
2307 otg_state_string(musb));
2308 return -EBUSY;
2309 } else
2310 return 0;
2311 }
2312
musb_bus_resume(struct usb_hcd * hcd)2313 static int musb_bus_resume(struct usb_hcd *hcd)
2314 {
2315 /* resuming child port does the work */
2316 return 0;
2317 }
2318
2319 const struct hc_driver musb_hc_driver = {
2320 .description = "musb-hcd",
2321 .product_desc = "MUSB HDRC host driver",
2322 .hcd_priv_size = sizeof(struct musb),
2323 .flags = HCD_USB2 | HCD_MEMORY,
2324
2325 /* not using irq handler or reset hooks from usbcore, since
2326 * those must be shared with peripheral code for OTG configs
2327 */
2328
2329 .start = musb_h_start,
2330 .stop = musb_h_stop,
2331
2332 .get_frame_number = musb_h_get_frame_number,
2333
2334 .urb_enqueue = musb_urb_enqueue,
2335 .urb_dequeue = musb_urb_dequeue,
2336 .endpoint_disable = musb_h_disable,
2337
2338 .hub_status_data = musb_hub_status_data,
2339 .hub_control = musb_hub_control,
2340 .bus_suspend = musb_bus_suspend,
2341 .bus_resume = musb_bus_resume,
2342 /* .start_port_reset = NULL, */
2343 /* .hub_irq_enable = NULL, */
2344 };
2345