1 /*
2  * OMAP clock: data structure definitions, function prototypes, shared macros
3  *
4  * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
5  * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6  * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #ifndef __ARCH_ARM_OMAP_CLOCK_H
14 #define __ARCH_ARM_OMAP_CLOCK_H
15 
16 #include <linux/list.h>
17 
18 struct module;
19 struct clk;
20 struct clockdomain;
21 
22 /**
23  * struct clkops - some clock function pointers
24  * @enable: fn ptr that enables the current clock in hardware
25  * @disable: fn ptr that enables the current clock in hardware
26  * @find_idlest: function returning the IDLEST register for the clock's IP blk
27  * @find_companion: function returning the "companion" clk reg for the clock
28  * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
29  * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
30  *
31  * A "companion" clk is an accompanying clock to the one being queried
32  * that must be enabled for the IP module connected to the clock to
33  * become accessible by the hardware.  Neither @find_idlest nor
34  * @find_companion should be needed; that information is IP
35  * block-specific; the hwmod code has been created to handle this, but
36  * until hwmod data is ready and drivers have been converted to use PM
37  * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
38  * @find_companion must, unfortunately, remain.
39  */
40 struct clkops {
41 	int			(*enable)(struct clk *);
42 	void			(*disable)(struct clk *);
43 	void			(*find_idlest)(struct clk *, void __iomem **,
44 					       u8 *, u8 *);
45 	void			(*find_companion)(struct clk *, void __iomem **,
46 						  u8 *);
47 	void			(*allow_idle)(struct clk *);
48 	void			(*deny_idle)(struct clk *);
49 };
50 
51 #ifdef CONFIG_ARCH_OMAP2PLUS
52 
53 /* struct clksel_rate.flags possibilities */
54 #define RATE_IN_242X		(1 << 0)
55 #define RATE_IN_243X		(1 << 1)
56 #define RATE_IN_3430ES1		(1 << 2)	/* 3430ES1 rates only */
57 #define RATE_IN_3430ES2PLUS	(1 << 3)	/* 3430 ES >= 2 rates only */
58 #define RATE_IN_36XX		(1 << 4)
59 #define RATE_IN_4430		(1 << 5)
60 #define RATE_IN_TI816X		(1 << 6)
61 #define RATE_IN_4460		(1 << 7)
62 #define RATE_IN_AM33XX		(1 << 8)
63 #define RATE_IN_TI814X		(1 << 9)
64 
65 #define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)
66 #define RATE_IN_34XX		(RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
67 #define RATE_IN_3XXX		(RATE_IN_34XX | RATE_IN_36XX)
68 #define RATE_IN_44XX		(RATE_IN_4430 | RATE_IN_4460)
69 
70 /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
71 #define RATE_IN_3430ES2PLUS_36XX	(RATE_IN_3430ES2PLUS | RATE_IN_36XX)
72 
73 
74 /**
75  * struct clksel_rate - register bitfield values corresponding to clk divisors
76  * @val: register bitfield value (shifted to bit 0)
77  * @div: clock divisor corresponding to @val
78  * @flags: (see "struct clksel_rate.flags possibilities" above)
79  *
80  * @val should match the value of a read from struct clk.clksel_reg
81  * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
82  *
83  * @div is the divisor that should be applied to the parent clock's rate
84  * to produce the current clock's rate.
85  */
86 struct clksel_rate {
87 	u32			val;
88 	u8			div;
89 	u16			flags;
90 };
91 
92 /**
93  * struct clksel - available parent clocks, and a pointer to their divisors
94  * @parent: struct clk * to a possible parent clock
95  * @rates: available divisors for this parent clock
96  *
97  * A struct clksel is always associated with one or more struct clks
98  * and one or more struct clksel_rates.
99  */
100 struct clksel {
101 	struct clk		 *parent;
102 	const struct clksel_rate *rates;
103 };
104 
105 /**
106  * struct dpll_data - DPLL registers and integration data
107  * @mult_div1_reg: register containing the DPLL M and N bitfields
108  * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
109  * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
110  * @clk_bypass: struct clk pointer to the clock's bypass clock input
111  * @clk_ref: struct clk pointer to the clock's reference clock input
112  * @control_reg: register containing the DPLL mode bitfield
113  * @enable_mask: mask of the DPLL mode bitfield in @control_reg
114  * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
115  * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
116  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
117  * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
118  * @min_divider: minimum valid non-bypass divider value (actual)
119  * @max_divider: maximum valid non-bypass divider value (actual)
120  * @modes: possible values of @enable_mask
121  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
122  * @idlest_reg: register containing the DPLL idle status bitfield
123  * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
124  * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
125  * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
126  * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
127  * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
128  * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
129  * @flags: DPLL type/features (see below)
130  *
131  * Possible values for @flags:
132  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
133  *
134  * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
135  *
136  * XXX Some DPLLs have multiple bypass inputs, so it's not technically
137  * correct to only have one @clk_bypass pointer.
138  *
139  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
140  * @last_rounded_n) should be separated from the runtime-fixed fields
141  * and placed into a different structure, so that the runtime-fixed data
142  * can be placed into read-only space.
143  */
144 struct dpll_data {
145 	void __iomem		*mult_div1_reg;
146 	u32			mult_mask;
147 	u32			div1_mask;
148 	struct clk		*clk_bypass;
149 	struct clk		*clk_ref;
150 	void __iomem		*control_reg;
151 	u32			enable_mask;
152 	unsigned long		last_rounded_rate;
153 	u16			last_rounded_m;
154 	u16			max_multiplier;
155 	u8			last_rounded_n;
156 	u8			min_divider;
157 	u16			max_divider;
158 	u8			modes;
159 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
160 	void __iomem		*autoidle_reg;
161 	void __iomem		*idlest_reg;
162 	u32			autoidle_mask;
163 	u32			freqsel_mask;
164 	u32			idlest_mask;
165 	u32			dco_mask;
166 	u32			sddiv_mask;
167 	u8			auto_recal_bit;
168 	u8			recal_en_bit;
169 	u8			recal_st_bit;
170 #  endif
171 	u8			flags;
172 };
173 
174 #endif
175 
176 /*
177  * struct clk.flags possibilities
178  *
179  * XXX document the rest of the clock flags here
180  *
181  * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
182  *     bits share the same register.  This flag allows the
183  *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
184  *     should be used.  This is a temporary solution - a better approach
185  *     would be to associate clock type-specific data with the clock,
186  *     similar to the struct dpll_data approach.
187  */
188 #define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
189 #define CLOCK_IDLE_CONTROL	(1 << 1)
190 #define CLOCK_NO_IDLE_PARENT	(1 << 2)
191 #define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */
192 #define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
193 #define CLOCK_CLKOUTX2		(1 << 5)
194 
195 /**
196  * struct clk - OMAP struct clk
197  * @node: list_head connecting this clock into the full clock list
198  * @ops: struct clkops * for this clock
199  * @name: the name of the clock in the hardware (used in hwmod data and debug)
200  * @parent: pointer to this clock's parent struct clk
201  * @children: list_head connecting to the child clks' @sibling list_heads
202  * @sibling: list_head connecting this clk to its parent clk's @children
203  * @rate: current clock rate
204  * @enable_reg: register to write to enable the clock (see @enable_bit)
205  * @recalc: fn ptr that returns the clock's current rate
206  * @set_rate: fn ptr that can change the clock's current rate
207  * @round_rate: fn ptr that can round the clock's current rate
208  * @init: fn ptr to do clock-specific initialization
209  * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
210  * @usecount: number of users that have requested this clock to be enabled
211  * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
212  * @flags: see "struct clk.flags possibilities" above
213  * @clksel_reg: for clksel clks, register va containing src/divisor select
214  * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
215  * @clksel: for clksel clks, pointer to struct clksel for this clock
216  * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
217  * @clkdm_name: clockdomain name that this clock is contained in
218  * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
219  * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
220  * @src_offset: bitshift for source selection bitfield (OMAP1 only)
221  *
222  * XXX @rate_offset, @src_offset should probably be removed and OMAP1
223  * clock code converted to use clksel.
224  *
225  * XXX @usecount is poorly named.  It should be "enable_count" or
226  * something similar.  "users" in the description refers to kernel
227  * code (core code or drivers) that have called clk_enable() and not
228  * yet called clk_disable(); the usecount of parent clocks is also
229  * incremented by the clock code when clk_enable() is called on child
230  * clocks and decremented by the clock code when clk_disable() is
231  * called on child clocks.
232  *
233  * XXX @clkdm, @usecount, @children, @sibling should be marked for
234  * internal use only.
235  *
236  * @children and @sibling are used to optimize parent-to-child clock
237  * tree traversals.  (child-to-parent traversals use @parent.)
238  *
239  * XXX The notion of the clock's current rate probably needs to be
240  * separated from the clock's target rate.
241  */
242 struct clk {
243 	struct list_head	node;
244 	const struct clkops	*ops;
245 	const char		*name;
246 	struct clk		*parent;
247 	struct list_head	children;
248 	struct list_head	sibling;	/* node for children */
249 	unsigned long		rate;
250 	void __iomem		*enable_reg;
251 	unsigned long		(*recalc)(struct clk *);
252 	int			(*set_rate)(struct clk *, unsigned long);
253 	long			(*round_rate)(struct clk *, unsigned long);
254 	void			(*init)(struct clk *);
255 	u8			enable_bit;
256 	s8			usecount;
257 	u8			fixed_div;
258 	u8			flags;
259 #ifdef CONFIG_ARCH_OMAP2PLUS
260 	void __iomem		*clksel_reg;
261 	u32			clksel_mask;
262 	const struct clksel	*clksel;
263 	struct dpll_data	*dpll_data;
264 	const char		*clkdm_name;
265 	struct clockdomain	*clkdm;
266 #else
267 	u8			rate_offset;
268 	u8			src_offset;
269 #endif
270 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
271 	struct dentry		*dent;	/* For visible tree hierarchy */
272 #endif
273 };
274 
275 struct clk_functions {
276 	int		(*clk_enable)(struct clk *clk);
277 	void		(*clk_disable)(struct clk *clk);
278 	long		(*clk_round_rate)(struct clk *clk, unsigned long rate);
279 	int		(*clk_set_rate)(struct clk *clk, unsigned long rate);
280 	int		(*clk_set_parent)(struct clk *clk, struct clk *parent);
281 	void		(*clk_allow_idle)(struct clk *clk);
282 	void		(*clk_deny_idle)(struct clk *clk);
283 	void		(*clk_disable_unused)(struct clk *clk);
284 };
285 
286 extern int mpurate;
287 
288 extern int clk_init(struct clk_functions *custom_clocks);
289 extern void clk_preinit(struct clk *clk);
290 extern int clk_register(struct clk *clk);
291 extern void clk_reparent(struct clk *child, struct clk *parent);
292 extern void clk_unregister(struct clk *clk);
293 extern void propagate_rate(struct clk *clk);
294 extern void recalculate_root_clocks(void);
295 extern unsigned long followparent_recalc(struct clk *clk);
296 extern void clk_enable_init_clocks(void);
297 unsigned long omap_fixed_divisor_recalc(struct clk *clk);
298 extern struct clk *omap_clk_get_by_name(const char *name);
299 extern int omap_clk_enable_autoidle_all(void);
300 extern int omap_clk_disable_autoidle_all(void);
301 
302 extern const struct clkops clkops_null;
303 
304 extern struct clk dummy_ck;
305 
306 #endif
307