1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015 MediaTek Inc.
4  */
5 
6 #include <drm/drm_fourcc.h>
7 
8 #include <linux/clk.h>
9 #include <linux/component.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/of_irq.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/soc/mediatek/mtk-cmdq.h>
16 
17 #include "mtk_disp_drv.h"
18 #include "mtk_drm_crtc.h"
19 #include "mtk_drm_ddp_comp.h"
20 
21 #define DISP_REG_OVL_INTEN			0x0004
22 #define OVL_FME_CPL_INT					BIT(1)
23 #define DISP_REG_OVL_INTSTA			0x0008
24 #define DISP_REG_OVL_EN				0x000c
25 #define DISP_REG_OVL_RST			0x0014
26 #define DISP_REG_OVL_ROI_SIZE			0x0020
27 #define DISP_REG_OVL_DATAPATH_CON		0x0024
28 #define OVL_LAYER_SMI_ID_EN				BIT(0)
29 #define OVL_BGCLR_SEL_IN				BIT(2)
30 #define DISP_REG_OVL_ROI_BGCLR			0x0028
31 #define DISP_REG_OVL_SRC_CON			0x002c
32 #define DISP_REG_OVL_CON(n)			(0x0030 + 0x20 * (n))
33 #define DISP_REG_OVL_SRC_SIZE(n)		(0x0038 + 0x20 * (n))
34 #define DISP_REG_OVL_OFFSET(n)			(0x003c + 0x20 * (n))
35 #define DISP_REG_OVL_PITCH(n)			(0x0044 + 0x20 * (n))
36 #define DISP_REG_OVL_RDMA_CTRL(n)		(0x00c0 + 0x20 * (n))
37 #define DISP_REG_OVL_RDMA_GMC(n)		(0x00c8 + 0x20 * (n))
38 #define DISP_REG_OVL_ADDR_MT2701		0x0040
39 #define DISP_REG_OVL_ADDR_MT8173		0x0f40
40 #define DISP_REG_OVL_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n))
41 
42 #define GMC_THRESHOLD_BITS	16
43 #define GMC_THRESHOLD_HIGH	((1 << GMC_THRESHOLD_BITS) / 4)
44 #define GMC_THRESHOLD_LOW	((1 << GMC_THRESHOLD_BITS) / 8)
45 
46 #define OVL_CON_BYTE_SWAP	BIT(24)
47 #define OVL_CON_MTX_YUV_TO_RGB	(6 << 16)
48 #define OVL_CON_CLRFMT_RGB	(1 << 12)
49 #define OVL_CON_CLRFMT_RGBA8888	(2 << 12)
50 #define OVL_CON_CLRFMT_ARGB8888	(3 << 12)
51 #define OVL_CON_CLRFMT_UYVY	(4 << 12)
52 #define OVL_CON_CLRFMT_YUYV	(5 << 12)
53 #define OVL_CON_CLRFMT_RGB565(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
54 					0 : OVL_CON_CLRFMT_RGB)
55 #define OVL_CON_CLRFMT_RGB888(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
56 					OVL_CON_CLRFMT_RGB : 0)
57 #define	OVL_CON_AEN		BIT(8)
58 #define	OVL_CON_ALPHA		0xff
59 #define	OVL_CON_VIRT_FLIP	BIT(9)
60 #define	OVL_CON_HORZ_FLIP	BIT(10)
61 
62 struct mtk_disp_ovl_data {
63 	unsigned int addr;
64 	unsigned int gmc_bits;
65 	unsigned int layer_nr;
66 	bool fmt_rgb565_is_0;
67 	bool smi_id_en;
68 };
69 
70 /*
71  * struct mtk_disp_ovl - DISP_OVL driver structure
72  * @crtc: associated crtc to report vblank events to
73  * @data: platform data
74  */
75 struct mtk_disp_ovl {
76 	struct drm_crtc			*crtc;
77 	struct clk			*clk;
78 	void __iomem			*regs;
79 	struct cmdq_client_reg		cmdq_reg;
80 	const struct mtk_disp_ovl_data	*data;
81 	void				(*vblank_cb)(void *data);
82 	void				*vblank_cb_data;
83 };
84 
mtk_disp_ovl_irq_handler(int irq,void * dev_id)85 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
86 {
87 	struct mtk_disp_ovl *priv = dev_id;
88 
89 	/* Clear frame completion interrupt */
90 	writel(0x0, priv->regs + DISP_REG_OVL_INTSTA);
91 
92 	if (!priv->vblank_cb)
93 		return IRQ_NONE;
94 
95 	priv->vblank_cb(priv->vblank_cb_data);
96 
97 	return IRQ_HANDLED;
98 }
99 
mtk_ovl_register_vblank_cb(struct device * dev,void (* vblank_cb)(void *),void * vblank_cb_data)100 void mtk_ovl_register_vblank_cb(struct device *dev,
101 				void (*vblank_cb)(void *),
102 				void *vblank_cb_data)
103 {
104 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
105 
106 	ovl->vblank_cb = vblank_cb;
107 	ovl->vblank_cb_data = vblank_cb_data;
108 }
109 
mtk_ovl_unregister_vblank_cb(struct device * dev)110 void mtk_ovl_unregister_vblank_cb(struct device *dev)
111 {
112 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
113 
114 	ovl->vblank_cb = NULL;
115 	ovl->vblank_cb_data = NULL;
116 }
117 
mtk_ovl_enable_vblank(struct device * dev)118 void mtk_ovl_enable_vblank(struct device *dev)
119 {
120 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
121 
122 	writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);
123 	writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN);
124 }
125 
mtk_ovl_disable_vblank(struct device * dev)126 void mtk_ovl_disable_vblank(struct device *dev)
127 {
128 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
129 
130 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);
131 }
132 
mtk_ovl_clk_enable(struct device * dev)133 int mtk_ovl_clk_enable(struct device *dev)
134 {
135 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
136 
137 	return clk_prepare_enable(ovl->clk);
138 }
139 
mtk_ovl_clk_disable(struct device * dev)140 void mtk_ovl_clk_disable(struct device *dev)
141 {
142 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
143 
144 	clk_disable_unprepare(ovl->clk);
145 }
146 
mtk_ovl_start(struct device * dev)147 void mtk_ovl_start(struct device *dev)
148 {
149 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
150 
151 	if (ovl->data->smi_id_en) {
152 		unsigned int reg;
153 
154 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
155 		reg = reg | OVL_LAYER_SMI_ID_EN;
156 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
157 	}
158 	writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
159 }
160 
mtk_ovl_stop(struct device * dev)161 void mtk_ovl_stop(struct device *dev)
162 {
163 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
164 
165 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
166 	if (ovl->data->smi_id_en) {
167 		unsigned int reg;
168 
169 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
170 		reg = reg & ~OVL_LAYER_SMI_ID_EN;
171 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
172 	}
173 
174 }
175 
mtk_ovl_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)176 void mtk_ovl_config(struct device *dev, unsigned int w,
177 		    unsigned int h, unsigned int vrefresh,
178 		    unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
179 {
180 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
181 
182 	if (w != 0 && h != 0)
183 		mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,
184 				      DISP_REG_OVL_ROI_SIZE);
185 	mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR);
186 
187 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
188 	mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
189 }
190 
mtk_ovl_layer_nr(struct device * dev)191 unsigned int mtk_ovl_layer_nr(struct device *dev)
192 {
193 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
194 
195 	return ovl->data->layer_nr;
196 }
197 
mtk_ovl_supported_rotations(struct device * dev)198 unsigned int mtk_ovl_supported_rotations(struct device *dev)
199 {
200 	return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
201 	       DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
202 }
203 
mtk_ovl_layer_check(struct device * dev,unsigned int idx,struct mtk_plane_state * mtk_state)204 int mtk_ovl_layer_check(struct device *dev, unsigned int idx,
205 			struct mtk_plane_state *mtk_state)
206 {
207 	struct drm_plane_state *state = &mtk_state->base;
208 	unsigned int rotation = 0;
209 
210 	rotation = drm_rotation_simplify(state->rotation,
211 					 DRM_MODE_ROTATE_0 |
212 					 DRM_MODE_REFLECT_X |
213 					 DRM_MODE_REFLECT_Y);
214 	rotation &= ~DRM_MODE_ROTATE_0;
215 
216 	/* We can only do reflection, not rotation */
217 	if ((rotation & DRM_MODE_ROTATE_MASK) != 0)
218 		return -EINVAL;
219 
220 	/*
221 	 * TODO: Rotating/reflecting YUV buffers is not supported at this time.
222 	 *	 Only RGB[AX] variants are supported.
223 	 */
224 	if (state->fb->format->is_yuv && rotation != 0)
225 		return -EINVAL;
226 
227 	state->rotation = rotation;
228 
229 	return 0;
230 }
231 
mtk_ovl_layer_on(struct device * dev,unsigned int idx,struct cmdq_pkt * cmdq_pkt)232 void mtk_ovl_layer_on(struct device *dev, unsigned int idx,
233 		      struct cmdq_pkt *cmdq_pkt)
234 {
235 	unsigned int gmc_thrshd_l;
236 	unsigned int gmc_thrshd_h;
237 	unsigned int gmc_value;
238 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
239 
240 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
241 		      DISP_REG_OVL_RDMA_CTRL(idx));
242 	gmc_thrshd_l = GMC_THRESHOLD_LOW >>
243 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
244 	gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
245 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
246 	if (ovl->data->gmc_bits == 10)
247 		gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16;
248 	else
249 		gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
250 			    gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
251 	mtk_ddp_write(cmdq_pkt, gmc_value,
252 		      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));
253 	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,
254 			   DISP_REG_OVL_SRC_CON, BIT(idx));
255 }
256 
mtk_ovl_layer_off(struct device * dev,unsigned int idx,struct cmdq_pkt * cmdq_pkt)257 void mtk_ovl_layer_off(struct device *dev, unsigned int idx,
258 		       struct cmdq_pkt *cmdq_pkt)
259 {
260 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
261 
262 	mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
263 			   DISP_REG_OVL_SRC_CON, BIT(idx));
264 	mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
265 		      DISP_REG_OVL_RDMA_CTRL(idx));
266 }
267 
ovl_fmt_convert(struct mtk_disp_ovl * ovl,unsigned int fmt)268 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
269 {
270 	/* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
271 	 * is defined in mediatek HW data sheet.
272 	 * The alphabet order in XXX is no relation to data
273 	 * arrangement in memory.
274 	 */
275 	switch (fmt) {
276 	default:
277 	case DRM_FORMAT_RGB565:
278 		return OVL_CON_CLRFMT_RGB565(ovl);
279 	case DRM_FORMAT_BGR565:
280 		return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP;
281 	case DRM_FORMAT_RGB888:
282 		return OVL_CON_CLRFMT_RGB888(ovl);
283 	case DRM_FORMAT_BGR888:
284 		return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
285 	case DRM_FORMAT_RGBX8888:
286 	case DRM_FORMAT_RGBA8888:
287 		return OVL_CON_CLRFMT_ARGB8888;
288 	case DRM_FORMAT_BGRX8888:
289 	case DRM_FORMAT_BGRA8888:
290 		return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
291 	case DRM_FORMAT_XRGB8888:
292 	case DRM_FORMAT_ARGB8888:
293 		return OVL_CON_CLRFMT_RGBA8888;
294 	case DRM_FORMAT_XBGR8888:
295 	case DRM_FORMAT_ABGR8888:
296 		return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
297 	case DRM_FORMAT_UYVY:
298 		return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;
299 	case DRM_FORMAT_YUYV:
300 		return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB;
301 	}
302 }
303 
mtk_ovl_layer_config(struct device * dev,unsigned int idx,struct mtk_plane_state * state,struct cmdq_pkt * cmdq_pkt)304 void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
305 			  struct mtk_plane_state *state,
306 			  struct cmdq_pkt *cmdq_pkt)
307 {
308 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
309 	struct mtk_plane_pending_state *pending = &state->pending;
310 	unsigned int addr = pending->addr;
311 	unsigned int pitch = pending->pitch & 0xffff;
312 	unsigned int fmt = pending->format;
313 	unsigned int offset = (pending->y << 16) | pending->x;
314 	unsigned int src_size = (pending->height << 16) | pending->width;
315 	unsigned int con;
316 
317 	if (!pending->enable) {
318 		mtk_ovl_layer_off(dev, idx, cmdq_pkt);
319 		return;
320 	}
321 
322 	con = ovl_fmt_convert(ovl, fmt);
323 	if (state->base.fb && state->base.fb->format->has_alpha)
324 		con |= OVL_CON_AEN | OVL_CON_ALPHA;
325 
326 	if (pending->rotation & DRM_MODE_REFLECT_Y) {
327 		con |= OVL_CON_VIRT_FLIP;
328 		addr += (pending->height - 1) * pending->pitch;
329 	}
330 
331 	if (pending->rotation & DRM_MODE_REFLECT_X) {
332 		con |= OVL_CON_HORZ_FLIP;
333 		addr += pending->pitch - 1;
334 	}
335 
336 	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
337 			      DISP_REG_OVL_CON(idx));
338 	mtk_ddp_write_relaxed(cmdq_pkt, pitch, &ovl->cmdq_reg, ovl->regs,
339 			      DISP_REG_OVL_PITCH(idx));
340 	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
341 			      DISP_REG_OVL_SRC_SIZE(idx));
342 	mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,
343 			      DISP_REG_OVL_OFFSET(idx));
344 	mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,
345 			      DISP_REG_OVL_ADDR(ovl, idx));
346 
347 	mtk_ovl_layer_on(dev, idx, cmdq_pkt);
348 }
349 
mtk_ovl_bgclr_in_on(struct device * dev)350 void mtk_ovl_bgclr_in_on(struct device *dev)
351 {
352 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
353 	unsigned int reg;
354 
355 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
356 	reg = reg | OVL_BGCLR_SEL_IN;
357 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
358 }
359 
mtk_ovl_bgclr_in_off(struct device * dev)360 void mtk_ovl_bgclr_in_off(struct device *dev)
361 {
362 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
363 	unsigned int reg;
364 
365 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
366 	reg = reg & ~OVL_BGCLR_SEL_IN;
367 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
368 }
369 
mtk_disp_ovl_bind(struct device * dev,struct device * master,void * data)370 static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
371 			     void *data)
372 {
373 	return 0;
374 }
375 
mtk_disp_ovl_unbind(struct device * dev,struct device * master,void * data)376 static void mtk_disp_ovl_unbind(struct device *dev, struct device *master,
377 				void *data)
378 {
379 }
380 
381 static const struct component_ops mtk_disp_ovl_component_ops = {
382 	.bind	= mtk_disp_ovl_bind,
383 	.unbind = mtk_disp_ovl_unbind,
384 };
385 
mtk_disp_ovl_probe(struct platform_device * pdev)386 static int mtk_disp_ovl_probe(struct platform_device *pdev)
387 {
388 	struct device *dev = &pdev->dev;
389 	struct mtk_disp_ovl *priv;
390 	struct resource *res;
391 	int irq;
392 	int ret;
393 
394 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
395 	if (!priv)
396 		return -ENOMEM;
397 
398 	irq = platform_get_irq(pdev, 0);
399 	if (irq < 0)
400 		return irq;
401 
402 	priv->clk = devm_clk_get(dev, NULL);
403 	if (IS_ERR(priv->clk)) {
404 		dev_err(dev, "failed to get ovl clk\n");
405 		return PTR_ERR(priv->clk);
406 	}
407 
408 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
409 	priv->regs = devm_ioremap_resource(dev, res);
410 	if (IS_ERR(priv->regs)) {
411 		dev_err(dev, "failed to ioremap ovl\n");
412 		return PTR_ERR(priv->regs);
413 	}
414 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
415 	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
416 	if (ret)
417 		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
418 #endif
419 
420 	priv->data = of_device_get_match_data(dev);
421 	platform_set_drvdata(pdev, priv);
422 
423 	ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
424 			       IRQF_TRIGGER_NONE, dev_name(dev), priv);
425 	if (ret < 0) {
426 		dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
427 		return ret;
428 	}
429 
430 	pm_runtime_enable(dev);
431 
432 	ret = component_add(dev, &mtk_disp_ovl_component_ops);
433 	if (ret) {
434 		pm_runtime_disable(dev);
435 		dev_err(dev, "Failed to add component: %d\n", ret);
436 	}
437 
438 	return ret;
439 }
440 
mtk_disp_ovl_remove(struct platform_device * pdev)441 static int mtk_disp_ovl_remove(struct platform_device *pdev)
442 {
443 	component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
444 	pm_runtime_disable(&pdev->dev);
445 
446 	return 0;
447 }
448 
449 static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
450 	.addr = DISP_REG_OVL_ADDR_MT2701,
451 	.gmc_bits = 8,
452 	.layer_nr = 4,
453 	.fmt_rgb565_is_0 = false,
454 };
455 
456 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
457 	.addr = DISP_REG_OVL_ADDR_MT8173,
458 	.gmc_bits = 8,
459 	.layer_nr = 4,
460 	.fmt_rgb565_is_0 = true,
461 };
462 
463 static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
464 	.addr = DISP_REG_OVL_ADDR_MT8173,
465 	.gmc_bits = 10,
466 	.layer_nr = 4,
467 	.fmt_rgb565_is_0 = true,
468 };
469 
470 static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
471 	.addr = DISP_REG_OVL_ADDR_MT8173,
472 	.gmc_bits = 10,
473 	.layer_nr = 2,
474 	.fmt_rgb565_is_0 = true,
475 };
476 
477 static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
478 	.addr = DISP_REG_OVL_ADDR_MT8173,
479 	.gmc_bits = 10,
480 	.layer_nr = 4,
481 	.fmt_rgb565_is_0 = true,
482 	.smi_id_en = true,
483 };
484 
485 static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
486 	.addr = DISP_REG_OVL_ADDR_MT8173,
487 	.gmc_bits = 10,
488 	.layer_nr = 2,
489 	.fmt_rgb565_is_0 = true,
490 	.smi_id_en = true,
491 };
492 
493 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
494 	{ .compatible = "mediatek,mt2701-disp-ovl",
495 	  .data = &mt2701_ovl_driver_data},
496 	{ .compatible = "mediatek,mt8173-disp-ovl",
497 	  .data = &mt8173_ovl_driver_data},
498 	{ .compatible = "mediatek,mt8183-disp-ovl",
499 	  .data = &mt8183_ovl_driver_data},
500 	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
501 	  .data = &mt8183_ovl_2l_driver_data},
502 	{ .compatible = "mediatek,mt8192-disp-ovl",
503 	  .data = &mt8192_ovl_driver_data},
504 	{ .compatible = "mediatek,mt8192-disp-ovl-2l",
505 	  .data = &mt8192_ovl_2l_driver_data},
506 	{},
507 };
508 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
509 
510 struct platform_driver mtk_disp_ovl_driver = {
511 	.probe		= mtk_disp_ovl_probe,
512 	.remove		= mtk_disp_ovl_remove,
513 	.driver		= {
514 		.name	= "mediatek-disp-ovl",
515 		.owner	= THIS_MODULE,
516 		.of_match_table = mtk_disp_ovl_driver_dt_match,
517 	},
518 };
519