1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Jie Qiu <jie.qiu@mediatek.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/of_gpio.h>
14 #include <linux/of_graph.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/types.h>
18
19 #include <video/videomode.h>
20
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_bridge.h>
23 #include <drm/drm_bridge_connector.h>
24 #include <drm/drm_crtc.h>
25 #include <drm/drm_of.h>
26 #include <drm/drm_simple_kms_helper.h>
27
28 #include "mtk_disp_drv.h"
29 #include "mtk_dpi_regs.h"
30 #include "mtk_drm_ddp_comp.h"
31
32 enum mtk_dpi_out_bit_num {
33 MTK_DPI_OUT_BIT_NUM_8BITS,
34 MTK_DPI_OUT_BIT_NUM_10BITS,
35 MTK_DPI_OUT_BIT_NUM_12BITS,
36 MTK_DPI_OUT_BIT_NUM_16BITS
37 };
38
39 enum mtk_dpi_out_yc_map {
40 MTK_DPI_OUT_YC_MAP_RGB,
41 MTK_DPI_OUT_YC_MAP_CYCY,
42 MTK_DPI_OUT_YC_MAP_YCYC,
43 MTK_DPI_OUT_YC_MAP_CY,
44 MTK_DPI_OUT_YC_MAP_YC
45 };
46
47 enum mtk_dpi_out_channel_swap {
48 MTK_DPI_OUT_CHANNEL_SWAP_RGB,
49 MTK_DPI_OUT_CHANNEL_SWAP_GBR,
50 MTK_DPI_OUT_CHANNEL_SWAP_BRG,
51 MTK_DPI_OUT_CHANNEL_SWAP_RBG,
52 MTK_DPI_OUT_CHANNEL_SWAP_GRB,
53 MTK_DPI_OUT_CHANNEL_SWAP_BGR
54 };
55
56 enum mtk_dpi_out_color_format {
57 MTK_DPI_COLOR_FORMAT_RGB
58 };
59
60 struct mtk_dpi {
61 struct drm_encoder encoder;
62 struct drm_bridge bridge;
63 struct drm_bridge *next_bridge;
64 struct drm_connector *connector;
65 void __iomem *regs;
66 struct device *dev;
67 struct clk *engine_clk;
68 struct clk *pixel_clk;
69 struct clk *tvd_clk;
70 int irq;
71 struct drm_display_mode mode;
72 const struct mtk_dpi_conf *conf;
73 enum mtk_dpi_out_color_format color_format;
74 enum mtk_dpi_out_yc_map yc_map;
75 enum mtk_dpi_out_bit_num bit_num;
76 enum mtk_dpi_out_channel_swap channel_swap;
77 struct pinctrl *pinctrl;
78 struct pinctrl_state *pins_gpio;
79 struct pinctrl_state *pins_dpi;
80 u32 output_fmt;
81 int refcount;
82 };
83
bridge_to_dpi(struct drm_bridge * b)84 static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b)
85 {
86 return container_of(b, struct mtk_dpi, bridge);
87 }
88
89 enum mtk_dpi_polarity {
90 MTK_DPI_POLARITY_RISING,
91 MTK_DPI_POLARITY_FALLING,
92 };
93
94 struct mtk_dpi_polarities {
95 enum mtk_dpi_polarity de_pol;
96 enum mtk_dpi_polarity ck_pol;
97 enum mtk_dpi_polarity hsync_pol;
98 enum mtk_dpi_polarity vsync_pol;
99 };
100
101 struct mtk_dpi_sync_param {
102 u32 sync_width;
103 u32 front_porch;
104 u32 back_porch;
105 bool shift_half_line;
106 };
107
108 struct mtk_dpi_yc_limit {
109 u16 y_top;
110 u16 y_bottom;
111 u16 c_top;
112 u16 c_bottom;
113 };
114
115 struct mtk_dpi_conf {
116 unsigned int (*cal_factor)(int clock);
117 u32 reg_h_fre_con;
118 u32 max_clock_khz;
119 bool edge_sel_en;
120 const u32 *output_fmts;
121 u32 num_output_fmts;
122 };
123
mtk_dpi_mask(struct mtk_dpi * dpi,u32 offset,u32 val,u32 mask)124 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
125 {
126 u32 tmp = readl(dpi->regs + offset) & ~mask;
127
128 tmp |= (val & mask);
129 writel(tmp, dpi->regs + offset);
130 }
131
mtk_dpi_sw_reset(struct mtk_dpi * dpi,bool reset)132 static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
133 {
134 mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
135 }
136
mtk_dpi_enable(struct mtk_dpi * dpi)137 static void mtk_dpi_enable(struct mtk_dpi *dpi)
138 {
139 mtk_dpi_mask(dpi, DPI_EN, EN, EN);
140 }
141
mtk_dpi_disable(struct mtk_dpi * dpi)142 static void mtk_dpi_disable(struct mtk_dpi *dpi)
143 {
144 mtk_dpi_mask(dpi, DPI_EN, 0, EN);
145 }
146
mtk_dpi_config_hsync(struct mtk_dpi * dpi,struct mtk_dpi_sync_param * sync)147 static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
148 struct mtk_dpi_sync_param *sync)
149 {
150 mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH,
151 sync->sync_width << HPW, HPW_MASK);
152 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH,
153 sync->back_porch << HBP, HBP_MASK);
154 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
155 HFP_MASK);
156 }
157
mtk_dpi_config_vsync(struct mtk_dpi * dpi,struct mtk_dpi_sync_param * sync,u32 width_addr,u32 porch_addr)158 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi,
159 struct mtk_dpi_sync_param *sync,
160 u32 width_addr, u32 porch_addr)
161 {
162 mtk_dpi_mask(dpi, width_addr,
163 sync->sync_width << VSYNC_WIDTH_SHIFT,
164 VSYNC_WIDTH_MASK);
165 mtk_dpi_mask(dpi, width_addr,
166 sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
167 VSYNC_HALF_LINE_MASK);
168 mtk_dpi_mask(dpi, porch_addr,
169 sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
170 VSYNC_BACK_PORCH_MASK);
171 mtk_dpi_mask(dpi, porch_addr,
172 sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
173 VSYNC_FRONT_PORCH_MASK);
174 }
175
mtk_dpi_config_vsync_lodd(struct mtk_dpi * dpi,struct mtk_dpi_sync_param * sync)176 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi,
177 struct mtk_dpi_sync_param *sync)
178 {
179 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH);
180 }
181
mtk_dpi_config_vsync_leven(struct mtk_dpi * dpi,struct mtk_dpi_sync_param * sync)182 static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi,
183 struct mtk_dpi_sync_param *sync)
184 {
185 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN,
186 DPI_TGEN_VPORCH_LEVEN);
187 }
188
mtk_dpi_config_vsync_rodd(struct mtk_dpi * dpi,struct mtk_dpi_sync_param * sync)189 static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi,
190 struct mtk_dpi_sync_param *sync)
191 {
192 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD,
193 DPI_TGEN_VPORCH_RODD);
194 }
195
mtk_dpi_config_vsync_reven(struct mtk_dpi * dpi,struct mtk_dpi_sync_param * sync)196 static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi,
197 struct mtk_dpi_sync_param *sync)
198 {
199 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN,
200 DPI_TGEN_VPORCH_REVEN);
201 }
202
mtk_dpi_config_pol(struct mtk_dpi * dpi,struct mtk_dpi_polarities * dpi_pol)203 static void mtk_dpi_config_pol(struct mtk_dpi *dpi,
204 struct mtk_dpi_polarities *dpi_pol)
205 {
206 unsigned int pol;
207
208 pol = (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 0 : CK_POL) |
209 (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 0 : DE_POL) |
210 (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) |
211 (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL);
212 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol,
213 CK_POL | DE_POL | HSYNC_POL | VSYNC_POL);
214 }
215
mtk_dpi_config_3d(struct mtk_dpi * dpi,bool en_3d)216 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d)
217 {
218 mtk_dpi_mask(dpi, DPI_CON, en_3d ? TDFP_EN : 0, TDFP_EN);
219 }
220
mtk_dpi_config_interface(struct mtk_dpi * dpi,bool inter)221 static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter)
222 {
223 mtk_dpi_mask(dpi, DPI_CON, inter ? INTL_EN : 0, INTL_EN);
224 }
225
mtk_dpi_config_fb_size(struct mtk_dpi * dpi,u32 width,u32 height)226 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height)
227 {
228 mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK);
229 mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK);
230 }
231
mtk_dpi_config_channel_limit(struct mtk_dpi * dpi,struct mtk_dpi_yc_limit * limit)232 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi,
233 struct mtk_dpi_yc_limit *limit)
234 {
235 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT,
236 Y_LIMINT_BOT_MASK);
237 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP,
238 Y_LIMINT_TOP_MASK);
239 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT,
240 C_LIMIT_BOT_MASK);
241 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP,
242 C_LIMIT_TOP_MASK);
243 }
244
mtk_dpi_config_bit_num(struct mtk_dpi * dpi,enum mtk_dpi_out_bit_num num)245 static void mtk_dpi_config_bit_num(struct mtk_dpi *dpi,
246 enum mtk_dpi_out_bit_num num)
247 {
248 u32 val;
249
250 switch (num) {
251 case MTK_DPI_OUT_BIT_NUM_8BITS:
252 val = OUT_BIT_8;
253 break;
254 case MTK_DPI_OUT_BIT_NUM_10BITS:
255 val = OUT_BIT_10;
256 break;
257 case MTK_DPI_OUT_BIT_NUM_12BITS:
258 val = OUT_BIT_12;
259 break;
260 case MTK_DPI_OUT_BIT_NUM_16BITS:
261 val = OUT_BIT_16;
262 break;
263 default:
264 val = OUT_BIT_8;
265 break;
266 }
267 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << OUT_BIT,
268 OUT_BIT_MASK);
269 }
270
mtk_dpi_config_yc_map(struct mtk_dpi * dpi,enum mtk_dpi_out_yc_map map)271 static void mtk_dpi_config_yc_map(struct mtk_dpi *dpi,
272 enum mtk_dpi_out_yc_map map)
273 {
274 u32 val;
275
276 switch (map) {
277 case MTK_DPI_OUT_YC_MAP_RGB:
278 val = YC_MAP_RGB;
279 break;
280 case MTK_DPI_OUT_YC_MAP_CYCY:
281 val = YC_MAP_CYCY;
282 break;
283 case MTK_DPI_OUT_YC_MAP_YCYC:
284 val = YC_MAP_YCYC;
285 break;
286 case MTK_DPI_OUT_YC_MAP_CY:
287 val = YC_MAP_CY;
288 break;
289 case MTK_DPI_OUT_YC_MAP_YC:
290 val = YC_MAP_YC;
291 break;
292 default:
293 val = YC_MAP_RGB;
294 break;
295 }
296
297 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK);
298 }
299
mtk_dpi_config_channel_swap(struct mtk_dpi * dpi,enum mtk_dpi_out_channel_swap swap)300 static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi,
301 enum mtk_dpi_out_channel_swap swap)
302 {
303 u32 val;
304
305 switch (swap) {
306 case MTK_DPI_OUT_CHANNEL_SWAP_RGB:
307 val = SWAP_RGB;
308 break;
309 case MTK_DPI_OUT_CHANNEL_SWAP_GBR:
310 val = SWAP_GBR;
311 break;
312 case MTK_DPI_OUT_CHANNEL_SWAP_BRG:
313 val = SWAP_BRG;
314 break;
315 case MTK_DPI_OUT_CHANNEL_SWAP_RBG:
316 val = SWAP_RBG;
317 break;
318 case MTK_DPI_OUT_CHANNEL_SWAP_GRB:
319 val = SWAP_GRB;
320 break;
321 case MTK_DPI_OUT_CHANNEL_SWAP_BGR:
322 val = SWAP_BGR;
323 break;
324 default:
325 val = SWAP_RGB;
326 break;
327 }
328
329 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK);
330 }
331
mtk_dpi_config_yuv422_enable(struct mtk_dpi * dpi,bool enable)332 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable)
333 {
334 mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN);
335 }
336
mtk_dpi_config_csc_enable(struct mtk_dpi * dpi,bool enable)337 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable)
338 {
339 mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE);
340 }
341
mtk_dpi_config_swap_input(struct mtk_dpi * dpi,bool enable)342 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
343 {
344 mtk_dpi_mask(dpi, DPI_CON, enable ? IN_RB_SWAP : 0, IN_RB_SWAP);
345 }
346
mtk_dpi_config_2n_h_fre(struct mtk_dpi * dpi)347 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
348 {
349 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
350 }
351
mtk_dpi_config_disable_edge(struct mtk_dpi * dpi)352 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
353 {
354 if (dpi->conf->edge_sel_en)
355 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
356 }
357
mtk_dpi_config_color_format(struct mtk_dpi * dpi,enum mtk_dpi_out_color_format format)358 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
359 enum mtk_dpi_out_color_format format)
360 {
361 /* only support RGB888 */
362 mtk_dpi_config_yuv422_enable(dpi, false);
363 mtk_dpi_config_csc_enable(dpi, false);
364 mtk_dpi_config_swap_input(dpi, false);
365 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
366 }
367
mtk_dpi_dual_edge(struct mtk_dpi * dpi)368 static void mtk_dpi_dual_edge(struct mtk_dpi *dpi)
369 {
370 if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
371 (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) {
372 mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
373 DDR_EN | DDR_4PHASE);
374 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
375 dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ?
376 EDGE_SEL : 0, EDGE_SEL);
377 } else {
378 mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0);
379 }
380 }
381
mtk_dpi_power_off(struct mtk_dpi * dpi)382 static void mtk_dpi_power_off(struct mtk_dpi *dpi)
383 {
384 if (WARN_ON(dpi->refcount == 0))
385 return;
386
387 if (--dpi->refcount != 0)
388 return;
389
390 if (dpi->pinctrl && dpi->pins_gpio)
391 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
392
393 mtk_dpi_disable(dpi);
394 clk_disable_unprepare(dpi->pixel_clk);
395 clk_disable_unprepare(dpi->engine_clk);
396 }
397
mtk_dpi_power_on(struct mtk_dpi * dpi)398 static int mtk_dpi_power_on(struct mtk_dpi *dpi)
399 {
400 int ret;
401
402 if (++dpi->refcount != 1)
403 return 0;
404
405 ret = clk_prepare_enable(dpi->engine_clk);
406 if (ret) {
407 dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret);
408 goto err_refcount;
409 }
410
411 ret = clk_prepare_enable(dpi->pixel_clk);
412 if (ret) {
413 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
414 goto err_pixel;
415 }
416
417 if (dpi->pinctrl && dpi->pins_dpi)
418 pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
419
420 return 0;
421
422 err_pixel:
423 clk_disable_unprepare(dpi->engine_clk);
424 err_refcount:
425 dpi->refcount--;
426 return ret;
427 }
428
mtk_dpi_set_display_mode(struct mtk_dpi * dpi,struct drm_display_mode * mode)429 static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
430 struct drm_display_mode *mode)
431 {
432 struct mtk_dpi_yc_limit limit;
433 struct mtk_dpi_polarities dpi_pol;
434 struct mtk_dpi_sync_param hsync;
435 struct mtk_dpi_sync_param vsync_lodd = { 0 };
436 struct mtk_dpi_sync_param vsync_leven = { 0 };
437 struct mtk_dpi_sync_param vsync_rodd = { 0 };
438 struct mtk_dpi_sync_param vsync_reven = { 0 };
439 struct videomode vm = { 0 };
440 unsigned long pll_rate;
441 unsigned int factor;
442
443 /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
444 factor = dpi->conf->cal_factor(mode->clock);
445 drm_display_mode_to_videomode(mode, &vm);
446 pll_rate = vm.pixelclock * factor;
447
448 dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
449 pll_rate, vm.pixelclock);
450
451 clk_set_rate(dpi->tvd_clk, pll_rate);
452 pll_rate = clk_get_rate(dpi->tvd_clk);
453
454 vm.pixelclock = pll_rate / factor;
455 if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
456 (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
457 clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
458 else
459 clk_set_rate(dpi->pixel_clk, vm.pixelclock);
460
461
462 vm.pixelclock = clk_get_rate(dpi->pixel_clk);
463
464 dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
465 pll_rate, vm.pixelclock);
466
467 limit.c_bottom = 0x0010;
468 limit.c_top = 0x0FE0;
469 limit.y_bottom = 0x0010;
470 limit.y_top = 0x0FE0;
471
472 dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
473 dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
474 dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ?
475 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
476 dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ?
477 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
478 hsync.sync_width = vm.hsync_len;
479 hsync.back_porch = vm.hback_porch;
480 hsync.front_porch = vm.hfront_porch;
481 hsync.shift_half_line = false;
482 vsync_lodd.sync_width = vm.vsync_len;
483 vsync_lodd.back_porch = vm.vback_porch;
484 vsync_lodd.front_porch = vm.vfront_porch;
485 vsync_lodd.shift_half_line = false;
486
487 if (vm.flags & DISPLAY_FLAGS_INTERLACED &&
488 mode->flags & DRM_MODE_FLAG_3D_MASK) {
489 vsync_leven = vsync_lodd;
490 vsync_rodd = vsync_lodd;
491 vsync_reven = vsync_lodd;
492 vsync_leven.shift_half_line = true;
493 vsync_reven.shift_half_line = true;
494 } else if (vm.flags & DISPLAY_FLAGS_INTERLACED &&
495 !(mode->flags & DRM_MODE_FLAG_3D_MASK)) {
496 vsync_leven = vsync_lodd;
497 vsync_leven.shift_half_line = true;
498 } else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) &&
499 mode->flags & DRM_MODE_FLAG_3D_MASK) {
500 vsync_rodd = vsync_lodd;
501 }
502 mtk_dpi_sw_reset(dpi, true);
503 mtk_dpi_config_pol(dpi, &dpi_pol);
504
505 mtk_dpi_config_hsync(dpi, &hsync);
506 mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd);
507 mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd);
508 mtk_dpi_config_vsync_leven(dpi, &vsync_leven);
509 mtk_dpi_config_vsync_reven(dpi, &vsync_reven);
510
511 mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK));
512 mtk_dpi_config_interface(dpi, !!(vm.flags &
513 DISPLAY_FLAGS_INTERLACED));
514 if (vm.flags & DISPLAY_FLAGS_INTERLACED)
515 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1);
516 else
517 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive);
518
519 mtk_dpi_config_channel_limit(dpi, &limit);
520 mtk_dpi_config_bit_num(dpi, dpi->bit_num);
521 mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
522 mtk_dpi_config_yc_map(dpi, dpi->yc_map);
523 mtk_dpi_config_color_format(dpi, dpi->color_format);
524 mtk_dpi_config_2n_h_fre(dpi);
525 mtk_dpi_dual_edge(dpi);
526 mtk_dpi_config_disable_edge(dpi);
527 mtk_dpi_sw_reset(dpi, false);
528
529 return 0;
530 }
531
mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,unsigned int * num_output_fmts)532 static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
533 struct drm_bridge_state *bridge_state,
534 struct drm_crtc_state *crtc_state,
535 struct drm_connector_state *conn_state,
536 unsigned int *num_output_fmts)
537 {
538 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
539 u32 *output_fmts;
540
541 *num_output_fmts = 0;
542
543 if (!dpi->conf->output_fmts) {
544 dev_err(dpi->dev, "output_fmts should not be null\n");
545 return NULL;
546 }
547
548 output_fmts = kcalloc(dpi->conf->num_output_fmts, sizeof(*output_fmts),
549 GFP_KERNEL);
550 if (!output_fmts)
551 return NULL;
552
553 *num_output_fmts = dpi->conf->num_output_fmts;
554
555 memcpy(output_fmts, dpi->conf->output_fmts,
556 sizeof(*output_fmts) * dpi->conf->num_output_fmts);
557
558 return output_fmts;
559 }
560
mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)561 static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
562 struct drm_bridge_state *bridge_state,
563 struct drm_crtc_state *crtc_state,
564 struct drm_connector_state *conn_state,
565 u32 output_fmt,
566 unsigned int *num_input_fmts)
567 {
568 u32 *input_fmts;
569
570 *num_input_fmts = 0;
571
572 input_fmts = kcalloc(1, sizeof(*input_fmts),
573 GFP_KERNEL);
574 if (!input_fmts)
575 return NULL;
576
577 *num_input_fmts = 1;
578 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
579
580 return input_fmts;
581 }
582
mtk_dpi_bridge_atomic_check(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)583 static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge,
584 struct drm_bridge_state *bridge_state,
585 struct drm_crtc_state *crtc_state,
586 struct drm_connector_state *conn_state)
587 {
588 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
589 unsigned int out_bus_format;
590
591 out_bus_format = bridge_state->output_bus_cfg.format;
592
593 if (out_bus_format == MEDIA_BUS_FMT_FIXED)
594 if (dpi->conf->num_output_fmts)
595 out_bus_format = dpi->conf->output_fmts[0];
596
597 dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n",
598 bridge_state->input_bus_cfg.format,
599 bridge_state->output_bus_cfg.format);
600
601 dpi->output_fmt = out_bus_format;
602 dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS;
603 dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB;
604 dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
605 dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
606
607 return 0;
608 }
609
mtk_dpi_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)610 static int mtk_dpi_bridge_attach(struct drm_bridge *bridge,
611 enum drm_bridge_attach_flags flags)
612 {
613 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
614
615 return drm_bridge_attach(bridge->encoder, dpi->next_bridge,
616 &dpi->bridge, flags);
617 }
618
mtk_dpi_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)619 static void mtk_dpi_bridge_mode_set(struct drm_bridge *bridge,
620 const struct drm_display_mode *mode,
621 const struct drm_display_mode *adjusted_mode)
622 {
623 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
624
625 drm_mode_copy(&dpi->mode, adjusted_mode);
626 }
627
mtk_dpi_bridge_disable(struct drm_bridge * bridge)628 static void mtk_dpi_bridge_disable(struct drm_bridge *bridge)
629 {
630 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
631
632 mtk_dpi_power_off(dpi);
633 }
634
mtk_dpi_bridge_enable(struct drm_bridge * bridge)635 static void mtk_dpi_bridge_enable(struct drm_bridge *bridge)
636 {
637 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
638
639 mtk_dpi_power_on(dpi);
640 mtk_dpi_set_display_mode(dpi, &dpi->mode);
641 mtk_dpi_enable(dpi);
642 }
643
644 static enum drm_mode_status
mtk_dpi_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)645 mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge,
646 const struct drm_display_info *info,
647 const struct drm_display_mode *mode)
648 {
649 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
650
651 if (mode->clock > dpi->conf->max_clock_khz)
652 return MODE_CLOCK_HIGH;
653
654 return MODE_OK;
655 }
656
657 static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
658 .attach = mtk_dpi_bridge_attach,
659 .mode_set = mtk_dpi_bridge_mode_set,
660 .mode_valid = mtk_dpi_bridge_mode_valid,
661 .disable = mtk_dpi_bridge_disable,
662 .enable = mtk_dpi_bridge_enable,
663 .atomic_check = mtk_dpi_bridge_atomic_check,
664 .atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts,
665 .atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts,
666 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
667 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
668 .atomic_reset = drm_atomic_helper_bridge_reset,
669 };
670
mtk_dpi_start(struct device * dev)671 void mtk_dpi_start(struct device *dev)
672 {
673 struct mtk_dpi *dpi = dev_get_drvdata(dev);
674
675 mtk_dpi_power_on(dpi);
676 }
677
mtk_dpi_stop(struct device * dev)678 void mtk_dpi_stop(struct device *dev)
679 {
680 struct mtk_dpi *dpi = dev_get_drvdata(dev);
681
682 mtk_dpi_power_off(dpi);
683 }
684
mtk_dpi_bind(struct device * dev,struct device * master,void * data)685 static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
686 {
687 struct mtk_dpi *dpi = dev_get_drvdata(dev);
688 struct drm_device *drm_dev = data;
689 int ret;
690
691 ret = drm_simple_encoder_init(drm_dev, &dpi->encoder,
692 DRM_MODE_ENCODER_TMDS);
693 if (ret) {
694 dev_err(dev, "Failed to initialize decoder: %d\n", ret);
695 return ret;
696 }
697
698 dpi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->dev);
699
700 ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL,
701 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
702 if (ret)
703 goto err_cleanup;
704
705 dpi->connector = drm_bridge_connector_init(drm_dev, &dpi->encoder);
706 if (IS_ERR(dpi->connector)) {
707 dev_err(dev, "Unable to create bridge connector\n");
708 ret = PTR_ERR(dpi->connector);
709 goto err_cleanup;
710 }
711 drm_connector_attach_encoder(dpi->connector, &dpi->encoder);
712
713 return 0;
714
715 err_cleanup:
716 drm_encoder_cleanup(&dpi->encoder);
717 return ret;
718 }
719
mtk_dpi_unbind(struct device * dev,struct device * master,void * data)720 static void mtk_dpi_unbind(struct device *dev, struct device *master,
721 void *data)
722 {
723 struct mtk_dpi *dpi = dev_get_drvdata(dev);
724
725 drm_encoder_cleanup(&dpi->encoder);
726 }
727
728 static const struct component_ops mtk_dpi_component_ops = {
729 .bind = mtk_dpi_bind,
730 .unbind = mtk_dpi_unbind,
731 };
732
mt8173_calculate_factor(int clock)733 static unsigned int mt8173_calculate_factor(int clock)
734 {
735 if (clock <= 27000)
736 return 3 << 4;
737 else if (clock <= 84000)
738 return 3 << 3;
739 else if (clock <= 167000)
740 return 3 << 2;
741 else
742 return 3 << 1;
743 }
744
mt2701_calculate_factor(int clock)745 static unsigned int mt2701_calculate_factor(int clock)
746 {
747 if (clock <= 64000)
748 return 4;
749 else if (clock <= 128000)
750 return 2;
751 else
752 return 1;
753 }
754
mt8183_calculate_factor(int clock)755 static unsigned int mt8183_calculate_factor(int clock)
756 {
757 if (clock <= 27000)
758 return 8;
759 else if (clock <= 167000)
760 return 4;
761 else
762 return 2;
763 }
764
765 static const u32 mt8173_output_fmts[] = {
766 MEDIA_BUS_FMT_RGB888_1X24,
767 };
768
769 static const u32 mt8183_output_fmts[] = {
770 MEDIA_BUS_FMT_RGB888_2X12_LE,
771 MEDIA_BUS_FMT_RGB888_2X12_BE,
772 };
773
774 static const struct mtk_dpi_conf mt8173_conf = {
775 .cal_factor = mt8173_calculate_factor,
776 .reg_h_fre_con = 0xe0,
777 .max_clock_khz = 300000,
778 .output_fmts = mt8173_output_fmts,
779 .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
780 };
781
782 static const struct mtk_dpi_conf mt2701_conf = {
783 .cal_factor = mt2701_calculate_factor,
784 .reg_h_fre_con = 0xb0,
785 .edge_sel_en = true,
786 .max_clock_khz = 150000,
787 .output_fmts = mt8173_output_fmts,
788 .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
789 };
790
791 static const struct mtk_dpi_conf mt8183_conf = {
792 .cal_factor = mt8183_calculate_factor,
793 .reg_h_fre_con = 0xe0,
794 .max_clock_khz = 100000,
795 .output_fmts = mt8183_output_fmts,
796 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
797 };
798
799 static const struct mtk_dpi_conf mt8192_conf = {
800 .cal_factor = mt8183_calculate_factor,
801 .reg_h_fre_con = 0xe0,
802 .max_clock_khz = 150000,
803 .output_fmts = mt8183_output_fmts,
804 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
805 };
806
mtk_dpi_probe(struct platform_device * pdev)807 static int mtk_dpi_probe(struct platform_device *pdev)
808 {
809 struct device *dev = &pdev->dev;
810 struct mtk_dpi *dpi;
811 struct resource *mem;
812 int ret;
813
814 dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
815 if (!dpi)
816 return -ENOMEM;
817
818 dpi->dev = dev;
819 dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev);
820 dpi->output_fmt = MEDIA_BUS_FMT_RGB888_1X24;
821
822 dpi->pinctrl = devm_pinctrl_get(&pdev->dev);
823 if (IS_ERR(dpi->pinctrl)) {
824 dpi->pinctrl = NULL;
825 dev_dbg(&pdev->dev, "Cannot find pinctrl!\n");
826 }
827 if (dpi->pinctrl) {
828 dpi->pins_gpio = pinctrl_lookup_state(dpi->pinctrl, "sleep");
829 if (IS_ERR(dpi->pins_gpio)) {
830 dpi->pins_gpio = NULL;
831 dev_dbg(&pdev->dev, "Cannot find pinctrl idle!\n");
832 }
833 if (dpi->pins_gpio)
834 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
835
836 dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "default");
837 if (IS_ERR(dpi->pins_dpi)) {
838 dpi->pins_dpi = NULL;
839 dev_dbg(&pdev->dev, "Cannot find pinctrl active!\n");
840 }
841 }
842 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
843 dpi->regs = devm_ioremap_resource(dev, mem);
844 if (IS_ERR(dpi->regs)) {
845 ret = PTR_ERR(dpi->regs);
846 dev_err(dev, "Failed to ioremap mem resource: %d\n", ret);
847 return ret;
848 }
849
850 dpi->engine_clk = devm_clk_get(dev, "engine");
851 if (IS_ERR(dpi->engine_clk)) {
852 ret = PTR_ERR(dpi->engine_clk);
853 if (ret != -EPROBE_DEFER)
854 dev_err(dev, "Failed to get engine clock: %d\n", ret);
855
856 return ret;
857 }
858
859 dpi->pixel_clk = devm_clk_get(dev, "pixel");
860 if (IS_ERR(dpi->pixel_clk)) {
861 ret = PTR_ERR(dpi->pixel_clk);
862 if (ret != -EPROBE_DEFER)
863 dev_err(dev, "Failed to get pixel clock: %d\n", ret);
864
865 return ret;
866 }
867
868 dpi->tvd_clk = devm_clk_get(dev, "pll");
869 if (IS_ERR(dpi->tvd_clk)) {
870 ret = PTR_ERR(dpi->tvd_clk);
871 if (ret != -EPROBE_DEFER)
872 dev_err(dev, "Failed to get tvdpll clock: %d\n", ret);
873
874 return ret;
875 }
876
877 dpi->irq = platform_get_irq(pdev, 0);
878 if (dpi->irq <= 0)
879 return -EINVAL;
880
881 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
882 NULL, &dpi->next_bridge);
883 if (ret)
884 return ret;
885
886 dev_info(dev, "Found bridge node: %pOF\n", dpi->next_bridge->of_node);
887
888 platform_set_drvdata(pdev, dpi);
889
890 dpi->bridge.funcs = &mtk_dpi_bridge_funcs;
891 dpi->bridge.of_node = dev->of_node;
892 dpi->bridge.type = DRM_MODE_CONNECTOR_DPI;
893
894 drm_bridge_add(&dpi->bridge);
895
896 ret = component_add(dev, &mtk_dpi_component_ops);
897 if (ret) {
898 drm_bridge_remove(&dpi->bridge);
899 dev_err(dev, "Failed to add component: %d\n", ret);
900 return ret;
901 }
902
903 return 0;
904 }
905
mtk_dpi_remove(struct platform_device * pdev)906 static int mtk_dpi_remove(struct platform_device *pdev)
907 {
908 struct mtk_dpi *dpi = platform_get_drvdata(pdev);
909
910 component_del(&pdev->dev, &mtk_dpi_component_ops);
911 drm_bridge_remove(&dpi->bridge);
912
913 return 0;
914 }
915
916 static const struct of_device_id mtk_dpi_of_ids[] = {
917 { .compatible = "mediatek,mt2701-dpi",
918 .data = &mt2701_conf,
919 },
920 { .compatible = "mediatek,mt8173-dpi",
921 .data = &mt8173_conf,
922 },
923 { .compatible = "mediatek,mt8183-dpi",
924 .data = &mt8183_conf,
925 },
926 { .compatible = "mediatek,mt8192-dpi",
927 .data = &mt8192_conf,
928 },
929 { },
930 };
931 MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
932
933 struct platform_driver mtk_dpi_driver = {
934 .probe = mtk_dpi_probe,
935 .remove = mtk_dpi_remove,
936 .driver = {
937 .name = "mediatek-dpi",
938 .of_match_table = mtk_dpi_of_ids,
939 },
940 };
941