1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl
4 *
5 * Copyright (c) 2021 MediaTek Inc.
6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
7 * Trevor Wu <trevor.wu@mediatek.com>
8 */
9
10 #include <linux/clk.h>
11
12 #include "mt8195-afe-common.h"
13 #include "mt8195-afe-clk.h"
14 #include "mt8195-reg.h"
15 #include "mt8195-audsys-clk.h"
16
17 static const char *aud_clks[MT8195_CLK_NUM] = {
18 /* xtal */
19 [MT8195_CLK_XTAL_26M] = "clk26m",
20 /* divider */
21 [MT8195_CLK_TOP_APLL1] = "apll1_ck",
22 [MT8195_CLK_TOP_APLL2] = "apll2_ck",
23 [MT8195_CLK_TOP_APLL12_DIV0] = "apll12_div0",
24 [MT8195_CLK_TOP_APLL12_DIV1] = "apll12_div1",
25 [MT8195_CLK_TOP_APLL12_DIV2] = "apll12_div2",
26 [MT8195_CLK_TOP_APLL12_DIV3] = "apll12_div3",
27 [MT8195_CLK_TOP_APLL12_DIV9] = "apll12_div9",
28 /* mux */
29 [MT8195_CLK_TOP_A1SYS_HP_SEL] = "a1sys_hp_sel",
30 [MT8195_CLK_TOP_AUD_INTBUS_SEL] = "aud_intbus_sel",
31 [MT8195_CLK_TOP_AUDIO_H_SEL] = "audio_h_sel",
32 [MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "audio_local_bus_sel",
33 [MT8195_CLK_TOP_DPTX_M_SEL] = "dptx_m_sel",
34 [MT8195_CLK_TOP_I2SO1_M_SEL] = "i2so1_m_sel",
35 [MT8195_CLK_TOP_I2SO2_M_SEL] = "i2so2_m_sel",
36 [MT8195_CLK_TOP_I2SI1_M_SEL] = "i2si1_m_sel",
37 [MT8195_CLK_TOP_I2SI2_M_SEL] = "i2si2_m_sel",
38 /* clock gate */
39 [MT8195_CLK_INFRA_AO_AUDIO_26M_B] = "infra_ao_audio_26m_b",
40 [MT8195_CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp",
41 /* afe clock gate */
42 [MT8195_CLK_AUD_AFE] = "aud_afe",
43 [MT8195_CLK_AUD_APLL1_TUNER] = "aud_apll1_tuner",
44 [MT8195_CLK_AUD_APLL2_TUNER] = "aud_apll2_tuner",
45 [MT8195_CLK_AUD_APLL] = "aud_apll",
46 [MT8195_CLK_AUD_APLL2] = "aud_apll2",
47 [MT8195_CLK_AUD_DAC] = "aud_dac",
48 [MT8195_CLK_AUD_ADC] = "aud_adc",
49 [MT8195_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
50 [MT8195_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
51 [MT8195_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
52 [MT8195_CLK_AUD_ADDA6_ADC] = "aud_adda6_adc",
53 [MT8195_CLK_AUD_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires",
54 [MT8195_CLK_AUD_I2SIN] = "aud_i2sin",
55 [MT8195_CLK_AUD_TDM_IN] = "aud_tdm_in",
56 [MT8195_CLK_AUD_I2S_OUT] = "aud_i2s_out",
57 [MT8195_CLK_AUD_TDM_OUT] = "aud_tdm_out",
58 [MT8195_CLK_AUD_HDMI_OUT] = "aud_hdmi_out",
59 [MT8195_CLK_AUD_ASRC11] = "aud_asrc11",
60 [MT8195_CLK_AUD_ASRC12] = "aud_asrc12",
61 [MT8195_CLK_AUD_A1SYS] = "aud_a1sys",
62 [MT8195_CLK_AUD_A2SYS] = "aud_a2sys",
63 [MT8195_CLK_AUD_PCMIF] = "aud_pcmif",
64 [MT8195_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1",
65 [MT8195_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2",
66 [MT8195_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3",
67 [MT8195_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4",
68 [MT8195_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5",
69 [MT8195_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6",
70 [MT8195_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8",
71 [MT8195_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9",
72 [MT8195_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10",
73 [MT8195_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2",
74 [MT8195_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3",
75 [MT8195_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6",
76 [MT8195_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7",
77 [MT8195_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8",
78 [MT8195_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10",
79 [MT8195_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11",
80 };
81
82 struct mt8195_afe_tuner_cfg {
83 unsigned int id;
84 int apll_div_reg;
85 unsigned int apll_div_shift;
86 unsigned int apll_div_maskbit;
87 unsigned int apll_div_default;
88 int ref_ck_sel_reg;
89 unsigned int ref_ck_sel_shift;
90 unsigned int ref_ck_sel_maskbit;
91 unsigned int ref_ck_sel_default;
92 int tuner_en_reg;
93 unsigned int tuner_en_shift;
94 unsigned int tuner_en_maskbit;
95 int upper_bound_reg;
96 unsigned int upper_bound_shift;
97 unsigned int upper_bound_maskbit;
98 unsigned int upper_bound_default;
99 spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/
100 int ref_cnt;
101 };
102
103 static struct mt8195_afe_tuner_cfg mt8195_afe_tuner_cfgs[MT8195_AUD_PLL_NUM] = {
104 [MT8195_AUD_PLL1] = {
105 .id = MT8195_AUD_PLL1,
106 .apll_div_reg = AFE_APLL_TUNER_CFG,
107 .apll_div_shift = 4,
108 .apll_div_maskbit = 0xf,
109 .apll_div_default = 0x7,
110 .ref_ck_sel_reg = AFE_APLL_TUNER_CFG,
111 .ref_ck_sel_shift = 1,
112 .ref_ck_sel_maskbit = 0x3,
113 .ref_ck_sel_default = 0x2,
114 .tuner_en_reg = AFE_APLL_TUNER_CFG,
115 .tuner_en_shift = 0,
116 .tuner_en_maskbit = 0x1,
117 .upper_bound_reg = AFE_APLL_TUNER_CFG,
118 .upper_bound_shift = 8,
119 .upper_bound_maskbit = 0xff,
120 .upper_bound_default = 0x2,
121 },
122 [MT8195_AUD_PLL2] = {
123 .id = MT8195_AUD_PLL2,
124 .apll_div_reg = AFE_APLL_TUNER_CFG1,
125 .apll_div_shift = 4,
126 .apll_div_maskbit = 0xf,
127 .apll_div_default = 0x7,
128 .ref_ck_sel_reg = AFE_APLL_TUNER_CFG1,
129 .ref_ck_sel_shift = 1,
130 .ref_ck_sel_maskbit = 0x3,
131 .ref_ck_sel_default = 0x1,
132 .tuner_en_reg = AFE_APLL_TUNER_CFG1,
133 .tuner_en_shift = 0,
134 .tuner_en_maskbit = 0x1,
135 .upper_bound_reg = AFE_APLL_TUNER_CFG1,
136 .upper_bound_shift = 8,
137 .upper_bound_maskbit = 0xff,
138 .upper_bound_default = 0x2,
139 },
140 [MT8195_AUD_PLL3] = {
141 .id = MT8195_AUD_PLL3,
142 .apll_div_reg = AFE_EARC_APLL_TUNER_CFG,
143 .apll_div_shift = 4,
144 .apll_div_maskbit = 0x3f,
145 .apll_div_default = 0x3,
146 .ref_ck_sel_reg = AFE_EARC_APLL_TUNER_CFG,
147 .ref_ck_sel_shift = 24,
148 .ref_ck_sel_maskbit = 0x3,
149 .ref_ck_sel_default = 0x0,
150 .tuner_en_reg = AFE_EARC_APLL_TUNER_CFG,
151 .tuner_en_shift = 0,
152 .tuner_en_maskbit = 0x1,
153 .upper_bound_reg = AFE_EARC_APLL_TUNER_CFG,
154 .upper_bound_shift = 12,
155 .upper_bound_maskbit = 0xff,
156 .upper_bound_default = 0x4,
157 },
158 [MT8195_AUD_PLL4] = {
159 .id = MT8195_AUD_PLL4,
160 .apll_div_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
161 .apll_div_shift = 4,
162 .apll_div_maskbit = 0x3f,
163 .apll_div_default = 0x7,
164 .ref_ck_sel_reg = AFE_SPDIFIN_APLL_TUNER_CFG1,
165 .ref_ck_sel_shift = 8,
166 .ref_ck_sel_maskbit = 0x1,
167 .ref_ck_sel_default = 0,
168 .tuner_en_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
169 .tuner_en_shift = 0,
170 .tuner_en_maskbit = 0x1,
171 .upper_bound_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
172 .upper_bound_shift = 12,
173 .upper_bound_maskbit = 0xff,
174 .upper_bound_default = 0x4,
175 },
176 [MT8195_AUD_PLL5] = {
177 .id = MT8195_AUD_PLL5,
178 .apll_div_reg = AFE_LINEIN_APLL_TUNER_CFG,
179 .apll_div_shift = 4,
180 .apll_div_maskbit = 0x3f,
181 .apll_div_default = 0x3,
182 .ref_ck_sel_reg = AFE_LINEIN_APLL_TUNER_CFG,
183 .ref_ck_sel_shift = 24,
184 .ref_ck_sel_maskbit = 0x1,
185 .ref_ck_sel_default = 0,
186 .tuner_en_reg = AFE_LINEIN_APLL_TUNER_CFG,
187 .tuner_en_shift = 0,
188 .tuner_en_maskbit = 0x1,
189 .upper_bound_reg = AFE_LINEIN_APLL_TUNER_CFG,
190 .upper_bound_shift = 12,
191 .upper_bound_maskbit = 0xff,
192 .upper_bound_default = 0x4,
193 },
194 };
195
mt8195_afe_found_apll_tuner(unsigned int id)196 static struct mt8195_afe_tuner_cfg *mt8195_afe_found_apll_tuner(unsigned int id)
197 {
198 if (id >= MT8195_AUD_PLL_NUM)
199 return NULL;
200
201 return &mt8195_afe_tuner_cfgs[id];
202 }
203
mt8195_afe_init_apll_tuner(unsigned int id)204 static int mt8195_afe_init_apll_tuner(unsigned int id)
205 {
206 struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id);
207
208 if (!cfg)
209 return -EINVAL;
210
211 cfg->ref_cnt = 0;
212 spin_lock_init(&cfg->ctrl_lock);
213
214 return 0;
215 }
216
mt8195_afe_setup_apll_tuner(struct mtk_base_afe * afe,unsigned int id)217 static int mt8195_afe_setup_apll_tuner(struct mtk_base_afe *afe,
218 unsigned int id)
219 {
220 const struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id);
221
222 if (!cfg)
223 return -EINVAL;
224
225 regmap_update_bits(afe->regmap, cfg->apll_div_reg,
226 cfg->apll_div_maskbit << cfg->apll_div_shift,
227 cfg->apll_div_default << cfg->apll_div_shift);
228
229 regmap_update_bits(afe->regmap, cfg->ref_ck_sel_reg,
230 cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift,
231 cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift);
232
233 regmap_update_bits(afe->regmap, cfg->upper_bound_reg,
234 cfg->upper_bound_maskbit << cfg->upper_bound_shift,
235 cfg->upper_bound_default << cfg->upper_bound_shift);
236
237 return 0;
238 }
239
mt8195_afe_enable_tuner_clk(struct mtk_base_afe * afe,unsigned int id)240 static int mt8195_afe_enable_tuner_clk(struct mtk_base_afe *afe,
241 unsigned int id)
242 {
243 struct mt8195_afe_private *afe_priv = afe->platform_priv;
244
245 switch (id) {
246 case MT8195_AUD_PLL1:
247 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]);
248 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]);
249 break;
250 case MT8195_AUD_PLL2:
251 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]);
252 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]);
253 break;
254 default:
255 break;
256 }
257
258 return 0;
259 }
260
mt8195_afe_disable_tuner_clk(struct mtk_base_afe * afe,unsigned int id)261 static int mt8195_afe_disable_tuner_clk(struct mtk_base_afe *afe,
262 unsigned int id)
263 {
264 struct mt8195_afe_private *afe_priv = afe->platform_priv;
265
266 switch (id) {
267 case MT8195_AUD_PLL1:
268 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]);
269 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]);
270 break;
271 case MT8195_AUD_PLL2:
272 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]);
273 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]);
274 break;
275 default:
276 break;
277 }
278
279 return 0;
280 }
281
mt8195_afe_enable_apll_tuner(struct mtk_base_afe * afe,unsigned int id)282 static int mt8195_afe_enable_apll_tuner(struct mtk_base_afe *afe,
283 unsigned int id)
284 {
285 struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id);
286 unsigned long flags;
287 int ret = 0;
288
289 if (!cfg)
290 return -EINVAL;
291
292 ret = mt8195_afe_setup_apll_tuner(afe, id);
293 if (ret)
294 return ret;
295
296 ret = mt8195_afe_enable_tuner_clk(afe, id);
297 if (ret)
298 return ret;
299
300 spin_lock_irqsave(&cfg->ctrl_lock, flags);
301
302 cfg->ref_cnt++;
303 if (cfg->ref_cnt == 1)
304 regmap_update_bits(afe->regmap,
305 cfg->tuner_en_reg,
306 cfg->tuner_en_maskbit << cfg->tuner_en_shift,
307 1 << cfg->tuner_en_shift);
308
309 spin_unlock_irqrestore(&cfg->ctrl_lock, flags);
310
311 return ret;
312 }
313
mt8195_afe_disable_apll_tuner(struct mtk_base_afe * afe,unsigned int id)314 static int mt8195_afe_disable_apll_tuner(struct mtk_base_afe *afe,
315 unsigned int id)
316 {
317 struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id);
318 unsigned long flags;
319 int ret = 0;
320
321 if (!cfg)
322 return -EINVAL;
323
324 spin_lock_irqsave(&cfg->ctrl_lock, flags);
325
326 cfg->ref_cnt--;
327 if (cfg->ref_cnt == 0)
328 regmap_update_bits(afe->regmap,
329 cfg->tuner_en_reg,
330 cfg->tuner_en_maskbit << cfg->tuner_en_shift,
331 0 << cfg->tuner_en_shift);
332 else if (cfg->ref_cnt < 0)
333 cfg->ref_cnt = 0;
334
335 spin_unlock_irqrestore(&cfg->ctrl_lock, flags);
336
337 ret = mt8195_afe_disable_tuner_clk(afe, id);
338 if (ret)
339 return ret;
340
341 return ret;
342 }
343
mt8195_afe_get_mclk_source_clk_id(int sel)344 int mt8195_afe_get_mclk_source_clk_id(int sel)
345 {
346 switch (sel) {
347 case MT8195_MCK_SEL_26M:
348 return MT8195_CLK_XTAL_26M;
349 case MT8195_MCK_SEL_APLL1:
350 return MT8195_CLK_TOP_APLL1;
351 case MT8195_MCK_SEL_APLL2:
352 return MT8195_CLK_TOP_APLL2;
353 default:
354 return -EINVAL;
355 }
356 }
357
mt8195_afe_get_mclk_source_rate(struct mtk_base_afe * afe,int apll)358 int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
359 {
360 struct mt8195_afe_private *afe_priv = afe->platform_priv;
361 int clk_id = mt8195_afe_get_mclk_source_clk_id(apll);
362
363 if (clk_id < 0) {
364 dev_dbg(afe->dev, "invalid clk id\n");
365 return 0;
366 }
367
368 return clk_get_rate(afe_priv->clk[clk_id]);
369 }
370
mt8195_afe_get_default_mclk_source_by_rate(int rate)371 int mt8195_afe_get_default_mclk_source_by_rate(int rate)
372 {
373 return ((rate % 8000) == 0) ?
374 MT8195_MCK_SEL_APLL1 : MT8195_MCK_SEL_APLL2;
375 }
376
mt8195_afe_init_clock(struct mtk_base_afe * afe)377 int mt8195_afe_init_clock(struct mtk_base_afe *afe)
378 {
379 struct mt8195_afe_private *afe_priv = afe->platform_priv;
380 int i, ret;
381
382 mt8195_audsys_clk_register(afe);
383
384 afe_priv->clk =
385 devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk),
386 GFP_KERNEL);
387 if (!afe_priv->clk)
388 return -ENOMEM;
389
390 for (i = 0; i < MT8195_CLK_NUM; i++) {
391 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
392 if (IS_ERR(afe_priv->clk[i])) {
393 dev_dbg(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
394 __func__, aud_clks[i],
395 PTR_ERR(afe_priv->clk[i]));
396 return PTR_ERR(afe_priv->clk[i]);
397 }
398 }
399
400 /* initial tuner */
401 for (i = 0; i < MT8195_AUD_PLL_NUM; i++) {
402 ret = mt8195_afe_init_apll_tuner(i);
403 if (ret) {
404 dev_dbg(afe->dev, "%s(), init apll_tuner%d failed",
405 __func__, (i + 1));
406 return -EINVAL;
407 }
408 }
409
410 return 0;
411 }
412
mt8195_afe_deinit_clock(struct mtk_base_afe * afe)413 void mt8195_afe_deinit_clock(struct mtk_base_afe *afe)
414 {
415 mt8195_audsys_clk_unregister(afe);
416 }
417
mt8195_afe_enable_clk(struct mtk_base_afe * afe,struct clk * clk)418 int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
419 {
420 int ret;
421
422 if (clk) {
423 ret = clk_prepare_enable(clk);
424 if (ret) {
425 dev_dbg(afe->dev, "%s(), failed to enable clk\n",
426 __func__);
427 return ret;
428 }
429 } else {
430 dev_dbg(afe->dev, "NULL clk\n");
431 }
432 return 0;
433 }
434 EXPORT_SYMBOL_GPL(mt8195_afe_enable_clk);
435
mt8195_afe_disable_clk(struct mtk_base_afe * afe,struct clk * clk)436 void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
437 {
438 if (clk)
439 clk_disable_unprepare(clk);
440 else
441 dev_dbg(afe->dev, "NULL clk\n");
442 }
443 EXPORT_SYMBOL_GPL(mt8195_afe_disable_clk);
444
mt8195_afe_prepare_clk(struct mtk_base_afe * afe,struct clk * clk)445 int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk)
446 {
447 int ret;
448
449 if (clk) {
450 ret = clk_prepare(clk);
451 if (ret) {
452 dev_dbg(afe->dev, "%s(), failed to prepare clk\n",
453 __func__);
454 return ret;
455 }
456 } else {
457 dev_dbg(afe->dev, "NULL clk\n");
458 }
459 return 0;
460 }
461
mt8195_afe_unprepare_clk(struct mtk_base_afe * afe,struct clk * clk)462 void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk)
463 {
464 if (clk)
465 clk_unprepare(clk);
466 else
467 dev_dbg(afe->dev, "NULL clk\n");
468 }
469
mt8195_afe_enable_clk_atomic(struct mtk_base_afe * afe,struct clk * clk)470 int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
471 {
472 int ret;
473
474 if (clk) {
475 ret = clk_enable(clk);
476 if (ret) {
477 dev_dbg(afe->dev, "%s(), failed to clk enable\n",
478 __func__);
479 return ret;
480 }
481 } else {
482 dev_dbg(afe->dev, "NULL clk\n");
483 }
484 return 0;
485 }
486
mt8195_afe_disable_clk_atomic(struct mtk_base_afe * afe,struct clk * clk)487 void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
488 {
489 if (clk)
490 clk_disable(clk);
491 else
492 dev_dbg(afe->dev, "NULL clk\n");
493 }
494
mt8195_afe_set_clk_rate(struct mtk_base_afe * afe,struct clk * clk,unsigned int rate)495 int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
496 unsigned int rate)
497 {
498 int ret;
499
500 if (clk) {
501 ret = clk_set_rate(clk, rate);
502 if (ret) {
503 dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
504 __func__);
505 return ret;
506 }
507 }
508
509 return 0;
510 }
511
mt8195_afe_set_clk_parent(struct mtk_base_afe * afe,struct clk * clk,struct clk * parent)512 int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
513 struct clk *parent)
514 {
515 int ret;
516
517 if (clk && parent) {
518 ret = clk_set_parent(clk, parent);
519 if (ret) {
520 dev_dbg(afe->dev, "%s(), failed to set clk parent\n",
521 __func__);
522 return ret;
523 }
524 }
525
526 return 0;
527 }
528
get_top_cg_reg(unsigned int cg_type)529 static unsigned int get_top_cg_reg(unsigned int cg_type)
530 {
531 switch (cg_type) {
532 case MT8195_TOP_CG_A1SYS_TIMING:
533 case MT8195_TOP_CG_A2SYS_TIMING:
534 case MT8195_TOP_CG_26M_TIMING:
535 return ASYS_TOP_CON;
536 default:
537 return 0;
538 }
539 }
540
get_top_cg_mask(unsigned int cg_type)541 static unsigned int get_top_cg_mask(unsigned int cg_type)
542 {
543 switch (cg_type) {
544 case MT8195_TOP_CG_A1SYS_TIMING:
545 return ASYS_TOP_CON_A1SYS_TIMING_ON;
546 case MT8195_TOP_CG_A2SYS_TIMING:
547 return ASYS_TOP_CON_A2SYS_TIMING_ON;
548 case MT8195_TOP_CG_26M_TIMING:
549 return ASYS_TOP_CON_26M_TIMING_ON;
550 default:
551 return 0;
552 }
553 }
554
get_top_cg_on_val(unsigned int cg_type)555 static unsigned int get_top_cg_on_val(unsigned int cg_type)
556 {
557 switch (cg_type) {
558 case MT8195_TOP_CG_A1SYS_TIMING:
559 case MT8195_TOP_CG_A2SYS_TIMING:
560 case MT8195_TOP_CG_26M_TIMING:
561 return get_top_cg_mask(cg_type);
562 default:
563 return 0;
564 }
565 }
566
get_top_cg_off_val(unsigned int cg_type)567 static unsigned int get_top_cg_off_val(unsigned int cg_type)
568 {
569 switch (cg_type) {
570 case MT8195_TOP_CG_A1SYS_TIMING:
571 case MT8195_TOP_CG_A2SYS_TIMING:
572 case MT8195_TOP_CG_26M_TIMING:
573 return 0;
574 default:
575 return get_top_cg_mask(cg_type);
576 }
577 }
578
mt8195_afe_enable_top_cg(struct mtk_base_afe * afe,unsigned int cg_type)579 static int mt8195_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
580 {
581 unsigned int reg = get_top_cg_reg(cg_type);
582 unsigned int mask = get_top_cg_mask(cg_type);
583 unsigned int val = get_top_cg_on_val(cg_type);
584
585 regmap_update_bits(afe->regmap, reg, mask, val);
586 return 0;
587 }
588
mt8195_afe_disable_top_cg(struct mtk_base_afe * afe,unsigned int cg_type)589 static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
590 {
591 unsigned int reg = get_top_cg_reg(cg_type);
592 unsigned int mask = get_top_cg_mask(cg_type);
593 unsigned int val = get_top_cg_off_val(cg_type);
594
595 regmap_update_bits(afe->regmap, reg, mask, val);
596 return 0;
597 }
598
mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe * afe)599 int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
600 {
601 struct mt8195_afe_private *afe_priv = afe->platform_priv;
602 int i;
603 static const unsigned int clk_array[] = {
604 MT8195_CLK_SCP_ADSP_AUDIODSP, /* bus clock for infra */
605 MT8195_CLK_TOP_AUDIO_H_SEL, /* clock for ADSP bus */
606 MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, /* bus clock for DRAM access */
607 MT8195_CLK_TOP_AUD_INTBUS_SEL, /* bus clock for AFE SRAM access */
608 MT8195_CLK_INFRA_AO_AUDIO_26M_B, /* audio 26M clock */
609 MT8195_CLK_AUD_AFE, /* AFE HW master switch */
610 MT8195_CLK_AUD_A1SYS_HP, /* AFE HW clock*/
611 MT8195_CLK_AUD_A1SYS, /* AFE HW clock */
612 };
613
614 for (i = 0; i < ARRAY_SIZE(clk_array); i++)
615 mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
616
617 return 0;
618 }
619
mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe * afe)620 int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
621 {
622 struct mt8195_afe_private *afe_priv = afe->platform_priv;
623 int i;
624 static const unsigned int clk_array[] = {
625 MT8195_CLK_AUD_A1SYS,
626 MT8195_CLK_AUD_A1SYS_HP,
627 MT8195_CLK_AUD_AFE,
628 MT8195_CLK_INFRA_AO_AUDIO_26M_B,
629 MT8195_CLK_TOP_AUD_INTBUS_SEL,
630 MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
631 MT8195_CLK_TOP_AUDIO_H_SEL,
632 MT8195_CLK_SCP_ADSP_AUDIODSP,
633 };
634
635 for (i = 0; i < ARRAY_SIZE(clk_array); i++)
636 mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
637
638 return 0;
639 }
640
mt8195_afe_enable_afe_on(struct mtk_base_afe * afe)641 static int mt8195_afe_enable_afe_on(struct mtk_base_afe *afe)
642 {
643 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
644 return 0;
645 }
646
mt8195_afe_disable_afe_on(struct mtk_base_afe * afe)647 static int mt8195_afe_disable_afe_on(struct mtk_base_afe *afe)
648 {
649 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
650 return 0;
651 }
652
mt8195_afe_enable_timing_sys(struct mtk_base_afe * afe)653 static int mt8195_afe_enable_timing_sys(struct mtk_base_afe *afe)
654 {
655 struct mt8195_afe_private *afe_priv = afe->platform_priv;
656 int i;
657 static const unsigned int clk_array[] = {
658 MT8195_CLK_AUD_A1SYS,
659 MT8195_CLK_AUD_A2SYS,
660 };
661 static const unsigned int cg_array[] = {
662 MT8195_TOP_CG_A1SYS_TIMING,
663 MT8195_TOP_CG_A2SYS_TIMING,
664 MT8195_TOP_CG_26M_TIMING,
665 };
666
667 for (i = 0; i < ARRAY_SIZE(clk_array); i++)
668 mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
669
670 for (i = 0; i < ARRAY_SIZE(cg_array); i++)
671 mt8195_afe_enable_top_cg(afe, cg_array[i]);
672
673 return 0;
674 }
675
mt8195_afe_disable_timing_sys(struct mtk_base_afe * afe)676 static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe)
677 {
678 struct mt8195_afe_private *afe_priv = afe->platform_priv;
679 int i;
680 static const unsigned int clk_array[] = {
681 MT8195_CLK_AUD_A2SYS,
682 MT8195_CLK_AUD_A1SYS,
683 };
684 static const unsigned int cg_array[] = {
685 MT8195_TOP_CG_26M_TIMING,
686 MT8195_TOP_CG_A2SYS_TIMING,
687 MT8195_TOP_CG_A1SYS_TIMING,
688 };
689
690 for (i = 0; i < ARRAY_SIZE(cg_array); i++)
691 mt8195_afe_disable_top_cg(afe, cg_array[i]);
692
693 for (i = 0; i < ARRAY_SIZE(clk_array); i++)
694 mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
695
696 return 0;
697 }
698
mt8195_afe_enable_main_clock(struct mtk_base_afe * afe)699 int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe)
700 {
701 mt8195_afe_enable_timing_sys(afe);
702
703 mt8195_afe_enable_afe_on(afe);
704
705 mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL1);
706 mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL2);
707
708 return 0;
709 }
710
mt8195_afe_disable_main_clock(struct mtk_base_afe * afe)711 int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe)
712 {
713 mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL2);
714 mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL1);
715
716 mt8195_afe_disable_afe_on(afe);
717
718 mt8195_afe_disable_timing_sys(afe);
719
720 return 0;
721 }
722