1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 */
5
6 #include <linux/dma-mapping.h>
7 #include "mt76.h"
8 #include "dma.h"
9
10 #if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED)
11
12 #define Q_READ(_dev, _q, _field) ({ \
13 u32 _offset = offsetof(struct mt76_queue_regs, _field); \
14 u32 _val; \
15 if ((_q)->flags & MT_QFLAG_WED) \
16 _val = mtk_wed_device_reg_read(&(_dev)->mmio.wed, \
17 ((_q)->wed_regs + \
18 _offset)); \
19 else \
20 _val = readl(&(_q)->regs->_field); \
21 _val; \
22 })
23
24 #define Q_WRITE(_dev, _q, _field, _val) do { \
25 u32 _offset = offsetof(struct mt76_queue_regs, _field); \
26 if ((_q)->flags & MT_QFLAG_WED) \
27 mtk_wed_device_reg_write(&(_dev)->mmio.wed, \
28 ((_q)->wed_regs + _offset), \
29 _val); \
30 else \
31 writel(_val, &(_q)->regs->_field); \
32 } while (0)
33
34 #else
35
36 #define Q_READ(_dev, _q, _field) readl(&(_q)->regs->_field)
37 #define Q_WRITE(_dev, _q, _field, _val) writel(_val, &(_q)->regs->_field)
38
39 #endif
40
41 static struct mt76_txwi_cache *
mt76_alloc_txwi(struct mt76_dev * dev)42 mt76_alloc_txwi(struct mt76_dev *dev)
43 {
44 struct mt76_txwi_cache *t;
45 dma_addr_t addr;
46 u8 *txwi;
47 int size;
48
49 size = L1_CACHE_ALIGN(dev->drv->txwi_size + sizeof(*t));
50 txwi = kzalloc(size, GFP_ATOMIC);
51 if (!txwi)
52 return NULL;
53
54 addr = dma_map_single(dev->dma_dev, txwi, dev->drv->txwi_size,
55 DMA_TO_DEVICE);
56 t = (struct mt76_txwi_cache *)(txwi + dev->drv->txwi_size);
57 t->dma_addr = addr;
58
59 return t;
60 }
61
62 static struct mt76_txwi_cache *
__mt76_get_txwi(struct mt76_dev * dev)63 __mt76_get_txwi(struct mt76_dev *dev)
64 {
65 struct mt76_txwi_cache *t = NULL;
66
67 spin_lock(&dev->lock);
68 if (!list_empty(&dev->txwi_cache)) {
69 t = list_first_entry(&dev->txwi_cache, struct mt76_txwi_cache,
70 list);
71 list_del(&t->list);
72 }
73 spin_unlock(&dev->lock);
74
75 return t;
76 }
77
78 static struct mt76_txwi_cache *
mt76_get_txwi(struct mt76_dev * dev)79 mt76_get_txwi(struct mt76_dev *dev)
80 {
81 struct mt76_txwi_cache *t = __mt76_get_txwi(dev);
82
83 if (t)
84 return t;
85
86 return mt76_alloc_txwi(dev);
87 }
88
89 void
mt76_put_txwi(struct mt76_dev * dev,struct mt76_txwi_cache * t)90 mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
91 {
92 if (!t)
93 return;
94
95 spin_lock(&dev->lock);
96 list_add(&t->list, &dev->txwi_cache);
97 spin_unlock(&dev->lock);
98 }
99 EXPORT_SYMBOL_GPL(mt76_put_txwi);
100
101 static void
mt76_free_pending_txwi(struct mt76_dev * dev)102 mt76_free_pending_txwi(struct mt76_dev *dev)
103 {
104 struct mt76_txwi_cache *t;
105
106 local_bh_disable();
107 while ((t = __mt76_get_txwi(dev)) != NULL) {
108 dma_unmap_single(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
109 DMA_TO_DEVICE);
110 kfree(mt76_get_txwi_ptr(dev, t));
111 }
112 local_bh_enable();
113 }
114
115 static void
mt76_dma_sync_idx(struct mt76_dev * dev,struct mt76_queue * q)116 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
117 {
118 Q_WRITE(dev, q, desc_base, q->desc_dma);
119 Q_WRITE(dev, q, ring_size, q->ndesc);
120 q->head = Q_READ(dev, q, dma_idx);
121 q->tail = q->head;
122 }
123
124 static void
mt76_dma_queue_reset(struct mt76_dev * dev,struct mt76_queue * q)125 mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
126 {
127 int i;
128
129 if (!q || !q->ndesc)
130 return;
131
132 /* clear descriptors */
133 for (i = 0; i < q->ndesc; i++)
134 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE);
135
136 Q_WRITE(dev, q, cpu_idx, 0);
137 Q_WRITE(dev, q, dma_idx, 0);
138 mt76_dma_sync_idx(dev, q);
139 }
140
141 static int
mt76_dma_add_buf(struct mt76_dev * dev,struct mt76_queue * q,struct mt76_queue_buf * buf,int nbufs,u32 info,struct sk_buff * skb,void * txwi)142 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
143 struct mt76_queue_buf *buf, int nbufs, u32 info,
144 struct sk_buff *skb, void *txwi)
145 {
146 struct mt76_queue_entry *entry;
147 struct mt76_desc *desc;
148 u32 ctrl;
149 int i, idx = -1;
150
151 if (txwi) {
152 q->entry[q->head].txwi = DMA_DUMMY_DATA;
153 q->entry[q->head].skip_buf0 = true;
154 }
155
156 for (i = 0; i < nbufs; i += 2, buf += 2) {
157 u32 buf0 = buf[0].addr, buf1 = 0;
158
159 idx = q->head;
160 q->head = (q->head + 1) % q->ndesc;
161
162 desc = &q->desc[idx];
163 entry = &q->entry[idx];
164
165 if (buf[0].skip_unmap)
166 entry->skip_buf0 = true;
167 entry->skip_buf1 = i == nbufs - 1;
168
169 entry->dma_addr[0] = buf[0].addr;
170 entry->dma_len[0] = buf[0].len;
171
172 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
173 if (i < nbufs - 1) {
174 entry->dma_addr[1] = buf[1].addr;
175 entry->dma_len[1] = buf[1].len;
176 buf1 = buf[1].addr;
177 ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
178 if (buf[1].skip_unmap)
179 entry->skip_buf1 = true;
180 }
181
182 if (i == nbufs - 1)
183 ctrl |= MT_DMA_CTL_LAST_SEC0;
184 else if (i == nbufs - 2)
185 ctrl |= MT_DMA_CTL_LAST_SEC1;
186
187 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
188 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
189 WRITE_ONCE(desc->info, cpu_to_le32(info));
190 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl));
191
192 q->queued++;
193 }
194
195 q->entry[idx].txwi = txwi;
196 q->entry[idx].skb = skb;
197 q->entry[idx].wcid = 0xffff;
198
199 return idx;
200 }
201
202 static void
mt76_dma_tx_cleanup_idx(struct mt76_dev * dev,struct mt76_queue * q,int idx,struct mt76_queue_entry * prev_e)203 mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx,
204 struct mt76_queue_entry *prev_e)
205 {
206 struct mt76_queue_entry *e = &q->entry[idx];
207
208 if (!e->skip_buf0)
209 dma_unmap_single(dev->dma_dev, e->dma_addr[0], e->dma_len[0],
210 DMA_TO_DEVICE);
211
212 if (!e->skip_buf1)
213 dma_unmap_single(dev->dma_dev, e->dma_addr[1], e->dma_len[1],
214 DMA_TO_DEVICE);
215
216 if (e->txwi == DMA_DUMMY_DATA)
217 e->txwi = NULL;
218
219 if (e->skb == DMA_DUMMY_DATA)
220 e->skb = NULL;
221
222 *prev_e = *e;
223 memset(e, 0, sizeof(*e));
224 }
225
226 static void
mt76_dma_kick_queue(struct mt76_dev * dev,struct mt76_queue * q)227 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q)
228 {
229 wmb();
230 Q_WRITE(dev, q, cpu_idx, q->head);
231 }
232
233 static void
mt76_dma_tx_cleanup(struct mt76_dev * dev,struct mt76_queue * q,bool flush)234 mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
235 {
236 struct mt76_queue_entry entry;
237 int last;
238
239 if (!q || !q->ndesc)
240 return;
241
242 spin_lock_bh(&q->cleanup_lock);
243 if (flush)
244 last = -1;
245 else
246 last = Q_READ(dev, q, dma_idx);
247
248 while (q->queued > 0 && q->tail != last) {
249 mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry);
250 mt76_queue_tx_complete(dev, q, &entry);
251
252 if (entry.txwi) {
253 if (!(dev->drv->drv_flags & MT_DRV_TXWI_NO_FREE))
254 mt76_put_txwi(dev, entry.txwi);
255 }
256
257 if (!flush && q->tail == last)
258 last = Q_READ(dev, q, dma_idx);
259 }
260 spin_unlock_bh(&q->cleanup_lock);
261
262 if (flush) {
263 spin_lock_bh(&q->lock);
264 mt76_dma_sync_idx(dev, q);
265 mt76_dma_kick_queue(dev, q);
266 spin_unlock_bh(&q->lock);
267 }
268
269 if (!q->queued)
270 wake_up(&dev->tx_wait);
271 }
272
273 static void *
mt76_dma_get_buf(struct mt76_dev * dev,struct mt76_queue * q,int idx,int * len,u32 * info,bool * more)274 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
275 int *len, u32 *info, bool *more)
276 {
277 struct mt76_queue_entry *e = &q->entry[idx];
278 struct mt76_desc *desc = &q->desc[idx];
279 dma_addr_t buf_addr;
280 void *buf = e->buf;
281 int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
282
283 buf_addr = e->dma_addr[0];
284 if (len) {
285 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl));
286 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
287 *more = !(ctl & MT_DMA_CTL_LAST_SEC0);
288 }
289
290 if (info)
291 *info = le32_to_cpu(desc->info);
292
293 dma_unmap_single(dev->dma_dev, buf_addr, buf_len, DMA_FROM_DEVICE);
294 e->buf = NULL;
295
296 return buf;
297 }
298
299 static void *
mt76_dma_dequeue(struct mt76_dev * dev,struct mt76_queue * q,bool flush,int * len,u32 * info,bool * more)300 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
301 int *len, u32 *info, bool *more)
302 {
303 int idx = q->tail;
304
305 *more = false;
306 if (!q->queued)
307 return NULL;
308
309 if (flush)
310 q->desc[idx].ctrl |= cpu_to_le32(MT_DMA_CTL_DMA_DONE);
311 else if (!(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE)))
312 return NULL;
313
314 q->tail = (q->tail + 1) % q->ndesc;
315 q->queued--;
316
317 return mt76_dma_get_buf(dev, q, idx, len, info, more);
318 }
319
320 static int
mt76_dma_tx_queue_skb_raw(struct mt76_dev * dev,struct mt76_queue * q,struct sk_buff * skb,u32 tx_info)321 mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q,
322 struct sk_buff *skb, u32 tx_info)
323 {
324 struct mt76_queue_buf buf = {};
325 dma_addr_t addr;
326
327 if (q->queued + 1 >= q->ndesc - 1)
328 goto error;
329
330 addr = dma_map_single(dev->dma_dev, skb->data, skb->len,
331 DMA_TO_DEVICE);
332 if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
333 goto error;
334
335 buf.addr = addr;
336 buf.len = skb->len;
337
338 spin_lock_bh(&q->lock);
339 mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
340 mt76_dma_kick_queue(dev, q);
341 spin_unlock_bh(&q->lock);
342
343 return 0;
344
345 error:
346 dev_kfree_skb(skb);
347 return -ENOMEM;
348 }
349
350 static int
mt76_dma_tx_queue_skb(struct mt76_dev * dev,struct mt76_queue * q,struct sk_buff * skb,struct mt76_wcid * wcid,struct ieee80211_sta * sta)351 mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
352 struct sk_buff *skb, struct mt76_wcid *wcid,
353 struct ieee80211_sta *sta)
354 {
355 struct ieee80211_tx_status status = {
356 .sta = sta,
357 };
358 struct mt76_tx_info tx_info = {
359 .skb = skb,
360 };
361 struct ieee80211_hw *hw;
362 int len, n = 0, ret = -ENOMEM;
363 struct mt76_txwi_cache *t;
364 struct sk_buff *iter;
365 dma_addr_t addr;
366 u8 *txwi;
367
368 t = mt76_get_txwi(dev);
369 if (!t)
370 goto free_skb;
371
372 txwi = mt76_get_txwi_ptr(dev, t);
373
374 skb->prev = skb->next = NULL;
375 if (dev->drv->drv_flags & MT_DRV_TX_ALIGNED4_SKBS)
376 mt76_insert_hdr_pad(skb);
377
378 len = skb_headlen(skb);
379 addr = dma_map_single(dev->dma_dev, skb->data, len, DMA_TO_DEVICE);
380 if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
381 goto free;
382
383 tx_info.buf[n].addr = t->dma_addr;
384 tx_info.buf[n++].len = dev->drv->txwi_size;
385 tx_info.buf[n].addr = addr;
386 tx_info.buf[n++].len = len;
387
388 skb_walk_frags(skb, iter) {
389 if (n == ARRAY_SIZE(tx_info.buf))
390 goto unmap;
391
392 addr = dma_map_single(dev->dma_dev, iter->data, iter->len,
393 DMA_TO_DEVICE);
394 if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
395 goto unmap;
396
397 tx_info.buf[n].addr = addr;
398 tx_info.buf[n++].len = iter->len;
399 }
400 tx_info.nbuf = n;
401
402 if (q->queued + (tx_info.nbuf + 1) / 2 >= q->ndesc - 1) {
403 ret = -ENOMEM;
404 goto unmap;
405 }
406
407 dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
408 DMA_TO_DEVICE);
409 ret = dev->drv->tx_prepare_skb(dev, txwi, q->qid, wcid, sta, &tx_info);
410 dma_sync_single_for_device(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
411 DMA_TO_DEVICE);
412 if (ret < 0)
413 goto unmap;
414
415 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf,
416 tx_info.info, tx_info.skb, t);
417
418 unmap:
419 for (n--; n > 0; n--)
420 dma_unmap_single(dev->dma_dev, tx_info.buf[n].addr,
421 tx_info.buf[n].len, DMA_TO_DEVICE);
422
423 free:
424 #ifdef CONFIG_NL80211_TESTMODE
425 /* fix tx_done accounting on queue overflow */
426 if (mt76_is_testmode_skb(dev, skb, &hw)) {
427 struct mt76_phy *phy = hw->priv;
428
429 if (tx_info.skb == phy->test.tx_skb)
430 phy->test.tx_done--;
431 }
432 #endif
433
434 mt76_put_txwi(dev, t);
435
436 free_skb:
437 status.skb = tx_info.skb;
438 hw = mt76_tx_status_get_hw(dev, tx_info.skb);
439 ieee80211_tx_status_ext(hw, &status);
440
441 return ret;
442 }
443
444 static int
mt76_dma_rx_fill(struct mt76_dev * dev,struct mt76_queue * q)445 mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
446 {
447 dma_addr_t addr;
448 void *buf;
449 int frames = 0;
450 int len = SKB_WITH_OVERHEAD(q->buf_size);
451 int offset = q->buf_offset;
452
453 if (!q->ndesc)
454 return 0;
455
456 spin_lock_bh(&q->lock);
457
458 while (q->queued < q->ndesc - 1) {
459 struct mt76_queue_buf qbuf;
460
461 buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
462 if (!buf)
463 break;
464
465 addr = dma_map_single(dev->dma_dev, buf, len, DMA_FROM_DEVICE);
466 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) {
467 skb_free_frag(buf);
468 break;
469 }
470
471 qbuf.addr = addr + offset;
472 qbuf.len = len - offset;
473 qbuf.skip_unmap = false;
474 mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL);
475 frames++;
476 }
477
478 if (frames)
479 mt76_dma_kick_queue(dev, q);
480
481 spin_unlock_bh(&q->lock);
482
483 return frames;
484 }
485
486 static int
mt76_dma_wed_setup(struct mt76_dev * dev,struct mt76_queue * q)487 mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q)
488 {
489 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
490 struct mtk_wed_device *wed = &dev->mmio.wed;
491 int ret, type, ring;
492 u8 flags = q->flags;
493
494 if (!mtk_wed_device_active(wed))
495 q->flags &= ~MT_QFLAG_WED;
496
497 if (!(q->flags & MT_QFLAG_WED))
498 return 0;
499
500 type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
501 ring = FIELD_GET(MT_QFLAG_WED_RING, q->flags);
502
503 switch (type) {
504 case MT76_WED_Q_TX:
505 ret = mtk_wed_device_tx_ring_setup(wed, ring, q->regs);
506 if (!ret)
507 q->wed_regs = wed->tx_ring[ring].reg_base;
508 break;
509 case MT76_WED_Q_TXFREE:
510 /* WED txfree queue needs ring to be initialized before setup */
511 q->flags = 0;
512 mt76_dma_queue_reset(dev, q);
513 mt76_dma_rx_fill(dev, q);
514 q->flags = flags;
515
516 ret = mtk_wed_device_txfree_ring_setup(wed, q->regs);
517 if (!ret)
518 q->wed_regs = wed->txfree_ring.reg_base;
519 break;
520 default:
521 ret = -EINVAL;
522 }
523
524 return ret;
525 #else
526 return 0;
527 #endif
528 }
529
530 static int
mt76_dma_alloc_queue(struct mt76_dev * dev,struct mt76_queue * q,int idx,int n_desc,int bufsize,u32 ring_base)531 mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
532 int idx, int n_desc, int bufsize,
533 u32 ring_base)
534 {
535 int ret, size;
536
537 spin_lock_init(&q->lock);
538 spin_lock_init(&q->cleanup_lock);
539
540 q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE;
541 q->ndesc = n_desc;
542 q->buf_size = bufsize;
543 q->hw_idx = idx;
544
545 size = q->ndesc * sizeof(struct mt76_desc);
546 q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
547 if (!q->desc)
548 return -ENOMEM;
549
550 size = q->ndesc * sizeof(*q->entry);
551 q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL);
552 if (!q->entry)
553 return -ENOMEM;
554
555 ret = mt76_dma_wed_setup(dev, q);
556 if (ret)
557 return ret;
558
559 if (q->flags != MT_WED_Q_TXFREE)
560 mt76_dma_queue_reset(dev, q);
561
562 return 0;
563 }
564
565 static void
mt76_dma_rx_cleanup(struct mt76_dev * dev,struct mt76_queue * q)566 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
567 {
568 struct page *page;
569 void *buf;
570 bool more;
571
572 if (!q->ndesc)
573 return;
574
575 spin_lock_bh(&q->lock);
576 do {
577 buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
578 if (!buf)
579 break;
580
581 skb_free_frag(buf);
582 } while (1);
583 spin_unlock_bh(&q->lock);
584
585 if (!q->rx_page.va)
586 return;
587
588 page = virt_to_page(q->rx_page.va);
589 __page_frag_cache_drain(page, q->rx_page.pagecnt_bias);
590 memset(&q->rx_page, 0, sizeof(q->rx_page));
591 }
592
593 static void
mt76_dma_rx_reset(struct mt76_dev * dev,enum mt76_rxq_id qid)594 mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
595 {
596 struct mt76_queue *q = &dev->q_rx[qid];
597 int i;
598
599 if (!q->ndesc)
600 return;
601
602 for (i = 0; i < q->ndesc; i++)
603 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE);
604
605 mt76_dma_rx_cleanup(dev, q);
606 mt76_dma_sync_idx(dev, q);
607 mt76_dma_rx_fill(dev, q);
608
609 if (!q->rx_head)
610 return;
611
612 dev_kfree_skb(q->rx_head);
613 q->rx_head = NULL;
614 }
615
616 static void
mt76_add_fragment(struct mt76_dev * dev,struct mt76_queue * q,void * data,int len,bool more)617 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
618 int len, bool more)
619 {
620 struct sk_buff *skb = q->rx_head;
621 struct skb_shared_info *shinfo = skb_shinfo(skb);
622 int nr_frags = shinfo->nr_frags;
623
624 if (nr_frags < ARRAY_SIZE(shinfo->frags)) {
625 struct page *page = virt_to_head_page(data);
626 int offset = data - page_address(page) + q->buf_offset;
627
628 skb_add_rx_frag(skb, nr_frags, page, offset, len, q->buf_size);
629 } else {
630 skb_free_frag(data);
631 }
632
633 if (more)
634 return;
635
636 q->rx_head = NULL;
637 if (nr_frags < ARRAY_SIZE(shinfo->frags))
638 dev->drv->rx_skb(dev, q - dev->q_rx, skb);
639 else
640 dev_kfree_skb(skb);
641 }
642
643 static int
mt76_dma_rx_process(struct mt76_dev * dev,struct mt76_queue * q,int budget)644 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
645 {
646 int len, data_len, done = 0, dma_idx;
647 struct sk_buff *skb;
648 unsigned char *data;
649 bool check_ddone = false;
650 bool more;
651
652 if (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) &&
653 q->flags == MT_WED_Q_TXFREE) {
654 dma_idx = Q_READ(dev, q, dma_idx);
655 check_ddone = true;
656 }
657
658 while (done < budget) {
659 u32 info;
660
661 if (check_ddone) {
662 if (q->tail == dma_idx)
663 dma_idx = Q_READ(dev, q, dma_idx);
664
665 if (q->tail == dma_idx)
666 break;
667 }
668
669 data = mt76_dma_dequeue(dev, q, false, &len, &info, &more);
670 if (!data)
671 break;
672
673 if (q->rx_head)
674 data_len = q->buf_size;
675 else
676 data_len = SKB_WITH_OVERHEAD(q->buf_size);
677
678 if (data_len < len + q->buf_offset) {
679 dev_kfree_skb(q->rx_head);
680 q->rx_head = NULL;
681 goto free_frag;
682 }
683
684 if (q->rx_head) {
685 mt76_add_fragment(dev, q, data, len, more);
686 continue;
687 }
688
689 if (!more && dev->drv->rx_check &&
690 !(dev->drv->rx_check(dev, data, len)))
691 goto free_frag;
692
693 skb = build_skb(data, q->buf_size);
694 if (!skb)
695 goto free_frag;
696
697 skb_reserve(skb, q->buf_offset);
698
699 if (q == &dev->q_rx[MT_RXQ_MCU]) {
700 u32 *rxfce = (u32 *)skb->cb;
701 *rxfce = info;
702 }
703
704 __skb_put(skb, len);
705 done++;
706
707 if (more) {
708 q->rx_head = skb;
709 continue;
710 }
711
712 dev->drv->rx_skb(dev, q - dev->q_rx, skb);
713 continue;
714
715 free_frag:
716 skb_free_frag(data);
717 }
718
719 mt76_dma_rx_fill(dev, q);
720 return done;
721 }
722
mt76_dma_rx_poll(struct napi_struct * napi,int budget)723 int mt76_dma_rx_poll(struct napi_struct *napi, int budget)
724 {
725 struct mt76_dev *dev;
726 int qid, done = 0, cur;
727
728 dev = container_of(napi->dev, struct mt76_dev, napi_dev);
729 qid = napi - dev->napi;
730
731 rcu_read_lock();
732
733 do {
734 cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done);
735 mt76_rx_poll_complete(dev, qid, napi);
736 done += cur;
737 } while (cur && done < budget);
738
739 rcu_read_unlock();
740
741 if (done < budget && napi_complete(napi))
742 dev->drv->rx_poll_complete(dev, qid);
743
744 return done;
745 }
746 EXPORT_SYMBOL_GPL(mt76_dma_rx_poll);
747
748 static int
mt76_dma_init(struct mt76_dev * dev,int (* poll)(struct napi_struct * napi,int budget))749 mt76_dma_init(struct mt76_dev *dev,
750 int (*poll)(struct napi_struct *napi, int budget))
751 {
752 int i;
753
754 init_dummy_netdev(&dev->napi_dev);
755 init_dummy_netdev(&dev->tx_napi_dev);
756 snprintf(dev->napi_dev.name, sizeof(dev->napi_dev.name), "%s",
757 wiphy_name(dev->hw->wiphy));
758 dev->napi_dev.threaded = 1;
759
760 mt76_for_each_q_rx(dev, i) {
761 netif_napi_add(&dev->napi_dev, &dev->napi[i], poll, 64);
762 mt76_dma_rx_fill(dev, &dev->q_rx[i]);
763 napi_enable(&dev->napi[i]);
764 }
765
766 return 0;
767 }
768
769 static const struct mt76_queue_ops mt76_dma_ops = {
770 .init = mt76_dma_init,
771 .alloc = mt76_dma_alloc_queue,
772 .reset_q = mt76_dma_queue_reset,
773 .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw,
774 .tx_queue_skb = mt76_dma_tx_queue_skb,
775 .tx_cleanup = mt76_dma_tx_cleanup,
776 .rx_cleanup = mt76_dma_rx_cleanup,
777 .rx_reset = mt76_dma_rx_reset,
778 .kick = mt76_dma_kick_queue,
779 };
780
mt76_dma_attach(struct mt76_dev * dev)781 void mt76_dma_attach(struct mt76_dev *dev)
782 {
783 dev->queue_ops = &mt76_dma_ops;
784 }
785 EXPORT_SYMBOL_GPL(mt76_dma_attach);
786
mt76_dma_cleanup(struct mt76_dev * dev)787 void mt76_dma_cleanup(struct mt76_dev *dev)
788 {
789 int i;
790
791 mt76_worker_disable(&dev->tx_worker);
792 netif_napi_del(&dev->tx_napi);
793
794 for (i = 0; i < ARRAY_SIZE(dev->phy.q_tx); i++) {
795 mt76_dma_tx_cleanup(dev, dev->phy.q_tx[i], true);
796 if (dev->phy2)
797 mt76_dma_tx_cleanup(dev, dev->phy2->q_tx[i], true);
798 }
799
800 for (i = 0; i < ARRAY_SIZE(dev->q_mcu); i++)
801 mt76_dma_tx_cleanup(dev, dev->q_mcu[i], true);
802
803 mt76_for_each_q_rx(dev, i) {
804 netif_napi_del(&dev->napi[i]);
805 mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
806 }
807
808 mt76_free_pending_txwi(dev);
809
810 if (mtk_wed_device_active(&dev->mmio.wed))
811 mtk_wed_device_detach(&dev->mmio.wed);
812 }
813 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);
814