1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * camss-ispif.c
4 *
5 * Qualcomm MSM Camera Subsystem - ISPIF (ISP Interface) Module
6 *
7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 * Copyright (C) 2015-2018 Linaro Ltd.
9 */
10 #include <linux/clk.h>
11 #include <linux/completion.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <linux/kernel.h>
16 #include <linux/mutex.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <media/media-entity.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-subdev.h>
22
23 #include "camss-ispif.h"
24 #include "camss.h"
25
26 #define MSM_ISPIF_NAME "msm_ispif"
27
28 #define ISPIF_RST_CMD_0 0x008
29 #define ISPIF_RST_CMD_1 0x00c
30 #define ISPIF_RST_CMD_0_STROBED_RST_EN (1 << 0)
31 #define ISPIF_RST_CMD_0_MISC_LOGIC_RST (1 << 1)
32 #define ISPIF_RST_CMD_0_SW_REG_RST (1 << 2)
33 #define ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST (1 << 3)
34 #define ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST (1 << 4)
35 #define ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST (1 << 5)
36 #define ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST (1 << 6)
37 #define ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST (1 << 7)
38 #define ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST (1 << 8)
39 #define ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST (1 << 9)
40 #define ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST (1 << 10)
41 #define ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST (1 << 11)
42 #define ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST (1 << 12)
43 #define ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST (1 << 16)
44 #define ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST (1 << 17)
45 #define ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST (1 << 18)
46 #define ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST (1 << 19)
47 #define ISPIF_IRQ_GLOBAL_CLEAR_CMD 0x01c
48 #define ISPIF_VFE_m_CTRL_0(m) (0x200 + 0x200 * (m))
49 #define ISPIF_VFE_m_CTRL_0_PIX0_LINE_BUF_EN (1 << 6)
50 #define ISPIF_VFE_m_IRQ_MASK_0(m) (0x208 + 0x200 * (m))
51 #define ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE 0x00001249
52 #define ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK 0x00001fff
53 #define ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE 0x02492000
54 #define ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK 0x03ffe000
55 #define ISPIF_VFE_m_IRQ_MASK_1(m) (0x20c + 0x200 * (m))
56 #define ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE 0x00001249
57 #define ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK 0x00001fff
58 #define ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE 0x02492000
59 #define ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK 0x03ffe000
60 #define ISPIF_VFE_m_IRQ_MASK_2(m) (0x210 + 0x200 * (m))
61 #define ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE 0x00001249
62 #define ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK 0x00001fff
63 #define ISPIF_VFE_m_IRQ_STATUS_0(m) (0x21c + 0x200 * (m))
64 #define ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW (1 << 12)
65 #define ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW (1 << 25)
66 #define ISPIF_VFE_m_IRQ_STATUS_1(m) (0x220 + 0x200 * (m))
67 #define ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW (1 << 12)
68 #define ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW (1 << 25)
69 #define ISPIF_VFE_m_IRQ_STATUS_2(m) (0x224 + 0x200 * (m))
70 #define ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW (1 << 12)
71 #define ISPIF_VFE_m_IRQ_CLEAR_0(m) (0x230 + 0x200 * (m))
72 #define ISPIF_VFE_m_IRQ_CLEAR_1(m) (0x234 + 0x200 * (m))
73 #define ISPIF_VFE_m_IRQ_CLEAR_2(m) (0x238 + 0x200 * (m))
74 #define ISPIF_VFE_m_INTF_INPUT_SEL(m) (0x244 + 0x200 * (m))
75 #define ISPIF_VFE_m_INTF_CMD_0(m) (0x248 + 0x200 * (m))
76 #define ISPIF_VFE_m_INTF_CMD_1(m) (0x24c + 0x200 * (m))
77 #define ISPIF_VFE_m_PIX_INTF_n_CID_MASK(m, n) \
78 (0x254 + 0x200 * (m) + 0x4 * (n))
79 #define ISPIF_VFE_m_RDI_INTF_n_CID_MASK(m, n) \
80 (0x264 + 0x200 * (m) + 0x4 * (n))
81 /* PACK_CFG registers are 8x96 only */
82 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(m, n) \
83 (0x270 + 0x200 * (m) + 0x4 * (n))
84 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(m, n) \
85 (0x27c + 0x200 * (m) + 0x4 * (n))
86 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(c) \
87 (1 << ((cid % 8) * 4))
88 #define ISPIF_VFE_m_PIX_INTF_n_STATUS(m, n) \
89 (0x2c0 + 0x200 * (m) + 0x4 * (n))
90 #define ISPIF_VFE_m_RDI_INTF_n_STATUS(m, n) \
91 (0x2d0 + 0x200 * (m) + 0x4 * (n))
92
93 #define CSI_PIX_CLK_MUX_SEL 0x000
94 #define CSI_RDI_CLK_MUX_SEL 0x008
95
96 #define ISPIF_TIMEOUT_SLEEP_US 1000
97 #define ISPIF_TIMEOUT_ALL_US 1000000
98 #define ISPIF_RESET_TIMEOUT_MS 500
99
100 enum ispif_intf_cmd {
101 CMD_DISABLE_FRAME_BOUNDARY = 0x0,
102 CMD_ENABLE_FRAME_BOUNDARY = 0x1,
103 CMD_DISABLE_IMMEDIATELY = 0x2,
104 CMD_ALL_DISABLE_IMMEDIATELY = 0xaaaaaaaa,
105 CMD_ALL_NO_CHANGE = 0xffffffff,
106 };
107
108 static const u32 ispif_formats_8x16[] = {
109 MEDIA_BUS_FMT_UYVY8_2X8,
110 MEDIA_BUS_FMT_VYUY8_2X8,
111 MEDIA_BUS_FMT_YUYV8_2X8,
112 MEDIA_BUS_FMT_YVYU8_2X8,
113 MEDIA_BUS_FMT_SBGGR8_1X8,
114 MEDIA_BUS_FMT_SGBRG8_1X8,
115 MEDIA_BUS_FMT_SGRBG8_1X8,
116 MEDIA_BUS_FMT_SRGGB8_1X8,
117 MEDIA_BUS_FMT_SBGGR10_1X10,
118 MEDIA_BUS_FMT_SGBRG10_1X10,
119 MEDIA_BUS_FMT_SGRBG10_1X10,
120 MEDIA_BUS_FMT_SRGGB10_1X10,
121 MEDIA_BUS_FMT_SBGGR12_1X12,
122 MEDIA_BUS_FMT_SGBRG12_1X12,
123 MEDIA_BUS_FMT_SGRBG12_1X12,
124 MEDIA_BUS_FMT_SRGGB12_1X12,
125 MEDIA_BUS_FMT_Y10_1X10,
126 };
127
128 static const u32 ispif_formats_8x96[] = {
129 MEDIA_BUS_FMT_UYVY8_2X8,
130 MEDIA_BUS_FMT_VYUY8_2X8,
131 MEDIA_BUS_FMT_YUYV8_2X8,
132 MEDIA_BUS_FMT_YVYU8_2X8,
133 MEDIA_BUS_FMT_SBGGR8_1X8,
134 MEDIA_BUS_FMT_SGBRG8_1X8,
135 MEDIA_BUS_FMT_SGRBG8_1X8,
136 MEDIA_BUS_FMT_SRGGB8_1X8,
137 MEDIA_BUS_FMT_SBGGR10_1X10,
138 MEDIA_BUS_FMT_SGBRG10_1X10,
139 MEDIA_BUS_FMT_SGRBG10_1X10,
140 MEDIA_BUS_FMT_SRGGB10_1X10,
141 MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
142 MEDIA_BUS_FMT_SBGGR12_1X12,
143 MEDIA_BUS_FMT_SGBRG12_1X12,
144 MEDIA_BUS_FMT_SGRBG12_1X12,
145 MEDIA_BUS_FMT_SRGGB12_1X12,
146 MEDIA_BUS_FMT_SBGGR14_1X14,
147 MEDIA_BUS_FMT_SGBRG14_1X14,
148 MEDIA_BUS_FMT_SGRBG14_1X14,
149 MEDIA_BUS_FMT_SRGGB14_1X14,
150 MEDIA_BUS_FMT_Y10_1X10,
151 MEDIA_BUS_FMT_Y10_2X8_PADHI_LE,
152 };
153
154 /*
155 * ispif_isr_8x96 - ISPIF module interrupt handler for 8x96
156 * @irq: Interrupt line
157 * @dev: ISPIF device
158 *
159 * Return IRQ_HANDLED on success
160 */
ispif_isr_8x96(int irq,void * dev)161 static irqreturn_t ispif_isr_8x96(int irq, void *dev)
162 {
163 struct ispif_device *ispif = dev;
164 struct camss *camss = ispif->camss;
165 u32 value0, value1, value2, value3, value4, value5;
166
167 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
168 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
169 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
170 value3 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(1));
171 value4 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(1));
172 value5 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(1));
173
174 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
175 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
176 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
177 writel_relaxed(value3, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(1));
178 writel_relaxed(value4, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(1));
179 writel_relaxed(value5, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(1));
180
181 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
182
183 if ((value0 >> 27) & 0x1)
184 complete(&ispif->reset_complete[0]);
185
186 if ((value3 >> 27) & 0x1)
187 complete(&ispif->reset_complete[1]);
188
189 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
190 dev_err_ratelimited(camss->dev, "VFE0 pix0 overflow\n");
191
192 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
193 dev_err_ratelimited(camss->dev, "VFE0 rdi0 overflow\n");
194
195 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
196 dev_err_ratelimited(camss->dev, "VFE0 pix1 overflow\n");
197
198 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
199 dev_err_ratelimited(camss->dev, "VFE0 rdi1 overflow\n");
200
201 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
202 dev_err_ratelimited(camss->dev, "VFE0 rdi2 overflow\n");
203
204 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
205 dev_err_ratelimited(camss->dev, "VFE1 pix0 overflow\n");
206
207 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
208 dev_err_ratelimited(camss->dev, "VFE1 rdi0 overflow\n");
209
210 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
211 dev_err_ratelimited(camss->dev, "VFE1 pix1 overflow\n");
212
213 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
214 dev_err_ratelimited(camss->dev, "VFE1 rdi1 overflow\n");
215
216 if (unlikely(value5 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
217 dev_err_ratelimited(camss->dev, "VFE1 rdi2 overflow\n");
218
219 return IRQ_HANDLED;
220 }
221
222 /*
223 * ispif_isr_8x16 - ISPIF module interrupt handler for 8x16
224 * @irq: Interrupt line
225 * @dev: ISPIF device
226 *
227 * Return IRQ_HANDLED on success
228 */
ispif_isr_8x16(int irq,void * dev)229 static irqreturn_t ispif_isr_8x16(int irq, void *dev)
230 {
231 struct ispif_device *ispif = dev;
232 struct camss *camss = ispif->camss;
233 u32 value0, value1, value2;
234
235 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
236 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
237 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
238
239 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
240 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
241 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
242
243 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
244
245 if ((value0 >> 27) & 0x1)
246 complete(&ispif->reset_complete[0]);
247
248 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
249 dev_err_ratelimited(camss->dev, "VFE0 pix0 overflow\n");
250
251 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
252 dev_err_ratelimited(camss->dev, "VFE0 rdi0 overflow\n");
253
254 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
255 dev_err_ratelimited(camss->dev, "VFE0 pix1 overflow\n");
256
257 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
258 dev_err_ratelimited(camss->dev, "VFE0 rdi1 overflow\n");
259
260 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
261 dev_err_ratelimited(camss->dev, "VFE0 rdi2 overflow\n");
262
263 return IRQ_HANDLED;
264 }
265
ispif_vfe_reset(struct ispif_device * ispif,u8 vfe_id)266 static int ispif_vfe_reset(struct ispif_device *ispif, u8 vfe_id)
267 {
268 struct camss *camss = ispif->camss;
269
270 unsigned long time;
271 u32 val;
272
273 if (vfe_id > (camss->vfe_num - 1)) {
274 dev_err(camss->dev,
275 "Error: asked reset for invalid VFE%d\n", vfe_id);
276 return -ENOENT;
277 }
278
279 reinit_completion(&ispif->reset_complete[vfe_id]);
280
281 val = ISPIF_RST_CMD_0_STROBED_RST_EN |
282 ISPIF_RST_CMD_0_MISC_LOGIC_RST |
283 ISPIF_RST_CMD_0_SW_REG_RST |
284 ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST |
285 ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST |
286 ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST |
287 ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST |
288 ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST |
289 ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST |
290 ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST |
291 ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST |
292 ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST |
293 ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST |
294 ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST |
295 ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST |
296 ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST |
297 ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST;
298
299 if (vfe_id == 1)
300 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_1);
301 else
302 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0);
303
304 time = wait_for_completion_timeout(&ispif->reset_complete[vfe_id],
305 msecs_to_jiffies(ISPIF_RESET_TIMEOUT_MS));
306 if (!time) {
307 dev_err(camss->dev,
308 "ISPIF for VFE%d reset timeout\n", vfe_id);
309 return -EIO;
310 }
311
312 return 0;
313 }
314
315 /*
316 * ispif_reset - Trigger reset on ISPIF module and wait to complete
317 * @ispif: ISPIF device
318 *
319 * Return 0 on success or a negative error code otherwise
320 */
ispif_reset(struct ispif_device * ispif,u8 vfe_id)321 static int ispif_reset(struct ispif_device *ispif, u8 vfe_id)
322 {
323 struct camss *camss = ispif->camss;
324 int ret;
325
326 ret = camss_pm_domain_on(camss, PM_DOMAIN_VFE0);
327 if (ret < 0)
328 return ret;
329
330 ret = camss_pm_domain_on(camss, PM_DOMAIN_VFE1);
331 if (ret < 0)
332 return ret;
333
334 ret = camss_enable_clocks(ispif->nclocks_for_reset,
335 ispif->clock_for_reset,
336 camss->dev);
337 if (ret < 0)
338 return ret;
339
340 ret = ispif_vfe_reset(ispif, vfe_id);
341 if (ret)
342 dev_dbg(camss->dev, "ISPIF Reset failed\n");
343
344 camss_disable_clocks(ispif->nclocks_for_reset, ispif->clock_for_reset);
345
346 camss_pm_domain_off(camss, PM_DOMAIN_VFE0);
347 camss_pm_domain_off(camss, PM_DOMAIN_VFE1);
348
349 return ret;
350 }
351
352 /*
353 * ispif_set_power - Power on/off ISPIF module
354 * @sd: ISPIF V4L2 subdevice
355 * @on: Requested power state
356 *
357 * Return 0 on success or a negative error code otherwise
358 */
ispif_set_power(struct v4l2_subdev * sd,int on)359 static int ispif_set_power(struct v4l2_subdev *sd, int on)
360 {
361 struct ispif_line *line = v4l2_get_subdevdata(sd);
362 struct ispif_device *ispif = line->ispif;
363 struct device *dev = ispif->camss->dev;
364 int ret = 0;
365
366 mutex_lock(&ispif->power_lock);
367
368 if (on) {
369 if (ispif->power_count) {
370 /* Power is already on */
371 ispif->power_count++;
372 goto exit;
373 }
374
375 ret = pm_runtime_resume_and_get(dev);
376 if (ret < 0)
377 goto exit;
378
379 ret = camss_enable_clocks(ispif->nclocks, ispif->clock, dev);
380 if (ret < 0) {
381 pm_runtime_put_sync(dev);
382 goto exit;
383 }
384
385 ret = ispif_reset(ispif, line->vfe_id);
386 if (ret < 0) {
387 pm_runtime_put_sync(dev);
388 camss_disable_clocks(ispif->nclocks, ispif->clock);
389 goto exit;
390 }
391
392 ispif->intf_cmd[line->vfe_id].cmd_0 = CMD_ALL_NO_CHANGE;
393 ispif->intf_cmd[line->vfe_id].cmd_1 = CMD_ALL_NO_CHANGE;
394
395 ispif->power_count++;
396 } else {
397 if (ispif->power_count == 0) {
398 dev_err(dev, "ispif power off on power_count == 0\n");
399 goto exit;
400 } else if (ispif->power_count == 1) {
401 camss_disable_clocks(ispif->nclocks, ispif->clock);
402 pm_runtime_put_sync(dev);
403 }
404
405 ispif->power_count--;
406 }
407
408 exit:
409 mutex_unlock(&ispif->power_lock);
410
411 return ret;
412 }
413
414 /*
415 * ispif_select_clk_mux - Select clock for PIX/RDI interface
416 * @ispif: ISPIF device
417 * @intf: VFE interface
418 * @csid: CSID HW module id
419 * @vfe: VFE HW module id
420 * @enable: enable or disable the selected clock
421 */
ispif_select_clk_mux(struct ispif_device * ispif,enum ispif_intf intf,u8 csid,u8 vfe,u8 enable)422 static void ispif_select_clk_mux(struct ispif_device *ispif,
423 enum ispif_intf intf, u8 csid,
424 u8 vfe, u8 enable)
425 {
426 u32 val;
427
428 switch (intf) {
429 case PIX0:
430 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
431 val &= ~(0xf << (vfe * 8));
432 if (enable)
433 val |= (csid << (vfe * 8));
434 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
435 break;
436
437 case RDI0:
438 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
439 val &= ~(0xf << (vfe * 12));
440 if (enable)
441 val |= (csid << (vfe * 12));
442 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
443 break;
444
445 case PIX1:
446 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
447 val &= ~(0xf << (4 + (vfe * 8)));
448 if (enable)
449 val |= (csid << (4 + (vfe * 8)));
450 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
451 break;
452
453 case RDI1:
454 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
455 val &= ~(0xf << (4 + (vfe * 12)));
456 if (enable)
457 val |= (csid << (4 + (vfe * 12)));
458 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
459 break;
460
461 case RDI2:
462 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
463 val &= ~(0xf << (8 + (vfe * 12)));
464 if (enable)
465 val |= (csid << (8 + (vfe * 12)));
466 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
467 break;
468 }
469
470 mb();
471 }
472
473 /*
474 * ispif_validate_intf_status - Validate current status of PIX/RDI interface
475 * @ispif: ISPIF device
476 * @intf: VFE interface
477 * @vfe: VFE HW module id
478 *
479 * Return 0 when interface is idle or -EBUSY otherwise
480 */
ispif_validate_intf_status(struct ispif_device * ispif,enum ispif_intf intf,u8 vfe)481 static int ispif_validate_intf_status(struct ispif_device *ispif,
482 enum ispif_intf intf, u8 vfe)
483 {
484 int ret = 0;
485 u32 val = 0;
486
487 switch (intf) {
488 case PIX0:
489 val = readl_relaxed(ispif->base +
490 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0));
491 break;
492 case RDI0:
493 val = readl_relaxed(ispif->base +
494 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0));
495 break;
496 case PIX1:
497 val = readl_relaxed(ispif->base +
498 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1));
499 break;
500 case RDI1:
501 val = readl_relaxed(ispif->base +
502 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1));
503 break;
504 case RDI2:
505 val = readl_relaxed(ispif->base +
506 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2));
507 break;
508 }
509
510 if ((val & 0xf) != 0xf) {
511 dev_err(ispif->camss->dev, "%s: ispif is busy: 0x%x\n",
512 __func__, val);
513 ret = -EBUSY;
514 }
515
516 return ret;
517 }
518
519 /*
520 * ispif_wait_for_stop - Wait for PIX/RDI interface to stop
521 * @ispif: ISPIF device
522 * @intf: VFE interface
523 * @vfe: VFE HW module id
524 *
525 * Return 0 on success or a negative error code otherwise
526 */
ispif_wait_for_stop(struct ispif_device * ispif,enum ispif_intf intf,u8 vfe)527 static int ispif_wait_for_stop(struct ispif_device *ispif,
528 enum ispif_intf intf, u8 vfe)
529 {
530 u32 addr = 0;
531 u32 stop_flag = 0;
532 int ret;
533
534 switch (intf) {
535 case PIX0:
536 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0);
537 break;
538 case RDI0:
539 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0);
540 break;
541 case PIX1:
542 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1);
543 break;
544 case RDI1:
545 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1);
546 break;
547 case RDI2:
548 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2);
549 break;
550 }
551
552 ret = readl_poll_timeout(ispif->base + addr,
553 stop_flag,
554 (stop_flag & 0xf) == 0xf,
555 ISPIF_TIMEOUT_SLEEP_US,
556 ISPIF_TIMEOUT_ALL_US);
557 if (ret < 0)
558 dev_err(ispif->camss->dev, "%s: ispif stop timeout\n",
559 __func__);
560
561 return ret;
562 }
563
564 /*
565 * ispif_select_csid - Select CSID HW module for input from
566 * @ispif: ISPIF device
567 * @intf: VFE interface
568 * @csid: CSID HW module id
569 * @vfe: VFE HW module id
570 * @enable: enable or disable the selected input
571 */
ispif_select_csid(struct ispif_device * ispif,enum ispif_intf intf,u8 csid,u8 vfe,u8 enable)572 static void ispif_select_csid(struct ispif_device *ispif, enum ispif_intf intf,
573 u8 csid, u8 vfe, u8 enable)
574 {
575 u32 val;
576
577 val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
578 switch (intf) {
579 case PIX0:
580 val &= ~(BIT(1) | BIT(0));
581 if (enable)
582 val |= csid;
583 break;
584 case RDI0:
585 val &= ~(BIT(5) | BIT(4));
586 if (enable)
587 val |= (csid << 4);
588 break;
589 case PIX1:
590 val &= ~(BIT(9) | BIT(8));
591 if (enable)
592 val |= (csid << 8);
593 break;
594 case RDI1:
595 val &= ~(BIT(13) | BIT(12));
596 if (enable)
597 val |= (csid << 12);
598 break;
599 case RDI2:
600 val &= ~(BIT(21) | BIT(20));
601 if (enable)
602 val |= (csid << 20);
603 break;
604 }
605
606 writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
607 }
608
609 /*
610 * ispif_select_cid - Enable/disable desired CID
611 * @ispif: ISPIF device
612 * @intf: VFE interface
613 * @cid: desired CID to enable/disable
614 * @vfe: VFE HW module id
615 * @enable: enable or disable the desired CID
616 */
ispif_select_cid(struct ispif_device * ispif,enum ispif_intf intf,u8 cid,u8 vfe,u8 enable)617 static void ispif_select_cid(struct ispif_device *ispif, enum ispif_intf intf,
618 u8 cid, u8 vfe, u8 enable)
619 {
620 u32 cid_mask = 1 << cid;
621 u32 addr = 0;
622 u32 val;
623
624 switch (intf) {
625 case PIX0:
626 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0);
627 break;
628 case RDI0:
629 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0);
630 break;
631 case PIX1:
632 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1);
633 break;
634 case RDI1:
635 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1);
636 break;
637 case RDI2:
638 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2);
639 break;
640 }
641
642 val = readl_relaxed(ispif->base + addr);
643 if (enable)
644 val |= cid_mask;
645 else
646 val &= ~cid_mask;
647
648 writel(val, ispif->base + addr);
649 }
650
651 /*
652 * ispif_config_irq - Enable/disable interrupts for PIX/RDI interface
653 * @ispif: ISPIF device
654 * @intf: VFE interface
655 * @vfe: VFE HW module id
656 * @enable: enable or disable
657 */
ispif_config_irq(struct ispif_device * ispif,enum ispif_intf intf,u8 vfe,u8 enable)658 static void ispif_config_irq(struct ispif_device *ispif, enum ispif_intf intf,
659 u8 vfe, u8 enable)
660 {
661 u32 val;
662
663 switch (intf) {
664 case PIX0:
665 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
666 val &= ~ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK;
667 if (enable)
668 val |= ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE;
669 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
670 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE,
671 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
672 break;
673 case RDI0:
674 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
675 val &= ~ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK;
676 if (enable)
677 val |= ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE;
678 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
679 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE,
680 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
681 break;
682 case PIX1:
683 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
684 val &= ~ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK;
685 if (enable)
686 val |= ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE;
687 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
688 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE,
689 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
690 break;
691 case RDI1:
692 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
693 val &= ~ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK;
694 if (enable)
695 val |= ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE;
696 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
697 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE,
698 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
699 break;
700 case RDI2:
701 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
702 val &= ~ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK;
703 if (enable)
704 val |= ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE;
705 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
706 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE,
707 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe));
708 break;
709 }
710
711 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
712 }
713
714 /*
715 * ispif_config_pack - Config packing for PRDI mode
716 * @ispif: ISPIF device
717 * @code: media bus format code
718 * @intf: VFE interface
719 * @cid: desired CID to handle
720 * @vfe: VFE HW module id
721 * @enable: enable or disable
722 */
ispif_config_pack(struct ispif_device * ispif,u32 code,enum ispif_intf intf,u8 cid,u8 vfe,u8 enable)723 static void ispif_config_pack(struct ispif_device *ispif, u32 code,
724 enum ispif_intf intf, u8 cid, u8 vfe, u8 enable)
725 {
726 u32 addr, val;
727
728 if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE &&
729 code != MEDIA_BUS_FMT_Y10_2X8_PADHI_LE)
730 return;
731
732 switch (intf) {
733 case RDI0:
734 if (cid < 8)
735 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0);
736 else
737 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0);
738 break;
739 case RDI1:
740 if (cid < 8)
741 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1);
742 else
743 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1);
744 break;
745 case RDI2:
746 if (cid < 8)
747 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2);
748 else
749 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2);
750 break;
751 default:
752 return;
753 }
754
755 if (enable)
756 val = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(cid);
757 else
758 val = 0;
759
760 writel_relaxed(val, ispif->base + addr);
761 }
762
763 /*
764 * ispif_set_intf_cmd - Set command to enable/disable interface
765 * @ispif: ISPIF device
766 * @cmd: interface command
767 * @intf: VFE interface
768 * @vfe: VFE HW module id
769 * @vc: virtual channel
770 */
ispif_set_intf_cmd(struct ispif_device * ispif,u8 cmd,enum ispif_intf intf,u8 vfe,u8 vc)771 static void ispif_set_intf_cmd(struct ispif_device *ispif, u8 cmd,
772 enum ispif_intf intf, u8 vfe, u8 vc)
773 {
774 u32 *val;
775
776 if (intf == RDI2) {
777 val = &ispif->intf_cmd[vfe].cmd_1;
778 *val &= ~(0x3 << (vc * 2 + 8));
779 *val |= (cmd << (vc * 2 + 8));
780 wmb();
781 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe));
782 wmb();
783 } else {
784 val = &ispif->intf_cmd[vfe].cmd_0;
785 *val &= ~(0x3 << (vc * 2 + intf * 8));
786 *val |= (cmd << (vc * 2 + intf * 8));
787 wmb();
788 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe));
789 wmb();
790 }
791 }
792
793 /*
794 * ispif_set_stream - Enable/disable streaming on ISPIF module
795 * @sd: ISPIF V4L2 subdevice
796 * @enable: Requested streaming state
797 *
798 * Main configuration of ISPIF module is also done here.
799 *
800 * Return 0 on success or a negative error code otherwise
801 */
ispif_set_stream(struct v4l2_subdev * sd,int enable)802 static int ispif_set_stream(struct v4l2_subdev *sd, int enable)
803 {
804 struct ispif_line *line = v4l2_get_subdevdata(sd);
805 struct ispif_device *ispif = line->ispif;
806 struct camss *camss = ispif->camss;
807 enum ispif_intf intf = line->interface;
808 u8 csid = line->csid_id;
809 u8 vfe = line->vfe_id;
810 u8 vc = 0; /* Virtual Channel 0 */
811 u8 cid = vc * 4; /* id of Virtual Channel and Data Type set */
812 int ret;
813
814 if (enable) {
815 if (!media_entity_remote_pad(&line->pads[MSM_ISPIF_PAD_SINK]))
816 return -ENOLINK;
817
818 /* Config */
819
820 mutex_lock(&ispif->config_lock);
821 ispif_select_clk_mux(ispif, intf, csid, vfe, 1);
822
823 ret = ispif_validate_intf_status(ispif, intf, vfe);
824 if (ret < 0) {
825 mutex_unlock(&ispif->config_lock);
826 return ret;
827 }
828
829 ispif_select_csid(ispif, intf, csid, vfe, 1);
830 ispif_select_cid(ispif, intf, cid, vfe, 1);
831 ispif_config_irq(ispif, intf, vfe, 1);
832 if (camss->version == CAMSS_8x96 ||
833 camss->version == CAMSS_660)
834 ispif_config_pack(ispif,
835 line->fmt[MSM_ISPIF_PAD_SINK].code,
836 intf, cid, vfe, 1);
837 ispif_set_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY,
838 intf, vfe, vc);
839 } else {
840 mutex_lock(&ispif->config_lock);
841 ispif_set_intf_cmd(ispif, CMD_DISABLE_FRAME_BOUNDARY,
842 intf, vfe, vc);
843 mutex_unlock(&ispif->config_lock);
844
845 ret = ispif_wait_for_stop(ispif, intf, vfe);
846 if (ret < 0)
847 return ret;
848
849 mutex_lock(&ispif->config_lock);
850 if (camss->version == CAMSS_8x96 ||
851 camss->version == CAMSS_660)
852 ispif_config_pack(ispif,
853 line->fmt[MSM_ISPIF_PAD_SINK].code,
854 intf, cid, vfe, 0);
855 ispif_config_irq(ispif, intf, vfe, 0);
856 ispif_select_cid(ispif, intf, cid, vfe, 0);
857 ispif_select_csid(ispif, intf, csid, vfe, 0);
858 ispif_select_clk_mux(ispif, intf, csid, vfe, 0);
859 }
860
861 mutex_unlock(&ispif->config_lock);
862
863 return 0;
864 }
865
866 /*
867 * __ispif_get_format - Get pointer to format structure
868 * @ispif: ISPIF line
869 * @cfg: V4L2 subdev pad configuration
870 * @pad: pad from which format is requested
871 * @which: TRY or ACTIVE format
872 *
873 * Return pointer to TRY or ACTIVE format structure
874 */
875 static struct v4l2_mbus_framefmt *
__ispif_get_format(struct ispif_line * line,struct v4l2_subdev_state * sd_state,unsigned int pad,enum v4l2_subdev_format_whence which)876 __ispif_get_format(struct ispif_line *line,
877 struct v4l2_subdev_state *sd_state,
878 unsigned int pad,
879 enum v4l2_subdev_format_whence which)
880 {
881 if (which == V4L2_SUBDEV_FORMAT_TRY)
882 return v4l2_subdev_get_try_format(&line->subdev, sd_state,
883 pad);
884
885 return &line->fmt[pad];
886 }
887
888 /*
889 * ispif_try_format - Handle try format by pad subdev method
890 * @ispif: ISPIF line
891 * @cfg: V4L2 subdev pad configuration
892 * @pad: pad on which format is requested
893 * @fmt: pointer to v4l2 format structure
894 * @which: wanted subdev format
895 */
ispif_try_format(struct ispif_line * line,struct v4l2_subdev_state * sd_state,unsigned int pad,struct v4l2_mbus_framefmt * fmt,enum v4l2_subdev_format_whence which)896 static void ispif_try_format(struct ispif_line *line,
897 struct v4l2_subdev_state *sd_state,
898 unsigned int pad,
899 struct v4l2_mbus_framefmt *fmt,
900 enum v4l2_subdev_format_whence which)
901 {
902 unsigned int i;
903
904 switch (pad) {
905 case MSM_ISPIF_PAD_SINK:
906 /* Set format on sink pad */
907
908 for (i = 0; i < line->nformats; i++)
909 if (fmt->code == line->formats[i])
910 break;
911
912 /* If not found, use UYVY as default */
913 if (i >= line->nformats)
914 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
915
916 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
917 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
918
919 fmt->field = V4L2_FIELD_NONE;
920 fmt->colorspace = V4L2_COLORSPACE_SRGB;
921
922 break;
923
924 case MSM_ISPIF_PAD_SRC:
925 /* Set and return a format same as sink pad */
926
927 *fmt = *__ispif_get_format(line, sd_state, MSM_ISPIF_PAD_SINK,
928 which);
929
930 break;
931 }
932
933 fmt->colorspace = V4L2_COLORSPACE_SRGB;
934 }
935
936 /*
937 * ispif_enum_mbus_code - Handle pixel format enumeration
938 * @sd: ISPIF V4L2 subdevice
939 * @cfg: V4L2 subdev pad configuration
940 * @code: pointer to v4l2_subdev_mbus_code_enum structure
941 * return -EINVAL or zero on success
942 */
ispif_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)943 static int ispif_enum_mbus_code(struct v4l2_subdev *sd,
944 struct v4l2_subdev_state *sd_state,
945 struct v4l2_subdev_mbus_code_enum *code)
946 {
947 struct ispif_line *line = v4l2_get_subdevdata(sd);
948 struct v4l2_mbus_framefmt *format;
949
950 if (code->pad == MSM_ISPIF_PAD_SINK) {
951 if (code->index >= line->nformats)
952 return -EINVAL;
953
954 code->code = line->formats[code->index];
955 } else {
956 if (code->index > 0)
957 return -EINVAL;
958
959 format = __ispif_get_format(line, sd_state,
960 MSM_ISPIF_PAD_SINK,
961 code->which);
962
963 code->code = format->code;
964 }
965
966 return 0;
967 }
968
969 /*
970 * ispif_enum_frame_size - Handle frame size enumeration
971 * @sd: ISPIF V4L2 subdevice
972 * @cfg: V4L2 subdev pad configuration
973 * @fse: pointer to v4l2_subdev_frame_size_enum structure
974 * return -EINVAL or zero on success
975 */
ispif_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)976 static int ispif_enum_frame_size(struct v4l2_subdev *sd,
977 struct v4l2_subdev_state *sd_state,
978 struct v4l2_subdev_frame_size_enum *fse)
979 {
980 struct ispif_line *line = v4l2_get_subdevdata(sd);
981 struct v4l2_mbus_framefmt format;
982
983 if (fse->index != 0)
984 return -EINVAL;
985
986 format.code = fse->code;
987 format.width = 1;
988 format.height = 1;
989 ispif_try_format(line, sd_state, fse->pad, &format, fse->which);
990 fse->min_width = format.width;
991 fse->min_height = format.height;
992
993 if (format.code != fse->code)
994 return -EINVAL;
995
996 format.code = fse->code;
997 format.width = -1;
998 format.height = -1;
999 ispif_try_format(line, sd_state, fse->pad, &format, fse->which);
1000 fse->max_width = format.width;
1001 fse->max_height = format.height;
1002
1003 return 0;
1004 }
1005
1006 /*
1007 * ispif_get_format - Handle get format by pads subdev method
1008 * @sd: ISPIF V4L2 subdevice
1009 * @cfg: V4L2 subdev pad configuration
1010 * @fmt: pointer to v4l2 subdev format structure
1011 *
1012 * Return -EINVAL or zero on success
1013 */
ispif_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)1014 static int ispif_get_format(struct v4l2_subdev *sd,
1015 struct v4l2_subdev_state *sd_state,
1016 struct v4l2_subdev_format *fmt)
1017 {
1018 struct ispif_line *line = v4l2_get_subdevdata(sd);
1019 struct v4l2_mbus_framefmt *format;
1020
1021 format = __ispif_get_format(line, sd_state, fmt->pad, fmt->which);
1022 if (format == NULL)
1023 return -EINVAL;
1024
1025 fmt->format = *format;
1026
1027 return 0;
1028 }
1029
1030 /*
1031 * ispif_set_format - Handle set format by pads subdev method
1032 * @sd: ISPIF V4L2 subdevice
1033 * @cfg: V4L2 subdev pad configuration
1034 * @fmt: pointer to v4l2 subdev format structure
1035 *
1036 * Return -EINVAL or zero on success
1037 */
ispif_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)1038 static int ispif_set_format(struct v4l2_subdev *sd,
1039 struct v4l2_subdev_state *sd_state,
1040 struct v4l2_subdev_format *fmt)
1041 {
1042 struct ispif_line *line = v4l2_get_subdevdata(sd);
1043 struct v4l2_mbus_framefmt *format;
1044
1045 format = __ispif_get_format(line, sd_state, fmt->pad, fmt->which);
1046 if (format == NULL)
1047 return -EINVAL;
1048
1049 ispif_try_format(line, sd_state, fmt->pad, &fmt->format, fmt->which);
1050 *format = fmt->format;
1051
1052 /* Propagate the format from sink to source */
1053 if (fmt->pad == MSM_ISPIF_PAD_SINK) {
1054 format = __ispif_get_format(line, sd_state, MSM_ISPIF_PAD_SRC,
1055 fmt->which);
1056
1057 *format = fmt->format;
1058 ispif_try_format(line, sd_state, MSM_ISPIF_PAD_SRC, format,
1059 fmt->which);
1060 }
1061
1062 return 0;
1063 }
1064
1065 /*
1066 * ispif_init_formats - Initialize formats on all pads
1067 * @sd: ISPIF V4L2 subdevice
1068 * @fh: V4L2 subdev file handle
1069 *
1070 * Initialize all pad formats with default values.
1071 *
1072 * Return 0 on success or a negative error code otherwise
1073 */
ispif_init_formats(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1074 static int ispif_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1075 {
1076 struct v4l2_subdev_format format = {
1077 .pad = MSM_ISPIF_PAD_SINK,
1078 .which = fh ? V4L2_SUBDEV_FORMAT_TRY :
1079 V4L2_SUBDEV_FORMAT_ACTIVE,
1080 .format = {
1081 .code = MEDIA_BUS_FMT_UYVY8_2X8,
1082 .width = 1920,
1083 .height = 1080
1084 }
1085 };
1086
1087 return ispif_set_format(sd, fh ? fh->state : NULL, &format);
1088 }
1089
1090 /*
1091 * msm_ispif_subdev_init - Initialize ISPIF device structure and resources
1092 * @ispif: ISPIF device
1093 * @res: ISPIF module resources table
1094 *
1095 * Return 0 on success or a negative error code otherwise
1096 */
msm_ispif_subdev_init(struct camss * camss,const struct resources_ispif * res)1097 int msm_ispif_subdev_init(struct camss *camss,
1098 const struct resources_ispif *res)
1099 {
1100 struct device *dev = camss->dev;
1101 struct ispif_device *ispif = camss->ispif;
1102 struct platform_device *pdev = to_platform_device(dev);
1103 int i;
1104 int ret;
1105
1106 if (!camss->ispif)
1107 return 0;
1108
1109 ispif->camss = camss;
1110
1111 /* Number of ISPIF lines - same as number of CSID hardware modules */
1112 if (camss->version == CAMSS_8x16)
1113 ispif->line_num = 2;
1114 else if (camss->version == CAMSS_8x96 ||
1115 camss->version == CAMSS_660)
1116 ispif->line_num = 4;
1117 else
1118 return -EINVAL;
1119
1120 ispif->line = devm_kcalloc(dev, ispif->line_num,
1121 sizeof(*ispif->line), GFP_KERNEL);
1122 if (!ispif->line)
1123 return -ENOMEM;
1124
1125 for (i = 0; i < ispif->line_num; i++) {
1126 ispif->line[i].ispif = ispif;
1127 ispif->line[i].id = i;
1128
1129 if (camss->version == CAMSS_8x16) {
1130 ispif->line[i].formats = ispif_formats_8x16;
1131 ispif->line[i].nformats =
1132 ARRAY_SIZE(ispif_formats_8x16);
1133 } else if (camss->version == CAMSS_8x96 ||
1134 camss->version == CAMSS_660) {
1135 ispif->line[i].formats = ispif_formats_8x96;
1136 ispif->line[i].nformats =
1137 ARRAY_SIZE(ispif_formats_8x96);
1138 } else {
1139 return -EINVAL;
1140 }
1141 }
1142
1143 /* Memory */
1144
1145 ispif->base = devm_platform_ioremap_resource_byname(pdev, res->reg[0]);
1146 if (IS_ERR(ispif->base))
1147 return PTR_ERR(ispif->base);
1148
1149 ispif->base_clk_mux = devm_platform_ioremap_resource_byname(pdev, res->reg[1]);
1150 if (IS_ERR(ispif->base_clk_mux))
1151 return PTR_ERR(ispif->base_clk_mux);
1152
1153 /* Interrupt */
1154
1155 ret = platform_get_irq_byname(pdev, res->interrupt);
1156 if (ret < 0)
1157 return ret;
1158
1159 ispif->irq = ret;
1160 snprintf(ispif->irq_name, sizeof(ispif->irq_name), "%s_%s",
1161 dev_name(dev), MSM_ISPIF_NAME);
1162 if (camss->version == CAMSS_8x16)
1163 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x16,
1164 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1165 else if (camss->version == CAMSS_8x96 ||
1166 camss->version == CAMSS_660)
1167 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x96,
1168 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1169 else
1170 ret = -EINVAL;
1171
1172 if (ret < 0) {
1173 dev_err(dev, "request_irq failed: %d\n", ret);
1174 return ret;
1175 }
1176
1177 /* Clocks */
1178
1179 ispif->nclocks = 0;
1180 while (res->clock[ispif->nclocks])
1181 ispif->nclocks++;
1182
1183 ispif->clock = devm_kcalloc(dev,
1184 ispif->nclocks, sizeof(*ispif->clock),
1185 GFP_KERNEL);
1186 if (!ispif->clock)
1187 return -ENOMEM;
1188
1189 for (i = 0; i < ispif->nclocks; i++) {
1190 struct camss_clock *clock = &ispif->clock[i];
1191
1192 clock->clk = devm_clk_get(dev, res->clock[i]);
1193 if (IS_ERR(clock->clk))
1194 return PTR_ERR(clock->clk);
1195
1196 clock->freq = NULL;
1197 clock->nfreqs = 0;
1198 }
1199
1200 ispif->nclocks_for_reset = 0;
1201 while (res->clock_for_reset[ispif->nclocks_for_reset])
1202 ispif->nclocks_for_reset++;
1203
1204 ispif->clock_for_reset = devm_kcalloc(dev,
1205 ispif->nclocks_for_reset,
1206 sizeof(*ispif->clock_for_reset),
1207 GFP_KERNEL);
1208 if (!ispif->clock_for_reset)
1209 return -ENOMEM;
1210
1211 for (i = 0; i < ispif->nclocks_for_reset; i++) {
1212 struct camss_clock *clock = &ispif->clock_for_reset[i];
1213
1214 clock->clk = devm_clk_get(dev, res->clock_for_reset[i]);
1215 if (IS_ERR(clock->clk))
1216 return PTR_ERR(clock->clk);
1217
1218 clock->freq = NULL;
1219 clock->nfreqs = 0;
1220 }
1221
1222 mutex_init(&ispif->power_lock);
1223 ispif->power_count = 0;
1224
1225 mutex_init(&ispif->config_lock);
1226
1227 for (i = 0; i < MSM_ISPIF_VFE_NUM; i++)
1228 init_completion(&ispif->reset_complete[i]);
1229
1230 return 0;
1231 }
1232
1233 /*
1234 * ispif_get_intf - Get ISPIF interface to use by VFE line id
1235 * @line_id: VFE line id that the ISPIF line is connected to
1236 *
1237 * Return ISPIF interface to use
1238 */
ispif_get_intf(enum vfe_line_id line_id)1239 static enum ispif_intf ispif_get_intf(enum vfe_line_id line_id)
1240 {
1241 switch (line_id) {
1242 case (VFE_LINE_RDI0):
1243 return RDI0;
1244 case (VFE_LINE_RDI1):
1245 return RDI1;
1246 case (VFE_LINE_RDI2):
1247 return RDI2;
1248 case (VFE_LINE_PIX):
1249 return PIX0;
1250 default:
1251 return RDI0;
1252 }
1253 }
1254
1255 /*
1256 * ispif_link_setup - Setup ISPIF connections
1257 * @entity: Pointer to media entity structure
1258 * @local: Pointer to local pad
1259 * @remote: Pointer to remote pad
1260 * @flags: Link flags
1261 *
1262 * Return 0 on success
1263 */
ispif_link_setup(struct media_entity * entity,const struct media_pad * local,const struct media_pad * remote,u32 flags)1264 static int ispif_link_setup(struct media_entity *entity,
1265 const struct media_pad *local,
1266 const struct media_pad *remote, u32 flags)
1267 {
1268 if (flags & MEDIA_LNK_FL_ENABLED) {
1269 if (media_entity_remote_pad(local))
1270 return -EBUSY;
1271
1272 if (local->flags & MEDIA_PAD_FL_SINK) {
1273 struct v4l2_subdev *sd;
1274 struct ispif_line *line;
1275
1276 sd = media_entity_to_v4l2_subdev(entity);
1277 line = v4l2_get_subdevdata(sd);
1278
1279 msm_csid_get_csid_id(remote->entity, &line->csid_id);
1280 } else { /* MEDIA_PAD_FL_SOURCE */
1281 struct v4l2_subdev *sd;
1282 struct ispif_line *line;
1283 enum vfe_line_id id;
1284
1285 sd = media_entity_to_v4l2_subdev(entity);
1286 line = v4l2_get_subdevdata(sd);
1287
1288 msm_vfe_get_vfe_id(remote->entity, &line->vfe_id);
1289 msm_vfe_get_vfe_line_id(remote->entity, &id);
1290 line->interface = ispif_get_intf(id);
1291 }
1292 }
1293
1294 return 0;
1295 }
1296
1297 static const struct v4l2_subdev_core_ops ispif_core_ops = {
1298 .s_power = ispif_set_power,
1299 };
1300
1301 static const struct v4l2_subdev_video_ops ispif_video_ops = {
1302 .s_stream = ispif_set_stream,
1303 };
1304
1305 static const struct v4l2_subdev_pad_ops ispif_pad_ops = {
1306 .enum_mbus_code = ispif_enum_mbus_code,
1307 .enum_frame_size = ispif_enum_frame_size,
1308 .get_fmt = ispif_get_format,
1309 .set_fmt = ispif_set_format,
1310 };
1311
1312 static const struct v4l2_subdev_ops ispif_v4l2_ops = {
1313 .core = &ispif_core_ops,
1314 .video = &ispif_video_ops,
1315 .pad = &ispif_pad_ops,
1316 };
1317
1318 static const struct v4l2_subdev_internal_ops ispif_v4l2_internal_ops = {
1319 .open = ispif_init_formats,
1320 };
1321
1322 static const struct media_entity_operations ispif_media_ops = {
1323 .link_setup = ispif_link_setup,
1324 .link_validate = v4l2_subdev_link_validate,
1325 };
1326
1327 /*
1328 * msm_ispif_register_entities - Register subdev node for ISPIF module
1329 * @ispif: ISPIF device
1330 * @v4l2_dev: V4L2 device
1331 *
1332 * Return 0 on success or a negative error code otherwise
1333 */
msm_ispif_register_entities(struct ispif_device * ispif,struct v4l2_device * v4l2_dev)1334 int msm_ispif_register_entities(struct ispif_device *ispif,
1335 struct v4l2_device *v4l2_dev)
1336 {
1337 struct camss *camss;
1338 int ret;
1339 int i;
1340
1341 if (!ispif)
1342 return 0;
1343
1344 camss = ispif->camss;
1345
1346 for (i = 0; i < ispif->line_num; i++) {
1347 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1348 struct media_pad *pads = ispif->line[i].pads;
1349
1350 v4l2_subdev_init(sd, &ispif_v4l2_ops);
1351 sd->internal_ops = &ispif_v4l2_internal_ops;
1352 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1353 snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d",
1354 MSM_ISPIF_NAME, i);
1355 v4l2_set_subdevdata(sd, &ispif->line[i]);
1356
1357 ret = ispif_init_formats(sd, NULL);
1358 if (ret < 0) {
1359 dev_err(camss->dev, "Failed to init format: %d\n", ret);
1360 goto error;
1361 }
1362
1363 pads[MSM_ISPIF_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1364 pads[MSM_ISPIF_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
1365
1366 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1367 sd->entity.ops = &ispif_media_ops;
1368 ret = media_entity_pads_init(&sd->entity, MSM_ISPIF_PADS_NUM,
1369 pads);
1370 if (ret < 0) {
1371 dev_err(camss->dev, "Failed to init media entity: %d\n",
1372 ret);
1373 goto error;
1374 }
1375
1376 ret = v4l2_device_register_subdev(v4l2_dev, sd);
1377 if (ret < 0) {
1378 dev_err(camss->dev, "Failed to register subdev: %d\n",
1379 ret);
1380 media_entity_cleanup(&sd->entity);
1381 goto error;
1382 }
1383 }
1384
1385 return 0;
1386
1387 error:
1388 for (i--; i >= 0; i--) {
1389 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1390
1391 v4l2_device_unregister_subdev(sd);
1392 media_entity_cleanup(&sd->entity);
1393 }
1394
1395 return ret;
1396 }
1397
1398 /*
1399 * msm_ispif_unregister_entities - Unregister ISPIF module subdev node
1400 * @ispif: ISPIF device
1401 */
msm_ispif_unregister_entities(struct ispif_device * ispif)1402 void msm_ispif_unregister_entities(struct ispif_device *ispif)
1403 {
1404 int i;
1405
1406 if (!ispif)
1407 return;
1408
1409 mutex_destroy(&ispif->power_lock);
1410 mutex_destroy(&ispif->config_lock);
1411
1412 for (i = 0; i < ispif->line_num; i++) {
1413 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1414
1415 v4l2_device_unregister_subdev(sd);
1416 media_entity_cleanup(&sd->entity);
1417 }
1418 }
1419