1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  */
6 
7 #include "msm_gpu.h"
8 #include "msm_gem.h"
9 #include "msm_mmu.h"
10 #include "msm_fence.h"
11 #include "msm_gpu_trace.h"
12 #include "adreno/adreno_gpu.h"
13 
14 #include <generated/utsrelease.h>
15 #include <linux/string_helpers.h>
16 #include <linux/devcoredump.h>
17 #include <linux/sched/task.h>
18 
19 /*
20  * Power Management:
21  */
22 
enable_pwrrail(struct msm_gpu * gpu)23 static int enable_pwrrail(struct msm_gpu *gpu)
24 {
25 	struct drm_device *dev = gpu->dev;
26 	int ret = 0;
27 
28 	if (gpu->gpu_reg) {
29 		ret = regulator_enable(gpu->gpu_reg);
30 		if (ret) {
31 			DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
32 			return ret;
33 		}
34 	}
35 
36 	if (gpu->gpu_cx) {
37 		ret = regulator_enable(gpu->gpu_cx);
38 		if (ret) {
39 			DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
40 			return ret;
41 		}
42 	}
43 
44 	return 0;
45 }
46 
disable_pwrrail(struct msm_gpu * gpu)47 static int disable_pwrrail(struct msm_gpu *gpu)
48 {
49 	if (gpu->gpu_cx)
50 		regulator_disable(gpu->gpu_cx);
51 	if (gpu->gpu_reg)
52 		regulator_disable(gpu->gpu_reg);
53 	return 0;
54 }
55 
enable_clk(struct msm_gpu * gpu)56 static int enable_clk(struct msm_gpu *gpu)
57 {
58 	if (gpu->core_clk && gpu->fast_rate)
59 		clk_set_rate(gpu->core_clk, gpu->fast_rate);
60 
61 	/* Set the RBBM timer rate to 19.2Mhz */
62 	if (gpu->rbbmtimer_clk)
63 		clk_set_rate(gpu->rbbmtimer_clk, 19200000);
64 
65 	return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
66 }
67 
disable_clk(struct msm_gpu * gpu)68 static int disable_clk(struct msm_gpu *gpu)
69 {
70 	clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
71 
72 	/*
73 	 * Set the clock to a deliberately low rate. On older targets the clock
74 	 * speed had to be non zero to avoid problems. On newer targets this
75 	 * will be rounded down to zero anyway so it all works out.
76 	 */
77 	if (gpu->core_clk)
78 		clk_set_rate(gpu->core_clk, 27000000);
79 
80 	if (gpu->rbbmtimer_clk)
81 		clk_set_rate(gpu->rbbmtimer_clk, 0);
82 
83 	return 0;
84 }
85 
enable_axi(struct msm_gpu * gpu)86 static int enable_axi(struct msm_gpu *gpu)
87 {
88 	return clk_prepare_enable(gpu->ebi1_clk);
89 }
90 
disable_axi(struct msm_gpu * gpu)91 static int disable_axi(struct msm_gpu *gpu)
92 {
93 	clk_disable_unprepare(gpu->ebi1_clk);
94 	return 0;
95 }
96 
msm_gpu_pm_resume(struct msm_gpu * gpu)97 int msm_gpu_pm_resume(struct msm_gpu *gpu)
98 {
99 	int ret;
100 
101 	DBG("%s", gpu->name);
102 	trace_msm_gpu_resume(0);
103 
104 	ret = enable_pwrrail(gpu);
105 	if (ret)
106 		return ret;
107 
108 	ret = enable_clk(gpu);
109 	if (ret)
110 		return ret;
111 
112 	ret = enable_axi(gpu);
113 	if (ret)
114 		return ret;
115 
116 	msm_devfreq_resume(gpu);
117 
118 	gpu->needs_hw_init = true;
119 
120 	return 0;
121 }
122 
msm_gpu_pm_suspend(struct msm_gpu * gpu)123 int msm_gpu_pm_suspend(struct msm_gpu *gpu)
124 {
125 	int ret;
126 
127 	DBG("%s", gpu->name);
128 	trace_msm_gpu_suspend(0);
129 
130 	msm_devfreq_suspend(gpu);
131 
132 	ret = disable_axi(gpu);
133 	if (ret)
134 		return ret;
135 
136 	ret = disable_clk(gpu);
137 	if (ret)
138 		return ret;
139 
140 	ret = disable_pwrrail(gpu);
141 	if (ret)
142 		return ret;
143 
144 	gpu->suspend_count++;
145 
146 	return 0;
147 }
148 
msm_gpu_hw_init(struct msm_gpu * gpu)149 int msm_gpu_hw_init(struct msm_gpu *gpu)
150 {
151 	int ret;
152 
153 	WARN_ON(!mutex_is_locked(&gpu->lock));
154 
155 	if (!gpu->needs_hw_init)
156 		return 0;
157 
158 	disable_irq(gpu->irq);
159 	ret = gpu->funcs->hw_init(gpu);
160 	if (!ret)
161 		gpu->needs_hw_init = false;
162 	enable_irq(gpu->irq);
163 
164 	return ret;
165 }
166 
167 #ifdef CONFIG_DEV_COREDUMP
msm_gpu_devcoredump_read(char * buffer,loff_t offset,size_t count,void * data,size_t datalen)168 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
169 		size_t count, void *data, size_t datalen)
170 {
171 	struct msm_gpu *gpu = data;
172 	struct drm_print_iterator iter;
173 	struct drm_printer p;
174 	struct msm_gpu_state *state;
175 
176 	state = msm_gpu_crashstate_get(gpu);
177 	if (!state)
178 		return 0;
179 
180 	iter.data = buffer;
181 	iter.offset = 0;
182 	iter.start = offset;
183 	iter.remain = count;
184 
185 	p = drm_coredump_printer(&iter);
186 
187 	drm_printf(&p, "---\n");
188 	drm_printf(&p, "kernel: " UTS_RELEASE "\n");
189 	drm_printf(&p, "module: " KBUILD_MODNAME "\n");
190 	drm_printf(&p, "time: %lld.%09ld\n",
191 		state->time.tv_sec, state->time.tv_nsec);
192 	if (state->comm)
193 		drm_printf(&p, "comm: %s\n", state->comm);
194 	if (state->cmd)
195 		drm_printf(&p, "cmdline: %s\n", state->cmd);
196 
197 	gpu->funcs->show(gpu, state, &p);
198 
199 	msm_gpu_crashstate_put(gpu);
200 
201 	return count - iter.remain;
202 }
203 
msm_gpu_devcoredump_free(void * data)204 static void msm_gpu_devcoredump_free(void *data)
205 {
206 	struct msm_gpu *gpu = data;
207 
208 	msm_gpu_crashstate_put(gpu);
209 }
210 
msm_gpu_crashstate_get_bo(struct msm_gpu_state * state,struct msm_gem_object * obj,u64 iova,u32 flags)211 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
212 		struct msm_gem_object *obj, u64 iova, u32 flags)
213 {
214 	struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
215 
216 	/* Don't record write only objects */
217 	state_bo->size = obj->base.size;
218 	state_bo->iova = iova;
219 
220 	/* Only store data for non imported buffer objects marked for read */
221 	if ((flags & MSM_SUBMIT_BO_READ) && !obj->base.import_attach) {
222 		void *ptr;
223 
224 		state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL);
225 		if (!state_bo->data)
226 			goto out;
227 
228 		msm_gem_lock(&obj->base);
229 		ptr = msm_gem_get_vaddr_active(&obj->base);
230 		msm_gem_unlock(&obj->base);
231 		if (IS_ERR(ptr)) {
232 			kvfree(state_bo->data);
233 			state_bo->data = NULL;
234 			goto out;
235 		}
236 
237 		memcpy(state_bo->data, ptr, obj->base.size);
238 		msm_gem_put_vaddr(&obj->base);
239 	}
240 out:
241 	state->nr_bos++;
242 }
243 
msm_gpu_crashstate_capture(struct msm_gpu * gpu,struct msm_gem_submit * submit,char * comm,char * cmd)244 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
245 		struct msm_gem_submit *submit, char *comm, char *cmd)
246 {
247 	struct msm_gpu_state *state;
248 
249 	/* Check if the target supports capturing crash state */
250 	if (!gpu->funcs->gpu_state_get)
251 		return;
252 
253 	/* Only save one crash state at a time */
254 	if (gpu->crashstate)
255 		return;
256 
257 	state = gpu->funcs->gpu_state_get(gpu);
258 	if (IS_ERR_OR_NULL(state))
259 		return;
260 
261 	/* Fill in the additional crash state information */
262 	state->comm = kstrdup(comm, GFP_KERNEL);
263 	state->cmd = kstrdup(cmd, GFP_KERNEL);
264 	state->fault_info = gpu->fault_info;
265 
266 	if (submit) {
267 		int i, nr = 0;
268 
269 		/* count # of buffers to dump: */
270 		for (i = 0; i < submit->nr_bos; i++)
271 			if (should_dump(submit, i))
272 				nr++;
273 		/* always dump cmd bo's, but don't double count them: */
274 		for (i = 0; i < submit->nr_cmds; i++)
275 			if (!should_dump(submit, submit->cmd[i].idx))
276 				nr++;
277 
278 		state->bos = kcalloc(nr,
279 			sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
280 
281 		for (i = 0; state->bos && i < submit->nr_bos; i++) {
282 			if (should_dump(submit, i)) {
283 				msm_gpu_crashstate_get_bo(state, submit->bos[i].obj,
284 					submit->bos[i].iova, submit->bos[i].flags);
285 			}
286 		}
287 
288 		for (i = 0; state->bos && i < submit->nr_cmds; i++) {
289 			int idx = submit->cmd[i].idx;
290 
291 			if (!should_dump(submit, submit->cmd[i].idx)) {
292 				msm_gpu_crashstate_get_bo(state, submit->bos[idx].obj,
293 					submit->bos[idx].iova, submit->bos[idx].flags);
294 			}
295 		}
296 	}
297 
298 	/* Set the active crash state to be dumped on failure */
299 	gpu->crashstate = state;
300 
301 	/* FIXME: Release the crashstate if this errors out? */
302 	dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
303 		msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
304 }
305 #else
msm_gpu_crashstate_capture(struct msm_gpu * gpu,struct msm_gem_submit * submit,char * comm,char * cmd)306 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
307 		struct msm_gem_submit *submit, char *comm, char *cmd)
308 {
309 }
310 #endif
311 
312 /*
313  * Hangcheck detection for locked gpu:
314  */
315 
316 static struct msm_gem_submit *
find_submit(struct msm_ringbuffer * ring,uint32_t fence)317 find_submit(struct msm_ringbuffer *ring, uint32_t fence)
318 {
319 	struct msm_gem_submit *submit;
320 	unsigned long flags;
321 
322 	spin_lock_irqsave(&ring->submit_lock, flags);
323 	list_for_each_entry(submit, &ring->submits, node) {
324 		if (submit->seqno == fence) {
325 			spin_unlock_irqrestore(&ring->submit_lock, flags);
326 			return submit;
327 		}
328 	}
329 	spin_unlock_irqrestore(&ring->submit_lock, flags);
330 
331 	return NULL;
332 }
333 
334 static void retire_submits(struct msm_gpu *gpu);
335 
get_comm_cmdline(struct msm_gem_submit * submit,char ** comm,char ** cmd)336 static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char **cmd)
337 {
338 	struct msm_file_private *ctx = submit->queue->ctx;
339 	struct task_struct *task;
340 
341 	/* Note that kstrdup will return NULL if argument is NULL: */
342 	*comm = kstrdup(ctx->comm, GFP_KERNEL);
343 	*cmd  = kstrdup(ctx->cmdline, GFP_KERNEL);
344 
345 	task = get_pid_task(submit->pid, PIDTYPE_PID);
346 	if (!task)
347 		return;
348 
349 	if (!*comm)
350 		*comm = kstrdup(task->comm, GFP_KERNEL);
351 
352 	if (!*cmd)
353 		*cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
354 
355 	put_task_struct(task);
356 }
357 
recover_worker(struct kthread_work * work)358 static void recover_worker(struct kthread_work *work)
359 {
360 	struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
361 	struct drm_device *dev = gpu->dev;
362 	struct msm_drm_private *priv = dev->dev_private;
363 	struct msm_gem_submit *submit;
364 	struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
365 	char *comm = NULL, *cmd = NULL;
366 	int i;
367 
368 	mutex_lock(&gpu->lock);
369 
370 	DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
371 
372 	submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
373 	if (submit) {
374 		/* Increment the fault counts */
375 		submit->queue->faults++;
376 		if (submit->aspace)
377 			submit->aspace->faults++;
378 
379 		get_comm_cmdline(submit, &comm, &cmd);
380 
381 		if (comm && cmd) {
382 			DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
383 				gpu->name, comm, cmd);
384 
385 			msm_rd_dump_submit(priv->hangrd, submit,
386 				"offending task: %s (%s)", comm, cmd);
387 		} else {
388 			msm_rd_dump_submit(priv->hangrd, submit, NULL);
389 		}
390 	} else {
391 		/*
392 		 * We couldn't attribute this fault to any particular context,
393 		 * so increment the global fault count instead.
394 		 */
395 		gpu->global_faults++;
396 	}
397 
398 	/* Record the crash state */
399 	pm_runtime_get_sync(&gpu->pdev->dev);
400 	msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
401 	pm_runtime_put_sync(&gpu->pdev->dev);
402 
403 	kfree(cmd);
404 	kfree(comm);
405 
406 	/*
407 	 * Update all the rings with the latest and greatest fence.. this
408 	 * needs to happen after msm_rd_dump_submit() to ensure that the
409 	 * bo's referenced by the offending submit are still around.
410 	 */
411 	for (i = 0; i < gpu->nr_rings; i++) {
412 		struct msm_ringbuffer *ring = gpu->rb[i];
413 
414 		uint32_t fence = ring->memptrs->fence;
415 
416 		/*
417 		 * For the current (faulting?) ring/submit advance the fence by
418 		 * one more to clear the faulting submit
419 		 */
420 		if (ring == cur_ring)
421 			ring->memptrs->fence = ++fence;
422 
423 		msm_update_fence(ring->fctx, fence);
424 	}
425 
426 	if (msm_gpu_active(gpu)) {
427 		/* retire completed submits, plus the one that hung: */
428 		retire_submits(gpu);
429 
430 		pm_runtime_get_sync(&gpu->pdev->dev);
431 		gpu->funcs->recover(gpu);
432 		pm_runtime_put_sync(&gpu->pdev->dev);
433 
434 		/*
435 		 * Replay all remaining submits starting with highest priority
436 		 * ring
437 		 */
438 		for (i = 0; i < gpu->nr_rings; i++) {
439 			struct msm_ringbuffer *ring = gpu->rb[i];
440 			unsigned long flags;
441 
442 			spin_lock_irqsave(&ring->submit_lock, flags);
443 			list_for_each_entry(submit, &ring->submits, node)
444 				gpu->funcs->submit(gpu, submit);
445 			spin_unlock_irqrestore(&ring->submit_lock, flags);
446 		}
447 	}
448 
449 	mutex_unlock(&gpu->lock);
450 
451 	msm_gpu_retire(gpu);
452 }
453 
fault_worker(struct kthread_work * work)454 static void fault_worker(struct kthread_work *work)
455 {
456 	struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work);
457 	struct msm_gem_submit *submit;
458 	struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
459 	char *comm = NULL, *cmd = NULL;
460 
461 	mutex_lock(&gpu->lock);
462 
463 	submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
464 	if (submit && submit->fault_dumped)
465 		goto resume_smmu;
466 
467 	if (submit) {
468 		get_comm_cmdline(submit, &comm, &cmd);
469 
470 		/*
471 		 * When we get GPU iova faults, we can get 1000s of them,
472 		 * but we really only want to log the first one.
473 		 */
474 		submit->fault_dumped = true;
475 	}
476 
477 	/* Record the crash state */
478 	pm_runtime_get_sync(&gpu->pdev->dev);
479 	msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
480 	pm_runtime_put_sync(&gpu->pdev->dev);
481 
482 	kfree(cmd);
483 	kfree(comm);
484 
485 resume_smmu:
486 	memset(&gpu->fault_info, 0, sizeof(gpu->fault_info));
487 	gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
488 
489 	mutex_unlock(&gpu->lock);
490 }
491 
hangcheck_timer_reset(struct msm_gpu * gpu)492 static void hangcheck_timer_reset(struct msm_gpu *gpu)
493 {
494 	struct msm_drm_private *priv = gpu->dev->dev_private;
495 	mod_timer(&gpu->hangcheck_timer,
496 			round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period)));
497 }
498 
hangcheck_handler(struct timer_list * t)499 static void hangcheck_handler(struct timer_list *t)
500 {
501 	struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
502 	struct drm_device *dev = gpu->dev;
503 	struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
504 	uint32_t fence = ring->memptrs->fence;
505 
506 	if (fence != ring->hangcheck_fence) {
507 		/* some progress has been made.. ya! */
508 		ring->hangcheck_fence = fence;
509 	} else if (fence_before(fence, ring->fctx->last_fence)) {
510 		/* no progress and not done.. hung! */
511 		ring->hangcheck_fence = fence;
512 		DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
513 				gpu->name, ring->id);
514 		DRM_DEV_ERROR(dev->dev, "%s:     completed fence: %u\n",
515 				gpu->name, fence);
516 		DRM_DEV_ERROR(dev->dev, "%s:     submitted fence: %u\n",
517 				gpu->name, ring->fctx->last_fence);
518 
519 		kthread_queue_work(gpu->worker, &gpu->recover_work);
520 	}
521 
522 	/* if still more pending work, reset the hangcheck timer: */
523 	if (fence_after(ring->fctx->last_fence, ring->hangcheck_fence))
524 		hangcheck_timer_reset(gpu);
525 
526 	/* workaround for missing irq: */
527 	msm_gpu_retire(gpu);
528 }
529 
530 /*
531  * Performance Counters:
532  */
533 
534 /* called under perf_lock */
update_hw_cntrs(struct msm_gpu * gpu,uint32_t ncntrs,uint32_t * cntrs)535 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
536 {
537 	uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
538 	int i, n = min(ncntrs, gpu->num_perfcntrs);
539 
540 	/* read current values: */
541 	for (i = 0; i < gpu->num_perfcntrs; i++)
542 		current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
543 
544 	/* update cntrs: */
545 	for (i = 0; i < n; i++)
546 		cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
547 
548 	/* save current values: */
549 	for (i = 0; i < gpu->num_perfcntrs; i++)
550 		gpu->last_cntrs[i] = current_cntrs[i];
551 
552 	return n;
553 }
554 
update_sw_cntrs(struct msm_gpu * gpu)555 static void update_sw_cntrs(struct msm_gpu *gpu)
556 {
557 	ktime_t time;
558 	uint32_t elapsed;
559 	unsigned long flags;
560 
561 	spin_lock_irqsave(&gpu->perf_lock, flags);
562 	if (!gpu->perfcntr_active)
563 		goto out;
564 
565 	time = ktime_get();
566 	elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
567 
568 	gpu->totaltime += elapsed;
569 	if (gpu->last_sample.active)
570 		gpu->activetime += elapsed;
571 
572 	gpu->last_sample.active = msm_gpu_active(gpu);
573 	gpu->last_sample.time = time;
574 
575 out:
576 	spin_unlock_irqrestore(&gpu->perf_lock, flags);
577 }
578 
msm_gpu_perfcntr_start(struct msm_gpu * gpu)579 void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
580 {
581 	unsigned long flags;
582 
583 	pm_runtime_get_sync(&gpu->pdev->dev);
584 
585 	spin_lock_irqsave(&gpu->perf_lock, flags);
586 	/* we could dynamically enable/disable perfcntr registers too.. */
587 	gpu->last_sample.active = msm_gpu_active(gpu);
588 	gpu->last_sample.time = ktime_get();
589 	gpu->activetime = gpu->totaltime = 0;
590 	gpu->perfcntr_active = true;
591 	update_hw_cntrs(gpu, 0, NULL);
592 	spin_unlock_irqrestore(&gpu->perf_lock, flags);
593 }
594 
msm_gpu_perfcntr_stop(struct msm_gpu * gpu)595 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
596 {
597 	gpu->perfcntr_active = false;
598 	pm_runtime_put_sync(&gpu->pdev->dev);
599 }
600 
601 /* returns -errno or # of cntrs sampled */
msm_gpu_perfcntr_sample(struct msm_gpu * gpu,uint32_t * activetime,uint32_t * totaltime,uint32_t ncntrs,uint32_t * cntrs)602 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
603 		uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
604 {
605 	unsigned long flags;
606 	int ret;
607 
608 	spin_lock_irqsave(&gpu->perf_lock, flags);
609 
610 	if (!gpu->perfcntr_active) {
611 		ret = -EINVAL;
612 		goto out;
613 	}
614 
615 	*activetime = gpu->activetime;
616 	*totaltime = gpu->totaltime;
617 
618 	gpu->activetime = gpu->totaltime = 0;
619 
620 	ret = update_hw_cntrs(gpu, ncntrs, cntrs);
621 
622 out:
623 	spin_unlock_irqrestore(&gpu->perf_lock, flags);
624 
625 	return ret;
626 }
627 
628 /*
629  * Cmdstream submission/retirement:
630  */
631 
retire_submit(struct msm_gpu * gpu,struct msm_ringbuffer * ring,struct msm_gem_submit * submit)632 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
633 		struct msm_gem_submit *submit)
634 {
635 	int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
636 	volatile struct msm_gpu_submit_stats *stats;
637 	u64 elapsed, clock = 0;
638 	unsigned long flags;
639 
640 	stats = &ring->memptrs->stats[index];
641 	/* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */
642 	elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
643 	do_div(elapsed, 192);
644 
645 	/* Calculate the clock frequency from the number of CP cycles */
646 	if (elapsed) {
647 		clock = (stats->cpcycles_end - stats->cpcycles_start) * 1000;
648 		do_div(clock, elapsed);
649 	}
650 
651 	trace_msm_gpu_submit_retired(submit, elapsed, clock,
652 		stats->alwayson_start, stats->alwayson_end);
653 
654 	msm_submit_retire(submit);
655 
656 	pm_runtime_mark_last_busy(&gpu->pdev->dev);
657 
658 	spin_lock_irqsave(&ring->submit_lock, flags);
659 	list_del(&submit->node);
660 	spin_unlock_irqrestore(&ring->submit_lock, flags);
661 
662 	/* Update devfreq on transition from active->idle: */
663 	mutex_lock(&gpu->active_lock);
664 	gpu->active_submits--;
665 	WARN_ON(gpu->active_submits < 0);
666 	if (!gpu->active_submits)
667 		msm_devfreq_idle(gpu);
668 	mutex_unlock(&gpu->active_lock);
669 
670 	pm_runtime_put_autosuspend(&gpu->pdev->dev);
671 
672 	msm_gem_submit_put(submit);
673 }
674 
retire_submits(struct msm_gpu * gpu)675 static void retire_submits(struct msm_gpu *gpu)
676 {
677 	int i;
678 
679 	/* Retire the commits starting with highest priority */
680 	for (i = 0; i < gpu->nr_rings; i++) {
681 		struct msm_ringbuffer *ring = gpu->rb[i];
682 
683 		while (true) {
684 			struct msm_gem_submit *submit = NULL;
685 			unsigned long flags;
686 
687 			spin_lock_irqsave(&ring->submit_lock, flags);
688 			submit = list_first_entry_or_null(&ring->submits,
689 					struct msm_gem_submit, node);
690 			spin_unlock_irqrestore(&ring->submit_lock, flags);
691 
692 			/*
693 			 * If no submit, we are done.  If submit->fence hasn't
694 			 * been signalled, then later submits are not signalled
695 			 * either, so we are also done.
696 			 */
697 			if (submit && dma_fence_is_signaled(submit->hw_fence)) {
698 				retire_submit(gpu, ring, submit);
699 			} else {
700 				break;
701 			}
702 		}
703 	}
704 
705 	wake_up_all(&gpu->retire_event);
706 }
707 
retire_worker(struct kthread_work * work)708 static void retire_worker(struct kthread_work *work)
709 {
710 	struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
711 
712 	retire_submits(gpu);
713 }
714 
715 /* call from irq handler to schedule work to retire bo's */
msm_gpu_retire(struct msm_gpu * gpu)716 void msm_gpu_retire(struct msm_gpu *gpu)
717 {
718 	int i;
719 
720 	for (i = 0; i < gpu->nr_rings; i++)
721 		msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence);
722 
723 	kthread_queue_work(gpu->worker, &gpu->retire_work);
724 	update_sw_cntrs(gpu);
725 }
726 
727 /* add bo's to gpu's ring, and kick gpu: */
msm_gpu_submit(struct msm_gpu * gpu,struct msm_gem_submit * submit)728 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
729 {
730 	struct drm_device *dev = gpu->dev;
731 	struct msm_drm_private *priv = dev->dev_private;
732 	struct msm_ringbuffer *ring = submit->ring;
733 	unsigned long flags;
734 
735 	WARN_ON(!mutex_is_locked(&gpu->lock));
736 
737 	pm_runtime_get_sync(&gpu->pdev->dev);
738 
739 	msm_gpu_hw_init(gpu);
740 
741 	submit->seqno = submit->hw_fence->seqno;
742 
743 	msm_rd_dump_submit(priv->rd, submit, NULL);
744 
745 	update_sw_cntrs(gpu);
746 
747 	/*
748 	 * ring->submits holds a ref to the submit, to deal with the case
749 	 * that a submit completes before msm_ioctl_gem_submit() returns.
750 	 */
751 	msm_gem_submit_get(submit);
752 
753 	spin_lock_irqsave(&ring->submit_lock, flags);
754 	list_add_tail(&submit->node, &ring->submits);
755 	spin_unlock_irqrestore(&ring->submit_lock, flags);
756 
757 	/* Update devfreq on transition from idle->active: */
758 	mutex_lock(&gpu->active_lock);
759 	if (!gpu->active_submits)
760 		msm_devfreq_active(gpu);
761 	gpu->active_submits++;
762 	mutex_unlock(&gpu->active_lock);
763 
764 	gpu->funcs->submit(gpu, submit);
765 	gpu->cur_ctx_seqno = submit->queue->ctx->seqno;
766 
767 	hangcheck_timer_reset(gpu);
768 }
769 
770 /*
771  * Init/Cleanup:
772  */
773 
irq_handler(int irq,void * data)774 static irqreturn_t irq_handler(int irq, void *data)
775 {
776 	struct msm_gpu *gpu = data;
777 	return gpu->funcs->irq(gpu);
778 }
779 
get_clocks(struct platform_device * pdev,struct msm_gpu * gpu)780 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
781 {
782 	int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
783 
784 	if (ret < 1) {
785 		gpu->nr_clocks = 0;
786 		return ret;
787 	}
788 
789 	gpu->nr_clocks = ret;
790 
791 	gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
792 		gpu->nr_clocks, "core");
793 
794 	gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
795 		gpu->nr_clocks, "rbbmtimer");
796 
797 	return 0;
798 }
799 
800 /* Return a new address space for a msm_drm_private instance */
801 struct msm_gem_address_space *
msm_gpu_create_private_address_space(struct msm_gpu * gpu,struct task_struct * task)802 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task)
803 {
804 	struct msm_gem_address_space *aspace = NULL;
805 	if (!gpu)
806 		return NULL;
807 
808 	/*
809 	 * If the target doesn't support private address spaces then return
810 	 * the global one
811 	 */
812 	if (gpu->funcs->create_private_address_space) {
813 		aspace = gpu->funcs->create_private_address_space(gpu);
814 		if (!IS_ERR(aspace))
815 			aspace->pid = get_pid(task_pid(task));
816 	}
817 
818 	if (IS_ERR_OR_NULL(aspace))
819 		aspace = msm_gem_address_space_get(gpu->aspace);
820 
821 	return aspace;
822 }
823 
msm_gpu_init(struct drm_device * drm,struct platform_device * pdev,struct msm_gpu * gpu,const struct msm_gpu_funcs * funcs,const char * name,struct msm_gpu_config * config)824 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
825 		struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
826 		const char *name, struct msm_gpu_config *config)
827 {
828 	int i, ret, nr_rings = config->nr_rings;
829 	void *memptrs;
830 	uint64_t memptrs_iova;
831 
832 	if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
833 		gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
834 
835 	gpu->dev = drm;
836 	gpu->funcs = funcs;
837 	gpu->name = name;
838 
839 	gpu->worker = kthread_create_worker(0, "gpu-worker");
840 	if (IS_ERR(gpu->worker)) {
841 		ret = PTR_ERR(gpu->worker);
842 		gpu->worker = NULL;
843 		goto fail;
844 	}
845 
846 	sched_set_fifo_low(gpu->worker->task);
847 
848 	INIT_LIST_HEAD(&gpu->active_list);
849 	mutex_init(&gpu->active_lock);
850 	mutex_init(&gpu->lock);
851 	init_waitqueue_head(&gpu->retire_event);
852 	kthread_init_work(&gpu->retire_work, retire_worker);
853 	kthread_init_work(&gpu->recover_work, recover_worker);
854 	kthread_init_work(&gpu->fault_work, fault_worker);
855 
856 	timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
857 
858 	spin_lock_init(&gpu->perf_lock);
859 
860 
861 	/* Map registers: */
862 	gpu->mmio = msm_ioremap(pdev, config->ioname);
863 	if (IS_ERR(gpu->mmio)) {
864 		ret = PTR_ERR(gpu->mmio);
865 		goto fail;
866 	}
867 
868 	/* Get Interrupt: */
869 	gpu->irq = platform_get_irq(pdev, 0);
870 	if (gpu->irq < 0) {
871 		ret = gpu->irq;
872 		DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret);
873 		goto fail;
874 	}
875 
876 	ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
877 			IRQF_TRIGGER_HIGH, "gpu-irq", gpu);
878 	if (ret) {
879 		DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
880 		goto fail;
881 	}
882 
883 	ret = get_clocks(pdev, gpu);
884 	if (ret)
885 		goto fail;
886 
887 	gpu->ebi1_clk = msm_clk_get(pdev, "bus");
888 	DBG("ebi1_clk: %p", gpu->ebi1_clk);
889 	if (IS_ERR(gpu->ebi1_clk))
890 		gpu->ebi1_clk = NULL;
891 
892 	/* Acquire regulators: */
893 	gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
894 	DBG("gpu_reg: %p", gpu->gpu_reg);
895 	if (IS_ERR(gpu->gpu_reg))
896 		gpu->gpu_reg = NULL;
897 
898 	gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
899 	DBG("gpu_cx: %p", gpu->gpu_cx);
900 	if (IS_ERR(gpu->gpu_cx))
901 		gpu->gpu_cx = NULL;
902 
903 	gpu->pdev = pdev;
904 	platform_set_drvdata(pdev, &gpu->adreno_smmu);
905 
906 	msm_devfreq_init(gpu);
907 
908 
909 	gpu->aspace = gpu->funcs->create_address_space(gpu, pdev);
910 
911 	if (gpu->aspace == NULL)
912 		DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
913 	else if (IS_ERR(gpu->aspace)) {
914 		ret = PTR_ERR(gpu->aspace);
915 		goto fail;
916 	}
917 
918 	memptrs = msm_gem_kernel_new(drm,
919 		sizeof(struct msm_rbmemptrs) * nr_rings,
920 		check_apriv(gpu, MSM_BO_UNCACHED), gpu->aspace, &gpu->memptrs_bo,
921 		&memptrs_iova);
922 
923 	if (IS_ERR(memptrs)) {
924 		ret = PTR_ERR(memptrs);
925 		DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
926 		goto fail;
927 	}
928 
929 	msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
930 
931 	if (nr_rings > ARRAY_SIZE(gpu->rb)) {
932 		DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
933 			ARRAY_SIZE(gpu->rb));
934 		nr_rings = ARRAY_SIZE(gpu->rb);
935 	}
936 
937 	/* Create ringbuffer(s): */
938 	for (i = 0; i < nr_rings; i++) {
939 		gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
940 
941 		if (IS_ERR(gpu->rb[i])) {
942 			ret = PTR_ERR(gpu->rb[i]);
943 			DRM_DEV_ERROR(drm->dev,
944 				"could not create ringbuffer %d: %d\n", i, ret);
945 			goto fail;
946 		}
947 
948 		memptrs += sizeof(struct msm_rbmemptrs);
949 		memptrs_iova += sizeof(struct msm_rbmemptrs);
950 	}
951 
952 	gpu->nr_rings = nr_rings;
953 
954 	refcount_set(&gpu->sysprof_active, 1);
955 
956 	return 0;
957 
958 fail:
959 	for (i = 0; i < ARRAY_SIZE(gpu->rb); i++)  {
960 		msm_ringbuffer_destroy(gpu->rb[i]);
961 		gpu->rb[i] = NULL;
962 	}
963 
964 	msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
965 
966 	platform_set_drvdata(pdev, NULL);
967 	return ret;
968 }
969 
msm_gpu_cleanup(struct msm_gpu * gpu)970 void msm_gpu_cleanup(struct msm_gpu *gpu)
971 {
972 	int i;
973 
974 	DBG("%s", gpu->name);
975 
976 	WARN_ON(!list_empty(&gpu->active_list));
977 
978 	for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
979 		msm_ringbuffer_destroy(gpu->rb[i]);
980 		gpu->rb[i] = NULL;
981 	}
982 
983 	msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
984 
985 	if (!IS_ERR_OR_NULL(gpu->aspace)) {
986 		gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu);
987 		msm_gem_address_space_put(gpu->aspace);
988 	}
989 
990 	if (gpu->worker) {
991 		kthread_destroy_worker(gpu->worker);
992 	}
993 
994 	msm_devfreq_cleanup(gpu);
995 }
996