1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *	Intel IO-APIC support for multi-Pentium hosts.
4  *
5  *	Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6  *
7  *	Many thanks to Stig Venaas for trying out countless experimental
8  *	patches and reporting/debugging problems patiently!
9  *
10  *	(c) 1999, Multiple IO-APIC support, developed by
11  *	Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13  *	further tested and cleaned up by Zach Brown <zab@redhat.com>
14  *	and Ingo Molnar <mingo@redhat.com>
15  *
16  *	Fixes
17  *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
18  *					thanks to Eric Gilmore
19  *					and Rolf G. Tews
20  *					for testing these extensively
21  *	Paul Diefenbaugh	:	Added full ACPI support
22  *
23  * Historical information which is worth to be preserved:
24  *
25  * - SiS APIC rmw bug:
26  *
27  *	We used to have a workaround for a bug in SiS chips which
28  *	required to rewrite the index register for a read-modify-write
29  *	operation as the chip lost the index information which was
30  *	setup for the read already. We cache the data now, so that
31  *	workaround has been removed.
32  */
33 
34 #include <linux/mm.h>
35 #include <linux/interrupt.h>
36 #include <linux/irq.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/pci.h>
41 #include <linux/mc146818rtc.h>
42 #include <linux/compiler.h>
43 #include <linux/acpi.h>
44 #include <linux/export.h>
45 #include <linux/syscore_ops.h>
46 #include <linux/freezer.h>
47 #include <linux/kthread.h>
48 #include <linux/jiffies.h>	/* time_after() */
49 #include <linux/slab.h>
50 #include <linux/memblock.h>
51 #include <linux/msi.h>
52 
53 #include <asm/irqdomain.h>
54 #include <asm/io.h>
55 #include <asm/smp.h>
56 #include <asm/cpu.h>
57 #include <asm/desc.h>
58 #include <asm/proto.h>
59 #include <asm/acpi.h>
60 #include <asm/dma.h>
61 #include <asm/timer.h>
62 #include <asm/time.h>
63 #include <asm/i8259.h>
64 #include <asm/setup.h>
65 #include <asm/irq_remapping.h>
66 #include <asm/hw_irq.h>
67 #include <asm/apic.h>
68 #include <asm/pgtable.h>
69 
70 #define	for_each_ioapic(idx)		\
71 	for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
72 #define	for_each_ioapic_reverse(idx)	\
73 	for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
74 #define	for_each_pin(idx, pin)		\
75 	for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
76 #define	for_each_ioapic_pin(idx, pin)	\
77 	for_each_ioapic((idx))		\
78 		for_each_pin((idx), (pin))
79 #define for_each_irq_pin(entry, head) \
80 	list_for_each_entry(entry, &head, list)
81 
82 static DEFINE_RAW_SPINLOCK(ioapic_lock);
83 static DEFINE_MUTEX(ioapic_mutex);
84 static unsigned int ioapic_dynirq_base;
85 static int ioapic_initialized;
86 
87 struct irq_pin_list {
88 	struct list_head list;
89 	int apic, pin;
90 };
91 
92 struct mp_chip_data {
93 	struct list_head		irq_2_pin;
94 	struct IO_APIC_route_entry	entry;
95 	bool				is_level;
96 	bool				active_low;
97 	bool				isa_irq;
98 	u32 count;
99 };
100 
101 struct mp_ioapic_gsi {
102 	u32 gsi_base;
103 	u32 gsi_end;
104 };
105 
106 static struct ioapic {
107 	/*
108 	 * # of IRQ routing registers
109 	 */
110 	int nr_registers;
111 	/*
112 	 * Saved state during suspend/resume, or while enabling intr-remap.
113 	 */
114 	struct IO_APIC_route_entry *saved_registers;
115 	/* I/O APIC config */
116 	struct mpc_ioapic mp_config;
117 	/* IO APIC gsi routing info */
118 	struct mp_ioapic_gsi  gsi_config;
119 	struct ioapic_domain_cfg irqdomain_cfg;
120 	struct irq_domain *irqdomain;
121 	struct resource *iomem_res;
122 } ioapics[MAX_IO_APICS];
123 
124 #define mpc_ioapic_ver(ioapic_idx)	ioapics[ioapic_idx].mp_config.apicver
125 
mpc_ioapic_id(int ioapic_idx)126 int mpc_ioapic_id(int ioapic_idx)
127 {
128 	return ioapics[ioapic_idx].mp_config.apicid;
129 }
130 
mpc_ioapic_addr(int ioapic_idx)131 unsigned int mpc_ioapic_addr(int ioapic_idx)
132 {
133 	return ioapics[ioapic_idx].mp_config.apicaddr;
134 }
135 
mp_ioapic_gsi_routing(int ioapic_idx)136 static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
137 {
138 	return &ioapics[ioapic_idx].gsi_config;
139 }
140 
mp_ioapic_pin_count(int ioapic)141 static inline int mp_ioapic_pin_count(int ioapic)
142 {
143 	struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
144 
145 	return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
146 }
147 
mp_pin_to_gsi(int ioapic,int pin)148 static inline u32 mp_pin_to_gsi(int ioapic, int pin)
149 {
150 	return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
151 }
152 
mp_is_legacy_irq(int irq)153 static inline bool mp_is_legacy_irq(int irq)
154 {
155 	return irq >= 0 && irq < nr_legacy_irqs();
156 }
157 
mp_ioapic_irqdomain(int ioapic)158 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
159 {
160 	return ioapics[ioapic].irqdomain;
161 }
162 
163 int nr_ioapics;
164 
165 /* The one past the highest gsi number used */
166 u32 gsi_top;
167 
168 /* MP IRQ source entries */
169 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
170 
171 /* # of MP IRQ source entries */
172 int mp_irq_entries;
173 
174 #ifdef CONFIG_EISA
175 int mp_bus_id_to_type[MAX_MP_BUSSES];
176 #endif
177 
178 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
179 
180 int skip_ioapic_setup;
181 
182 /**
183  * disable_ioapic_support() - disables ioapic support at runtime
184  */
disable_ioapic_support(void)185 void disable_ioapic_support(void)
186 {
187 #ifdef CONFIG_PCI
188 	noioapicquirk = 1;
189 	noioapicreroute = -1;
190 #endif
191 	skip_ioapic_setup = 1;
192 }
193 
parse_noapic(char * str)194 static int __init parse_noapic(char *str)
195 {
196 	/* disable IO-APIC */
197 	disable_ioapic_support();
198 	return 0;
199 }
200 early_param("noapic", parse_noapic);
201 
202 /* Will be called in mpparse/ACPI codes for saving IRQ info */
mp_save_irq(struct mpc_intsrc * m)203 void mp_save_irq(struct mpc_intsrc *m)
204 {
205 	int i;
206 
207 	apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
208 		" IRQ %02x, APIC ID %x, APIC INT %02x\n",
209 		m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
210 		m->srcbusirq, m->dstapic, m->dstirq);
211 
212 	for (i = 0; i < mp_irq_entries; i++) {
213 		if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
214 			return;
215 	}
216 
217 	memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
218 	if (++mp_irq_entries == MAX_IRQ_SOURCES)
219 		panic("Max # of irq sources exceeded!!\n");
220 }
221 
alloc_ioapic_saved_registers(int idx)222 static void alloc_ioapic_saved_registers(int idx)
223 {
224 	size_t size;
225 
226 	if (ioapics[idx].saved_registers)
227 		return;
228 
229 	size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
230 	ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
231 	if (!ioapics[idx].saved_registers)
232 		pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
233 }
234 
free_ioapic_saved_registers(int idx)235 static void free_ioapic_saved_registers(int idx)
236 {
237 	kfree(ioapics[idx].saved_registers);
238 	ioapics[idx].saved_registers = NULL;
239 }
240 
arch_early_ioapic_init(void)241 int __init arch_early_ioapic_init(void)
242 {
243 	int i;
244 
245 	if (!nr_legacy_irqs())
246 		io_apic_irqs = ~0UL;
247 
248 	for_each_ioapic(i)
249 		alloc_ioapic_saved_registers(i);
250 
251 	return 0;
252 }
253 
254 struct io_apic {
255 	unsigned int index;
256 	unsigned int unused[3];
257 	unsigned int data;
258 	unsigned int unused2[11];
259 	unsigned int eoi;
260 };
261 
io_apic_base(int idx)262 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
263 {
264 	return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
265 		+ (mpc_ioapic_addr(idx) & ~PAGE_MASK);
266 }
267 
io_apic_eoi(unsigned int apic,unsigned int vector)268 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
269 {
270 	struct io_apic __iomem *io_apic = io_apic_base(apic);
271 	writel(vector, &io_apic->eoi);
272 }
273 
native_io_apic_read(unsigned int apic,unsigned int reg)274 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
275 {
276 	struct io_apic __iomem *io_apic = io_apic_base(apic);
277 	writel(reg, &io_apic->index);
278 	return readl(&io_apic->data);
279 }
280 
io_apic_write(unsigned int apic,unsigned int reg,unsigned int value)281 static void io_apic_write(unsigned int apic, unsigned int reg,
282 			  unsigned int value)
283 {
284 	struct io_apic __iomem *io_apic = io_apic_base(apic);
285 
286 	writel(reg, &io_apic->index);
287 	writel(value, &io_apic->data);
288 }
289 
__ioapic_read_entry(int apic,int pin)290 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
291 {
292 	struct IO_APIC_route_entry entry;
293 
294 	entry.w1 = io_apic_read(apic, 0x10 + 2 * pin);
295 	entry.w2 = io_apic_read(apic, 0x11 + 2 * pin);
296 
297 	return entry;
298 }
299 
ioapic_read_entry(int apic,int pin)300 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
301 {
302 	struct IO_APIC_route_entry entry;
303 	unsigned long flags;
304 
305 	raw_spin_lock_irqsave(&ioapic_lock, flags);
306 	entry = __ioapic_read_entry(apic, pin);
307 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
308 
309 	return entry;
310 }
311 
312 /*
313  * When we write a new IO APIC routing entry, we need to write the high
314  * word first! If the mask bit in the low word is clear, we will enable
315  * the interrupt, and we need to make sure the entry is fully populated
316  * before that happens.
317  */
__ioapic_write_entry(int apic,int pin,struct IO_APIC_route_entry e)318 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
319 {
320 	io_apic_write(apic, 0x11 + 2*pin, e.w2);
321 	io_apic_write(apic, 0x10 + 2*pin, e.w1);
322 }
323 
ioapic_write_entry(int apic,int pin,struct IO_APIC_route_entry e)324 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
325 {
326 	unsigned long flags;
327 
328 	raw_spin_lock_irqsave(&ioapic_lock, flags);
329 	__ioapic_write_entry(apic, pin, e);
330 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
331 }
332 
333 /*
334  * When we mask an IO APIC routing entry, we need to write the low
335  * word first, in order to set the mask bit before we change the
336  * high bits!
337  */
ioapic_mask_entry(int apic,int pin)338 static void ioapic_mask_entry(int apic, int pin)
339 {
340 	struct IO_APIC_route_entry e = { .masked = true };
341 	unsigned long flags;
342 
343 	raw_spin_lock_irqsave(&ioapic_lock, flags);
344 	io_apic_write(apic, 0x10 + 2*pin, e.w1);
345 	io_apic_write(apic, 0x11 + 2*pin, e.w2);
346 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
347 }
348 
349 /*
350  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
351  * shared ISA-space IRQs, so we have to support them. We are super
352  * fast in the common case, and fast for shared ISA-space IRQs.
353  */
__add_pin_to_irq_node(struct mp_chip_data * data,int node,int apic,int pin)354 static int __add_pin_to_irq_node(struct mp_chip_data *data,
355 				 int node, int apic, int pin)
356 {
357 	struct irq_pin_list *entry;
358 
359 	/* don't allow duplicates */
360 	for_each_irq_pin(entry, data->irq_2_pin)
361 		if (entry->apic == apic && entry->pin == pin)
362 			return 0;
363 
364 	entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
365 	if (!entry) {
366 		pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
367 		       node, apic, pin);
368 		return -ENOMEM;
369 	}
370 	entry->apic = apic;
371 	entry->pin = pin;
372 	list_add_tail(&entry->list, &data->irq_2_pin);
373 
374 	return 0;
375 }
376 
__remove_pin_from_irq(struct mp_chip_data * data,int apic,int pin)377 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
378 {
379 	struct irq_pin_list *tmp, *entry;
380 
381 	list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
382 		if (entry->apic == apic && entry->pin == pin) {
383 			list_del(&entry->list);
384 			kfree(entry);
385 			return;
386 		}
387 }
388 
add_pin_to_irq_node(struct mp_chip_data * data,int node,int apic,int pin)389 static void add_pin_to_irq_node(struct mp_chip_data *data,
390 				int node, int apic, int pin)
391 {
392 	if (__add_pin_to_irq_node(data, node, apic, pin))
393 		panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
394 }
395 
396 /*
397  * Reroute an IRQ to a different pin.
398  */
replace_pin_at_irq_node(struct mp_chip_data * data,int node,int oldapic,int oldpin,int newapic,int newpin)399 static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
400 					   int oldapic, int oldpin,
401 					   int newapic, int newpin)
402 {
403 	struct irq_pin_list *entry;
404 
405 	for_each_irq_pin(entry, data->irq_2_pin) {
406 		if (entry->apic == oldapic && entry->pin == oldpin) {
407 			entry->apic = newapic;
408 			entry->pin = newpin;
409 			/* every one is different, right? */
410 			return;
411 		}
412 	}
413 
414 	/* old apic/pin didn't exist, so just add new ones */
415 	add_pin_to_irq_node(data, node, newapic, newpin);
416 }
417 
io_apic_modify_irq(struct mp_chip_data * data,bool masked,void (* final)(struct irq_pin_list * entry))418 static void io_apic_modify_irq(struct mp_chip_data *data, bool masked,
419 			       void (*final)(struct irq_pin_list *entry))
420 {
421 	struct irq_pin_list *entry;
422 
423 	data->entry.masked = masked;
424 
425 	for_each_irq_pin(entry, data->irq_2_pin) {
426 		io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1);
427 		if (final)
428 			final(entry);
429 	}
430 }
431 
io_apic_sync(struct irq_pin_list * entry)432 static void io_apic_sync(struct irq_pin_list *entry)
433 {
434 	/*
435 	 * Synchronize the IO-APIC and the CPU by doing
436 	 * a dummy read from the IO-APIC
437 	 */
438 	struct io_apic __iomem *io_apic;
439 
440 	io_apic = io_apic_base(entry->apic);
441 	readl(&io_apic->data);
442 }
443 
mask_ioapic_irq(struct irq_data * irq_data)444 static void mask_ioapic_irq(struct irq_data *irq_data)
445 {
446 	struct mp_chip_data *data = irq_data->chip_data;
447 	unsigned long flags;
448 
449 	raw_spin_lock_irqsave(&ioapic_lock, flags);
450 	io_apic_modify_irq(data, true, &io_apic_sync);
451 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
452 }
453 
__unmask_ioapic(struct mp_chip_data * data)454 static void __unmask_ioapic(struct mp_chip_data *data)
455 {
456 	io_apic_modify_irq(data, false, NULL);
457 }
458 
unmask_ioapic_irq(struct irq_data * irq_data)459 static void unmask_ioapic_irq(struct irq_data *irq_data)
460 {
461 	struct mp_chip_data *data = irq_data->chip_data;
462 	unsigned long flags;
463 
464 	raw_spin_lock_irqsave(&ioapic_lock, flags);
465 	__unmask_ioapic(data);
466 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
467 }
468 
469 /*
470  * IO-APIC versions below 0x20 don't support EOI register.
471  * For the record, here is the information about various versions:
472  *     0Xh     82489DX
473  *     1Xh     I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
474  *     2Xh     I/O(x)APIC which is PCI 2.2 Compliant
475  *     30h-FFh Reserved
476  *
477  * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
478  * version as 0x2. This is an error with documentation and these ICH chips
479  * use io-apic's of version 0x20.
480  *
481  * For IO-APIC's with EOI register, we use that to do an explicit EOI.
482  * Otherwise, we simulate the EOI message manually by changing the trigger
483  * mode to edge and then back to level, with RTE being masked during this.
484  */
__eoi_ioapic_pin(int apic,int pin,int vector)485 static void __eoi_ioapic_pin(int apic, int pin, int vector)
486 {
487 	if (mpc_ioapic_ver(apic) >= 0x20) {
488 		io_apic_eoi(apic, vector);
489 	} else {
490 		struct IO_APIC_route_entry entry, entry1;
491 
492 		entry = entry1 = __ioapic_read_entry(apic, pin);
493 
494 		/*
495 		 * Mask the entry and change the trigger mode to edge.
496 		 */
497 		entry1.masked = true;
498 		entry1.is_level = false;
499 
500 		__ioapic_write_entry(apic, pin, entry1);
501 
502 		/*
503 		 * Restore the previous level triggered entry.
504 		 */
505 		__ioapic_write_entry(apic, pin, entry);
506 	}
507 }
508 
eoi_ioapic_pin(int vector,struct mp_chip_data * data)509 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
510 {
511 	unsigned long flags;
512 	struct irq_pin_list *entry;
513 
514 	raw_spin_lock_irqsave(&ioapic_lock, flags);
515 	for_each_irq_pin(entry, data->irq_2_pin)
516 		__eoi_ioapic_pin(entry->apic, entry->pin, vector);
517 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
518 }
519 
clear_IO_APIC_pin(unsigned int apic,unsigned int pin)520 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
521 {
522 	struct IO_APIC_route_entry entry;
523 
524 	/* Check delivery_mode to be sure we're not clearing an SMI pin */
525 	entry = ioapic_read_entry(apic, pin);
526 	if (entry.delivery_mode == APIC_DELIVERY_MODE_SMI)
527 		return;
528 
529 	/*
530 	 * Make sure the entry is masked and re-read the contents to check
531 	 * if it is a level triggered pin and if the remote-IRR is set.
532 	 */
533 	if (!entry.masked) {
534 		entry.masked = true;
535 		ioapic_write_entry(apic, pin, entry);
536 		entry = ioapic_read_entry(apic, pin);
537 	}
538 
539 	if (entry.irr) {
540 		unsigned long flags;
541 
542 		/*
543 		 * Make sure the trigger mode is set to level. Explicit EOI
544 		 * doesn't clear the remote-IRR if the trigger mode is not
545 		 * set to level.
546 		 */
547 		if (!entry.is_level) {
548 			entry.is_level = true;
549 			ioapic_write_entry(apic, pin, entry);
550 		}
551 		raw_spin_lock_irqsave(&ioapic_lock, flags);
552 		__eoi_ioapic_pin(apic, pin, entry.vector);
553 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
554 	}
555 
556 	/*
557 	 * Clear the rest of the bits in the IO-APIC RTE except for the mask
558 	 * bit.
559 	 */
560 	ioapic_mask_entry(apic, pin);
561 	entry = ioapic_read_entry(apic, pin);
562 	if (entry.irr)
563 		pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
564 		       mpc_ioapic_id(apic), pin);
565 }
566 
clear_IO_APIC(void)567 void clear_IO_APIC (void)
568 {
569 	int apic, pin;
570 
571 	for_each_ioapic_pin(apic, pin)
572 		clear_IO_APIC_pin(apic, pin);
573 }
574 
575 #ifdef CONFIG_X86_32
576 /*
577  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
578  * specific CPU-side IRQs.
579  */
580 
581 #define MAX_PIRQS 8
582 static int pirq_entries[MAX_PIRQS] = {
583 	[0 ... MAX_PIRQS - 1] = -1
584 };
585 
ioapic_pirq_setup(char * str)586 static int __init ioapic_pirq_setup(char *str)
587 {
588 	int i, max;
589 	int ints[MAX_PIRQS+1];
590 
591 	get_options(str, ARRAY_SIZE(ints), ints);
592 
593 	apic_printk(APIC_VERBOSE, KERN_INFO
594 			"PIRQ redirection, working around broken MP-BIOS.\n");
595 	max = MAX_PIRQS;
596 	if (ints[0] < MAX_PIRQS)
597 		max = ints[0];
598 
599 	for (i = 0; i < max; i++) {
600 		apic_printk(APIC_VERBOSE, KERN_DEBUG
601 				"... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
602 		/*
603 		 * PIRQs are mapped upside down, usually.
604 		 */
605 		pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
606 	}
607 	return 1;
608 }
609 
610 __setup("pirq=", ioapic_pirq_setup);
611 #endif /* CONFIG_X86_32 */
612 
613 /*
614  * Saves all the IO-APIC RTE's
615  */
save_ioapic_entries(void)616 int save_ioapic_entries(void)
617 {
618 	int apic, pin;
619 	int err = 0;
620 
621 	for_each_ioapic(apic) {
622 		if (!ioapics[apic].saved_registers) {
623 			err = -ENOMEM;
624 			continue;
625 		}
626 
627 		for_each_pin(apic, pin)
628 			ioapics[apic].saved_registers[pin] =
629 				ioapic_read_entry(apic, pin);
630 	}
631 
632 	return err;
633 }
634 
635 /*
636  * Mask all IO APIC entries.
637  */
mask_ioapic_entries(void)638 void mask_ioapic_entries(void)
639 {
640 	int apic, pin;
641 
642 	for_each_ioapic(apic) {
643 		if (!ioapics[apic].saved_registers)
644 			continue;
645 
646 		for_each_pin(apic, pin) {
647 			struct IO_APIC_route_entry entry;
648 
649 			entry = ioapics[apic].saved_registers[pin];
650 			if (!entry.masked) {
651 				entry.masked = true;
652 				ioapic_write_entry(apic, pin, entry);
653 			}
654 		}
655 	}
656 }
657 
658 /*
659  * Restore IO APIC entries which was saved in the ioapic structure.
660  */
restore_ioapic_entries(void)661 int restore_ioapic_entries(void)
662 {
663 	int apic, pin;
664 
665 	for_each_ioapic(apic) {
666 		if (!ioapics[apic].saved_registers)
667 			continue;
668 
669 		for_each_pin(apic, pin)
670 			ioapic_write_entry(apic, pin,
671 					   ioapics[apic].saved_registers[pin]);
672 	}
673 	return 0;
674 }
675 
676 /*
677  * Find the IRQ entry number of a certain pin.
678  */
find_irq_entry(int ioapic_idx,int pin,int type)679 static int find_irq_entry(int ioapic_idx, int pin, int type)
680 {
681 	int i;
682 
683 	for (i = 0; i < mp_irq_entries; i++)
684 		if (mp_irqs[i].irqtype == type &&
685 		    (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
686 		     mp_irqs[i].dstapic == MP_APIC_ALL) &&
687 		    mp_irqs[i].dstirq == pin)
688 			return i;
689 
690 	return -1;
691 }
692 
693 /*
694  * Find the pin to which IRQ[irq] (ISA) is connected
695  */
find_isa_irq_pin(int irq,int type)696 static int __init find_isa_irq_pin(int irq, int type)
697 {
698 	int i;
699 
700 	for (i = 0; i < mp_irq_entries; i++) {
701 		int lbus = mp_irqs[i].srcbus;
702 
703 		if (test_bit(lbus, mp_bus_not_pci) &&
704 		    (mp_irqs[i].irqtype == type) &&
705 		    (mp_irqs[i].srcbusirq == irq))
706 
707 			return mp_irqs[i].dstirq;
708 	}
709 	return -1;
710 }
711 
find_isa_irq_apic(int irq,int type)712 static int __init find_isa_irq_apic(int irq, int type)
713 {
714 	int i;
715 
716 	for (i = 0; i < mp_irq_entries; i++) {
717 		int lbus = mp_irqs[i].srcbus;
718 
719 		if (test_bit(lbus, mp_bus_not_pci) &&
720 		    (mp_irqs[i].irqtype == type) &&
721 		    (mp_irqs[i].srcbusirq == irq))
722 			break;
723 	}
724 
725 	if (i < mp_irq_entries) {
726 		int ioapic_idx;
727 
728 		for_each_ioapic(ioapic_idx)
729 			if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
730 				return ioapic_idx;
731 	}
732 
733 	return -1;
734 }
735 
irq_active_low(int idx)736 static bool irq_active_low(int idx)
737 {
738 	int bus = mp_irqs[idx].srcbus;
739 
740 	/*
741 	 * Determine IRQ line polarity (high active or low active):
742 	 */
743 	switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
744 	case MP_IRQPOL_DEFAULT:
745 		/*
746 		 * Conforms to spec, ie. bus-type dependent polarity.  PCI
747 		 * defaults to low active. [E]ISA defaults to high active.
748 		 */
749 		return !test_bit(bus, mp_bus_not_pci);
750 	case MP_IRQPOL_ACTIVE_HIGH:
751 		return false;
752 	case MP_IRQPOL_RESERVED:
753 		pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
754 		fallthrough;
755 	case MP_IRQPOL_ACTIVE_LOW:
756 	default: /* Pointless default required due to do gcc stupidity */
757 		return true;
758 	}
759 }
760 
761 #ifdef CONFIG_EISA
762 /*
763  * EISA Edge/Level control register, ELCR
764  */
EISA_ELCR(unsigned int irq)765 static bool EISA_ELCR(unsigned int irq)
766 {
767 	if (irq < nr_legacy_irqs()) {
768 		unsigned int port = PIC_ELCR1 + (irq >> 3);
769 		return (inb(port) >> (irq & 7)) & 1;
770 	}
771 	apic_printk(APIC_VERBOSE, KERN_INFO
772 			"Broken MPtable reports ISA irq %d\n", irq);
773 	return false;
774 }
775 
776 /*
777  * EISA interrupts are always active high and can be edge or level
778  * triggered depending on the ELCR value.  If an interrupt is listed as
779  * EISA conforming in the MP table, that means its trigger type must be
780  * read in from the ELCR.
781  */
eisa_irq_is_level(int idx,int bus,bool level)782 static bool eisa_irq_is_level(int idx, int bus, bool level)
783 {
784 	switch (mp_bus_id_to_type[bus]) {
785 	case MP_BUS_PCI:
786 	case MP_BUS_ISA:
787 		return level;
788 	case MP_BUS_EISA:
789 		return EISA_ELCR(mp_irqs[idx].srcbusirq);
790 	}
791 	pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
792 	return true;
793 }
794 #else
eisa_irq_is_level(int idx,int bus,bool level)795 static inline int eisa_irq_is_level(int idx, int bus, bool level)
796 {
797 	return level;
798 }
799 #endif
800 
irq_is_level(int idx)801 static bool irq_is_level(int idx)
802 {
803 	int bus = mp_irqs[idx].srcbus;
804 	bool level;
805 
806 	/*
807 	 * Determine IRQ trigger mode (edge or level sensitive):
808 	 */
809 	switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
810 	case MP_IRQTRIG_DEFAULT:
811 		/*
812 		 * Conforms to spec, ie. bus-type dependent trigger
813 		 * mode. PCI defaults to level, ISA to edge.
814 		 */
815 		level = !test_bit(bus, mp_bus_not_pci);
816 		/* Take EISA into account */
817 		return eisa_irq_is_level(idx, bus, level);
818 	case MP_IRQTRIG_EDGE:
819 		return false;
820 	case MP_IRQTRIG_RESERVED:
821 		pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
822 		fallthrough;
823 	case MP_IRQTRIG_LEVEL:
824 	default: /* Pointless default required due to do gcc stupidity */
825 		return true;
826 	}
827 }
828 
__acpi_get_override_irq(u32 gsi,bool * trigger,bool * polarity)829 static int __acpi_get_override_irq(u32 gsi, bool *trigger, bool *polarity)
830 {
831 	int ioapic, pin, idx;
832 
833 	if (skip_ioapic_setup)
834 		return -1;
835 
836 	ioapic = mp_find_ioapic(gsi);
837 	if (ioapic < 0)
838 		return -1;
839 
840 	pin = mp_find_ioapic_pin(ioapic, gsi);
841 	if (pin < 0)
842 		return -1;
843 
844 	idx = find_irq_entry(ioapic, pin, mp_INT);
845 	if (idx < 0)
846 		return -1;
847 
848 	*trigger = irq_is_level(idx);
849 	*polarity = irq_active_low(idx);
850 	return 0;
851 }
852 
853 #ifdef CONFIG_ACPI
acpi_get_override_irq(u32 gsi,int * is_level,int * active_low)854 int acpi_get_override_irq(u32 gsi, int *is_level, int *active_low)
855 {
856 	*is_level = *active_low = 0;
857 	return __acpi_get_override_irq(gsi, (bool *)is_level,
858 				       (bool *)active_low);
859 }
860 #endif
861 
ioapic_set_alloc_attr(struct irq_alloc_info * info,int node,int trigger,int polarity)862 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
863 			   int trigger, int polarity)
864 {
865 	init_irq_alloc_info(info, NULL);
866 	info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
867 	info->ioapic.node = node;
868 	info->ioapic.is_level = trigger;
869 	info->ioapic.active_low = polarity;
870 	info->ioapic.valid = 1;
871 }
872 
ioapic_copy_alloc_attr(struct irq_alloc_info * dst,struct irq_alloc_info * src,u32 gsi,int ioapic_idx,int pin)873 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
874 				   struct irq_alloc_info *src,
875 				   u32 gsi, int ioapic_idx, int pin)
876 {
877 	bool level, pol_low;
878 
879 	copy_irq_alloc_info(dst, src);
880 	dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
881 	dst->devid = mpc_ioapic_id(ioapic_idx);
882 	dst->ioapic.pin = pin;
883 	dst->ioapic.valid = 1;
884 	if (src && src->ioapic.valid) {
885 		dst->ioapic.node = src->ioapic.node;
886 		dst->ioapic.is_level = src->ioapic.is_level;
887 		dst->ioapic.active_low = src->ioapic.active_low;
888 	} else {
889 		dst->ioapic.node = NUMA_NO_NODE;
890 		if (__acpi_get_override_irq(gsi, &level, &pol_low) >= 0) {
891 			dst->ioapic.is_level = level;
892 			dst->ioapic.active_low = pol_low;
893 		} else {
894 			/*
895 			 * PCI interrupts are always active low level
896 			 * triggered.
897 			 */
898 			dst->ioapic.is_level = true;
899 			dst->ioapic.active_low = true;
900 		}
901 	}
902 }
903 
ioapic_alloc_attr_node(struct irq_alloc_info * info)904 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
905 {
906 	return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE;
907 }
908 
mp_register_handler(unsigned int irq,bool level)909 static void mp_register_handler(unsigned int irq, bool level)
910 {
911 	irq_flow_handler_t hdl;
912 	bool fasteoi;
913 
914 	if (level) {
915 		irq_set_status_flags(irq, IRQ_LEVEL);
916 		fasteoi = true;
917 	} else {
918 		irq_clear_status_flags(irq, IRQ_LEVEL);
919 		fasteoi = false;
920 	}
921 
922 	hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
923 	__irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
924 }
925 
mp_check_pin_attr(int irq,struct irq_alloc_info * info)926 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
927 {
928 	struct mp_chip_data *data = irq_get_chip_data(irq);
929 
930 	/*
931 	 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
932 	 * and polarity attributes. So allow the first user to reprogram the
933 	 * pin with real trigger and polarity attributes.
934 	 */
935 	if (irq < nr_legacy_irqs() && data->count == 1) {
936 		if (info->ioapic.is_level != data->is_level)
937 			mp_register_handler(irq, info->ioapic.is_level);
938 		data->entry.is_level = data->is_level = info->ioapic.is_level;
939 		data->entry.active_low = data->active_low = info->ioapic.active_low;
940 	}
941 
942 	return data->is_level == info->ioapic.is_level &&
943 	       data->active_low == info->ioapic.active_low;
944 }
945 
alloc_irq_from_domain(struct irq_domain * domain,int ioapic,u32 gsi,struct irq_alloc_info * info)946 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
947 				 struct irq_alloc_info *info)
948 {
949 	bool legacy = false;
950 	int irq = -1;
951 	int type = ioapics[ioapic].irqdomain_cfg.type;
952 
953 	switch (type) {
954 	case IOAPIC_DOMAIN_LEGACY:
955 		/*
956 		 * Dynamically allocate IRQ number for non-ISA IRQs in the first
957 		 * 16 GSIs on some weird platforms.
958 		 */
959 		if (!ioapic_initialized || gsi >= nr_legacy_irqs())
960 			irq = gsi;
961 		legacy = mp_is_legacy_irq(irq);
962 		break;
963 	case IOAPIC_DOMAIN_STRICT:
964 		irq = gsi;
965 		break;
966 	case IOAPIC_DOMAIN_DYNAMIC:
967 		break;
968 	default:
969 		WARN(1, "ioapic: unknown irqdomain type %d\n", type);
970 		return -1;
971 	}
972 
973 	return __irq_domain_alloc_irqs(domain, irq, 1,
974 				       ioapic_alloc_attr_node(info),
975 				       info, legacy, NULL);
976 }
977 
978 /*
979  * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
980  * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
981  * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
982  * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
983  * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
984  * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
985  * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
986  * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
987  */
alloc_isa_irq_from_domain(struct irq_domain * domain,int irq,int ioapic,int pin,struct irq_alloc_info * info)988 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
989 				     int irq, int ioapic, int pin,
990 				     struct irq_alloc_info *info)
991 {
992 	struct mp_chip_data *data;
993 	struct irq_data *irq_data = irq_get_irq_data(irq);
994 	int node = ioapic_alloc_attr_node(info);
995 
996 	/*
997 	 * Legacy ISA IRQ has already been allocated, just add pin to
998 	 * the pin list associated with this IRQ and program the IOAPIC
999 	 * entry. The IOAPIC entry
1000 	 */
1001 	if (irq_data && irq_data->parent_data) {
1002 		if (!mp_check_pin_attr(irq, info))
1003 			return -EBUSY;
1004 		if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1005 					  info->ioapic.pin))
1006 			return -ENOMEM;
1007 	} else {
1008 		info->flags |= X86_IRQ_ALLOC_LEGACY;
1009 		irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1010 					      NULL);
1011 		if (irq >= 0) {
1012 			irq_data = irq_domain_get_irq_data(domain, irq);
1013 			data = irq_data->chip_data;
1014 			data->isa_irq = true;
1015 		}
1016 	}
1017 
1018 	return irq;
1019 }
1020 
mp_map_pin_to_irq(u32 gsi,int idx,int ioapic,int pin,unsigned int flags,struct irq_alloc_info * info)1021 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1022 			     unsigned int flags, struct irq_alloc_info *info)
1023 {
1024 	int irq;
1025 	bool legacy = false;
1026 	struct irq_alloc_info tmp;
1027 	struct mp_chip_data *data;
1028 	struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1029 
1030 	if (!domain)
1031 		return -ENOSYS;
1032 
1033 	if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1034 		irq = mp_irqs[idx].srcbusirq;
1035 		legacy = mp_is_legacy_irq(irq);
1036 		/*
1037 		 * IRQ2 is unusable for historical reasons on systems which
1038 		 * have a legacy PIC. See the comment vs. IRQ2 further down.
1039 		 *
1040 		 * If this gets removed at some point then the related code
1041 		 * in lapic_assign_system_vectors() needs to be adjusted as
1042 		 * well.
1043 		 */
1044 		if (legacy && irq == PIC_CASCADE_IR)
1045 			return -EINVAL;
1046 	}
1047 
1048 	mutex_lock(&ioapic_mutex);
1049 	if (!(flags & IOAPIC_MAP_ALLOC)) {
1050 		if (!legacy) {
1051 			irq = irq_find_mapping(domain, pin);
1052 			if (irq == 0)
1053 				irq = -ENOENT;
1054 		}
1055 	} else {
1056 		ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1057 		if (legacy)
1058 			irq = alloc_isa_irq_from_domain(domain, irq,
1059 							ioapic, pin, &tmp);
1060 		else if ((irq = irq_find_mapping(domain, pin)) == 0)
1061 			irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1062 		else if (!mp_check_pin_attr(irq, &tmp))
1063 			irq = -EBUSY;
1064 		if (irq >= 0) {
1065 			data = irq_get_chip_data(irq);
1066 			data->count++;
1067 		}
1068 	}
1069 	mutex_unlock(&ioapic_mutex);
1070 
1071 	return irq;
1072 }
1073 
pin_2_irq(int idx,int ioapic,int pin,unsigned int flags)1074 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1075 {
1076 	u32 gsi = mp_pin_to_gsi(ioapic, pin);
1077 
1078 	/*
1079 	 * Debugging check, we are in big trouble if this message pops up!
1080 	 */
1081 	if (mp_irqs[idx].dstirq != pin)
1082 		pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1083 
1084 #ifdef CONFIG_X86_32
1085 	/*
1086 	 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1087 	 */
1088 	if ((pin >= 16) && (pin <= 23)) {
1089 		if (pirq_entries[pin-16] != -1) {
1090 			if (!pirq_entries[pin-16]) {
1091 				apic_printk(APIC_VERBOSE, KERN_DEBUG
1092 						"disabling PIRQ%d\n", pin-16);
1093 			} else {
1094 				int irq = pirq_entries[pin-16];
1095 				apic_printk(APIC_VERBOSE, KERN_DEBUG
1096 						"using PIRQ%d -> IRQ %d\n",
1097 						pin-16, irq);
1098 				return irq;
1099 			}
1100 		}
1101 	}
1102 #endif
1103 
1104 	return  mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1105 }
1106 
mp_map_gsi_to_irq(u32 gsi,unsigned int flags,struct irq_alloc_info * info)1107 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1108 {
1109 	int ioapic, pin, idx;
1110 
1111 	ioapic = mp_find_ioapic(gsi);
1112 	if (ioapic < 0)
1113 		return -ENODEV;
1114 
1115 	pin = mp_find_ioapic_pin(ioapic, gsi);
1116 	idx = find_irq_entry(ioapic, pin, mp_INT);
1117 	if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1118 		return -ENODEV;
1119 
1120 	return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1121 }
1122 
mp_unmap_irq(int irq)1123 void mp_unmap_irq(int irq)
1124 {
1125 	struct irq_data *irq_data = irq_get_irq_data(irq);
1126 	struct mp_chip_data *data;
1127 
1128 	if (!irq_data || !irq_data->domain)
1129 		return;
1130 
1131 	data = irq_data->chip_data;
1132 	if (!data || data->isa_irq)
1133 		return;
1134 
1135 	mutex_lock(&ioapic_mutex);
1136 	if (--data->count == 0)
1137 		irq_domain_free_irqs(irq, 1);
1138 	mutex_unlock(&ioapic_mutex);
1139 }
1140 
1141 /*
1142  * Find a specific PCI IRQ entry.
1143  * Not an __init, possibly needed by modules
1144  */
IO_APIC_get_PCI_irq_vector(int bus,int slot,int pin)1145 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1146 {
1147 	int irq, i, best_ioapic = -1, best_idx = -1;
1148 
1149 	apic_printk(APIC_DEBUG,
1150 		    "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1151 		    bus, slot, pin);
1152 	if (test_bit(bus, mp_bus_not_pci)) {
1153 		apic_printk(APIC_VERBOSE,
1154 			    "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1155 		return -1;
1156 	}
1157 
1158 	for (i = 0; i < mp_irq_entries; i++) {
1159 		int lbus = mp_irqs[i].srcbus;
1160 		int ioapic_idx, found = 0;
1161 
1162 		if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1163 		    slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1164 			continue;
1165 
1166 		for_each_ioapic(ioapic_idx)
1167 			if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1168 			    mp_irqs[i].dstapic == MP_APIC_ALL) {
1169 				found = 1;
1170 				break;
1171 			}
1172 		if (!found)
1173 			continue;
1174 
1175 		/* Skip ISA IRQs */
1176 		irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1177 		if (irq > 0 && !IO_APIC_IRQ(irq))
1178 			continue;
1179 
1180 		if (pin == (mp_irqs[i].srcbusirq & 3)) {
1181 			best_idx = i;
1182 			best_ioapic = ioapic_idx;
1183 			goto out;
1184 		}
1185 
1186 		/*
1187 		 * Use the first all-but-pin matching entry as a
1188 		 * best-guess fuzzy result for broken mptables.
1189 		 */
1190 		if (best_idx < 0) {
1191 			best_idx = i;
1192 			best_ioapic = ioapic_idx;
1193 		}
1194 	}
1195 	if (best_idx < 0)
1196 		return -1;
1197 
1198 out:
1199 	return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1200 			 IOAPIC_MAP_ALLOC);
1201 }
1202 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1203 
1204 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1205 
setup_IO_APIC_irqs(void)1206 static void __init setup_IO_APIC_irqs(void)
1207 {
1208 	unsigned int ioapic, pin;
1209 	int idx;
1210 
1211 	apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1212 
1213 	for_each_ioapic_pin(ioapic, pin) {
1214 		idx = find_irq_entry(ioapic, pin, mp_INT);
1215 		if (idx < 0)
1216 			apic_printk(APIC_VERBOSE,
1217 				    KERN_DEBUG " apic %d pin %d not connected\n",
1218 				    mpc_ioapic_id(ioapic), pin);
1219 		else
1220 			pin_2_irq(idx, ioapic, pin,
1221 				  ioapic ? 0 : IOAPIC_MAP_ALLOC);
1222 	}
1223 }
1224 
ioapic_zap_locks(void)1225 void ioapic_zap_locks(void)
1226 {
1227 	raw_spin_lock_init(&ioapic_lock);
1228 }
1229 
io_apic_print_entries(unsigned int apic,unsigned int nr_entries)1230 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1231 {
1232 	struct IO_APIC_route_entry entry;
1233 	char buf[256];
1234 	int i;
1235 
1236 	printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1237 	for (i = 0; i <= nr_entries; i++) {
1238 		entry = ioapic_read_entry(apic, i);
1239 		snprintf(buf, sizeof(buf),
1240 			 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1241 			 i,
1242 			 entry.masked ? "disabled" : "enabled ",
1243 			 entry.is_level ? "level" : "edge ",
1244 			 entry.active_low ? "low " : "high",
1245 			 entry.vector, entry.irr, entry.delivery_status);
1246 		if (entry.ir_format) {
1247 			printk(KERN_DEBUG "%s, remapped, I(%04X),  Z(%X)\n",
1248 			       buf,
1249 			       (entry.ir_index_15 << 15) | entry.ir_index_0_14,
1250 				entry.ir_zero);
1251 		} else {
1252 			printk(KERN_DEBUG "%s, %s, D(%02X%02X), M(%1d)\n", buf,
1253 			       entry.dest_mode_logical ? "logical " : "physical",
1254 			       entry.virt_destid_8_14, entry.destid_0_7,
1255 			       entry.delivery_mode);
1256 		}
1257 	}
1258 }
1259 
print_IO_APIC(int ioapic_idx)1260 static void __init print_IO_APIC(int ioapic_idx)
1261 {
1262 	union IO_APIC_reg_00 reg_00;
1263 	union IO_APIC_reg_01 reg_01;
1264 	union IO_APIC_reg_02 reg_02;
1265 	union IO_APIC_reg_03 reg_03;
1266 	unsigned long flags;
1267 
1268 	raw_spin_lock_irqsave(&ioapic_lock, flags);
1269 	reg_00.raw = io_apic_read(ioapic_idx, 0);
1270 	reg_01.raw = io_apic_read(ioapic_idx, 1);
1271 	if (reg_01.bits.version >= 0x10)
1272 		reg_02.raw = io_apic_read(ioapic_idx, 2);
1273 	if (reg_01.bits.version >= 0x20)
1274 		reg_03.raw = io_apic_read(ioapic_idx, 3);
1275 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1276 
1277 	printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1278 	printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1279 	printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1280 	printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1281 	printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1282 
1283 	printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1284 	printk(KERN_DEBUG ".......     : max redirection entries: %02X\n",
1285 		reg_01.bits.entries);
1286 
1287 	printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1288 	printk(KERN_DEBUG ".......     : IO APIC version: %02X\n",
1289 		reg_01.bits.version);
1290 
1291 	/*
1292 	 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1293 	 * but the value of reg_02 is read as the previous read register
1294 	 * value, so ignore it if reg_02 == reg_01.
1295 	 */
1296 	if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1297 		printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1298 		printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1299 	}
1300 
1301 	/*
1302 	 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1303 	 * or reg_03, but the value of reg_0[23] is read as the previous read
1304 	 * register value, so ignore it if reg_03 == reg_0[12].
1305 	 */
1306 	if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1307 	    reg_03.raw != reg_01.raw) {
1308 		printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1309 		printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1310 	}
1311 
1312 	printk(KERN_DEBUG ".... IRQ redirection table:\n");
1313 	io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1314 }
1315 
print_IO_APICs(void)1316 void __init print_IO_APICs(void)
1317 {
1318 	int ioapic_idx;
1319 	unsigned int irq;
1320 
1321 	printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1322 	for_each_ioapic(ioapic_idx)
1323 		printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1324 		       mpc_ioapic_id(ioapic_idx),
1325 		       ioapics[ioapic_idx].nr_registers);
1326 
1327 	/*
1328 	 * We are a bit conservative about what we expect.  We have to
1329 	 * know about every hardware change ASAP.
1330 	 */
1331 	printk(KERN_INFO "testing the IO APIC.......................\n");
1332 
1333 	for_each_ioapic(ioapic_idx)
1334 		print_IO_APIC(ioapic_idx);
1335 
1336 	printk(KERN_DEBUG "IRQ to pin mappings:\n");
1337 	for_each_active_irq(irq) {
1338 		struct irq_pin_list *entry;
1339 		struct irq_chip *chip;
1340 		struct mp_chip_data *data;
1341 
1342 		chip = irq_get_chip(irq);
1343 		if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1344 			continue;
1345 		data = irq_get_chip_data(irq);
1346 		if (!data)
1347 			continue;
1348 		if (list_empty(&data->irq_2_pin))
1349 			continue;
1350 
1351 		printk(KERN_DEBUG "IRQ%d ", irq);
1352 		for_each_irq_pin(entry, data->irq_2_pin)
1353 			pr_cont("-> %d:%d", entry->apic, entry->pin);
1354 		pr_cont("\n");
1355 	}
1356 
1357 	printk(KERN_INFO ".................................... done.\n");
1358 }
1359 
1360 /* Where if anywhere is the i8259 connect in external int mode */
1361 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1362 
enable_IO_APIC(void)1363 void __init enable_IO_APIC(void)
1364 {
1365 	int i8259_apic, i8259_pin;
1366 	int apic, pin;
1367 
1368 	if (skip_ioapic_setup)
1369 		nr_ioapics = 0;
1370 
1371 	if (!nr_legacy_irqs() || !nr_ioapics)
1372 		return;
1373 
1374 	for_each_ioapic_pin(apic, pin) {
1375 		/* See if any of the pins is in ExtINT mode */
1376 		struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1377 
1378 		/* If the interrupt line is enabled and in ExtInt mode
1379 		 * I have found the pin where the i8259 is connected.
1380 		 */
1381 		if (!entry.masked &&
1382 		    entry.delivery_mode == APIC_DELIVERY_MODE_EXTINT) {
1383 			ioapic_i8259.apic = apic;
1384 			ioapic_i8259.pin  = pin;
1385 			goto found_i8259;
1386 		}
1387 	}
1388  found_i8259:
1389 	/* Look to see what if the MP table has reported the ExtINT */
1390 	/* If we could not find the appropriate pin by looking at the ioapic
1391 	 * the i8259 probably is not connected the ioapic but give the
1392 	 * mptable a chance anyway.
1393 	 */
1394 	i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1395 	i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1396 	/* Trust the MP table if nothing is setup in the hardware */
1397 	if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1398 		printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1399 		ioapic_i8259.pin  = i8259_pin;
1400 		ioapic_i8259.apic = i8259_apic;
1401 	}
1402 	/* Complain if the MP table and the hardware disagree */
1403 	if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1404 		(i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1405 	{
1406 		printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1407 	}
1408 
1409 	/*
1410 	 * Do not trust the IO-APIC being empty at bootup
1411 	 */
1412 	clear_IO_APIC();
1413 }
1414 
native_restore_boot_irq_mode(void)1415 void native_restore_boot_irq_mode(void)
1416 {
1417 	/*
1418 	 * If the i8259 is routed through an IOAPIC
1419 	 * Put that IOAPIC in virtual wire mode
1420 	 * so legacy interrupts can be delivered.
1421 	 */
1422 	if (ioapic_i8259.pin != -1) {
1423 		struct IO_APIC_route_entry entry;
1424 		u32 apic_id = read_apic_id();
1425 
1426 		memset(&entry, 0, sizeof(entry));
1427 		entry.masked		= false;
1428 		entry.is_level		= false;
1429 		entry.active_low	= false;
1430 		entry.dest_mode_logical	= false;
1431 		entry.delivery_mode	= APIC_DELIVERY_MODE_EXTINT;
1432 		entry.destid_0_7	= apic_id & 0xFF;
1433 		entry.virt_destid_8_14	= apic_id >> 8;
1434 
1435 		/*
1436 		 * Add it to the IO-APIC irq-routing table:
1437 		 */
1438 		ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1439 	}
1440 
1441 	if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1442 		disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1443 }
1444 
restore_boot_irq_mode(void)1445 void restore_boot_irq_mode(void)
1446 {
1447 	if (!nr_legacy_irqs())
1448 		return;
1449 
1450 	x86_apic_ops.restore();
1451 }
1452 
1453 #ifdef CONFIG_X86_32
1454 /*
1455  * function to set the IO-APIC physical IDs based on the
1456  * values stored in the MPC table.
1457  *
1458  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1459  */
setup_ioapic_ids_from_mpc_nocheck(void)1460 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1461 {
1462 	union IO_APIC_reg_00 reg_00;
1463 	physid_mask_t phys_id_present_map;
1464 	int ioapic_idx;
1465 	int i;
1466 	unsigned char old_id;
1467 	unsigned long flags;
1468 
1469 	/*
1470 	 * This is broken; anything with a real cpu count has to
1471 	 * circumvent this idiocy regardless.
1472 	 */
1473 	apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1474 
1475 	/*
1476 	 * Set the IOAPIC ID to the value stored in the MPC table.
1477 	 */
1478 	for_each_ioapic(ioapic_idx) {
1479 		/* Read the register 0 value */
1480 		raw_spin_lock_irqsave(&ioapic_lock, flags);
1481 		reg_00.raw = io_apic_read(ioapic_idx, 0);
1482 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1483 
1484 		old_id = mpc_ioapic_id(ioapic_idx);
1485 
1486 		if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1487 			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1488 				ioapic_idx, mpc_ioapic_id(ioapic_idx));
1489 			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1490 				reg_00.bits.ID);
1491 			ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1492 		}
1493 
1494 		/*
1495 		 * Sanity check, is the ID really free? Every APIC in a
1496 		 * system must have a unique ID or we get lots of nice
1497 		 * 'stuck on smp_invalidate_needed IPI wait' messages.
1498 		 */
1499 		if (apic->check_apicid_used(&phys_id_present_map,
1500 					    mpc_ioapic_id(ioapic_idx))) {
1501 			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1502 				ioapic_idx, mpc_ioapic_id(ioapic_idx));
1503 			for (i = 0; i < get_physical_broadcast(); i++)
1504 				if (!physid_isset(i, phys_id_present_map))
1505 					break;
1506 			if (i >= get_physical_broadcast())
1507 				panic("Max APIC ID exceeded!\n");
1508 			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1509 				i);
1510 			physid_set(i, phys_id_present_map);
1511 			ioapics[ioapic_idx].mp_config.apicid = i;
1512 		} else {
1513 			physid_mask_t tmp;
1514 			apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1515 						    &tmp);
1516 			apic_printk(APIC_VERBOSE, "Setting %d in the "
1517 					"phys_id_present_map\n",
1518 					mpc_ioapic_id(ioapic_idx));
1519 			physids_or(phys_id_present_map, phys_id_present_map, tmp);
1520 		}
1521 
1522 		/*
1523 		 * We need to adjust the IRQ routing table
1524 		 * if the ID changed.
1525 		 */
1526 		if (old_id != mpc_ioapic_id(ioapic_idx))
1527 			for (i = 0; i < mp_irq_entries; i++)
1528 				if (mp_irqs[i].dstapic == old_id)
1529 					mp_irqs[i].dstapic
1530 						= mpc_ioapic_id(ioapic_idx);
1531 
1532 		/*
1533 		 * Update the ID register according to the right value
1534 		 * from the MPC table if they are different.
1535 		 */
1536 		if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1537 			continue;
1538 
1539 		apic_printk(APIC_VERBOSE, KERN_INFO
1540 			"...changing IO-APIC physical APIC ID to %d ...",
1541 			mpc_ioapic_id(ioapic_idx));
1542 
1543 		reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1544 		raw_spin_lock_irqsave(&ioapic_lock, flags);
1545 		io_apic_write(ioapic_idx, 0, reg_00.raw);
1546 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1547 
1548 		/*
1549 		 * Sanity check
1550 		 */
1551 		raw_spin_lock_irqsave(&ioapic_lock, flags);
1552 		reg_00.raw = io_apic_read(ioapic_idx, 0);
1553 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1554 		if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1555 			pr_cont("could not set ID!\n");
1556 		else
1557 			apic_printk(APIC_VERBOSE, " ok.\n");
1558 	}
1559 }
1560 
setup_ioapic_ids_from_mpc(void)1561 void __init setup_ioapic_ids_from_mpc(void)
1562 {
1563 
1564 	if (acpi_ioapic)
1565 		return;
1566 	/*
1567 	 * Don't check I/O APIC IDs for xAPIC systems.  They have
1568 	 * no meaning without the serial APIC bus.
1569 	 */
1570 	if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1571 		|| APIC_XAPIC(boot_cpu_apic_version))
1572 		return;
1573 	setup_ioapic_ids_from_mpc_nocheck();
1574 }
1575 #endif
1576 
1577 int no_timer_check __initdata;
1578 
notimercheck(char * s)1579 static int __init notimercheck(char *s)
1580 {
1581 	no_timer_check = 1;
1582 	return 1;
1583 }
1584 __setup("no_timer_check", notimercheck);
1585 
delay_with_tsc(void)1586 static void __init delay_with_tsc(void)
1587 {
1588 	unsigned long long start, now;
1589 	unsigned long end = jiffies + 4;
1590 
1591 	start = rdtsc();
1592 
1593 	/*
1594 	 * We don't know the TSC frequency yet, but waiting for
1595 	 * 40000000000/HZ TSC cycles is safe:
1596 	 * 4 GHz == 10 jiffies
1597 	 * 1 GHz == 40 jiffies
1598 	 */
1599 	do {
1600 		rep_nop();
1601 		now = rdtsc();
1602 	} while ((now - start) < 40000000000ULL / HZ &&
1603 		time_before_eq(jiffies, end));
1604 }
1605 
delay_without_tsc(void)1606 static void __init delay_without_tsc(void)
1607 {
1608 	unsigned long end = jiffies + 4;
1609 	int band = 1;
1610 
1611 	/*
1612 	 * We don't know any frequency yet, but waiting for
1613 	 * 40940000000/HZ cycles is safe:
1614 	 * 4 GHz == 10 jiffies
1615 	 * 1 GHz == 40 jiffies
1616 	 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1617 	 */
1618 	do {
1619 		__delay(((1U << band++) * 10000000UL) / HZ);
1620 	} while (band < 12 && time_before_eq(jiffies, end));
1621 }
1622 
1623 /*
1624  * There is a nasty bug in some older SMP boards, their mptable lies
1625  * about the timer IRQ. We do the following to work around the situation:
1626  *
1627  *	- timer IRQ defaults to IO-APIC IRQ
1628  *	- if this function detects that timer IRQs are defunct, then we fall
1629  *	  back to ISA timer IRQs
1630  */
timer_irq_works(void)1631 static int __init timer_irq_works(void)
1632 {
1633 	unsigned long t1 = jiffies;
1634 
1635 	if (no_timer_check)
1636 		return 1;
1637 
1638 	local_irq_enable();
1639 	if (boot_cpu_has(X86_FEATURE_TSC))
1640 		delay_with_tsc();
1641 	else
1642 		delay_without_tsc();
1643 
1644 	/*
1645 	 * Expect a few ticks at least, to be sure some possible
1646 	 * glue logic does not lock up after one or two first
1647 	 * ticks in a non-ExtINT mode.  Also the local APIC
1648 	 * might have cached one ExtINT interrupt.  Finally, at
1649 	 * least one tick may be lost due to delays.
1650 	 */
1651 
1652 	local_irq_disable();
1653 
1654 	/* Did jiffies advance? */
1655 	return time_after(jiffies, t1 + 4);
1656 }
1657 
1658 /*
1659  * In the SMP+IOAPIC case it might happen that there are an unspecified
1660  * number of pending IRQ events unhandled. These cases are very rare,
1661  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1662  * better to do it this way as thus we do not have to be aware of
1663  * 'pending' interrupts in the IRQ path, except at this point.
1664  */
1665 /*
1666  * Edge triggered needs to resend any interrupt
1667  * that was delayed but this is now handled in the device
1668  * independent code.
1669  */
1670 
1671 /*
1672  * Starting up a edge-triggered IO-APIC interrupt is
1673  * nasty - we need to make sure that we get the edge.
1674  * If it is already asserted for some reason, we need
1675  * return 1 to indicate that is was pending.
1676  *
1677  * This is not complete - we should be able to fake
1678  * an edge even if it isn't on the 8259A...
1679  */
startup_ioapic_irq(struct irq_data * data)1680 static unsigned int startup_ioapic_irq(struct irq_data *data)
1681 {
1682 	int was_pending = 0, irq = data->irq;
1683 	unsigned long flags;
1684 
1685 	raw_spin_lock_irqsave(&ioapic_lock, flags);
1686 	if (irq < nr_legacy_irqs()) {
1687 		legacy_pic->mask(irq);
1688 		if (legacy_pic->irq_pending(irq))
1689 			was_pending = 1;
1690 	}
1691 	__unmask_ioapic(data->chip_data);
1692 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1693 
1694 	return was_pending;
1695 }
1696 
1697 atomic_t irq_mis_count;
1698 
1699 #ifdef CONFIG_GENERIC_PENDING_IRQ
io_apic_level_ack_pending(struct mp_chip_data * data)1700 static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1701 {
1702 	struct irq_pin_list *entry;
1703 	unsigned long flags;
1704 
1705 	raw_spin_lock_irqsave(&ioapic_lock, flags);
1706 	for_each_irq_pin(entry, data->irq_2_pin) {
1707 		struct IO_APIC_route_entry e;
1708 		int pin;
1709 
1710 		pin = entry->pin;
1711 		e.w1 = io_apic_read(entry->apic, 0x10 + pin*2);
1712 		/* Is the remote IRR bit set? */
1713 		if (e.irr) {
1714 			raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1715 			return true;
1716 		}
1717 	}
1718 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1719 
1720 	return false;
1721 }
1722 
ioapic_prepare_move(struct irq_data * data)1723 static inline bool ioapic_prepare_move(struct irq_data *data)
1724 {
1725 	/* If we are moving the IRQ we need to mask it */
1726 	if (unlikely(irqd_is_setaffinity_pending(data))) {
1727 		if (!irqd_irq_masked(data))
1728 			mask_ioapic_irq(data);
1729 		return true;
1730 	}
1731 	return false;
1732 }
1733 
ioapic_finish_move(struct irq_data * data,bool moveit)1734 static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1735 {
1736 	if (unlikely(moveit)) {
1737 		/* Only migrate the irq if the ack has been received.
1738 		 *
1739 		 * On rare occasions the broadcast level triggered ack gets
1740 		 * delayed going to ioapics, and if we reprogram the
1741 		 * vector while Remote IRR is still set the irq will never
1742 		 * fire again.
1743 		 *
1744 		 * To prevent this scenario we read the Remote IRR bit
1745 		 * of the ioapic.  This has two effects.
1746 		 * - On any sane system the read of the ioapic will
1747 		 *   flush writes (and acks) going to the ioapic from
1748 		 *   this cpu.
1749 		 * - We get to see if the ACK has actually been delivered.
1750 		 *
1751 		 * Based on failed experiments of reprogramming the
1752 		 * ioapic entry from outside of irq context starting
1753 		 * with masking the ioapic entry and then polling until
1754 		 * Remote IRR was clear before reprogramming the
1755 		 * ioapic I don't trust the Remote IRR bit to be
1756 		 * completely accurate.
1757 		 *
1758 		 * However there appears to be no other way to plug
1759 		 * this race, so if the Remote IRR bit is not
1760 		 * accurate and is causing problems then it is a hardware bug
1761 		 * and you can go talk to the chipset vendor about it.
1762 		 */
1763 		if (!io_apic_level_ack_pending(data->chip_data))
1764 			irq_move_masked_irq(data);
1765 		/* If the IRQ is masked in the core, leave it: */
1766 		if (!irqd_irq_masked(data))
1767 			unmask_ioapic_irq(data);
1768 	}
1769 }
1770 #else
ioapic_prepare_move(struct irq_data * data)1771 static inline bool ioapic_prepare_move(struct irq_data *data)
1772 {
1773 	return false;
1774 }
ioapic_finish_move(struct irq_data * data,bool moveit)1775 static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1776 {
1777 }
1778 #endif
1779 
ioapic_ack_level(struct irq_data * irq_data)1780 static void ioapic_ack_level(struct irq_data *irq_data)
1781 {
1782 	struct irq_cfg *cfg = irqd_cfg(irq_data);
1783 	unsigned long v;
1784 	bool moveit;
1785 	int i;
1786 
1787 	irq_complete_move(cfg);
1788 	moveit = ioapic_prepare_move(irq_data);
1789 
1790 	/*
1791 	 * It appears there is an erratum which affects at least version 0x11
1792 	 * of I/O APIC (that's the 82093AA and cores integrated into various
1793 	 * chipsets).  Under certain conditions a level-triggered interrupt is
1794 	 * erroneously delivered as edge-triggered one but the respective IRR
1795 	 * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1796 	 * message but it will never arrive and further interrupts are blocked
1797 	 * from the source.  The exact reason is so far unknown, but the
1798 	 * phenomenon was observed when two consecutive interrupt requests
1799 	 * from a given source get delivered to the same CPU and the source is
1800 	 * temporarily disabled in between.
1801 	 *
1802 	 * A workaround is to simulate an EOI message manually.  We achieve it
1803 	 * by setting the trigger mode to edge and then to level when the edge
1804 	 * trigger mode gets detected in the TMR of a local APIC for a
1805 	 * level-triggered interrupt.  We mask the source for the time of the
1806 	 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1807 	 * The idea is from Manfred Spraul.  --macro
1808 	 *
1809 	 * Also in the case when cpu goes offline, fixup_irqs() will forward
1810 	 * any unhandled interrupt on the offlined cpu to the new cpu
1811 	 * destination that is handling the corresponding interrupt. This
1812 	 * interrupt forwarding is done via IPI's. Hence, in this case also
1813 	 * level-triggered io-apic interrupt will be seen as an edge
1814 	 * interrupt in the IRR. And we can't rely on the cpu's EOI
1815 	 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1816 	 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1817 	 * supporting EOI register, we do an explicit EOI to clear the
1818 	 * remote IRR and on IO-APIC's which don't have an EOI register,
1819 	 * we use the above logic (mask+edge followed by unmask+level) from
1820 	 * Manfred Spraul to clear the remote IRR.
1821 	 */
1822 	i = cfg->vector;
1823 	v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1824 
1825 	/*
1826 	 * We must acknowledge the irq before we move it or the acknowledge will
1827 	 * not propagate properly.
1828 	 */
1829 	ack_APIC_irq();
1830 
1831 	/*
1832 	 * Tail end of clearing remote IRR bit (either by delivering the EOI
1833 	 * message via io-apic EOI register write or simulating it using
1834 	 * mask+edge followed by unmask+level logic) manually when the
1835 	 * level triggered interrupt is seen as the edge triggered interrupt
1836 	 * at the cpu.
1837 	 */
1838 	if (!(v & (1 << (i & 0x1f)))) {
1839 		atomic_inc(&irq_mis_count);
1840 		eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1841 	}
1842 
1843 	ioapic_finish_move(irq_data, moveit);
1844 }
1845 
ioapic_ir_ack_level(struct irq_data * irq_data)1846 static void ioapic_ir_ack_level(struct irq_data *irq_data)
1847 {
1848 	struct mp_chip_data *data = irq_data->chip_data;
1849 
1850 	/*
1851 	 * Intr-remapping uses pin number as the virtual vector
1852 	 * in the RTE. Actual vector is programmed in
1853 	 * intr-remapping table entry. Hence for the io-apic
1854 	 * EOI we use the pin number.
1855 	 */
1856 	apic_ack_irq(irq_data);
1857 	eoi_ioapic_pin(data->entry.vector, data);
1858 }
1859 
1860 /*
1861  * The I/OAPIC is just a device for generating MSI messages from legacy
1862  * interrupt pins. Various fields of the RTE translate into bits of the
1863  * resulting MSI which had a historical meaning.
1864  *
1865  * With interrupt remapping, many of those bits have different meanings
1866  * in the underlying MSI, but the way that the I/OAPIC transforms them
1867  * from its RTE to the MSI message is the same. This function allows
1868  * the parent IRQ domain to compose the MSI message, then takes the
1869  * relevant bits to put them in the appropriate places in the RTE in
1870  * order to generate that message when the IRQ happens.
1871  *
1872  * The setup here relies on a preconfigured route entry (is_level,
1873  * active_low, masked) because the parent domain is merely composing the
1874  * generic message routing information which is used for the MSI.
1875  */
ioapic_setup_msg_from_msi(struct irq_data * irq_data,struct IO_APIC_route_entry * entry)1876 static void ioapic_setup_msg_from_msi(struct irq_data *irq_data,
1877 				      struct IO_APIC_route_entry *entry)
1878 {
1879 	struct msi_msg msg;
1880 
1881 	/* Let the parent domain compose the MSI message */
1882 	irq_chip_compose_msi_msg(irq_data, &msg);
1883 
1884 	/*
1885 	 * - Real vector
1886 	 * - DMAR/IR: 8bit subhandle (ioapic.pin)
1887 	 * - AMD/IR:  8bit IRTE index
1888 	 */
1889 	entry->vector			= msg.arch_data.vector;
1890 	/* Delivery mode (for DMAR/IR all 0) */
1891 	entry->delivery_mode		= msg.arch_data.delivery_mode;
1892 	/* Destination mode or DMAR/IR index bit 15 */
1893 	entry->dest_mode_logical	= msg.arch_addr_lo.dest_mode_logical;
1894 	/* DMAR/IR: 1, 0 for all other modes */
1895 	entry->ir_format		= msg.arch_addr_lo.dmar_format;
1896 	/*
1897 	 * - DMAR/IR: index bit 0-14.
1898 	 *
1899 	 * - Virt: If the host supports x2apic without a virtualized IR
1900 	 *	   unit then bit 0-6 of dmar_index_0_14 are providing bit
1901 	 *	   8-14 of the destination id.
1902 	 *
1903 	 * All other modes have bit 0-6 of dmar_index_0_14 cleared and the
1904 	 * topmost 8 bits are destination id bit 0-7 (entry::destid_0_7).
1905 	 */
1906 	entry->ir_index_0_14		= msg.arch_addr_lo.dmar_index_0_14;
1907 }
1908 
ioapic_configure_entry(struct irq_data * irqd)1909 static void ioapic_configure_entry(struct irq_data *irqd)
1910 {
1911 	struct mp_chip_data *mpd = irqd->chip_data;
1912 	struct irq_pin_list *entry;
1913 
1914 	ioapic_setup_msg_from_msi(irqd, &mpd->entry);
1915 
1916 	for_each_irq_pin(entry, mpd->irq_2_pin)
1917 		__ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1918 }
1919 
ioapic_set_affinity(struct irq_data * irq_data,const struct cpumask * mask,bool force)1920 static int ioapic_set_affinity(struct irq_data *irq_data,
1921 			       const struct cpumask *mask, bool force)
1922 {
1923 	struct irq_data *parent = irq_data->parent_data;
1924 	unsigned long flags;
1925 	int ret;
1926 
1927 	ret = parent->chip->irq_set_affinity(parent, mask, force);
1928 	raw_spin_lock_irqsave(&ioapic_lock, flags);
1929 	if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1930 		ioapic_configure_entry(irq_data);
1931 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1932 
1933 	return ret;
1934 }
1935 
1936 /*
1937  * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1938  * be in flight, but not yet serviced by the target CPU. That means
1939  * __synchronize_hardirq() would return and claim that everything is calmed
1940  * down. So free_irq() would proceed and deactivate the interrupt and free
1941  * resources.
1942  *
1943  * Once the target CPU comes around to service it it will find a cleared
1944  * vector and complain. While the spurious interrupt is harmless, the full
1945  * release of resources might prevent the interrupt from being acknowledged
1946  * which keeps the hardware in a weird state.
1947  *
1948  * Verify that the corresponding Remote-IRR bits are clear.
1949  */
ioapic_irq_get_chip_state(struct irq_data * irqd,enum irqchip_irq_state which,bool * state)1950 static int ioapic_irq_get_chip_state(struct irq_data *irqd,
1951 				   enum irqchip_irq_state which,
1952 				   bool *state)
1953 {
1954 	struct mp_chip_data *mcd = irqd->chip_data;
1955 	struct IO_APIC_route_entry rentry;
1956 	struct irq_pin_list *p;
1957 
1958 	if (which != IRQCHIP_STATE_ACTIVE)
1959 		return -EINVAL;
1960 
1961 	*state = false;
1962 	raw_spin_lock(&ioapic_lock);
1963 	for_each_irq_pin(p, mcd->irq_2_pin) {
1964 		rentry = __ioapic_read_entry(p->apic, p->pin);
1965 		/*
1966 		 * The remote IRR is only valid in level trigger mode. It's
1967 		 * meaning is undefined for edge triggered interrupts and
1968 		 * irrelevant because the IO-APIC treats them as fire and
1969 		 * forget.
1970 		 */
1971 		if (rentry.irr && rentry.is_level) {
1972 			*state = true;
1973 			break;
1974 		}
1975 	}
1976 	raw_spin_unlock(&ioapic_lock);
1977 	return 0;
1978 }
1979 
1980 static struct irq_chip ioapic_chip __read_mostly = {
1981 	.name			= "IO-APIC",
1982 	.irq_startup		= startup_ioapic_irq,
1983 	.irq_mask		= mask_ioapic_irq,
1984 	.irq_unmask		= unmask_ioapic_irq,
1985 	.irq_ack		= irq_chip_ack_parent,
1986 	.irq_eoi		= ioapic_ack_level,
1987 	.irq_set_affinity	= ioapic_set_affinity,
1988 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
1989 	.irq_get_irqchip_state	= ioapic_irq_get_chip_state,
1990 	.flags			= IRQCHIP_SKIP_SET_WAKE |
1991 				  IRQCHIP_AFFINITY_PRE_STARTUP,
1992 };
1993 
1994 static struct irq_chip ioapic_ir_chip __read_mostly = {
1995 	.name			= "IR-IO-APIC",
1996 	.irq_startup		= startup_ioapic_irq,
1997 	.irq_mask		= mask_ioapic_irq,
1998 	.irq_unmask		= unmask_ioapic_irq,
1999 	.irq_ack		= irq_chip_ack_parent,
2000 	.irq_eoi		= ioapic_ir_ack_level,
2001 	.irq_set_affinity	= ioapic_set_affinity,
2002 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
2003 	.irq_get_irqchip_state	= ioapic_irq_get_chip_state,
2004 	.flags			= IRQCHIP_SKIP_SET_WAKE |
2005 				  IRQCHIP_AFFINITY_PRE_STARTUP,
2006 };
2007 
init_IO_APIC_traps(void)2008 static inline void init_IO_APIC_traps(void)
2009 {
2010 	struct irq_cfg *cfg;
2011 	unsigned int irq;
2012 
2013 	for_each_active_irq(irq) {
2014 		cfg = irq_cfg(irq);
2015 		if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2016 			/*
2017 			 * Hmm.. We don't have an entry for this,
2018 			 * so default to an old-fashioned 8259
2019 			 * interrupt if we can..
2020 			 */
2021 			if (irq < nr_legacy_irqs())
2022 				legacy_pic->make_irq(irq);
2023 			else
2024 				/* Strange. Oh, well.. */
2025 				irq_set_chip(irq, &no_irq_chip);
2026 		}
2027 	}
2028 }
2029 
2030 /*
2031  * The local APIC irq-chip implementation:
2032  */
2033 
mask_lapic_irq(struct irq_data * data)2034 static void mask_lapic_irq(struct irq_data *data)
2035 {
2036 	unsigned long v;
2037 
2038 	v = apic_read(APIC_LVT0);
2039 	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2040 }
2041 
unmask_lapic_irq(struct irq_data * data)2042 static void unmask_lapic_irq(struct irq_data *data)
2043 {
2044 	unsigned long v;
2045 
2046 	v = apic_read(APIC_LVT0);
2047 	apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2048 }
2049 
ack_lapic_irq(struct irq_data * data)2050 static void ack_lapic_irq(struct irq_data *data)
2051 {
2052 	ack_APIC_irq();
2053 }
2054 
2055 static struct irq_chip lapic_chip __read_mostly = {
2056 	.name		= "local-APIC",
2057 	.irq_mask	= mask_lapic_irq,
2058 	.irq_unmask	= unmask_lapic_irq,
2059 	.irq_ack	= ack_lapic_irq,
2060 };
2061 
lapic_register_intr(int irq)2062 static void lapic_register_intr(int irq)
2063 {
2064 	irq_clear_status_flags(irq, IRQ_LEVEL);
2065 	irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2066 				      "edge");
2067 }
2068 
2069 /*
2070  * This looks a bit hackish but it's about the only one way of sending
2071  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2072  * not support the ExtINT mode, unfortunately.  We need to send these
2073  * cycles as some i82489DX-based boards have glue logic that keeps the
2074  * 8259A interrupt line asserted until INTA.  --macro
2075  */
unlock_ExtINT_logic(void)2076 static inline void __init unlock_ExtINT_logic(void)
2077 {
2078 	int apic, pin, i;
2079 	struct IO_APIC_route_entry entry0, entry1;
2080 	unsigned char save_control, save_freq_select;
2081 	u32 apic_id;
2082 
2083 	pin  = find_isa_irq_pin(8, mp_INT);
2084 	if (pin == -1) {
2085 		WARN_ON_ONCE(1);
2086 		return;
2087 	}
2088 	apic = find_isa_irq_apic(8, mp_INT);
2089 	if (apic == -1) {
2090 		WARN_ON_ONCE(1);
2091 		return;
2092 	}
2093 
2094 	entry0 = ioapic_read_entry(apic, pin);
2095 	clear_IO_APIC_pin(apic, pin);
2096 
2097 	apic_id = hard_smp_processor_id();
2098 	memset(&entry1, 0, sizeof(entry1));
2099 
2100 	entry1.dest_mode_logical	= true;
2101 	entry1.masked			= false;
2102 	entry1.destid_0_7		= apic_id & 0xFF;
2103 	entry1.virt_destid_8_14		= apic_id >> 8;
2104 	entry1.delivery_mode		= APIC_DELIVERY_MODE_EXTINT;
2105 	entry1.active_low		= entry0.active_low;
2106 	entry1.is_level			= false;
2107 	entry1.vector = 0;
2108 
2109 	ioapic_write_entry(apic, pin, entry1);
2110 
2111 	save_control = CMOS_READ(RTC_CONTROL);
2112 	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2113 	CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2114 		   RTC_FREQ_SELECT);
2115 	CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2116 
2117 	i = 100;
2118 	while (i-- > 0) {
2119 		mdelay(10);
2120 		if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2121 			i -= 10;
2122 	}
2123 
2124 	CMOS_WRITE(save_control, RTC_CONTROL);
2125 	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2126 	clear_IO_APIC_pin(apic, pin);
2127 
2128 	ioapic_write_entry(apic, pin, entry0);
2129 }
2130 
2131 static int disable_timer_pin_1 __initdata;
2132 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
disable_timer_pin_setup(char * arg)2133 static int __init disable_timer_pin_setup(char *arg)
2134 {
2135 	disable_timer_pin_1 = 1;
2136 	return 0;
2137 }
2138 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2139 
mp_alloc_timer_irq(int ioapic,int pin)2140 static int mp_alloc_timer_irq(int ioapic, int pin)
2141 {
2142 	int irq = -1;
2143 	struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2144 
2145 	if (domain) {
2146 		struct irq_alloc_info info;
2147 
2148 		ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2149 		info.devid = mpc_ioapic_id(ioapic);
2150 		info.ioapic.pin = pin;
2151 		mutex_lock(&ioapic_mutex);
2152 		irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2153 		mutex_unlock(&ioapic_mutex);
2154 	}
2155 
2156 	return irq;
2157 }
2158 
2159 /*
2160  * This code may look a bit paranoid, but it's supposed to cooperate with
2161  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2162  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2163  * fanatically on his truly buggy board.
2164  *
2165  * FIXME: really need to revamp this for all platforms.
2166  */
check_timer(void)2167 static inline void __init check_timer(void)
2168 {
2169 	struct irq_data *irq_data = irq_get_irq_data(0);
2170 	struct mp_chip_data *data = irq_data->chip_data;
2171 	struct irq_cfg *cfg = irqd_cfg(irq_data);
2172 	int node = cpu_to_node(0);
2173 	int apic1, pin1, apic2, pin2;
2174 	int no_pin1 = 0;
2175 
2176 	if (!global_clock_event)
2177 		return;
2178 
2179 	local_irq_disable();
2180 
2181 	/*
2182 	 * get/set the timer IRQ vector:
2183 	 */
2184 	legacy_pic->mask(0);
2185 
2186 	/*
2187 	 * As IRQ0 is to be enabled in the 8259A, the virtual
2188 	 * wire has to be disabled in the local APIC.  Also
2189 	 * timer interrupts need to be acknowledged manually in
2190 	 * the 8259A for the i82489DX when using the NMI
2191 	 * watchdog as that APIC treats NMIs as level-triggered.
2192 	 * The AEOI mode will finish them in the 8259A
2193 	 * automatically.
2194 	 */
2195 	apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2196 	legacy_pic->init(1);
2197 
2198 	pin1  = find_isa_irq_pin(0, mp_INT);
2199 	apic1 = find_isa_irq_apic(0, mp_INT);
2200 	pin2  = ioapic_i8259.pin;
2201 	apic2 = ioapic_i8259.apic;
2202 
2203 	apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2204 		    "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2205 		    cfg->vector, apic1, pin1, apic2, pin2);
2206 
2207 	/*
2208 	 * Some BIOS writers are clueless and report the ExtINTA
2209 	 * I/O APIC input from the cascaded 8259A as the timer
2210 	 * interrupt input.  So just in case, if only one pin
2211 	 * was found above, try it both directly and through the
2212 	 * 8259A.
2213 	 */
2214 	if (pin1 == -1) {
2215 		panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2216 		pin1 = pin2;
2217 		apic1 = apic2;
2218 		no_pin1 = 1;
2219 	} else if (pin2 == -1) {
2220 		pin2 = pin1;
2221 		apic2 = apic1;
2222 	}
2223 
2224 	if (pin1 != -1) {
2225 		/* Ok, does IRQ0 through the IOAPIC work? */
2226 		if (no_pin1) {
2227 			mp_alloc_timer_irq(apic1, pin1);
2228 		} else {
2229 			/*
2230 			 * for edge trigger, it's already unmasked,
2231 			 * so only need to unmask if it is level-trigger
2232 			 * do we really have level trigger timer?
2233 			 */
2234 			int idx = find_irq_entry(apic1, pin1, mp_INT);
2235 
2236 			if (idx != -1 && irq_is_level(idx))
2237 				unmask_ioapic_irq(irq_get_irq_data(0));
2238 		}
2239 		irq_domain_deactivate_irq(irq_data);
2240 		irq_domain_activate_irq(irq_data, false);
2241 		if (timer_irq_works()) {
2242 			if (disable_timer_pin_1 > 0)
2243 				clear_IO_APIC_pin(0, pin1);
2244 			goto out;
2245 		}
2246 		panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2247 		clear_IO_APIC_pin(apic1, pin1);
2248 		if (!no_pin1)
2249 			apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2250 				    "8254 timer not connected to IO-APIC\n");
2251 
2252 		apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2253 			    "(IRQ0) through the 8259A ...\n");
2254 		apic_printk(APIC_QUIET, KERN_INFO
2255 			    "..... (found apic %d pin %d) ...\n", apic2, pin2);
2256 		/*
2257 		 * legacy devices should be connected to IO APIC #0
2258 		 */
2259 		replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2260 		irq_domain_deactivate_irq(irq_data);
2261 		irq_domain_activate_irq(irq_data, false);
2262 		legacy_pic->unmask(0);
2263 		if (timer_irq_works()) {
2264 			apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2265 			goto out;
2266 		}
2267 		/*
2268 		 * Cleanup, just in case ...
2269 		 */
2270 		legacy_pic->mask(0);
2271 		clear_IO_APIC_pin(apic2, pin2);
2272 		apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2273 	}
2274 
2275 	apic_printk(APIC_QUIET, KERN_INFO
2276 		    "...trying to set up timer as Virtual Wire IRQ...\n");
2277 
2278 	lapic_register_intr(0);
2279 	apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);	/* Fixed mode */
2280 	legacy_pic->unmask(0);
2281 
2282 	if (timer_irq_works()) {
2283 		apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2284 		goto out;
2285 	}
2286 	legacy_pic->mask(0);
2287 	apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2288 	apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2289 
2290 	apic_printk(APIC_QUIET, KERN_INFO
2291 		    "...trying to set up timer as ExtINT IRQ...\n");
2292 
2293 	legacy_pic->init(0);
2294 	legacy_pic->make_irq(0);
2295 	apic_write(APIC_LVT0, APIC_DM_EXTINT);
2296 	legacy_pic->unmask(0);
2297 
2298 	unlock_ExtINT_logic();
2299 
2300 	if (timer_irq_works()) {
2301 		apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2302 		goto out;
2303 	}
2304 	apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2305 	if (apic_is_x2apic_enabled())
2306 		apic_printk(APIC_QUIET, KERN_INFO
2307 			    "Perhaps problem with the pre-enabled x2apic mode\n"
2308 			    "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2309 	panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2310 		"report.  Then try booting with the 'noapic' option.\n");
2311 out:
2312 	local_irq_enable();
2313 }
2314 
2315 /*
2316  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2317  * to devices.  However there may be an I/O APIC pin available for
2318  * this interrupt regardless.  The pin may be left unconnected, but
2319  * typically it will be reused as an ExtINT cascade interrupt for
2320  * the master 8259A.  In the MPS case such a pin will normally be
2321  * reported as an ExtINT interrupt in the MP table.  With ACPI
2322  * there is no provision for ExtINT interrupts, and in the absence
2323  * of an override it would be treated as an ordinary ISA I/O APIC
2324  * interrupt, that is edge-triggered and unmasked by default.  We
2325  * used to do this, but it caused problems on some systems because
2326  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2327  * the same ExtINT cascade interrupt to drive the local APIC of the
2328  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
2329  * the I/O APIC in all cases now.  No actual device should request
2330  * it anyway.  --macro
2331  */
2332 #define PIC_IRQS	(1UL << PIC_CASCADE_IR)
2333 
mp_irqdomain_create(int ioapic)2334 static int mp_irqdomain_create(int ioapic)
2335 {
2336 	struct irq_domain *parent;
2337 	int hwirqs = mp_ioapic_pin_count(ioapic);
2338 	struct ioapic *ip = &ioapics[ioapic];
2339 	struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2340 	struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2341 	struct fwnode_handle *fn;
2342 	struct irq_fwspec fwspec;
2343 
2344 	if (cfg->type == IOAPIC_DOMAIN_INVALID)
2345 		return 0;
2346 
2347 	/* Handle device tree enumerated APICs proper */
2348 	if (cfg->dev) {
2349 		fn = of_node_to_fwnode(cfg->dev);
2350 	} else {
2351 		fn = irq_domain_alloc_named_id_fwnode("IO-APIC", mpc_ioapic_id(ioapic));
2352 		if (!fn)
2353 			return -ENOMEM;
2354 	}
2355 
2356 	fwspec.fwnode = fn;
2357 	fwspec.param_count = 1;
2358 	fwspec.param[0] = mpc_ioapic_id(ioapic);
2359 
2360 	parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_ANY);
2361 	if (!parent) {
2362 		if (!cfg->dev)
2363 			irq_domain_free_fwnode(fn);
2364 		return -ENODEV;
2365 	}
2366 
2367 	ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops,
2368 						 (void *)(long)ioapic);
2369 
2370 	if (!ip->irqdomain) {
2371 		/* Release fw handle if it was allocated above */
2372 		if (!cfg->dev)
2373 			irq_domain_free_fwnode(fn);
2374 		return -ENOMEM;
2375 	}
2376 
2377 	ip->irqdomain->parent = parent;
2378 
2379 	if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2380 	    cfg->type == IOAPIC_DOMAIN_STRICT)
2381 		ioapic_dynirq_base = max(ioapic_dynirq_base,
2382 					 gsi_cfg->gsi_end + 1);
2383 
2384 	return 0;
2385 }
2386 
ioapic_destroy_irqdomain(int idx)2387 static void ioapic_destroy_irqdomain(int idx)
2388 {
2389 	struct ioapic_domain_cfg *cfg = &ioapics[idx].irqdomain_cfg;
2390 	struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode;
2391 
2392 	if (ioapics[idx].irqdomain) {
2393 		irq_domain_remove(ioapics[idx].irqdomain);
2394 		if (!cfg->dev)
2395 			irq_domain_free_fwnode(fn);
2396 		ioapics[idx].irqdomain = NULL;
2397 	}
2398 }
2399 
setup_IO_APIC(void)2400 void __init setup_IO_APIC(void)
2401 {
2402 	int ioapic;
2403 
2404 	if (skip_ioapic_setup || !nr_ioapics)
2405 		return;
2406 
2407 	io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2408 
2409 	apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2410 	for_each_ioapic(ioapic)
2411 		BUG_ON(mp_irqdomain_create(ioapic));
2412 
2413 	/*
2414          * Set up IO-APIC IRQ routing.
2415          */
2416 	x86_init.mpparse.setup_ioapic_ids();
2417 
2418 	sync_Arb_IDs();
2419 	setup_IO_APIC_irqs();
2420 	init_IO_APIC_traps();
2421 	if (nr_legacy_irqs())
2422 		check_timer();
2423 
2424 	ioapic_initialized = 1;
2425 }
2426 
resume_ioapic_id(int ioapic_idx)2427 static void resume_ioapic_id(int ioapic_idx)
2428 {
2429 	unsigned long flags;
2430 	union IO_APIC_reg_00 reg_00;
2431 
2432 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2433 	reg_00.raw = io_apic_read(ioapic_idx, 0);
2434 	if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2435 		reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2436 		io_apic_write(ioapic_idx, 0, reg_00.raw);
2437 	}
2438 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2439 }
2440 
ioapic_resume(void)2441 static void ioapic_resume(void)
2442 {
2443 	int ioapic_idx;
2444 
2445 	for_each_ioapic_reverse(ioapic_idx)
2446 		resume_ioapic_id(ioapic_idx);
2447 
2448 	restore_ioapic_entries();
2449 }
2450 
2451 static struct syscore_ops ioapic_syscore_ops = {
2452 	.suspend = save_ioapic_entries,
2453 	.resume = ioapic_resume,
2454 };
2455 
ioapic_init_ops(void)2456 static int __init ioapic_init_ops(void)
2457 {
2458 	register_syscore_ops(&ioapic_syscore_ops);
2459 
2460 	return 0;
2461 }
2462 
2463 device_initcall(ioapic_init_ops);
2464 
io_apic_get_redir_entries(int ioapic)2465 static int io_apic_get_redir_entries(int ioapic)
2466 {
2467 	union IO_APIC_reg_01	reg_01;
2468 	unsigned long flags;
2469 
2470 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2471 	reg_01.raw = io_apic_read(ioapic, 1);
2472 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2473 
2474 	/* The register returns the maximum index redir index
2475 	 * supported, which is one less than the total number of redir
2476 	 * entries.
2477 	 */
2478 	return reg_01.bits.entries + 1;
2479 }
2480 
arch_dynirq_lower_bound(unsigned int from)2481 unsigned int arch_dynirq_lower_bound(unsigned int from)
2482 {
2483 	/*
2484 	 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2485 	 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2486 	 */
2487 	if (!ioapic_initialized)
2488 		return gsi_top;
2489 	/*
2490 	 * For DT enabled machines ioapic_dynirq_base is irrelevant and not
2491 	 * updated. So simply return @from if ioapic_dynirq_base == 0.
2492 	 */
2493 	return ioapic_dynirq_base ? : from;
2494 }
2495 
2496 #ifdef CONFIG_X86_32
io_apic_get_unique_id(int ioapic,int apic_id)2497 static int io_apic_get_unique_id(int ioapic, int apic_id)
2498 {
2499 	union IO_APIC_reg_00 reg_00;
2500 	static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2501 	physid_mask_t tmp;
2502 	unsigned long flags;
2503 	int i = 0;
2504 
2505 	/*
2506 	 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2507 	 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2508 	 * supports up to 16 on one shared APIC bus.
2509 	 *
2510 	 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2511 	 *      advantage of new APIC bus architecture.
2512 	 */
2513 
2514 	if (physids_empty(apic_id_map))
2515 		apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2516 
2517 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2518 	reg_00.raw = io_apic_read(ioapic, 0);
2519 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2520 
2521 	if (apic_id >= get_physical_broadcast()) {
2522 		printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2523 			"%d\n", ioapic, apic_id, reg_00.bits.ID);
2524 		apic_id = reg_00.bits.ID;
2525 	}
2526 
2527 	/*
2528 	 * Every APIC in a system must have a unique ID or we get lots of nice
2529 	 * 'stuck on smp_invalidate_needed IPI wait' messages.
2530 	 */
2531 	if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2532 
2533 		for (i = 0; i < get_physical_broadcast(); i++) {
2534 			if (!apic->check_apicid_used(&apic_id_map, i))
2535 				break;
2536 		}
2537 
2538 		if (i == get_physical_broadcast())
2539 			panic("Max apic_id exceeded!\n");
2540 
2541 		printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2542 			"trying %d\n", ioapic, apic_id, i);
2543 
2544 		apic_id = i;
2545 	}
2546 
2547 	apic->apicid_to_cpu_present(apic_id, &tmp);
2548 	physids_or(apic_id_map, apic_id_map, tmp);
2549 
2550 	if (reg_00.bits.ID != apic_id) {
2551 		reg_00.bits.ID = apic_id;
2552 
2553 		raw_spin_lock_irqsave(&ioapic_lock, flags);
2554 		io_apic_write(ioapic, 0, reg_00.raw);
2555 		reg_00.raw = io_apic_read(ioapic, 0);
2556 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2557 
2558 		/* Sanity check */
2559 		if (reg_00.bits.ID != apic_id) {
2560 			pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2561 			       ioapic);
2562 			return -1;
2563 		}
2564 	}
2565 
2566 	apic_printk(APIC_VERBOSE, KERN_INFO
2567 			"IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2568 
2569 	return apic_id;
2570 }
2571 
io_apic_unique_id(int idx,u8 id)2572 static u8 io_apic_unique_id(int idx, u8 id)
2573 {
2574 	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2575 	    !APIC_XAPIC(boot_cpu_apic_version))
2576 		return io_apic_get_unique_id(idx, id);
2577 	else
2578 		return id;
2579 }
2580 #else
io_apic_unique_id(int idx,u8 id)2581 static u8 io_apic_unique_id(int idx, u8 id)
2582 {
2583 	union IO_APIC_reg_00 reg_00;
2584 	DECLARE_BITMAP(used, 256);
2585 	unsigned long flags;
2586 	u8 new_id;
2587 	int i;
2588 
2589 	bitmap_zero(used, 256);
2590 	for_each_ioapic(i)
2591 		__set_bit(mpc_ioapic_id(i), used);
2592 
2593 	/* Hand out the requested id if available */
2594 	if (!test_bit(id, used))
2595 		return id;
2596 
2597 	/*
2598 	 * Read the current id from the ioapic and keep it if
2599 	 * available.
2600 	 */
2601 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2602 	reg_00.raw = io_apic_read(idx, 0);
2603 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2604 	new_id = reg_00.bits.ID;
2605 	if (!test_bit(new_id, used)) {
2606 		apic_printk(APIC_VERBOSE, KERN_INFO
2607 			"IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2608 			 idx, new_id, id);
2609 		return new_id;
2610 	}
2611 
2612 	/*
2613 	 * Get the next free id and write it to the ioapic.
2614 	 */
2615 	new_id = find_first_zero_bit(used, 256);
2616 	reg_00.bits.ID = new_id;
2617 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2618 	io_apic_write(idx, 0, reg_00.raw);
2619 	reg_00.raw = io_apic_read(idx, 0);
2620 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2621 	/* Sanity check */
2622 	BUG_ON(reg_00.bits.ID != new_id);
2623 
2624 	return new_id;
2625 }
2626 #endif
2627 
io_apic_get_version(int ioapic)2628 static int io_apic_get_version(int ioapic)
2629 {
2630 	union IO_APIC_reg_01	reg_01;
2631 	unsigned long flags;
2632 
2633 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2634 	reg_01.raw = io_apic_read(ioapic, 1);
2635 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2636 
2637 	return reg_01.bits.version;
2638 }
2639 
2640 /*
2641  * This function updates target affinity of IOAPIC interrupts to include
2642  * the CPUs which came online during SMP bringup.
2643  */
2644 #define IOAPIC_RESOURCE_NAME_SIZE 11
2645 
2646 static struct resource *ioapic_resources;
2647 
ioapic_setup_resources(void)2648 static struct resource * __init ioapic_setup_resources(void)
2649 {
2650 	unsigned long n;
2651 	struct resource *res;
2652 	char *mem;
2653 	int i;
2654 
2655 	if (nr_ioapics == 0)
2656 		return NULL;
2657 
2658 	n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2659 	n *= nr_ioapics;
2660 
2661 	mem = memblock_alloc(n, SMP_CACHE_BYTES);
2662 	if (!mem)
2663 		panic("%s: Failed to allocate %lu bytes\n", __func__, n);
2664 	res = (void *)mem;
2665 
2666 	mem += sizeof(struct resource) * nr_ioapics;
2667 
2668 	for_each_ioapic(i) {
2669 		res[i].name = mem;
2670 		res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2671 		snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2672 		mem += IOAPIC_RESOURCE_NAME_SIZE;
2673 		ioapics[i].iomem_res = &res[i];
2674 	}
2675 
2676 	ioapic_resources = res;
2677 
2678 	return res;
2679 }
2680 
io_apic_set_fixmap(enum fixed_addresses idx,phys_addr_t phys)2681 static void io_apic_set_fixmap(enum fixed_addresses idx, phys_addr_t phys)
2682 {
2683 	pgprot_t flags = FIXMAP_PAGE_NOCACHE;
2684 
2685 	/*
2686 	 * Ensure fixmaps for IOAPIC MMIO respect memory encryption pgprot
2687 	 * bits, just like normal ioremap():
2688 	 */
2689 	flags = pgprot_decrypted(flags);
2690 
2691 	__set_fixmap(idx, phys, flags);
2692 }
2693 
io_apic_init_mappings(void)2694 void __init io_apic_init_mappings(void)
2695 {
2696 	unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2697 	struct resource *ioapic_res;
2698 	int i;
2699 
2700 	ioapic_res = ioapic_setup_resources();
2701 	for_each_ioapic(i) {
2702 		if (smp_found_config) {
2703 			ioapic_phys = mpc_ioapic_addr(i);
2704 #ifdef CONFIG_X86_32
2705 			if (!ioapic_phys) {
2706 				printk(KERN_ERR
2707 				       "WARNING: bogus zero IO-APIC "
2708 				       "address found in MPTABLE, "
2709 				       "disabling IO/APIC support!\n");
2710 				smp_found_config = 0;
2711 				skip_ioapic_setup = 1;
2712 				goto fake_ioapic_page;
2713 			}
2714 #endif
2715 		} else {
2716 #ifdef CONFIG_X86_32
2717 fake_ioapic_page:
2718 #endif
2719 			ioapic_phys = (unsigned long)memblock_alloc(PAGE_SIZE,
2720 								    PAGE_SIZE);
2721 			if (!ioapic_phys)
2722 				panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
2723 				      __func__, PAGE_SIZE, PAGE_SIZE);
2724 			ioapic_phys = __pa(ioapic_phys);
2725 		}
2726 		io_apic_set_fixmap(idx, ioapic_phys);
2727 		apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2728 			__fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2729 			ioapic_phys);
2730 		idx++;
2731 
2732 		ioapic_res->start = ioapic_phys;
2733 		ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2734 		ioapic_res++;
2735 	}
2736 }
2737 
ioapic_insert_resources(void)2738 void __init ioapic_insert_resources(void)
2739 {
2740 	int i;
2741 	struct resource *r = ioapic_resources;
2742 
2743 	if (!r) {
2744 		if (nr_ioapics > 0)
2745 			printk(KERN_ERR
2746 				"IO APIC resources couldn't be allocated.\n");
2747 		return;
2748 	}
2749 
2750 	for_each_ioapic(i) {
2751 		insert_resource(&iomem_resource, r);
2752 		r++;
2753 	}
2754 }
2755 
mp_find_ioapic(u32 gsi)2756 int mp_find_ioapic(u32 gsi)
2757 {
2758 	int i;
2759 
2760 	if (nr_ioapics == 0)
2761 		return -1;
2762 
2763 	/* Find the IOAPIC that manages this GSI. */
2764 	for_each_ioapic(i) {
2765 		struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2766 		if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2767 			return i;
2768 	}
2769 
2770 	printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2771 	return -1;
2772 }
2773 
mp_find_ioapic_pin(int ioapic,u32 gsi)2774 int mp_find_ioapic_pin(int ioapic, u32 gsi)
2775 {
2776 	struct mp_ioapic_gsi *gsi_cfg;
2777 
2778 	if (WARN_ON(ioapic < 0))
2779 		return -1;
2780 
2781 	gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2782 	if (WARN_ON(gsi > gsi_cfg->gsi_end))
2783 		return -1;
2784 
2785 	return gsi - gsi_cfg->gsi_base;
2786 }
2787 
bad_ioapic_register(int idx)2788 static int bad_ioapic_register(int idx)
2789 {
2790 	union IO_APIC_reg_00 reg_00;
2791 	union IO_APIC_reg_01 reg_01;
2792 	union IO_APIC_reg_02 reg_02;
2793 
2794 	reg_00.raw = io_apic_read(idx, 0);
2795 	reg_01.raw = io_apic_read(idx, 1);
2796 	reg_02.raw = io_apic_read(idx, 2);
2797 
2798 	if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2799 		pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2800 			mpc_ioapic_addr(idx));
2801 		return 1;
2802 	}
2803 
2804 	return 0;
2805 }
2806 
find_free_ioapic_entry(void)2807 static int find_free_ioapic_entry(void)
2808 {
2809 	int idx;
2810 
2811 	for (idx = 0; idx < MAX_IO_APICS; idx++)
2812 		if (ioapics[idx].nr_registers == 0)
2813 			return idx;
2814 
2815 	return MAX_IO_APICS;
2816 }
2817 
2818 /**
2819  * mp_register_ioapic - Register an IOAPIC device
2820  * @id:		hardware IOAPIC ID
2821  * @address:	physical address of IOAPIC register area
2822  * @gsi_base:	base of GSI associated with the IOAPIC
2823  * @cfg:	configuration information for the IOAPIC
2824  */
mp_register_ioapic(int id,u32 address,u32 gsi_base,struct ioapic_domain_cfg * cfg)2825 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2826 		       struct ioapic_domain_cfg *cfg)
2827 {
2828 	bool hotplug = !!ioapic_initialized;
2829 	struct mp_ioapic_gsi *gsi_cfg;
2830 	int idx, ioapic, entries;
2831 	u32 gsi_end;
2832 
2833 	if (!address) {
2834 		pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2835 		return -EINVAL;
2836 	}
2837 	for_each_ioapic(ioapic)
2838 		if (ioapics[ioapic].mp_config.apicaddr == address) {
2839 			pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2840 				address, ioapic);
2841 			return -EEXIST;
2842 		}
2843 
2844 	idx = find_free_ioapic_entry();
2845 	if (idx >= MAX_IO_APICS) {
2846 		pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2847 			MAX_IO_APICS, idx);
2848 		return -ENOSPC;
2849 	}
2850 
2851 	ioapics[idx].mp_config.type = MP_IOAPIC;
2852 	ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2853 	ioapics[idx].mp_config.apicaddr = address;
2854 
2855 	io_apic_set_fixmap(FIX_IO_APIC_BASE_0 + idx, address);
2856 	if (bad_ioapic_register(idx)) {
2857 		clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2858 		return -ENODEV;
2859 	}
2860 
2861 	ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2862 	ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2863 
2864 	/*
2865 	 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2866 	 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2867 	 */
2868 	entries = io_apic_get_redir_entries(idx);
2869 	gsi_end = gsi_base + entries - 1;
2870 	for_each_ioapic(ioapic) {
2871 		gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2872 		if ((gsi_base >= gsi_cfg->gsi_base &&
2873 		     gsi_base <= gsi_cfg->gsi_end) ||
2874 		    (gsi_end >= gsi_cfg->gsi_base &&
2875 		     gsi_end <= gsi_cfg->gsi_end)) {
2876 			pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2877 				gsi_base, gsi_end,
2878 				gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2879 			clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2880 			return -ENOSPC;
2881 		}
2882 	}
2883 	gsi_cfg = mp_ioapic_gsi_routing(idx);
2884 	gsi_cfg->gsi_base = gsi_base;
2885 	gsi_cfg->gsi_end = gsi_end;
2886 
2887 	ioapics[idx].irqdomain = NULL;
2888 	ioapics[idx].irqdomain_cfg = *cfg;
2889 
2890 	/*
2891 	 * If mp_register_ioapic() is called during early boot stage when
2892 	 * walking ACPI/DT tables, it's too early to create irqdomain,
2893 	 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2894 	 */
2895 	if (hotplug) {
2896 		if (mp_irqdomain_create(idx)) {
2897 			clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2898 			return -ENOMEM;
2899 		}
2900 		alloc_ioapic_saved_registers(idx);
2901 	}
2902 
2903 	if (gsi_cfg->gsi_end >= gsi_top)
2904 		gsi_top = gsi_cfg->gsi_end + 1;
2905 	if (nr_ioapics <= idx)
2906 		nr_ioapics = idx + 1;
2907 
2908 	/* Set nr_registers to mark entry present */
2909 	ioapics[idx].nr_registers = entries;
2910 
2911 	pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2912 		idx, mpc_ioapic_id(idx),
2913 		mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2914 		gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2915 
2916 	return 0;
2917 }
2918 
mp_unregister_ioapic(u32 gsi_base)2919 int mp_unregister_ioapic(u32 gsi_base)
2920 {
2921 	int ioapic, pin;
2922 	int found = 0;
2923 
2924 	for_each_ioapic(ioapic)
2925 		if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2926 			found = 1;
2927 			break;
2928 		}
2929 	if (!found) {
2930 		pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2931 		return -ENODEV;
2932 	}
2933 
2934 	for_each_pin(ioapic, pin) {
2935 		u32 gsi = mp_pin_to_gsi(ioapic, pin);
2936 		int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2937 		struct mp_chip_data *data;
2938 
2939 		if (irq >= 0) {
2940 			data = irq_get_chip_data(irq);
2941 			if (data && data->count) {
2942 				pr_warn("pin%d on IOAPIC%d is still in use.\n",
2943 					pin, ioapic);
2944 				return -EBUSY;
2945 			}
2946 		}
2947 	}
2948 
2949 	/* Mark entry not present */
2950 	ioapics[ioapic].nr_registers  = 0;
2951 	ioapic_destroy_irqdomain(ioapic);
2952 	free_ioapic_saved_registers(ioapic);
2953 	if (ioapics[ioapic].iomem_res)
2954 		release_resource(ioapics[ioapic].iomem_res);
2955 	clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2956 	memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2957 
2958 	return 0;
2959 }
2960 
mp_ioapic_registered(u32 gsi_base)2961 int mp_ioapic_registered(u32 gsi_base)
2962 {
2963 	int ioapic;
2964 
2965 	for_each_ioapic(ioapic)
2966 		if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2967 			return 1;
2968 
2969 	return 0;
2970 }
2971 
mp_irqdomain_get_attr(u32 gsi,struct mp_chip_data * data,struct irq_alloc_info * info)2972 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2973 				  struct irq_alloc_info *info)
2974 {
2975 	if (info && info->ioapic.valid) {
2976 		data->is_level = info->ioapic.is_level;
2977 		data->active_low = info->ioapic.active_low;
2978 	} else if (__acpi_get_override_irq(gsi, &data->is_level,
2979 					   &data->active_low) < 0) {
2980 		/* PCI interrupts are always active low level triggered. */
2981 		data->is_level = true;
2982 		data->active_low = true;
2983 	}
2984 }
2985 
2986 /*
2987  * Configure the I/O-APIC specific fields in the routing entry.
2988  *
2989  * This is important to setup the I/O-APIC specific bits (is_level,
2990  * active_low, masked) because the underlying parent domain will only
2991  * provide the routing information and is oblivious of the I/O-APIC
2992  * specific bits.
2993  *
2994  * The entry is just preconfigured at this point and not written into the
2995  * RTE. This happens later during activation which will fill in the actual
2996  * routing information.
2997  */
mp_preconfigure_entry(struct mp_chip_data * data)2998 static void mp_preconfigure_entry(struct mp_chip_data *data)
2999 {
3000 	struct IO_APIC_route_entry *entry = &data->entry;
3001 
3002 	memset(entry, 0, sizeof(*entry));
3003 	entry->is_level		 = data->is_level;
3004 	entry->active_low	 = data->active_low;
3005 	/*
3006 	 * Mask level triggered irqs. Edge triggered irqs are masked
3007 	 * by the irq core code in case they fire.
3008 	 */
3009 	entry->masked		= data->is_level;
3010 }
3011 
mp_irqdomain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)3012 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
3013 		       unsigned int nr_irqs, void *arg)
3014 {
3015 	struct irq_alloc_info *info = arg;
3016 	struct mp_chip_data *data;
3017 	struct irq_data *irq_data;
3018 	int ret, ioapic, pin;
3019 	unsigned long flags;
3020 
3021 	if (!info || nr_irqs > 1)
3022 		return -EINVAL;
3023 	irq_data = irq_domain_get_irq_data(domain, virq);
3024 	if (!irq_data)
3025 		return -EINVAL;
3026 
3027 	ioapic = mp_irqdomain_ioapic_idx(domain);
3028 	pin = info->ioapic.pin;
3029 	if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
3030 		return -EEXIST;
3031 
3032 	data = kzalloc(sizeof(*data), GFP_KERNEL);
3033 	if (!data)
3034 		return -ENOMEM;
3035 
3036 	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
3037 	if (ret < 0) {
3038 		kfree(data);
3039 		return ret;
3040 	}
3041 
3042 	INIT_LIST_HEAD(&data->irq_2_pin);
3043 	irq_data->hwirq = info->ioapic.pin;
3044 	irq_data->chip = (domain->parent == x86_vector_domain) ?
3045 			  &ioapic_chip : &ioapic_ir_chip;
3046 	irq_data->chip_data = data;
3047 	mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
3048 
3049 	add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
3050 
3051 	mp_preconfigure_entry(data);
3052 	mp_register_handler(virq, data->is_level);
3053 
3054 	local_irq_save(flags);
3055 	if (virq < nr_legacy_irqs())
3056 		legacy_pic->mask(virq);
3057 	local_irq_restore(flags);
3058 
3059 	apic_printk(APIC_VERBOSE, KERN_DEBUG
3060 		    "IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i ActiveLow:%i)\n",
3061 		    ioapic, mpc_ioapic_id(ioapic), pin, virq,
3062 		    data->is_level, data->active_low);
3063 	return 0;
3064 }
3065 
mp_irqdomain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)3066 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
3067 		       unsigned int nr_irqs)
3068 {
3069 	struct irq_data *irq_data;
3070 	struct mp_chip_data *data;
3071 
3072 	BUG_ON(nr_irqs != 1);
3073 	irq_data = irq_domain_get_irq_data(domain, virq);
3074 	if (irq_data && irq_data->chip_data) {
3075 		data = irq_data->chip_data;
3076 		__remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
3077 				      (int)irq_data->hwirq);
3078 		WARN_ON(!list_empty(&data->irq_2_pin));
3079 		kfree(irq_data->chip_data);
3080 	}
3081 	irq_domain_free_irqs_top(domain, virq, nr_irqs);
3082 }
3083 
mp_irqdomain_activate(struct irq_domain * domain,struct irq_data * irq_data,bool reserve)3084 int mp_irqdomain_activate(struct irq_domain *domain,
3085 			  struct irq_data *irq_data, bool reserve)
3086 {
3087 	unsigned long flags;
3088 
3089 	raw_spin_lock_irqsave(&ioapic_lock, flags);
3090 	ioapic_configure_entry(irq_data);
3091 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3092 	return 0;
3093 }
3094 
mp_irqdomain_deactivate(struct irq_domain * domain,struct irq_data * irq_data)3095 void mp_irqdomain_deactivate(struct irq_domain *domain,
3096 			     struct irq_data *irq_data)
3097 {
3098 	/* It won't be called for IRQ with multiple IOAPIC pins associated */
3099 	ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3100 			  (int)irq_data->hwirq);
3101 }
3102 
mp_irqdomain_ioapic_idx(struct irq_domain * domain)3103 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3104 {
3105 	return (int)(long)domain->host_data;
3106 }
3107 
3108 const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3109 	.alloc		= mp_irqdomain_alloc,
3110 	.free		= mp_irqdomain_free,
3111 	.activate	= mp_irqdomain_activate,
3112 	.deactivate	= mp_irqdomain_deactivate,
3113 };
3114