1 #include <linux/init.h>
2 #include <linux/suspend.h>
3 #include <linux/io.h>
4 #include <asm/time.h>
5 #include <asm/cacheflush.h>
6 #include <asm/mpc52xx.h>
7
8 /* these are defined in mpc52xx_sleep.S, and only used here */
9 extern void mpc52xx_deep_sleep(void __iomem *sram, void __iomem *sdram_regs,
10 struct mpc52xx_cdm __iomem *, struct mpc52xx_intr __iomem*);
11 extern void mpc52xx_ds_sram(void);
12 extern const long mpc52xx_ds_sram_size;
13 extern void mpc52xx_ds_cached(void);
14 extern const long mpc52xx_ds_cached_size;
15
16 static void __iomem *mbar;
17 static void __iomem *sdram;
18 static struct mpc52xx_cdm __iomem *cdm;
19 static struct mpc52xx_intr __iomem *intr;
20 static struct mpc52xx_gpio_wkup __iomem *gpiow;
21 static void __iomem *sram;
22 static int sram_size;
23
24 struct mpc52xx_suspend mpc52xx_suspend;
25
mpc52xx_pm_valid(suspend_state_t state)26 static int mpc52xx_pm_valid(suspend_state_t state)
27 {
28 switch (state) {
29 case PM_SUSPEND_STANDBY:
30 return 1;
31 default:
32 return 0;
33 }
34 }
35
mpc52xx_set_wakeup_gpio(u8 pin,u8 level)36 int mpc52xx_set_wakeup_gpio(u8 pin, u8 level)
37 {
38 u16 tmp;
39
40 /* enable gpio */
41 out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin));
42 /* set as input */
43 out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin));
44 /* enable deep sleep interrupt */
45 out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin));
46 /* low/high level creates wakeup interrupt */
47 tmp = in_be16(&gpiow->wkup_itype);
48 tmp &= ~(0x3 << (pin * 2));
49 tmp |= (!level + 1) << (pin * 2);
50 out_be16(&gpiow->wkup_itype, tmp);
51 /* master enable */
52 out_8(&gpiow->wkup_maste, 1);
53
54 return 0;
55 }
56
mpc52xx_pm_prepare(void)57 int mpc52xx_pm_prepare(void)
58 {
59 struct device_node *np;
60 const struct of_device_id immr_ids[] = {
61 { .compatible = "fsl,mpc5200-immr", },
62 { .compatible = "fsl,mpc5200b-immr", },
63 { .type = "soc", .compatible = "mpc5200", }, /* lite5200 */
64 { .type = "builtin", .compatible = "mpc5200", }, /* efika */
65 {}
66 };
67 struct resource res;
68
69 /* map the whole register space */
70 np = of_find_matching_node(NULL, immr_ids);
71
72 if (of_address_to_resource(np, 0, &res)) {
73 pr_err("mpc52xx_pm_prepare(): could not get IMMR address\n");
74 of_node_put(np);
75 return -ENOSYS;
76 }
77
78 mbar = ioremap(res.start, 0xc000); /* we should map whole region including SRAM */
79
80 of_node_put(np);
81 if (!mbar) {
82 pr_err("mpc52xx_pm_prepare(): could not map registers\n");
83 return -ENOSYS;
84 }
85 /* these offsets are from mpc5200 users manual */
86 sdram = mbar + 0x100;
87 cdm = mbar + 0x200;
88 intr = mbar + 0x500;
89 gpiow = mbar + 0xc00;
90 sram = mbar + 0x8000; /* Those will be handled by the */
91 sram_size = 0x4000; /* bestcomm driver soon */
92
93 /* call board suspend code, if applicable */
94 if (mpc52xx_suspend.board_suspend_prepare)
95 mpc52xx_suspend.board_suspend_prepare(mbar);
96 else {
97 printk(KERN_ALERT "%s: %i don't know how to wake up the board\n",
98 __func__, __LINE__);
99 goto out_unmap;
100 }
101
102 return 0;
103
104 out_unmap:
105 iounmap(mbar);
106 return -ENOSYS;
107 }
108
109
110 char saved_sram[0x4000];
111
mpc52xx_pm_enter(suspend_state_t state)112 int mpc52xx_pm_enter(suspend_state_t state)
113 {
114 u32 clk_enables;
115 u32 msr, hid0;
116 u32 intr_main_mask;
117 void __iomem * irq_0x500 = (void __iomem *)CONFIG_KERNEL_START + 0x500;
118 unsigned long irq_0x500_stop = (unsigned long)irq_0x500 + mpc52xx_ds_cached_size;
119 char saved_0x500[mpc52xx_ds_cached_size];
120
121 /* disable all interrupts in PIC */
122 intr_main_mask = in_be32(&intr->main_mask);
123 out_be32(&intr->main_mask, intr_main_mask | 0x1ffff);
124
125 /* don't let DEC expire any time soon */
126 mtspr(SPRN_DEC, 0x7fffffff);
127
128 /* save SRAM */
129 memcpy(saved_sram, sram, sram_size);
130
131 /* copy low level suspend code to sram */
132 memcpy(sram, mpc52xx_ds_sram, mpc52xx_ds_sram_size);
133
134 out_8(&cdm->ccs_sleep_enable, 1);
135 out_8(&cdm->osc_sleep_enable, 1);
136 out_8(&cdm->ccs_qreq_test, 1);
137
138 /* disable all but SDRAM and bestcomm (SRAM) clocks */
139 clk_enables = in_be32(&cdm->clk_enables);
140 out_be32(&cdm->clk_enables, clk_enables & 0x00088000);
141
142 /* disable power management */
143 msr = mfmsr();
144 mtmsr(msr & ~MSR_POW);
145
146 /* enable sleep mode, disable others */
147 hid0 = mfspr(SPRN_HID0);
148 mtspr(SPRN_HID0, (hid0 & ~(HID0_DOZE | HID0_NAP | HID0_DPM)) | HID0_SLEEP);
149
150 /* save original, copy our irq handler, flush from dcache and invalidate icache */
151 memcpy(saved_0x500, irq_0x500, mpc52xx_ds_cached_size);
152 memcpy(irq_0x500, mpc52xx_ds_cached, mpc52xx_ds_cached_size);
153 flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop);
154
155 /* call low-level sleep code */
156 mpc52xx_deep_sleep(sram, sdram, cdm, intr);
157
158 /* restore original irq handler */
159 memcpy(irq_0x500, saved_0x500, mpc52xx_ds_cached_size);
160 flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop);
161
162 /* restore old power mode */
163 mtmsr(msr & ~MSR_POW);
164 mtspr(SPRN_HID0, hid0);
165 mtmsr(msr);
166
167 out_be32(&cdm->clk_enables, clk_enables);
168 out_8(&cdm->ccs_sleep_enable, 0);
169 out_8(&cdm->osc_sleep_enable, 0);
170
171 /* restore SRAM */
172 memcpy(sram, saved_sram, sram_size);
173
174 /* reenable interrupts in PIC */
175 out_be32(&intr->main_mask, intr_main_mask);
176
177 return 0;
178 }
179
mpc52xx_pm_finish(void)180 void mpc52xx_pm_finish(void)
181 {
182 /* call board resume code */
183 if (mpc52xx_suspend.board_resume_finish)
184 mpc52xx_suspend.board_resume_finish(mbar);
185
186 iounmap(mbar);
187 }
188
189 static const struct platform_suspend_ops mpc52xx_pm_ops = {
190 .valid = mpc52xx_pm_valid,
191 .prepare = mpc52xx_pm_prepare,
192 .enter = mpc52xx_pm_enter,
193 .finish = mpc52xx_pm_finish,
194 };
195
mpc52xx_pm_init(void)196 int __init mpc52xx_pm_init(void)
197 {
198 suspend_set_ops(&mpc52xx_pm_ops);
199 return 0;
200 }
201