1 /*
2 * linux/arch/arm/mach-mmp/mmp2.c
3 *
4 * code name MMP2
5 *
6 * Copyright (C) 2009 Marvell International Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/platform_device.h>
17
18 #include <asm/hardware/cache-tauros2.h>
19
20 #include <asm/mach/time.h>
21 #include <mach/addr-map.h>
22 #include <mach/regs-apbc.h>
23 #include <mach/regs-apmu.h>
24 #include <mach/cputype.h>
25 #include <mach/irqs.h>
26 #include <mach/dma.h>
27 #include <mach/mfp.h>
28 #include <mach/devices.h>
29 #include <mach/mmp2.h>
30
31 #include "common.h"
32 #include "clock.h"
33
34 #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
35
36 static struct mfp_addr_map mmp2_addr_map[] __initdata = {
37
38 MFP_ADDR_X(GPIO0, GPIO58, 0x54),
39 MFP_ADDR_X(GPIO59, GPIO73, 0x280),
40 MFP_ADDR_X(GPIO74, GPIO101, 0x170),
41
42 MFP_ADDR(GPIO102, 0x0),
43 MFP_ADDR(GPIO103, 0x4),
44 MFP_ADDR(GPIO104, 0x1fc),
45 MFP_ADDR(GPIO105, 0x1f8),
46 MFP_ADDR(GPIO106, 0x1f4),
47 MFP_ADDR(GPIO107, 0x1f0),
48 MFP_ADDR(GPIO108, 0x21c),
49 MFP_ADDR(GPIO109, 0x218),
50 MFP_ADDR(GPIO110, 0x214),
51 MFP_ADDR(GPIO111, 0x200),
52 MFP_ADDR(GPIO112, 0x244),
53 MFP_ADDR(GPIO113, 0x25c),
54 MFP_ADDR(GPIO114, 0x164),
55 MFP_ADDR_X(GPIO115, GPIO122, 0x260),
56
57 MFP_ADDR(GPIO123, 0x148),
58 MFP_ADDR_X(GPIO124, GPIO141, 0xc),
59
60 MFP_ADDR(GPIO142, 0x8),
61 MFP_ADDR_X(GPIO143, GPIO151, 0x220),
62 MFP_ADDR_X(GPIO152, GPIO153, 0x248),
63 MFP_ADDR_X(GPIO154, GPIO155, 0x254),
64 MFP_ADDR_X(GPIO156, GPIO159, 0x14c),
65
66 MFP_ADDR(GPIO160, 0x250),
67 MFP_ADDR(GPIO161, 0x210),
68 MFP_ADDR(GPIO162, 0x20c),
69 MFP_ADDR(GPIO163, 0x208),
70 MFP_ADDR(GPIO164, 0x204),
71 MFP_ADDR(GPIO165, 0x1ec),
72 MFP_ADDR(GPIO166, 0x1e8),
73 MFP_ADDR(GPIO167, 0x1e4),
74 MFP_ADDR(GPIO168, 0x1e0),
75
76 MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140),
77 MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc),
78
79 MFP_ADDR(PMIC_INT, 0x2c4),
80 MFP_ADDR(CLK_REQ, 0x160),
81
82 MFP_ADDR_END,
83 };
84
mmp2_clear_pmic_int(void)85 void mmp2_clear_pmic_int(void)
86 {
87 void __iomem *mfpr_pmic;
88 unsigned long data;
89
90 mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4;
91 data = __raw_readl(mfpr_pmic);
92 __raw_writel(data | (1 << 6), mfpr_pmic);
93 __raw_writel(data, mfpr_pmic);
94 }
95
mmp2_init_irq(void)96 void __init mmp2_init_irq(void)
97 {
98 mmp2_init_icu();
99 }
100
sdhc_clk_enable(struct clk * clk)101 static void sdhc_clk_enable(struct clk *clk)
102 {
103 uint32_t clk_rst;
104
105 clk_rst = __raw_readl(clk->clk_rst);
106 clk_rst |= clk->enable_val;
107 __raw_writel(clk_rst, clk->clk_rst);
108 }
109
sdhc_clk_disable(struct clk * clk)110 static void sdhc_clk_disable(struct clk *clk)
111 {
112 uint32_t clk_rst;
113
114 clk_rst = __raw_readl(clk->clk_rst);
115 clk_rst &= ~clk->enable_val;
116 __raw_writel(clk_rst, clk->clk_rst);
117 }
118
119 struct clkops sdhc_clk_ops = {
120 .enable = sdhc_clk_enable,
121 .disable = sdhc_clk_disable,
122 };
123
124 /* APB peripheral clocks */
125 static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
126 static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
127 static APBC_CLK(uart3, MMP2_UART3, 1, 26000000);
128 static APBC_CLK(uart4, MMP2_UART4, 1, 26000000);
129 static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000);
130 static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000);
131 static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
132 static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
133 static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
134 static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
135 static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000);
136
137 static APMU_CLK(nand, NAND, 0xbf, 100000000);
138 static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
139 static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
140 static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
141 static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
142
143 static struct clk_lookup mmp2_clkregs[] = {
144 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
145 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
146 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
147 INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
148 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
149 INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
150 INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
151 INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
152 INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
153 INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
154 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
155 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
156 INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
157 INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
158 INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
159 INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
160 };
161
mmp2_init(void)162 static int __init mmp2_init(void)
163 {
164 if (cpu_is_mmp2()) {
165 #ifdef CONFIG_CACHE_TAUROS2
166 tauros2_init();
167 #endif
168 mfp_init_base(MFPR_VIRT_BASE);
169 mfp_init_addr(mmp2_addr_map);
170 pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16);
171 clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
172 }
173
174 return 0;
175 }
176 postcore_initcall(mmp2_init);
177
mmp2_timer_init(void)178 static void __init mmp2_timer_init(void)
179 {
180 unsigned long clk_rst;
181
182 __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS);
183
184 /*
185 * enable bus/functional clock, enable 6.5MHz (divider 4),
186 * release reset
187 */
188 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
189 __raw_writel(clk_rst, APBC_MMP2_TIMERS);
190
191 timer_init(IRQ_MMP2_TIMER1);
192 }
193
194 struct sys_timer mmp2_timer = {
195 .init = mmp2_timer_init,
196 };
197
198 /* on-chip devices */
199 MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5);
200 MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21);
201 MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23);
202 MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19);
203 MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70);
204 MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70);
205 MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70);
206 MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
207 MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
208 MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
209 MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
210 MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120);
211 MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120);
212 MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120);
213 MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120);
214 MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000);
215 /* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */
216 MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000);
217
218 struct resource mmp2_resource_gpio[] = {
219 {
220 .start = 0xd4019000,
221 .end = 0xd4019fff,
222 .flags = IORESOURCE_MEM,
223 }, {
224 .start = IRQ_MMP2_GPIO,
225 .end = IRQ_MMP2_GPIO,
226 .name = "gpio_mux",
227 .flags = IORESOURCE_IRQ,
228 },
229 };
230
231 struct platform_device mmp2_device_gpio = {
232 .name = "pxa-gpio",
233 .id = -1,
234 .num_resources = ARRAY_SIZE(mmp2_resource_gpio),
235 .resource = mmp2_resource_gpio,
236 };
237