1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2018 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_NIC2_QM1_REGS_H_
14 #define ASIC_REG_NIC2_QM1_REGS_H_
15 
16 /*
17  *****************************************
18  *   NIC2_QM1 (Prototype: QMAN)
19  *****************************************
20  */
21 
22 #define mmNIC2_QM1_GLBL_CFG0                                         0xD62000
23 
24 #define mmNIC2_QM1_GLBL_CFG1                                         0xD62004
25 
26 #define mmNIC2_QM1_GLBL_PROT                                         0xD62008
27 
28 #define mmNIC2_QM1_GLBL_ERR_CFG                                      0xD6200C
29 
30 #define mmNIC2_QM1_GLBL_SECURE_PROPS_0                               0xD62010
31 
32 #define mmNIC2_QM1_GLBL_SECURE_PROPS_1                               0xD62014
33 
34 #define mmNIC2_QM1_GLBL_SECURE_PROPS_2                               0xD62018
35 
36 #define mmNIC2_QM1_GLBL_SECURE_PROPS_3                               0xD6201C
37 
38 #define mmNIC2_QM1_GLBL_SECURE_PROPS_4                               0xD62020
39 
40 #define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_0                           0xD62024
41 
42 #define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_1                           0xD62028
43 
44 #define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_2                           0xD6202C
45 
46 #define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_3                           0xD62030
47 
48 #define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_4                           0xD62034
49 
50 #define mmNIC2_QM1_GLBL_STS0                                         0xD62038
51 
52 #define mmNIC2_QM1_GLBL_STS1_0                                       0xD62040
53 
54 #define mmNIC2_QM1_GLBL_STS1_1                                       0xD62044
55 
56 #define mmNIC2_QM1_GLBL_STS1_2                                       0xD62048
57 
58 #define mmNIC2_QM1_GLBL_STS1_3                                       0xD6204C
59 
60 #define mmNIC2_QM1_GLBL_STS1_4                                       0xD62050
61 
62 #define mmNIC2_QM1_GLBL_MSG_EN_0                                     0xD62054
63 
64 #define mmNIC2_QM1_GLBL_MSG_EN_1                                     0xD62058
65 
66 #define mmNIC2_QM1_GLBL_MSG_EN_2                                     0xD6205C
67 
68 #define mmNIC2_QM1_GLBL_MSG_EN_3                                     0xD62060
69 
70 #define mmNIC2_QM1_GLBL_MSG_EN_4                                     0xD62068
71 
72 #define mmNIC2_QM1_PQ_BASE_LO_0                                      0xD62070
73 
74 #define mmNIC2_QM1_PQ_BASE_LO_1                                      0xD62074
75 
76 #define mmNIC2_QM1_PQ_BASE_LO_2                                      0xD62078
77 
78 #define mmNIC2_QM1_PQ_BASE_LO_3                                      0xD6207C
79 
80 #define mmNIC2_QM1_PQ_BASE_HI_0                                      0xD62080
81 
82 #define mmNIC2_QM1_PQ_BASE_HI_1                                      0xD62084
83 
84 #define mmNIC2_QM1_PQ_BASE_HI_2                                      0xD62088
85 
86 #define mmNIC2_QM1_PQ_BASE_HI_3                                      0xD6208C
87 
88 #define mmNIC2_QM1_PQ_SIZE_0                                         0xD62090
89 
90 #define mmNIC2_QM1_PQ_SIZE_1                                         0xD62094
91 
92 #define mmNIC2_QM1_PQ_SIZE_2                                         0xD62098
93 
94 #define mmNIC2_QM1_PQ_SIZE_3                                         0xD6209C
95 
96 #define mmNIC2_QM1_PQ_PI_0                                           0xD620A0
97 
98 #define mmNIC2_QM1_PQ_PI_1                                           0xD620A4
99 
100 #define mmNIC2_QM1_PQ_PI_2                                           0xD620A8
101 
102 #define mmNIC2_QM1_PQ_PI_3                                           0xD620AC
103 
104 #define mmNIC2_QM1_PQ_CI_0                                           0xD620B0
105 
106 #define mmNIC2_QM1_PQ_CI_1                                           0xD620B4
107 
108 #define mmNIC2_QM1_PQ_CI_2                                           0xD620B8
109 
110 #define mmNIC2_QM1_PQ_CI_3                                           0xD620BC
111 
112 #define mmNIC2_QM1_PQ_CFG0_0                                         0xD620C0
113 
114 #define mmNIC2_QM1_PQ_CFG0_1                                         0xD620C4
115 
116 #define mmNIC2_QM1_PQ_CFG0_2                                         0xD620C8
117 
118 #define mmNIC2_QM1_PQ_CFG0_3                                         0xD620CC
119 
120 #define mmNIC2_QM1_PQ_CFG1_0                                         0xD620D0
121 
122 #define mmNIC2_QM1_PQ_CFG1_1                                         0xD620D4
123 
124 #define mmNIC2_QM1_PQ_CFG1_2                                         0xD620D8
125 
126 #define mmNIC2_QM1_PQ_CFG1_3                                         0xD620DC
127 
128 #define mmNIC2_QM1_PQ_ARUSER_31_11_0                                 0xD620E0
129 
130 #define mmNIC2_QM1_PQ_ARUSER_31_11_1                                 0xD620E4
131 
132 #define mmNIC2_QM1_PQ_ARUSER_31_11_2                                 0xD620E8
133 
134 #define mmNIC2_QM1_PQ_ARUSER_31_11_3                                 0xD620EC
135 
136 #define mmNIC2_QM1_PQ_STS0_0                                         0xD620F0
137 
138 #define mmNIC2_QM1_PQ_STS0_1                                         0xD620F4
139 
140 #define mmNIC2_QM1_PQ_STS0_2                                         0xD620F8
141 
142 #define mmNIC2_QM1_PQ_STS0_3                                         0xD620FC
143 
144 #define mmNIC2_QM1_PQ_STS1_0                                         0xD62100
145 
146 #define mmNIC2_QM1_PQ_STS1_1                                         0xD62104
147 
148 #define mmNIC2_QM1_PQ_STS1_2                                         0xD62108
149 
150 #define mmNIC2_QM1_PQ_STS1_3                                         0xD6210C
151 
152 #define mmNIC2_QM1_CQ_CFG0_0                                         0xD62110
153 
154 #define mmNIC2_QM1_CQ_CFG0_1                                         0xD62114
155 
156 #define mmNIC2_QM1_CQ_CFG0_2                                         0xD62118
157 
158 #define mmNIC2_QM1_CQ_CFG0_3                                         0xD6211C
159 
160 #define mmNIC2_QM1_CQ_CFG0_4                                         0xD62120
161 
162 #define mmNIC2_QM1_CQ_CFG1_0                                         0xD62124
163 
164 #define mmNIC2_QM1_CQ_CFG1_1                                         0xD62128
165 
166 #define mmNIC2_QM1_CQ_CFG1_2                                         0xD6212C
167 
168 #define mmNIC2_QM1_CQ_CFG1_3                                         0xD62130
169 
170 #define mmNIC2_QM1_CQ_CFG1_4                                         0xD62134
171 
172 #define mmNIC2_QM1_CQ_ARUSER_31_11_0                                 0xD62138
173 
174 #define mmNIC2_QM1_CQ_ARUSER_31_11_1                                 0xD6213C
175 
176 #define mmNIC2_QM1_CQ_ARUSER_31_11_2                                 0xD62140
177 
178 #define mmNIC2_QM1_CQ_ARUSER_31_11_3                                 0xD62144
179 
180 #define mmNIC2_QM1_CQ_ARUSER_31_11_4                                 0xD62148
181 
182 #define mmNIC2_QM1_CQ_STS0_0                                         0xD6214C
183 
184 #define mmNIC2_QM1_CQ_STS0_1                                         0xD62150
185 
186 #define mmNIC2_QM1_CQ_STS0_2                                         0xD62154
187 
188 #define mmNIC2_QM1_CQ_STS0_3                                         0xD62158
189 
190 #define mmNIC2_QM1_CQ_STS0_4                                         0xD6215C
191 
192 #define mmNIC2_QM1_CQ_STS1_0                                         0xD62160
193 
194 #define mmNIC2_QM1_CQ_STS1_1                                         0xD62164
195 
196 #define mmNIC2_QM1_CQ_STS1_2                                         0xD62168
197 
198 #define mmNIC2_QM1_CQ_STS1_3                                         0xD6216C
199 
200 #define mmNIC2_QM1_CQ_STS1_4                                         0xD62170
201 
202 #define mmNIC2_QM1_CQ_PTR_LO_0                                       0xD62174
203 
204 #define mmNIC2_QM1_CQ_PTR_HI_0                                       0xD62178
205 
206 #define mmNIC2_QM1_CQ_TSIZE_0                                        0xD6217C
207 
208 #define mmNIC2_QM1_CQ_CTL_0                                          0xD62180
209 
210 #define mmNIC2_QM1_CQ_PTR_LO_1                                       0xD62184
211 
212 #define mmNIC2_QM1_CQ_PTR_HI_1                                       0xD62188
213 
214 #define mmNIC2_QM1_CQ_TSIZE_1                                        0xD6218C
215 
216 #define mmNIC2_QM1_CQ_CTL_1                                          0xD62190
217 
218 #define mmNIC2_QM1_CQ_PTR_LO_2                                       0xD62194
219 
220 #define mmNIC2_QM1_CQ_PTR_HI_2                                       0xD62198
221 
222 #define mmNIC2_QM1_CQ_TSIZE_2                                        0xD6219C
223 
224 #define mmNIC2_QM1_CQ_CTL_2                                          0xD621A0
225 
226 #define mmNIC2_QM1_CQ_PTR_LO_3                                       0xD621A4
227 
228 #define mmNIC2_QM1_CQ_PTR_HI_3                                       0xD621A8
229 
230 #define mmNIC2_QM1_CQ_TSIZE_3                                        0xD621AC
231 
232 #define mmNIC2_QM1_CQ_CTL_3                                          0xD621B0
233 
234 #define mmNIC2_QM1_CQ_PTR_LO_4                                       0xD621B4
235 
236 #define mmNIC2_QM1_CQ_PTR_HI_4                                       0xD621B8
237 
238 #define mmNIC2_QM1_CQ_TSIZE_4                                        0xD621BC
239 
240 #define mmNIC2_QM1_CQ_CTL_4                                          0xD621C0
241 
242 #define mmNIC2_QM1_CQ_PTR_LO_STS_0                                   0xD621C4
243 
244 #define mmNIC2_QM1_CQ_PTR_LO_STS_1                                   0xD621C8
245 
246 #define mmNIC2_QM1_CQ_PTR_LO_STS_2                                   0xD621CC
247 
248 #define mmNIC2_QM1_CQ_PTR_LO_STS_3                                   0xD621D0
249 
250 #define mmNIC2_QM1_CQ_PTR_LO_STS_4                                   0xD621D4
251 
252 #define mmNIC2_QM1_CQ_PTR_HI_STS_0                                   0xD621D8
253 
254 #define mmNIC2_QM1_CQ_PTR_HI_STS_1                                   0xD621DC
255 
256 #define mmNIC2_QM1_CQ_PTR_HI_STS_2                                   0xD621E0
257 
258 #define mmNIC2_QM1_CQ_PTR_HI_STS_3                                   0xD621E4
259 
260 #define mmNIC2_QM1_CQ_PTR_HI_STS_4                                   0xD621E8
261 
262 #define mmNIC2_QM1_CQ_TSIZE_STS_0                                    0xD621EC
263 
264 #define mmNIC2_QM1_CQ_TSIZE_STS_1                                    0xD621F0
265 
266 #define mmNIC2_QM1_CQ_TSIZE_STS_2                                    0xD621F4
267 
268 #define mmNIC2_QM1_CQ_TSIZE_STS_3                                    0xD621F8
269 
270 #define mmNIC2_QM1_CQ_TSIZE_STS_4                                    0xD621FC
271 
272 #define mmNIC2_QM1_CQ_CTL_STS_0                                      0xD62200
273 
274 #define mmNIC2_QM1_CQ_CTL_STS_1                                      0xD62204
275 
276 #define mmNIC2_QM1_CQ_CTL_STS_2                                      0xD62208
277 
278 #define mmNIC2_QM1_CQ_CTL_STS_3                                      0xD6220C
279 
280 #define mmNIC2_QM1_CQ_CTL_STS_4                                      0xD62210
281 
282 #define mmNIC2_QM1_CQ_IFIFO_CNT_0                                    0xD62214
283 
284 #define mmNIC2_QM1_CQ_IFIFO_CNT_1                                    0xD62218
285 
286 #define mmNIC2_QM1_CQ_IFIFO_CNT_2                                    0xD6221C
287 
288 #define mmNIC2_QM1_CQ_IFIFO_CNT_3                                    0xD62220
289 
290 #define mmNIC2_QM1_CQ_IFIFO_CNT_4                                    0xD62224
291 
292 #define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_0                            0xD62228
293 
294 #define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_1                            0xD6222C
295 
296 #define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_2                            0xD62230
297 
298 #define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_3                            0xD62234
299 
300 #define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_4                            0xD62238
301 
302 #define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_0                            0xD6223C
303 
304 #define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_1                            0xD62240
305 
306 #define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_2                            0xD62244
307 
308 #define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_3                            0xD62248
309 
310 #define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_4                            0xD6224C
311 
312 #define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_0                            0xD62250
313 
314 #define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_1                            0xD62254
315 
316 #define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_2                            0xD62258
317 
318 #define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_3                            0xD6225C
319 
320 #define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_4                            0xD62260
321 
322 #define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_0                            0xD62264
323 
324 #define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_1                            0xD62268
325 
326 #define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_2                            0xD6226C
327 
328 #define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_3                            0xD62270
329 
330 #define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_4                            0xD62274
331 
332 #define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_0                            0xD62278
333 
334 #define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_1                            0xD6227C
335 
336 #define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_2                            0xD62280
337 
338 #define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_3                            0xD62284
339 
340 #define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_4                            0xD62288
341 
342 #define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_0                            0xD6228C
343 
344 #define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_1                            0xD62290
345 
346 #define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_2                            0xD62294
347 
348 #define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_3                            0xD62298
349 
350 #define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_4                            0xD6229C
351 
352 #define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_0                            0xD622A0
353 
354 #define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_1                            0xD622A4
355 
356 #define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_2                            0xD622A8
357 
358 #define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_3                            0xD622AC
359 
360 #define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_4                            0xD622B0
361 
362 #define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_0                            0xD622B4
363 
364 #define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_1                            0xD622B8
365 
366 #define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_2                            0xD622BC
367 
368 #define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_3                            0xD622C0
369 
370 #define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_4                            0xD622C4
371 
372 #define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_0                            0xD622C8
373 
374 #define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_1                            0xD622CC
375 
376 #define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_2                            0xD622D0
377 
378 #define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_3                            0xD622D4
379 
380 #define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_4                            0xD622D8
381 
382 #define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0                      0xD622E0
383 
384 #define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1                      0xD622E4
385 
386 #define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2                      0xD622E8
387 
388 #define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3                      0xD622EC
389 
390 #define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4                      0xD622F0
391 
392 #define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0                      0xD622F4
393 
394 #define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1                      0xD622F8
395 
396 #define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2                      0xD622FC
397 
398 #define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3                      0xD62300
399 
400 #define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4                      0xD62304
401 
402 #define mmNIC2_QM1_CP_FENCE0_RDATA_0                                 0xD62308
403 
404 #define mmNIC2_QM1_CP_FENCE0_RDATA_1                                 0xD6230C
405 
406 #define mmNIC2_QM1_CP_FENCE0_RDATA_2                                 0xD62310
407 
408 #define mmNIC2_QM1_CP_FENCE0_RDATA_3                                 0xD62314
409 
410 #define mmNIC2_QM1_CP_FENCE0_RDATA_4                                 0xD62318
411 
412 #define mmNIC2_QM1_CP_FENCE1_RDATA_0                                 0xD6231C
413 
414 #define mmNIC2_QM1_CP_FENCE1_RDATA_1                                 0xD62320
415 
416 #define mmNIC2_QM1_CP_FENCE1_RDATA_2                                 0xD62324
417 
418 #define mmNIC2_QM1_CP_FENCE1_RDATA_3                                 0xD62328
419 
420 #define mmNIC2_QM1_CP_FENCE1_RDATA_4                                 0xD6232C
421 
422 #define mmNIC2_QM1_CP_FENCE2_RDATA_0                                 0xD62330
423 
424 #define mmNIC2_QM1_CP_FENCE2_RDATA_1                                 0xD62334
425 
426 #define mmNIC2_QM1_CP_FENCE2_RDATA_2                                 0xD62338
427 
428 #define mmNIC2_QM1_CP_FENCE2_RDATA_3                                 0xD6233C
429 
430 #define mmNIC2_QM1_CP_FENCE2_RDATA_4                                 0xD62340
431 
432 #define mmNIC2_QM1_CP_FENCE3_RDATA_0                                 0xD62344
433 
434 #define mmNIC2_QM1_CP_FENCE3_RDATA_1                                 0xD62348
435 
436 #define mmNIC2_QM1_CP_FENCE3_RDATA_2                                 0xD6234C
437 
438 #define mmNIC2_QM1_CP_FENCE3_RDATA_3                                 0xD62350
439 
440 #define mmNIC2_QM1_CP_FENCE3_RDATA_4                                 0xD62354
441 
442 #define mmNIC2_QM1_CP_FENCE0_CNT_0                                   0xD62358
443 
444 #define mmNIC2_QM1_CP_FENCE0_CNT_1                                   0xD6235C
445 
446 #define mmNIC2_QM1_CP_FENCE0_CNT_2                                   0xD62360
447 
448 #define mmNIC2_QM1_CP_FENCE0_CNT_3                                   0xD62364
449 
450 #define mmNIC2_QM1_CP_FENCE0_CNT_4                                   0xD62368
451 
452 #define mmNIC2_QM1_CP_FENCE1_CNT_0                                   0xD6236C
453 
454 #define mmNIC2_QM1_CP_FENCE1_CNT_1                                   0xD62370
455 
456 #define mmNIC2_QM1_CP_FENCE1_CNT_2                                   0xD62374
457 
458 #define mmNIC2_QM1_CP_FENCE1_CNT_3                                   0xD62378
459 
460 #define mmNIC2_QM1_CP_FENCE1_CNT_4                                   0xD6237C
461 
462 #define mmNIC2_QM1_CP_FENCE2_CNT_0                                   0xD62380
463 
464 #define mmNIC2_QM1_CP_FENCE2_CNT_1                                   0xD62384
465 
466 #define mmNIC2_QM1_CP_FENCE2_CNT_2                                   0xD62388
467 
468 #define mmNIC2_QM1_CP_FENCE2_CNT_3                                   0xD6238C
469 
470 #define mmNIC2_QM1_CP_FENCE2_CNT_4                                   0xD62390
471 
472 #define mmNIC2_QM1_CP_FENCE3_CNT_0                                   0xD62394
473 
474 #define mmNIC2_QM1_CP_FENCE3_CNT_1                                   0xD62398
475 
476 #define mmNIC2_QM1_CP_FENCE3_CNT_2                                   0xD6239C
477 
478 #define mmNIC2_QM1_CP_FENCE3_CNT_3                                   0xD623A0
479 
480 #define mmNIC2_QM1_CP_FENCE3_CNT_4                                   0xD623A4
481 
482 #define mmNIC2_QM1_CP_STS_0                                          0xD623A8
483 
484 #define mmNIC2_QM1_CP_STS_1                                          0xD623AC
485 
486 #define mmNIC2_QM1_CP_STS_2                                          0xD623B0
487 
488 #define mmNIC2_QM1_CP_STS_3                                          0xD623B4
489 
490 #define mmNIC2_QM1_CP_STS_4                                          0xD623B8
491 
492 #define mmNIC2_QM1_CP_CURRENT_INST_LO_0                              0xD623BC
493 
494 #define mmNIC2_QM1_CP_CURRENT_INST_LO_1                              0xD623C0
495 
496 #define mmNIC2_QM1_CP_CURRENT_INST_LO_2                              0xD623C4
497 
498 #define mmNIC2_QM1_CP_CURRENT_INST_LO_3                              0xD623C8
499 
500 #define mmNIC2_QM1_CP_CURRENT_INST_LO_4                              0xD623CC
501 
502 #define mmNIC2_QM1_CP_CURRENT_INST_HI_0                              0xD623D0
503 
504 #define mmNIC2_QM1_CP_CURRENT_INST_HI_1                              0xD623D4
505 
506 #define mmNIC2_QM1_CP_CURRENT_INST_HI_2                              0xD623D8
507 
508 #define mmNIC2_QM1_CP_CURRENT_INST_HI_3                              0xD623DC
509 
510 #define mmNIC2_QM1_CP_CURRENT_INST_HI_4                              0xD623E0
511 
512 #define mmNIC2_QM1_CP_BARRIER_CFG_0                                  0xD623F4
513 
514 #define mmNIC2_QM1_CP_BARRIER_CFG_1                                  0xD623F8
515 
516 #define mmNIC2_QM1_CP_BARRIER_CFG_2                                  0xD623FC
517 
518 #define mmNIC2_QM1_CP_BARRIER_CFG_3                                  0xD62400
519 
520 #define mmNIC2_QM1_CP_BARRIER_CFG_4                                  0xD62404
521 
522 #define mmNIC2_QM1_CP_DBG_0_0                                        0xD62408
523 
524 #define mmNIC2_QM1_CP_DBG_0_1                                        0xD6240C
525 
526 #define mmNIC2_QM1_CP_DBG_0_2                                        0xD62410
527 
528 #define mmNIC2_QM1_CP_DBG_0_3                                        0xD62414
529 
530 #define mmNIC2_QM1_CP_DBG_0_4                                        0xD62418
531 
532 #define mmNIC2_QM1_CP_ARUSER_31_11_0                                 0xD6241C
533 
534 #define mmNIC2_QM1_CP_ARUSER_31_11_1                                 0xD62420
535 
536 #define mmNIC2_QM1_CP_ARUSER_31_11_2                                 0xD62424
537 
538 #define mmNIC2_QM1_CP_ARUSER_31_11_3                                 0xD62428
539 
540 #define mmNIC2_QM1_CP_ARUSER_31_11_4                                 0xD6242C
541 
542 #define mmNIC2_QM1_CP_AWUSER_31_11_0                                 0xD62430
543 
544 #define mmNIC2_QM1_CP_AWUSER_31_11_1                                 0xD62434
545 
546 #define mmNIC2_QM1_CP_AWUSER_31_11_2                                 0xD62438
547 
548 #define mmNIC2_QM1_CP_AWUSER_31_11_3                                 0xD6243C
549 
550 #define mmNIC2_QM1_CP_AWUSER_31_11_4                                 0xD62440
551 
552 #define mmNIC2_QM1_ARB_CFG_0                                         0xD62A00
553 
554 #define mmNIC2_QM1_ARB_CHOISE_Q_PUSH                                 0xD62A04
555 
556 #define mmNIC2_QM1_ARB_WRR_WEIGHT_0                                  0xD62A08
557 
558 #define mmNIC2_QM1_ARB_WRR_WEIGHT_1                                  0xD62A0C
559 
560 #define mmNIC2_QM1_ARB_WRR_WEIGHT_2                                  0xD62A10
561 
562 #define mmNIC2_QM1_ARB_WRR_WEIGHT_3                                  0xD62A14
563 
564 #define mmNIC2_QM1_ARB_CFG_1                                         0xD62A18
565 
566 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_0                              0xD62A20
567 
568 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_1                              0xD62A24
569 
570 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_2                              0xD62A28
571 
572 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_3                              0xD62A2C
573 
574 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_4                              0xD62A30
575 
576 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_5                              0xD62A34
577 
578 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_6                              0xD62A38
579 
580 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_7                              0xD62A3C
581 
582 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_8                              0xD62A40
583 
584 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_9                              0xD62A44
585 
586 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_10                             0xD62A48
587 
588 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_11                             0xD62A4C
589 
590 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_12                             0xD62A50
591 
592 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_13                             0xD62A54
593 
594 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_14                             0xD62A58
595 
596 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_15                             0xD62A5C
597 
598 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_16                             0xD62A60
599 
600 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_17                             0xD62A64
601 
602 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_18                             0xD62A68
603 
604 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_19                             0xD62A6C
605 
606 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_20                             0xD62A70
607 
608 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_21                             0xD62A74
609 
610 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_22                             0xD62A78
611 
612 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_23                             0xD62A7C
613 
614 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_24                             0xD62A80
615 
616 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_25                             0xD62A84
617 
618 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_26                             0xD62A88
619 
620 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_27                             0xD62A8C
621 
622 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_28                             0xD62A90
623 
624 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_29                             0xD62A94
625 
626 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_30                             0xD62A98
627 
628 #define mmNIC2_QM1_ARB_MST_AVAIL_CRED_31                             0xD62A9C
629 
630 #define mmNIC2_QM1_ARB_MST_CRED_INC                                  0xD62AA0
631 
632 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_0                        0xD62AA4
633 
634 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_1                        0xD62AA8
635 
636 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_2                        0xD62AAC
637 
638 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_3                        0xD62AB0
639 
640 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_4                        0xD62AB4
641 
642 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_5                        0xD62AB8
643 
644 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_6                        0xD62ABC
645 
646 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_7                        0xD62AC0
647 
648 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_8                        0xD62AC4
649 
650 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_9                        0xD62AC8
651 
652 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_10                       0xD62ACC
653 
654 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_11                       0xD62AD0
655 
656 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_12                       0xD62AD4
657 
658 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_13                       0xD62AD8
659 
660 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_14                       0xD62ADC
661 
662 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_15                       0xD62AE0
663 
664 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_16                       0xD62AE4
665 
666 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_17                       0xD62AE8
667 
668 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_18                       0xD62AEC
669 
670 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_19                       0xD62AF0
671 
672 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_20                       0xD62AF4
673 
674 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_21                       0xD62AF8
675 
676 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_22                       0xD62AFC
677 
678 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_23                       0xD62B00
679 
680 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_24                       0xD62B04
681 
682 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_25                       0xD62B08
683 
684 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_26                       0xD62B0C
685 
686 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_27                       0xD62B10
687 
688 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_28                       0xD62B14
689 
690 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_29                       0xD62B18
691 
692 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_30                       0xD62B1C
693 
694 #define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_31                       0xD62B20
695 
696 #define mmNIC2_QM1_ARB_SLV_MASTER_INC_CRED_OFST                      0xD62B28
697 
698 #define mmNIC2_QM1_ARB_MST_SLAVE_EN                                  0xD62B2C
699 
700 #define mmNIC2_QM1_ARB_MST_QUIET_PER                                 0xD62B34
701 
702 #define mmNIC2_QM1_ARB_SLV_CHOISE_WDT                                0xD62B38
703 
704 #define mmNIC2_QM1_ARB_SLV_ID                                        0xD62B3C
705 
706 #define mmNIC2_QM1_ARB_MSG_MAX_INFLIGHT                              0xD62B44
707 
708 #define mmNIC2_QM1_ARB_MSG_AWUSER_31_11                              0xD62B48
709 
710 #define mmNIC2_QM1_ARB_MSG_AWUSER_SEC_PROP                           0xD62B4C
711 
712 #define mmNIC2_QM1_ARB_MSG_AWUSER_NON_SEC_PROP                       0xD62B50
713 
714 #define mmNIC2_QM1_ARB_BASE_LO                                       0xD62B54
715 
716 #define mmNIC2_QM1_ARB_BASE_HI                                       0xD62B58
717 
718 #define mmNIC2_QM1_ARB_STATE_STS                                     0xD62B80
719 
720 #define mmNIC2_QM1_ARB_CHOISE_FULLNESS_STS                           0xD62B84
721 
722 #define mmNIC2_QM1_ARB_MSG_STS                                       0xD62B88
723 
724 #define mmNIC2_QM1_ARB_SLV_CHOISE_Q_HEAD                             0xD62B8C
725 
726 #define mmNIC2_QM1_ARB_ERR_CAUSE                                     0xD62B9C
727 
728 #define mmNIC2_QM1_ARB_ERR_MSG_EN                                    0xD62BA0
729 
730 #define mmNIC2_QM1_ARB_ERR_STS_DRP                                   0xD62BA8
731 
732 #define mmNIC2_QM1_ARB_MST_CRED_STS_0                                0xD62BB0
733 
734 #define mmNIC2_QM1_ARB_MST_CRED_STS_1                                0xD62BB4
735 
736 #define mmNIC2_QM1_ARB_MST_CRED_STS_2                                0xD62BB8
737 
738 #define mmNIC2_QM1_ARB_MST_CRED_STS_3                                0xD62BBC
739 
740 #define mmNIC2_QM1_ARB_MST_CRED_STS_4                                0xD62BC0
741 
742 #define mmNIC2_QM1_ARB_MST_CRED_STS_5                                0xD62BC4
743 
744 #define mmNIC2_QM1_ARB_MST_CRED_STS_6                                0xD62BC8
745 
746 #define mmNIC2_QM1_ARB_MST_CRED_STS_7                                0xD62BCC
747 
748 #define mmNIC2_QM1_ARB_MST_CRED_STS_8                                0xD62BD0
749 
750 #define mmNIC2_QM1_ARB_MST_CRED_STS_9                                0xD62BD4
751 
752 #define mmNIC2_QM1_ARB_MST_CRED_STS_10                               0xD62BD8
753 
754 #define mmNIC2_QM1_ARB_MST_CRED_STS_11                               0xD62BDC
755 
756 #define mmNIC2_QM1_ARB_MST_CRED_STS_12                               0xD62BE0
757 
758 #define mmNIC2_QM1_ARB_MST_CRED_STS_13                               0xD62BE4
759 
760 #define mmNIC2_QM1_ARB_MST_CRED_STS_14                               0xD62BE8
761 
762 #define mmNIC2_QM1_ARB_MST_CRED_STS_15                               0xD62BEC
763 
764 #define mmNIC2_QM1_ARB_MST_CRED_STS_16                               0xD62BF0
765 
766 #define mmNIC2_QM1_ARB_MST_CRED_STS_17                               0xD62BF4
767 
768 #define mmNIC2_QM1_ARB_MST_CRED_STS_18                               0xD62BF8
769 
770 #define mmNIC2_QM1_ARB_MST_CRED_STS_19                               0xD62BFC
771 
772 #define mmNIC2_QM1_ARB_MST_CRED_STS_20                               0xD62C00
773 
774 #define mmNIC2_QM1_ARB_MST_CRED_STS_21                               0xD62C04
775 
776 #define mmNIC2_QM1_ARB_MST_CRED_STS_22                               0xD62C08
777 
778 #define mmNIC2_QM1_ARB_MST_CRED_STS_23                               0xD62C0C
779 
780 #define mmNIC2_QM1_ARB_MST_CRED_STS_24                               0xD62C10
781 
782 #define mmNIC2_QM1_ARB_MST_CRED_STS_25                               0xD62C14
783 
784 #define mmNIC2_QM1_ARB_MST_CRED_STS_26                               0xD62C18
785 
786 #define mmNIC2_QM1_ARB_MST_CRED_STS_27                               0xD62C1C
787 
788 #define mmNIC2_QM1_ARB_MST_CRED_STS_28                               0xD62C20
789 
790 #define mmNIC2_QM1_ARB_MST_CRED_STS_29                               0xD62C24
791 
792 #define mmNIC2_QM1_ARB_MST_CRED_STS_30                               0xD62C28
793 
794 #define mmNIC2_QM1_ARB_MST_CRED_STS_31                               0xD62C2C
795 
796 #define mmNIC2_QM1_CGM_CFG                                           0xD62C70
797 
798 #define mmNIC2_QM1_CGM_STS                                           0xD62C74
799 
800 #define mmNIC2_QM1_CGM_CFG1                                          0xD62C78
801 
802 #define mmNIC2_QM1_LOCAL_RANGE_BASE                                  0xD62C80
803 
804 #define mmNIC2_QM1_LOCAL_RANGE_SIZE                                  0xD62C84
805 
806 #define mmNIC2_QM1_CSMR_STRICT_PRIO_CFG                              0xD62C90
807 
808 #define mmNIC2_QM1_HBW_RD_RATE_LIM_CFG_1                             0xD62C94
809 
810 #define mmNIC2_QM1_LBW_WR_RATE_LIM_CFG_0                             0xD62C98
811 
812 #define mmNIC2_QM1_LBW_WR_RATE_LIM_CFG_1                             0xD62C9C
813 
814 #define mmNIC2_QM1_HBW_RD_RATE_LIM_CFG_0                             0xD62CA0
815 
816 #define mmNIC2_QM1_GLBL_AXCACHE                                      0xD62CA4
817 
818 #define mmNIC2_QM1_IND_GW_APB_CFG                                    0xD62CB0
819 
820 #define mmNIC2_QM1_IND_GW_APB_WDATA                                  0xD62CB4
821 
822 #define mmNIC2_QM1_IND_GW_APB_RDATA                                  0xD62CB8
823 
824 #define mmNIC2_QM1_IND_GW_APB_STATUS                                 0xD62CBC
825 
826 #define mmNIC2_QM1_GLBL_ERR_ADDR_LO                                  0xD62CD0
827 
828 #define mmNIC2_QM1_GLBL_ERR_ADDR_HI                                  0xD62CD4
829 
830 #define mmNIC2_QM1_GLBL_ERR_WDATA                                    0xD62CD8
831 
832 #define mmNIC2_QM1_GLBL_MEM_INIT_BUSY                                0xD62D00
833 
834 #endif /* ASIC_REG_NIC2_QM1_REGS_H_ */
835