1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_NIC1_QM0_REGS_H_ 14 #define ASIC_REG_NIC1_QM0_REGS_H_ 15 16 /* 17 ***************************************** 18 * NIC1_QM0 (Prototype: QMAN) 19 ***************************************** 20 */ 21 22 #define mmNIC1_QM0_GLBL_CFG0 0xD20000 23 24 #define mmNIC1_QM0_GLBL_CFG1 0xD20004 25 26 #define mmNIC1_QM0_GLBL_PROT 0xD20008 27 28 #define mmNIC1_QM0_GLBL_ERR_CFG 0xD2000C 29 30 #define mmNIC1_QM0_GLBL_SECURE_PROPS_0 0xD20010 31 32 #define mmNIC1_QM0_GLBL_SECURE_PROPS_1 0xD20014 33 34 #define mmNIC1_QM0_GLBL_SECURE_PROPS_2 0xD20018 35 36 #define mmNIC1_QM0_GLBL_SECURE_PROPS_3 0xD2001C 37 38 #define mmNIC1_QM0_GLBL_SECURE_PROPS_4 0xD20020 39 40 #define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_0 0xD20024 41 42 #define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_1 0xD20028 43 44 #define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_2 0xD2002C 45 46 #define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_3 0xD20030 47 48 #define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_4 0xD20034 49 50 #define mmNIC1_QM0_GLBL_STS0 0xD20038 51 52 #define mmNIC1_QM0_GLBL_STS1_0 0xD20040 53 54 #define mmNIC1_QM0_GLBL_STS1_1 0xD20044 55 56 #define mmNIC1_QM0_GLBL_STS1_2 0xD20048 57 58 #define mmNIC1_QM0_GLBL_STS1_3 0xD2004C 59 60 #define mmNIC1_QM0_GLBL_STS1_4 0xD20050 61 62 #define mmNIC1_QM0_GLBL_MSG_EN_0 0xD20054 63 64 #define mmNIC1_QM0_GLBL_MSG_EN_1 0xD20058 65 66 #define mmNIC1_QM0_GLBL_MSG_EN_2 0xD2005C 67 68 #define mmNIC1_QM0_GLBL_MSG_EN_3 0xD20060 69 70 #define mmNIC1_QM0_GLBL_MSG_EN_4 0xD20068 71 72 #define mmNIC1_QM0_PQ_BASE_LO_0 0xD20070 73 74 #define mmNIC1_QM0_PQ_BASE_LO_1 0xD20074 75 76 #define mmNIC1_QM0_PQ_BASE_LO_2 0xD20078 77 78 #define mmNIC1_QM0_PQ_BASE_LO_3 0xD2007C 79 80 #define mmNIC1_QM0_PQ_BASE_HI_0 0xD20080 81 82 #define mmNIC1_QM0_PQ_BASE_HI_1 0xD20084 83 84 #define mmNIC1_QM0_PQ_BASE_HI_2 0xD20088 85 86 #define mmNIC1_QM0_PQ_BASE_HI_3 0xD2008C 87 88 #define mmNIC1_QM0_PQ_SIZE_0 0xD20090 89 90 #define mmNIC1_QM0_PQ_SIZE_1 0xD20094 91 92 #define mmNIC1_QM0_PQ_SIZE_2 0xD20098 93 94 #define mmNIC1_QM0_PQ_SIZE_3 0xD2009C 95 96 #define mmNIC1_QM0_PQ_PI_0 0xD200A0 97 98 #define mmNIC1_QM0_PQ_PI_1 0xD200A4 99 100 #define mmNIC1_QM0_PQ_PI_2 0xD200A8 101 102 #define mmNIC1_QM0_PQ_PI_3 0xD200AC 103 104 #define mmNIC1_QM0_PQ_CI_0 0xD200B0 105 106 #define mmNIC1_QM0_PQ_CI_1 0xD200B4 107 108 #define mmNIC1_QM0_PQ_CI_2 0xD200B8 109 110 #define mmNIC1_QM0_PQ_CI_3 0xD200BC 111 112 #define mmNIC1_QM0_PQ_CFG0_0 0xD200C0 113 114 #define mmNIC1_QM0_PQ_CFG0_1 0xD200C4 115 116 #define mmNIC1_QM0_PQ_CFG0_2 0xD200C8 117 118 #define mmNIC1_QM0_PQ_CFG0_3 0xD200CC 119 120 #define mmNIC1_QM0_PQ_CFG1_0 0xD200D0 121 122 #define mmNIC1_QM0_PQ_CFG1_1 0xD200D4 123 124 #define mmNIC1_QM0_PQ_CFG1_2 0xD200D8 125 126 #define mmNIC1_QM0_PQ_CFG1_3 0xD200DC 127 128 #define mmNIC1_QM0_PQ_ARUSER_31_11_0 0xD200E0 129 130 #define mmNIC1_QM0_PQ_ARUSER_31_11_1 0xD200E4 131 132 #define mmNIC1_QM0_PQ_ARUSER_31_11_2 0xD200E8 133 134 #define mmNIC1_QM0_PQ_ARUSER_31_11_3 0xD200EC 135 136 #define mmNIC1_QM0_PQ_STS0_0 0xD200F0 137 138 #define mmNIC1_QM0_PQ_STS0_1 0xD200F4 139 140 #define mmNIC1_QM0_PQ_STS0_2 0xD200F8 141 142 #define mmNIC1_QM0_PQ_STS0_3 0xD200FC 143 144 #define mmNIC1_QM0_PQ_STS1_0 0xD20100 145 146 #define mmNIC1_QM0_PQ_STS1_1 0xD20104 147 148 #define mmNIC1_QM0_PQ_STS1_2 0xD20108 149 150 #define mmNIC1_QM0_PQ_STS1_3 0xD2010C 151 152 #define mmNIC1_QM0_CQ_CFG0_0 0xD20110 153 154 #define mmNIC1_QM0_CQ_CFG0_1 0xD20114 155 156 #define mmNIC1_QM0_CQ_CFG0_2 0xD20118 157 158 #define mmNIC1_QM0_CQ_CFG0_3 0xD2011C 159 160 #define mmNIC1_QM0_CQ_CFG0_4 0xD20120 161 162 #define mmNIC1_QM0_CQ_CFG1_0 0xD20124 163 164 #define mmNIC1_QM0_CQ_CFG1_1 0xD20128 165 166 #define mmNIC1_QM0_CQ_CFG1_2 0xD2012C 167 168 #define mmNIC1_QM0_CQ_CFG1_3 0xD20130 169 170 #define mmNIC1_QM0_CQ_CFG1_4 0xD20134 171 172 #define mmNIC1_QM0_CQ_ARUSER_31_11_0 0xD20138 173 174 #define mmNIC1_QM0_CQ_ARUSER_31_11_1 0xD2013C 175 176 #define mmNIC1_QM0_CQ_ARUSER_31_11_2 0xD20140 177 178 #define mmNIC1_QM0_CQ_ARUSER_31_11_3 0xD20144 179 180 #define mmNIC1_QM0_CQ_ARUSER_31_11_4 0xD20148 181 182 #define mmNIC1_QM0_CQ_STS0_0 0xD2014C 183 184 #define mmNIC1_QM0_CQ_STS0_1 0xD20150 185 186 #define mmNIC1_QM0_CQ_STS0_2 0xD20154 187 188 #define mmNIC1_QM0_CQ_STS0_3 0xD20158 189 190 #define mmNIC1_QM0_CQ_STS0_4 0xD2015C 191 192 #define mmNIC1_QM0_CQ_STS1_0 0xD20160 193 194 #define mmNIC1_QM0_CQ_STS1_1 0xD20164 195 196 #define mmNIC1_QM0_CQ_STS1_2 0xD20168 197 198 #define mmNIC1_QM0_CQ_STS1_3 0xD2016C 199 200 #define mmNIC1_QM0_CQ_STS1_4 0xD20170 201 202 #define mmNIC1_QM0_CQ_PTR_LO_0 0xD20174 203 204 #define mmNIC1_QM0_CQ_PTR_HI_0 0xD20178 205 206 #define mmNIC1_QM0_CQ_TSIZE_0 0xD2017C 207 208 #define mmNIC1_QM0_CQ_CTL_0 0xD20180 209 210 #define mmNIC1_QM0_CQ_PTR_LO_1 0xD20184 211 212 #define mmNIC1_QM0_CQ_PTR_HI_1 0xD20188 213 214 #define mmNIC1_QM0_CQ_TSIZE_1 0xD2018C 215 216 #define mmNIC1_QM0_CQ_CTL_1 0xD20190 217 218 #define mmNIC1_QM0_CQ_PTR_LO_2 0xD20194 219 220 #define mmNIC1_QM0_CQ_PTR_HI_2 0xD20198 221 222 #define mmNIC1_QM0_CQ_TSIZE_2 0xD2019C 223 224 #define mmNIC1_QM0_CQ_CTL_2 0xD201A0 225 226 #define mmNIC1_QM0_CQ_PTR_LO_3 0xD201A4 227 228 #define mmNIC1_QM0_CQ_PTR_HI_3 0xD201A8 229 230 #define mmNIC1_QM0_CQ_TSIZE_3 0xD201AC 231 232 #define mmNIC1_QM0_CQ_CTL_3 0xD201B0 233 234 #define mmNIC1_QM0_CQ_PTR_LO_4 0xD201B4 235 236 #define mmNIC1_QM0_CQ_PTR_HI_4 0xD201B8 237 238 #define mmNIC1_QM0_CQ_TSIZE_4 0xD201BC 239 240 #define mmNIC1_QM0_CQ_CTL_4 0xD201C0 241 242 #define mmNIC1_QM0_CQ_PTR_LO_STS_0 0xD201C4 243 244 #define mmNIC1_QM0_CQ_PTR_LO_STS_1 0xD201C8 245 246 #define mmNIC1_QM0_CQ_PTR_LO_STS_2 0xD201CC 247 248 #define mmNIC1_QM0_CQ_PTR_LO_STS_3 0xD201D0 249 250 #define mmNIC1_QM0_CQ_PTR_LO_STS_4 0xD201D4 251 252 #define mmNIC1_QM0_CQ_PTR_HI_STS_0 0xD201D8 253 254 #define mmNIC1_QM0_CQ_PTR_HI_STS_1 0xD201DC 255 256 #define mmNIC1_QM0_CQ_PTR_HI_STS_2 0xD201E0 257 258 #define mmNIC1_QM0_CQ_PTR_HI_STS_3 0xD201E4 259 260 #define mmNIC1_QM0_CQ_PTR_HI_STS_4 0xD201E8 261 262 #define mmNIC1_QM0_CQ_TSIZE_STS_0 0xD201EC 263 264 #define mmNIC1_QM0_CQ_TSIZE_STS_1 0xD201F0 265 266 #define mmNIC1_QM0_CQ_TSIZE_STS_2 0xD201F4 267 268 #define mmNIC1_QM0_CQ_TSIZE_STS_3 0xD201F8 269 270 #define mmNIC1_QM0_CQ_TSIZE_STS_4 0xD201FC 271 272 #define mmNIC1_QM0_CQ_CTL_STS_0 0xD20200 273 274 #define mmNIC1_QM0_CQ_CTL_STS_1 0xD20204 275 276 #define mmNIC1_QM0_CQ_CTL_STS_2 0xD20208 277 278 #define mmNIC1_QM0_CQ_CTL_STS_3 0xD2020C 279 280 #define mmNIC1_QM0_CQ_CTL_STS_4 0xD20210 281 282 #define mmNIC1_QM0_CQ_IFIFO_CNT_0 0xD20214 283 284 #define mmNIC1_QM0_CQ_IFIFO_CNT_1 0xD20218 285 286 #define mmNIC1_QM0_CQ_IFIFO_CNT_2 0xD2021C 287 288 #define mmNIC1_QM0_CQ_IFIFO_CNT_3 0xD20220 289 290 #define mmNIC1_QM0_CQ_IFIFO_CNT_4 0xD20224 291 292 #define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_0 0xD20228 293 294 #define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_1 0xD2022C 295 296 #define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_2 0xD20230 297 298 #define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_3 0xD20234 299 300 #define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_4 0xD20238 301 302 #define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_0 0xD2023C 303 304 #define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_1 0xD20240 305 306 #define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_2 0xD20244 307 308 #define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_3 0xD20248 309 310 #define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_4 0xD2024C 311 312 #define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_0 0xD20250 313 314 #define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_1 0xD20254 315 316 #define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_2 0xD20258 317 318 #define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_3 0xD2025C 319 320 #define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_4 0xD20260 321 322 #define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_0 0xD20264 323 324 #define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_1 0xD20268 325 326 #define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_2 0xD2026C 327 328 #define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_3 0xD20270 329 330 #define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_4 0xD20274 331 332 #define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_0 0xD20278 333 334 #define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_1 0xD2027C 335 336 #define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_2 0xD20280 337 338 #define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_3 0xD20284 339 340 #define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_4 0xD20288 341 342 #define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_0 0xD2028C 343 344 #define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_1 0xD20290 345 346 #define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_2 0xD20294 347 348 #define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_3 0xD20298 349 350 #define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_4 0xD2029C 351 352 #define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_0 0xD202A0 353 354 #define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_1 0xD202A4 355 356 #define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_2 0xD202A8 357 358 #define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_3 0xD202AC 359 360 #define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_4 0xD202B0 361 362 #define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_0 0xD202B4 363 364 #define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_1 0xD202B8 365 366 #define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_2 0xD202BC 367 368 #define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_3 0xD202C0 369 370 #define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_4 0xD202C4 371 372 #define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_0 0xD202C8 373 374 #define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_1 0xD202CC 375 376 #define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_2 0xD202D0 377 378 #define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_3 0xD202D4 379 380 #define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_4 0xD202D8 381 382 #define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xD202E0 383 384 #define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xD202E4 385 386 #define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xD202E8 387 388 #define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xD202EC 389 390 #define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xD202F0 391 392 #define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xD202F4 393 394 #define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xD202F8 395 396 #define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xD202FC 397 398 #define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xD20300 399 400 #define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xD20304 401 402 #define mmNIC1_QM0_CP_FENCE0_RDATA_0 0xD20308 403 404 #define mmNIC1_QM0_CP_FENCE0_RDATA_1 0xD2030C 405 406 #define mmNIC1_QM0_CP_FENCE0_RDATA_2 0xD20310 407 408 #define mmNIC1_QM0_CP_FENCE0_RDATA_3 0xD20314 409 410 #define mmNIC1_QM0_CP_FENCE0_RDATA_4 0xD20318 411 412 #define mmNIC1_QM0_CP_FENCE1_RDATA_0 0xD2031C 413 414 #define mmNIC1_QM0_CP_FENCE1_RDATA_1 0xD20320 415 416 #define mmNIC1_QM0_CP_FENCE1_RDATA_2 0xD20324 417 418 #define mmNIC1_QM0_CP_FENCE1_RDATA_3 0xD20328 419 420 #define mmNIC1_QM0_CP_FENCE1_RDATA_4 0xD2032C 421 422 #define mmNIC1_QM0_CP_FENCE2_RDATA_0 0xD20330 423 424 #define mmNIC1_QM0_CP_FENCE2_RDATA_1 0xD20334 425 426 #define mmNIC1_QM0_CP_FENCE2_RDATA_2 0xD20338 427 428 #define mmNIC1_QM0_CP_FENCE2_RDATA_3 0xD2033C 429 430 #define mmNIC1_QM0_CP_FENCE2_RDATA_4 0xD20340 431 432 #define mmNIC1_QM0_CP_FENCE3_RDATA_0 0xD20344 433 434 #define mmNIC1_QM0_CP_FENCE3_RDATA_1 0xD20348 435 436 #define mmNIC1_QM0_CP_FENCE3_RDATA_2 0xD2034C 437 438 #define mmNIC1_QM0_CP_FENCE3_RDATA_3 0xD20350 439 440 #define mmNIC1_QM0_CP_FENCE3_RDATA_4 0xD20354 441 442 #define mmNIC1_QM0_CP_FENCE0_CNT_0 0xD20358 443 444 #define mmNIC1_QM0_CP_FENCE0_CNT_1 0xD2035C 445 446 #define mmNIC1_QM0_CP_FENCE0_CNT_2 0xD20360 447 448 #define mmNIC1_QM0_CP_FENCE0_CNT_3 0xD20364 449 450 #define mmNIC1_QM0_CP_FENCE0_CNT_4 0xD20368 451 452 #define mmNIC1_QM0_CP_FENCE1_CNT_0 0xD2036C 453 454 #define mmNIC1_QM0_CP_FENCE1_CNT_1 0xD20370 455 456 #define mmNIC1_QM0_CP_FENCE1_CNT_2 0xD20374 457 458 #define mmNIC1_QM0_CP_FENCE1_CNT_3 0xD20378 459 460 #define mmNIC1_QM0_CP_FENCE1_CNT_4 0xD2037C 461 462 #define mmNIC1_QM0_CP_FENCE2_CNT_0 0xD20380 463 464 #define mmNIC1_QM0_CP_FENCE2_CNT_1 0xD20384 465 466 #define mmNIC1_QM0_CP_FENCE2_CNT_2 0xD20388 467 468 #define mmNIC1_QM0_CP_FENCE2_CNT_3 0xD2038C 469 470 #define mmNIC1_QM0_CP_FENCE2_CNT_4 0xD20390 471 472 #define mmNIC1_QM0_CP_FENCE3_CNT_0 0xD20394 473 474 #define mmNIC1_QM0_CP_FENCE3_CNT_1 0xD20398 475 476 #define mmNIC1_QM0_CP_FENCE3_CNT_2 0xD2039C 477 478 #define mmNIC1_QM0_CP_FENCE3_CNT_3 0xD203A0 479 480 #define mmNIC1_QM0_CP_FENCE3_CNT_4 0xD203A4 481 482 #define mmNIC1_QM0_CP_STS_0 0xD203A8 483 484 #define mmNIC1_QM0_CP_STS_1 0xD203AC 485 486 #define mmNIC1_QM0_CP_STS_2 0xD203B0 487 488 #define mmNIC1_QM0_CP_STS_3 0xD203B4 489 490 #define mmNIC1_QM0_CP_STS_4 0xD203B8 491 492 #define mmNIC1_QM0_CP_CURRENT_INST_LO_0 0xD203BC 493 494 #define mmNIC1_QM0_CP_CURRENT_INST_LO_1 0xD203C0 495 496 #define mmNIC1_QM0_CP_CURRENT_INST_LO_2 0xD203C4 497 498 #define mmNIC1_QM0_CP_CURRENT_INST_LO_3 0xD203C8 499 500 #define mmNIC1_QM0_CP_CURRENT_INST_LO_4 0xD203CC 501 502 #define mmNIC1_QM0_CP_CURRENT_INST_HI_0 0xD203D0 503 504 #define mmNIC1_QM0_CP_CURRENT_INST_HI_1 0xD203D4 505 506 #define mmNIC1_QM0_CP_CURRENT_INST_HI_2 0xD203D8 507 508 #define mmNIC1_QM0_CP_CURRENT_INST_HI_3 0xD203DC 509 510 #define mmNIC1_QM0_CP_CURRENT_INST_HI_4 0xD203E0 511 512 #define mmNIC1_QM0_CP_BARRIER_CFG_0 0xD203F4 513 514 #define mmNIC1_QM0_CP_BARRIER_CFG_1 0xD203F8 515 516 #define mmNIC1_QM0_CP_BARRIER_CFG_2 0xD203FC 517 518 #define mmNIC1_QM0_CP_BARRIER_CFG_3 0xD20400 519 520 #define mmNIC1_QM0_CP_BARRIER_CFG_4 0xD20404 521 522 #define mmNIC1_QM0_CP_DBG_0_0 0xD20408 523 524 #define mmNIC1_QM0_CP_DBG_0_1 0xD2040C 525 526 #define mmNIC1_QM0_CP_DBG_0_2 0xD20410 527 528 #define mmNIC1_QM0_CP_DBG_0_3 0xD20414 529 530 #define mmNIC1_QM0_CP_DBG_0_4 0xD20418 531 532 #define mmNIC1_QM0_CP_ARUSER_31_11_0 0xD2041C 533 534 #define mmNIC1_QM0_CP_ARUSER_31_11_1 0xD20420 535 536 #define mmNIC1_QM0_CP_ARUSER_31_11_2 0xD20424 537 538 #define mmNIC1_QM0_CP_ARUSER_31_11_3 0xD20428 539 540 #define mmNIC1_QM0_CP_ARUSER_31_11_4 0xD2042C 541 542 #define mmNIC1_QM0_CP_AWUSER_31_11_0 0xD20430 543 544 #define mmNIC1_QM0_CP_AWUSER_31_11_1 0xD20434 545 546 #define mmNIC1_QM0_CP_AWUSER_31_11_2 0xD20438 547 548 #define mmNIC1_QM0_CP_AWUSER_31_11_3 0xD2043C 549 550 #define mmNIC1_QM0_CP_AWUSER_31_11_4 0xD20440 551 552 #define mmNIC1_QM0_ARB_CFG_0 0xD20A00 553 554 #define mmNIC1_QM0_ARB_CHOISE_Q_PUSH 0xD20A04 555 556 #define mmNIC1_QM0_ARB_WRR_WEIGHT_0 0xD20A08 557 558 #define mmNIC1_QM0_ARB_WRR_WEIGHT_1 0xD20A0C 559 560 #define mmNIC1_QM0_ARB_WRR_WEIGHT_2 0xD20A10 561 562 #define mmNIC1_QM0_ARB_WRR_WEIGHT_3 0xD20A14 563 564 #define mmNIC1_QM0_ARB_CFG_1 0xD20A18 565 566 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_0 0xD20A20 567 568 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_1 0xD20A24 569 570 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_2 0xD20A28 571 572 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_3 0xD20A2C 573 574 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_4 0xD20A30 575 576 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_5 0xD20A34 577 578 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_6 0xD20A38 579 580 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_7 0xD20A3C 581 582 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_8 0xD20A40 583 584 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_9 0xD20A44 585 586 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_10 0xD20A48 587 588 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_11 0xD20A4C 589 590 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_12 0xD20A50 591 592 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_13 0xD20A54 593 594 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_14 0xD20A58 595 596 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_15 0xD20A5C 597 598 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_16 0xD20A60 599 600 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_17 0xD20A64 601 602 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_18 0xD20A68 603 604 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_19 0xD20A6C 605 606 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_20 0xD20A70 607 608 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_21 0xD20A74 609 610 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_22 0xD20A78 611 612 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_23 0xD20A7C 613 614 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_24 0xD20A80 615 616 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_25 0xD20A84 617 618 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_26 0xD20A88 619 620 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_27 0xD20A8C 621 622 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_28 0xD20A90 623 624 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_29 0xD20A94 625 626 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_30 0xD20A98 627 628 #define mmNIC1_QM0_ARB_MST_AVAIL_CRED_31 0xD20A9C 629 630 #define mmNIC1_QM0_ARB_MST_CRED_INC 0xD20AA0 631 632 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xD20AA4 633 634 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xD20AA8 635 636 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xD20AAC 637 638 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xD20AB0 639 640 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xD20AB4 641 642 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xD20AB8 643 644 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xD20ABC 645 646 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xD20AC0 647 648 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xD20AC4 649 650 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xD20AC8 651 652 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xD20ACC 653 654 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xD20AD0 655 656 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xD20AD4 657 658 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xD20AD8 659 660 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xD20ADC 661 662 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xD20AE0 663 664 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xD20AE4 665 666 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xD20AE8 667 668 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xD20AEC 669 670 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xD20AF0 671 672 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xD20AF4 673 674 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xD20AF8 675 676 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xD20AFC 677 678 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xD20B00 679 680 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xD20B04 681 682 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xD20B08 683 684 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xD20B0C 685 686 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xD20B10 687 688 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xD20B14 689 690 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xD20B18 691 692 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xD20B1C 693 694 #define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xD20B20 695 696 #define mmNIC1_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xD20B28 697 698 #define mmNIC1_QM0_ARB_MST_SLAVE_EN 0xD20B2C 699 700 #define mmNIC1_QM0_ARB_MST_QUIET_PER 0xD20B34 701 702 #define mmNIC1_QM0_ARB_SLV_CHOISE_WDT 0xD20B38 703 704 #define mmNIC1_QM0_ARB_SLV_ID 0xD20B3C 705 706 #define mmNIC1_QM0_ARB_MSG_MAX_INFLIGHT 0xD20B44 707 708 #define mmNIC1_QM0_ARB_MSG_AWUSER_31_11 0xD20B48 709 710 #define mmNIC1_QM0_ARB_MSG_AWUSER_SEC_PROP 0xD20B4C 711 712 #define mmNIC1_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xD20B50 713 714 #define mmNIC1_QM0_ARB_BASE_LO 0xD20B54 715 716 #define mmNIC1_QM0_ARB_BASE_HI 0xD20B58 717 718 #define mmNIC1_QM0_ARB_STATE_STS 0xD20B80 719 720 #define mmNIC1_QM0_ARB_CHOISE_FULLNESS_STS 0xD20B84 721 722 #define mmNIC1_QM0_ARB_MSG_STS 0xD20B88 723 724 #define mmNIC1_QM0_ARB_SLV_CHOISE_Q_HEAD 0xD20B8C 725 726 #define mmNIC1_QM0_ARB_ERR_CAUSE 0xD20B9C 727 728 #define mmNIC1_QM0_ARB_ERR_MSG_EN 0xD20BA0 729 730 #define mmNIC1_QM0_ARB_ERR_STS_DRP 0xD20BA8 731 732 #define mmNIC1_QM0_ARB_MST_CRED_STS_0 0xD20BB0 733 734 #define mmNIC1_QM0_ARB_MST_CRED_STS_1 0xD20BB4 735 736 #define mmNIC1_QM0_ARB_MST_CRED_STS_2 0xD20BB8 737 738 #define mmNIC1_QM0_ARB_MST_CRED_STS_3 0xD20BBC 739 740 #define mmNIC1_QM0_ARB_MST_CRED_STS_4 0xD20BC0 741 742 #define mmNIC1_QM0_ARB_MST_CRED_STS_5 0xD20BC4 743 744 #define mmNIC1_QM0_ARB_MST_CRED_STS_6 0xD20BC8 745 746 #define mmNIC1_QM0_ARB_MST_CRED_STS_7 0xD20BCC 747 748 #define mmNIC1_QM0_ARB_MST_CRED_STS_8 0xD20BD0 749 750 #define mmNIC1_QM0_ARB_MST_CRED_STS_9 0xD20BD4 751 752 #define mmNIC1_QM0_ARB_MST_CRED_STS_10 0xD20BD8 753 754 #define mmNIC1_QM0_ARB_MST_CRED_STS_11 0xD20BDC 755 756 #define mmNIC1_QM0_ARB_MST_CRED_STS_12 0xD20BE0 757 758 #define mmNIC1_QM0_ARB_MST_CRED_STS_13 0xD20BE4 759 760 #define mmNIC1_QM0_ARB_MST_CRED_STS_14 0xD20BE8 761 762 #define mmNIC1_QM0_ARB_MST_CRED_STS_15 0xD20BEC 763 764 #define mmNIC1_QM0_ARB_MST_CRED_STS_16 0xD20BF0 765 766 #define mmNIC1_QM0_ARB_MST_CRED_STS_17 0xD20BF4 767 768 #define mmNIC1_QM0_ARB_MST_CRED_STS_18 0xD20BF8 769 770 #define mmNIC1_QM0_ARB_MST_CRED_STS_19 0xD20BFC 771 772 #define mmNIC1_QM0_ARB_MST_CRED_STS_20 0xD20C00 773 774 #define mmNIC1_QM0_ARB_MST_CRED_STS_21 0xD20C04 775 776 #define mmNIC1_QM0_ARB_MST_CRED_STS_22 0xD20C08 777 778 #define mmNIC1_QM0_ARB_MST_CRED_STS_23 0xD20C0C 779 780 #define mmNIC1_QM0_ARB_MST_CRED_STS_24 0xD20C10 781 782 #define mmNIC1_QM0_ARB_MST_CRED_STS_25 0xD20C14 783 784 #define mmNIC1_QM0_ARB_MST_CRED_STS_26 0xD20C18 785 786 #define mmNIC1_QM0_ARB_MST_CRED_STS_27 0xD20C1C 787 788 #define mmNIC1_QM0_ARB_MST_CRED_STS_28 0xD20C20 789 790 #define mmNIC1_QM0_ARB_MST_CRED_STS_29 0xD20C24 791 792 #define mmNIC1_QM0_ARB_MST_CRED_STS_30 0xD20C28 793 794 #define mmNIC1_QM0_ARB_MST_CRED_STS_31 0xD20C2C 795 796 #define mmNIC1_QM0_CGM_CFG 0xD20C70 797 798 #define mmNIC1_QM0_CGM_STS 0xD20C74 799 800 #define mmNIC1_QM0_CGM_CFG1 0xD20C78 801 802 #define mmNIC1_QM0_LOCAL_RANGE_BASE 0xD20C80 803 804 #define mmNIC1_QM0_LOCAL_RANGE_SIZE 0xD20C84 805 806 #define mmNIC1_QM0_CSMR_STRICT_PRIO_CFG 0xD20C90 807 808 #define mmNIC1_QM0_HBW_RD_RATE_LIM_CFG_1 0xD20C94 809 810 #define mmNIC1_QM0_LBW_WR_RATE_LIM_CFG_0 0xD20C98 811 812 #define mmNIC1_QM0_LBW_WR_RATE_LIM_CFG_1 0xD20C9C 813 814 #define mmNIC1_QM0_HBW_RD_RATE_LIM_CFG_0 0xD20CA0 815 816 #define mmNIC1_QM0_GLBL_AXCACHE 0xD20CA4 817 818 #define mmNIC1_QM0_IND_GW_APB_CFG 0xD20CB0 819 820 #define mmNIC1_QM0_IND_GW_APB_WDATA 0xD20CB4 821 822 #define mmNIC1_QM0_IND_GW_APB_RDATA 0xD20CB8 823 824 #define mmNIC1_QM0_IND_GW_APB_STATUS 0xD20CBC 825 826 #define mmNIC1_QM0_GLBL_ERR_ADDR_LO 0xD20CD0 827 828 #define mmNIC1_QM0_GLBL_ERR_ADDR_HI 0xD20CD4 829 830 #define mmNIC1_QM0_GLBL_ERR_WDATA 0xD20CD8 831 832 #define mmNIC1_QM0_GLBL_MEM_INIT_BUSY 0xD20D00 833 834 #endif /* ASIC_REG_NIC1_QM0_REGS_H_ */ 835