1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DMA3_QM_REGS_H_ 14 #define ASIC_REG_DMA3_QM_REGS_H_ 15 16 /* 17 ***************************************** 18 * DMA3_QM (Prototype: QMAN) 19 ***************************************** 20 */ 21 22 #define mmDMA3_QM_GLBL_CFG0 0x568000 23 24 #define mmDMA3_QM_GLBL_CFG1 0x568004 25 26 #define mmDMA3_QM_GLBL_PROT 0x568008 27 28 #define mmDMA3_QM_GLBL_ERR_CFG 0x56800C 29 30 #define mmDMA3_QM_GLBL_SECURE_PROPS_0 0x568010 31 32 #define mmDMA3_QM_GLBL_SECURE_PROPS_1 0x568014 33 34 #define mmDMA3_QM_GLBL_SECURE_PROPS_2 0x568018 35 36 #define mmDMA3_QM_GLBL_SECURE_PROPS_3 0x56801C 37 38 #define mmDMA3_QM_GLBL_SECURE_PROPS_4 0x568020 39 40 #define mmDMA3_QM_GLBL_NON_SECURE_PROPS_0 0x568024 41 42 #define mmDMA3_QM_GLBL_NON_SECURE_PROPS_1 0x568028 43 44 #define mmDMA3_QM_GLBL_NON_SECURE_PROPS_2 0x56802C 45 46 #define mmDMA3_QM_GLBL_NON_SECURE_PROPS_3 0x568030 47 48 #define mmDMA3_QM_GLBL_NON_SECURE_PROPS_4 0x568034 49 50 #define mmDMA3_QM_GLBL_STS0 0x568038 51 52 #define mmDMA3_QM_GLBL_STS1_0 0x568040 53 54 #define mmDMA3_QM_GLBL_STS1_1 0x568044 55 56 #define mmDMA3_QM_GLBL_STS1_2 0x568048 57 58 #define mmDMA3_QM_GLBL_STS1_3 0x56804C 59 60 #define mmDMA3_QM_GLBL_STS1_4 0x568050 61 62 #define mmDMA3_QM_GLBL_MSG_EN_0 0x568054 63 64 #define mmDMA3_QM_GLBL_MSG_EN_1 0x568058 65 66 #define mmDMA3_QM_GLBL_MSG_EN_2 0x56805C 67 68 #define mmDMA3_QM_GLBL_MSG_EN_3 0x568060 69 70 #define mmDMA3_QM_GLBL_MSG_EN_4 0x568068 71 72 #define mmDMA3_QM_PQ_BASE_LO_0 0x568070 73 74 #define mmDMA3_QM_PQ_BASE_LO_1 0x568074 75 76 #define mmDMA3_QM_PQ_BASE_LO_2 0x568078 77 78 #define mmDMA3_QM_PQ_BASE_LO_3 0x56807C 79 80 #define mmDMA3_QM_PQ_BASE_HI_0 0x568080 81 82 #define mmDMA3_QM_PQ_BASE_HI_1 0x568084 83 84 #define mmDMA3_QM_PQ_BASE_HI_2 0x568088 85 86 #define mmDMA3_QM_PQ_BASE_HI_3 0x56808C 87 88 #define mmDMA3_QM_PQ_SIZE_0 0x568090 89 90 #define mmDMA3_QM_PQ_SIZE_1 0x568094 91 92 #define mmDMA3_QM_PQ_SIZE_2 0x568098 93 94 #define mmDMA3_QM_PQ_SIZE_3 0x56809C 95 96 #define mmDMA3_QM_PQ_PI_0 0x5680A0 97 98 #define mmDMA3_QM_PQ_PI_1 0x5680A4 99 100 #define mmDMA3_QM_PQ_PI_2 0x5680A8 101 102 #define mmDMA3_QM_PQ_PI_3 0x5680AC 103 104 #define mmDMA3_QM_PQ_CI_0 0x5680B0 105 106 #define mmDMA3_QM_PQ_CI_1 0x5680B4 107 108 #define mmDMA3_QM_PQ_CI_2 0x5680B8 109 110 #define mmDMA3_QM_PQ_CI_3 0x5680BC 111 112 #define mmDMA3_QM_PQ_CFG0_0 0x5680C0 113 114 #define mmDMA3_QM_PQ_CFG0_1 0x5680C4 115 116 #define mmDMA3_QM_PQ_CFG0_2 0x5680C8 117 118 #define mmDMA3_QM_PQ_CFG0_3 0x5680CC 119 120 #define mmDMA3_QM_PQ_CFG1_0 0x5680D0 121 122 #define mmDMA3_QM_PQ_CFG1_1 0x5680D4 123 124 #define mmDMA3_QM_PQ_CFG1_2 0x5680D8 125 126 #define mmDMA3_QM_PQ_CFG1_3 0x5680DC 127 128 #define mmDMA3_QM_PQ_ARUSER_31_11_0 0x5680E0 129 130 #define mmDMA3_QM_PQ_ARUSER_31_11_1 0x5680E4 131 132 #define mmDMA3_QM_PQ_ARUSER_31_11_2 0x5680E8 133 134 #define mmDMA3_QM_PQ_ARUSER_31_11_3 0x5680EC 135 136 #define mmDMA3_QM_PQ_STS0_0 0x5680F0 137 138 #define mmDMA3_QM_PQ_STS0_1 0x5680F4 139 140 #define mmDMA3_QM_PQ_STS0_2 0x5680F8 141 142 #define mmDMA3_QM_PQ_STS0_3 0x5680FC 143 144 #define mmDMA3_QM_PQ_STS1_0 0x568100 145 146 #define mmDMA3_QM_PQ_STS1_1 0x568104 147 148 #define mmDMA3_QM_PQ_STS1_2 0x568108 149 150 #define mmDMA3_QM_PQ_STS1_3 0x56810C 151 152 #define mmDMA3_QM_CQ_CFG0_0 0x568110 153 154 #define mmDMA3_QM_CQ_CFG0_1 0x568114 155 156 #define mmDMA3_QM_CQ_CFG0_2 0x568118 157 158 #define mmDMA3_QM_CQ_CFG0_3 0x56811C 159 160 #define mmDMA3_QM_CQ_CFG0_4 0x568120 161 162 #define mmDMA3_QM_CQ_CFG1_0 0x568124 163 164 #define mmDMA3_QM_CQ_CFG1_1 0x568128 165 166 #define mmDMA3_QM_CQ_CFG1_2 0x56812C 167 168 #define mmDMA3_QM_CQ_CFG1_3 0x568130 169 170 #define mmDMA3_QM_CQ_CFG1_4 0x568134 171 172 #define mmDMA3_QM_CQ_ARUSER_31_11_0 0x568138 173 174 #define mmDMA3_QM_CQ_ARUSER_31_11_1 0x56813C 175 176 #define mmDMA3_QM_CQ_ARUSER_31_11_2 0x568140 177 178 #define mmDMA3_QM_CQ_ARUSER_31_11_3 0x568144 179 180 #define mmDMA3_QM_CQ_ARUSER_31_11_4 0x568148 181 182 #define mmDMA3_QM_CQ_STS0_0 0x56814C 183 184 #define mmDMA3_QM_CQ_STS0_1 0x568150 185 186 #define mmDMA3_QM_CQ_STS0_2 0x568154 187 188 #define mmDMA3_QM_CQ_STS0_3 0x568158 189 190 #define mmDMA3_QM_CQ_STS0_4 0x56815C 191 192 #define mmDMA3_QM_CQ_STS1_0 0x568160 193 194 #define mmDMA3_QM_CQ_STS1_1 0x568164 195 196 #define mmDMA3_QM_CQ_STS1_2 0x568168 197 198 #define mmDMA3_QM_CQ_STS1_3 0x56816C 199 200 #define mmDMA3_QM_CQ_STS1_4 0x568170 201 202 #define mmDMA3_QM_CQ_PTR_LO_0 0x568174 203 204 #define mmDMA3_QM_CQ_PTR_HI_0 0x568178 205 206 #define mmDMA3_QM_CQ_TSIZE_0 0x56817C 207 208 #define mmDMA3_QM_CQ_CTL_0 0x568180 209 210 #define mmDMA3_QM_CQ_PTR_LO_1 0x568184 211 212 #define mmDMA3_QM_CQ_PTR_HI_1 0x568188 213 214 #define mmDMA3_QM_CQ_TSIZE_1 0x56818C 215 216 #define mmDMA3_QM_CQ_CTL_1 0x568190 217 218 #define mmDMA3_QM_CQ_PTR_LO_2 0x568194 219 220 #define mmDMA3_QM_CQ_PTR_HI_2 0x568198 221 222 #define mmDMA3_QM_CQ_TSIZE_2 0x56819C 223 224 #define mmDMA3_QM_CQ_CTL_2 0x5681A0 225 226 #define mmDMA3_QM_CQ_PTR_LO_3 0x5681A4 227 228 #define mmDMA3_QM_CQ_PTR_HI_3 0x5681A8 229 230 #define mmDMA3_QM_CQ_TSIZE_3 0x5681AC 231 232 #define mmDMA3_QM_CQ_CTL_3 0x5681B0 233 234 #define mmDMA3_QM_CQ_PTR_LO_4 0x5681B4 235 236 #define mmDMA3_QM_CQ_PTR_HI_4 0x5681B8 237 238 #define mmDMA3_QM_CQ_TSIZE_4 0x5681BC 239 240 #define mmDMA3_QM_CQ_CTL_4 0x5681C0 241 242 #define mmDMA3_QM_CQ_PTR_LO_STS_0 0x5681C4 243 244 #define mmDMA3_QM_CQ_PTR_LO_STS_1 0x5681C8 245 246 #define mmDMA3_QM_CQ_PTR_LO_STS_2 0x5681CC 247 248 #define mmDMA3_QM_CQ_PTR_LO_STS_3 0x5681D0 249 250 #define mmDMA3_QM_CQ_PTR_LO_STS_4 0x5681D4 251 252 #define mmDMA3_QM_CQ_PTR_HI_STS_0 0x5681D8 253 254 #define mmDMA3_QM_CQ_PTR_HI_STS_1 0x5681DC 255 256 #define mmDMA3_QM_CQ_PTR_HI_STS_2 0x5681E0 257 258 #define mmDMA3_QM_CQ_PTR_HI_STS_3 0x5681E4 259 260 #define mmDMA3_QM_CQ_PTR_HI_STS_4 0x5681E8 261 262 #define mmDMA3_QM_CQ_TSIZE_STS_0 0x5681EC 263 264 #define mmDMA3_QM_CQ_TSIZE_STS_1 0x5681F0 265 266 #define mmDMA3_QM_CQ_TSIZE_STS_2 0x5681F4 267 268 #define mmDMA3_QM_CQ_TSIZE_STS_3 0x5681F8 269 270 #define mmDMA3_QM_CQ_TSIZE_STS_4 0x5681FC 271 272 #define mmDMA3_QM_CQ_CTL_STS_0 0x568200 273 274 #define mmDMA3_QM_CQ_CTL_STS_1 0x568204 275 276 #define mmDMA3_QM_CQ_CTL_STS_2 0x568208 277 278 #define mmDMA3_QM_CQ_CTL_STS_3 0x56820C 279 280 #define mmDMA3_QM_CQ_CTL_STS_4 0x568210 281 282 #define mmDMA3_QM_CQ_IFIFO_CNT_0 0x568214 283 284 #define mmDMA3_QM_CQ_IFIFO_CNT_1 0x568218 285 286 #define mmDMA3_QM_CQ_IFIFO_CNT_2 0x56821C 287 288 #define mmDMA3_QM_CQ_IFIFO_CNT_3 0x568220 289 290 #define mmDMA3_QM_CQ_IFIFO_CNT_4 0x568224 291 292 #define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_0 0x568228 293 294 #define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_1 0x56822C 295 296 #define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_2 0x568230 297 298 #define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_3 0x568234 299 300 #define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_4 0x568238 301 302 #define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_0 0x56823C 303 304 #define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_1 0x568240 305 306 #define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_2 0x568244 307 308 #define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_3 0x568248 309 310 #define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_4 0x56824C 311 312 #define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_0 0x568250 313 314 #define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_1 0x568254 315 316 #define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_2 0x568258 317 318 #define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_3 0x56825C 319 320 #define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_4 0x568260 321 322 #define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_0 0x568264 323 324 #define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_1 0x568268 325 326 #define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_2 0x56826C 327 328 #define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_3 0x568270 329 330 #define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_4 0x568274 331 332 #define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_0 0x568278 333 334 #define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_1 0x56827C 335 336 #define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 0x568280 337 338 #define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_3 0x568284 339 340 #define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_4 0x568288 341 342 #define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_0 0x56828C 343 344 #define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_1 0x568290 345 346 #define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_2 0x568294 347 348 #define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_3 0x568298 349 350 #define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_4 0x56829C 351 352 #define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_0 0x5682A0 353 354 #define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_1 0x5682A4 355 356 #define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_2 0x5682A8 357 358 #define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_3 0x5682AC 359 360 #define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_4 0x5682B0 361 362 #define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_0 0x5682B4 363 364 #define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_1 0x5682B8 365 366 #define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_2 0x5682BC 367 368 #define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_3 0x5682C0 369 370 #define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_4 0x5682C4 371 372 #define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_0 0x5682C8 373 374 #define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_1 0x5682CC 375 376 #define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_2 0x5682D0 377 378 #define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_3 0x5682D4 379 380 #define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_4 0x5682D8 381 382 #define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5682E0 383 384 #define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5682E4 385 386 #define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5682E8 387 388 #define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5682EC 389 390 #define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5682F0 391 392 #define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5682F4 393 394 #define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5682F8 395 396 #define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5682FC 397 398 #define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x568300 399 400 #define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x568304 401 402 #define mmDMA3_QM_CP_FENCE0_RDATA_0 0x568308 403 404 #define mmDMA3_QM_CP_FENCE0_RDATA_1 0x56830C 405 406 #define mmDMA3_QM_CP_FENCE0_RDATA_2 0x568310 407 408 #define mmDMA3_QM_CP_FENCE0_RDATA_3 0x568314 409 410 #define mmDMA3_QM_CP_FENCE0_RDATA_4 0x568318 411 412 #define mmDMA3_QM_CP_FENCE1_RDATA_0 0x56831C 413 414 #define mmDMA3_QM_CP_FENCE1_RDATA_1 0x568320 415 416 #define mmDMA3_QM_CP_FENCE1_RDATA_2 0x568324 417 418 #define mmDMA3_QM_CP_FENCE1_RDATA_3 0x568328 419 420 #define mmDMA3_QM_CP_FENCE1_RDATA_4 0x56832C 421 422 #define mmDMA3_QM_CP_FENCE2_RDATA_0 0x568330 423 424 #define mmDMA3_QM_CP_FENCE2_RDATA_1 0x568334 425 426 #define mmDMA3_QM_CP_FENCE2_RDATA_2 0x568338 427 428 #define mmDMA3_QM_CP_FENCE2_RDATA_3 0x56833C 429 430 #define mmDMA3_QM_CP_FENCE2_RDATA_4 0x568340 431 432 #define mmDMA3_QM_CP_FENCE3_RDATA_0 0x568344 433 434 #define mmDMA3_QM_CP_FENCE3_RDATA_1 0x568348 435 436 #define mmDMA3_QM_CP_FENCE3_RDATA_2 0x56834C 437 438 #define mmDMA3_QM_CP_FENCE3_RDATA_3 0x568350 439 440 #define mmDMA3_QM_CP_FENCE3_RDATA_4 0x568354 441 442 #define mmDMA3_QM_CP_FENCE0_CNT_0 0x568358 443 444 #define mmDMA3_QM_CP_FENCE0_CNT_1 0x56835C 445 446 #define mmDMA3_QM_CP_FENCE0_CNT_2 0x568360 447 448 #define mmDMA3_QM_CP_FENCE0_CNT_3 0x568364 449 450 #define mmDMA3_QM_CP_FENCE0_CNT_4 0x568368 451 452 #define mmDMA3_QM_CP_FENCE1_CNT_0 0x56836C 453 454 #define mmDMA3_QM_CP_FENCE1_CNT_1 0x568370 455 456 #define mmDMA3_QM_CP_FENCE1_CNT_2 0x568374 457 458 #define mmDMA3_QM_CP_FENCE1_CNT_3 0x568378 459 460 #define mmDMA3_QM_CP_FENCE1_CNT_4 0x56837C 461 462 #define mmDMA3_QM_CP_FENCE2_CNT_0 0x568380 463 464 #define mmDMA3_QM_CP_FENCE2_CNT_1 0x568384 465 466 #define mmDMA3_QM_CP_FENCE2_CNT_2 0x568388 467 468 #define mmDMA3_QM_CP_FENCE2_CNT_3 0x56838C 469 470 #define mmDMA3_QM_CP_FENCE2_CNT_4 0x568390 471 472 #define mmDMA3_QM_CP_FENCE3_CNT_0 0x568394 473 474 #define mmDMA3_QM_CP_FENCE3_CNT_1 0x568398 475 476 #define mmDMA3_QM_CP_FENCE3_CNT_2 0x56839C 477 478 #define mmDMA3_QM_CP_FENCE3_CNT_3 0x5683A0 479 480 #define mmDMA3_QM_CP_FENCE3_CNT_4 0x5683A4 481 482 #define mmDMA3_QM_CP_STS_0 0x5683A8 483 484 #define mmDMA3_QM_CP_STS_1 0x5683AC 485 486 #define mmDMA3_QM_CP_STS_2 0x5683B0 487 488 #define mmDMA3_QM_CP_STS_3 0x5683B4 489 490 #define mmDMA3_QM_CP_STS_4 0x5683B8 491 492 #define mmDMA3_QM_CP_CURRENT_INST_LO_0 0x5683BC 493 494 #define mmDMA3_QM_CP_CURRENT_INST_LO_1 0x5683C0 495 496 #define mmDMA3_QM_CP_CURRENT_INST_LO_2 0x5683C4 497 498 #define mmDMA3_QM_CP_CURRENT_INST_LO_3 0x5683C8 499 500 #define mmDMA3_QM_CP_CURRENT_INST_LO_4 0x5683CC 501 502 #define mmDMA3_QM_CP_CURRENT_INST_HI_0 0x5683D0 503 504 #define mmDMA3_QM_CP_CURRENT_INST_HI_1 0x5683D4 505 506 #define mmDMA3_QM_CP_CURRENT_INST_HI_2 0x5683D8 507 508 #define mmDMA3_QM_CP_CURRENT_INST_HI_3 0x5683DC 509 510 #define mmDMA3_QM_CP_CURRENT_INST_HI_4 0x5683E0 511 512 #define mmDMA3_QM_CP_BARRIER_CFG_0 0x5683F4 513 514 #define mmDMA3_QM_CP_BARRIER_CFG_1 0x5683F8 515 516 #define mmDMA3_QM_CP_BARRIER_CFG_2 0x5683FC 517 518 #define mmDMA3_QM_CP_BARRIER_CFG_3 0x568400 519 520 #define mmDMA3_QM_CP_BARRIER_CFG_4 0x568404 521 522 #define mmDMA3_QM_CP_DBG_0_0 0x568408 523 524 #define mmDMA3_QM_CP_DBG_0_1 0x56840C 525 526 #define mmDMA3_QM_CP_DBG_0_2 0x568410 527 528 #define mmDMA3_QM_CP_DBG_0_3 0x568414 529 530 #define mmDMA3_QM_CP_DBG_0_4 0x568418 531 532 #define mmDMA3_QM_CP_ARUSER_31_11_0 0x56841C 533 534 #define mmDMA3_QM_CP_ARUSER_31_11_1 0x568420 535 536 #define mmDMA3_QM_CP_ARUSER_31_11_2 0x568424 537 538 #define mmDMA3_QM_CP_ARUSER_31_11_3 0x568428 539 540 #define mmDMA3_QM_CP_ARUSER_31_11_4 0x56842C 541 542 #define mmDMA3_QM_CP_AWUSER_31_11_0 0x568430 543 544 #define mmDMA3_QM_CP_AWUSER_31_11_1 0x568434 545 546 #define mmDMA3_QM_CP_AWUSER_31_11_2 0x568438 547 548 #define mmDMA3_QM_CP_AWUSER_31_11_3 0x56843C 549 550 #define mmDMA3_QM_CP_AWUSER_31_11_4 0x568440 551 552 #define mmDMA3_QM_ARB_CFG_0 0x568A00 553 554 #define mmDMA3_QM_ARB_CHOISE_Q_PUSH 0x568A04 555 556 #define mmDMA3_QM_ARB_WRR_WEIGHT_0 0x568A08 557 558 #define mmDMA3_QM_ARB_WRR_WEIGHT_1 0x568A0C 559 560 #define mmDMA3_QM_ARB_WRR_WEIGHT_2 0x568A10 561 562 #define mmDMA3_QM_ARB_WRR_WEIGHT_3 0x568A14 563 564 #define mmDMA3_QM_ARB_CFG_1 0x568A18 565 566 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_0 0x568A20 567 568 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_1 0x568A24 569 570 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_2 0x568A28 571 572 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_3 0x568A2C 573 574 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_4 0x568A30 575 576 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_5 0x568A34 577 578 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_6 0x568A38 579 580 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_7 0x568A3C 581 582 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_8 0x568A40 583 584 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_9 0x568A44 585 586 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_10 0x568A48 587 588 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_11 0x568A4C 589 590 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_12 0x568A50 591 592 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_13 0x568A54 593 594 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_14 0x568A58 595 596 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_15 0x568A5C 597 598 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_16 0x568A60 599 600 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_17 0x568A64 601 602 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_18 0x568A68 603 604 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_19 0x568A6C 605 606 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_20 0x568A70 607 608 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_21 0x568A74 609 610 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_22 0x568A78 611 612 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_23 0x568A7C 613 614 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_24 0x568A80 615 616 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_25 0x568A84 617 618 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_26 0x568A88 619 620 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_27 0x568A8C 621 622 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_28 0x568A90 623 624 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_29 0x568A94 625 626 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_30 0x568A98 627 628 #define mmDMA3_QM_ARB_MST_AVAIL_CRED_31 0x568A9C 629 630 #define mmDMA3_QM_ARB_MST_CRED_INC 0x568AA0 631 632 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x568AA4 633 634 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x568AA8 635 636 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x568AAC 637 638 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x568AB0 639 640 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x568AB4 641 642 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x568AB8 643 644 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x568ABC 645 646 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x568AC0 647 648 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x568AC4 649 650 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x568AC8 651 652 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x568ACC 653 654 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x568AD0 655 656 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x568AD4 657 658 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x568AD8 659 660 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x568ADC 661 662 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x568AE0 663 664 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x568AE4 665 666 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x568AE8 667 668 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x568AEC 669 670 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x568AF0 671 672 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x568AF4 673 674 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x568AF8 675 676 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x568AFC 677 678 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x568B00 679 680 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x568B04 681 682 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x568B08 683 684 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x568B0C 685 686 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x568B10 687 688 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x568B14 689 690 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x568B18 691 692 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x568B1C 693 694 #define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x568B20 695 696 #define mmDMA3_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x568B28 697 698 #define mmDMA3_QM_ARB_MST_SLAVE_EN 0x568B2C 699 700 #define mmDMA3_QM_ARB_MST_QUIET_PER 0x568B34 701 702 #define mmDMA3_QM_ARB_SLV_CHOISE_WDT 0x568B38 703 704 #define mmDMA3_QM_ARB_SLV_ID 0x568B3C 705 706 #define mmDMA3_QM_ARB_MSG_MAX_INFLIGHT 0x568B44 707 708 #define mmDMA3_QM_ARB_MSG_AWUSER_31_11 0x568B48 709 710 #define mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP 0x568B4C 711 712 #define mmDMA3_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x568B50 713 714 #define mmDMA3_QM_ARB_BASE_LO 0x568B54 715 716 #define mmDMA3_QM_ARB_BASE_HI 0x568B58 717 718 #define mmDMA3_QM_ARB_STATE_STS 0x568B80 719 720 #define mmDMA3_QM_ARB_CHOISE_FULLNESS_STS 0x568B84 721 722 #define mmDMA3_QM_ARB_MSG_STS 0x568B88 723 724 #define mmDMA3_QM_ARB_SLV_CHOISE_Q_HEAD 0x568B8C 725 726 #define mmDMA3_QM_ARB_ERR_CAUSE 0x568B9C 727 728 #define mmDMA3_QM_ARB_ERR_MSG_EN 0x568BA0 729 730 #define mmDMA3_QM_ARB_ERR_STS_DRP 0x568BA8 731 732 #define mmDMA3_QM_ARB_MST_CRED_STS_0 0x568BB0 733 734 #define mmDMA3_QM_ARB_MST_CRED_STS_1 0x568BB4 735 736 #define mmDMA3_QM_ARB_MST_CRED_STS_2 0x568BB8 737 738 #define mmDMA3_QM_ARB_MST_CRED_STS_3 0x568BBC 739 740 #define mmDMA3_QM_ARB_MST_CRED_STS_4 0x568BC0 741 742 #define mmDMA3_QM_ARB_MST_CRED_STS_5 0x568BC4 743 744 #define mmDMA3_QM_ARB_MST_CRED_STS_6 0x568BC8 745 746 #define mmDMA3_QM_ARB_MST_CRED_STS_7 0x568BCC 747 748 #define mmDMA3_QM_ARB_MST_CRED_STS_8 0x568BD0 749 750 #define mmDMA3_QM_ARB_MST_CRED_STS_9 0x568BD4 751 752 #define mmDMA3_QM_ARB_MST_CRED_STS_10 0x568BD8 753 754 #define mmDMA3_QM_ARB_MST_CRED_STS_11 0x568BDC 755 756 #define mmDMA3_QM_ARB_MST_CRED_STS_12 0x568BE0 757 758 #define mmDMA3_QM_ARB_MST_CRED_STS_13 0x568BE4 759 760 #define mmDMA3_QM_ARB_MST_CRED_STS_14 0x568BE8 761 762 #define mmDMA3_QM_ARB_MST_CRED_STS_15 0x568BEC 763 764 #define mmDMA3_QM_ARB_MST_CRED_STS_16 0x568BF0 765 766 #define mmDMA3_QM_ARB_MST_CRED_STS_17 0x568BF4 767 768 #define mmDMA3_QM_ARB_MST_CRED_STS_18 0x568BF8 769 770 #define mmDMA3_QM_ARB_MST_CRED_STS_19 0x568BFC 771 772 #define mmDMA3_QM_ARB_MST_CRED_STS_20 0x568C00 773 774 #define mmDMA3_QM_ARB_MST_CRED_STS_21 0x568C04 775 776 #define mmDMA3_QM_ARB_MST_CRED_STS_22 0x568C08 777 778 #define mmDMA3_QM_ARB_MST_CRED_STS_23 0x568C0C 779 780 #define mmDMA3_QM_ARB_MST_CRED_STS_24 0x568C10 781 782 #define mmDMA3_QM_ARB_MST_CRED_STS_25 0x568C14 783 784 #define mmDMA3_QM_ARB_MST_CRED_STS_26 0x568C18 785 786 #define mmDMA3_QM_ARB_MST_CRED_STS_27 0x568C1C 787 788 #define mmDMA3_QM_ARB_MST_CRED_STS_28 0x568C20 789 790 #define mmDMA3_QM_ARB_MST_CRED_STS_29 0x568C24 791 792 #define mmDMA3_QM_ARB_MST_CRED_STS_30 0x568C28 793 794 #define mmDMA3_QM_ARB_MST_CRED_STS_31 0x568C2C 795 796 #define mmDMA3_QM_CGM_CFG 0x568C70 797 798 #define mmDMA3_QM_CGM_STS 0x568C74 799 800 #define mmDMA3_QM_CGM_CFG1 0x568C78 801 802 #define mmDMA3_QM_LOCAL_RANGE_BASE 0x568C80 803 804 #define mmDMA3_QM_LOCAL_RANGE_SIZE 0x568C84 805 806 #define mmDMA3_QM_CSMR_STRICT_PRIO_CFG 0x568C90 807 808 #define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_1 0x568C94 809 810 #define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_0 0x568C98 811 812 #define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_1 0x568C9C 813 814 #define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_0 0x568CA0 815 816 #define mmDMA3_QM_GLBL_AXCACHE 0x568CA4 817 818 #define mmDMA3_QM_IND_GW_APB_CFG 0x568CB0 819 820 #define mmDMA3_QM_IND_GW_APB_WDATA 0x568CB4 821 822 #define mmDMA3_QM_IND_GW_APB_RDATA 0x568CB8 823 824 #define mmDMA3_QM_IND_GW_APB_STATUS 0x568CBC 825 826 #define mmDMA3_QM_GLBL_ERR_ADDR_LO 0x568CD0 827 828 #define mmDMA3_QM_GLBL_ERR_ADDR_HI 0x568CD4 829 830 #define mmDMA3_QM_GLBL_ERR_WDATA 0x568CD8 831 832 #define mmDMA3_QM_GLBL_MEM_INIT_BUSY 0x568D00 833 834 #endif /* ASIC_REG_DMA3_QM_REGS_H_ */ 835