1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
7 #include <linux/pci.h>
8 #include <linux/netdevice.h>
9 #include <linux/etherdevice.h>
10 #include <linux/ethtool.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/skbuff.h>
14 #include <linux/if_vlan.h>
15 #include <linux/if_bridge.h>
16 #include <linux/workqueue.h>
17 #include <linux/jiffies.h>
18 #include <linux/bitops.h>
19 #include <linux/list.h>
20 #include <linux/notifier.h>
21 #include <linux/dcbnl.h>
22 #include <linux/inetdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/jhash.h>
25 #include <linux/log2.h>
26 #include <linux/refcount.h>
27 #include <linux/rhashtable.h>
28 #include <net/switchdev.h>
29 #include <net/pkt_cls.h>
30 #include <net/netevent.h>
31 #include <net/addrconf.h>
32 #include <linux/ptp_classify.h>
33
34 #include "spectrum.h"
35 #include "pci.h"
36 #include "core.h"
37 #include "core_env.h"
38 #include "reg.h"
39 #include "port.h"
40 #include "trap.h"
41 #include "txheader.h"
42 #include "spectrum_cnt.h"
43 #include "spectrum_dpipe.h"
44 #include "spectrum_acl_flex_actions.h"
45 #include "spectrum_span.h"
46 #include "spectrum_ptp.h"
47 #include "spectrum_trap.h"
48
49 #define MLXSW_SP_FWREV_MINOR 2010
50 #define MLXSW_SP_FWREV_SUBMINOR 1006
51
52 #define MLXSW_SP1_FWREV_MAJOR 13
53 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
54
55 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
56 .major = MLXSW_SP1_FWREV_MAJOR,
57 .minor = MLXSW_SP_FWREV_MINOR,
58 .subminor = MLXSW_SP_FWREV_SUBMINOR,
59 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
60 };
61
62 #define MLXSW_SP1_FW_FILENAME \
63 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
64 "." __stringify(MLXSW_SP_FWREV_MINOR) \
65 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2"
66
67 #define MLXSW_SP2_FWREV_MAJOR 29
68
69 static const struct mlxsw_fw_rev mlxsw_sp2_fw_rev = {
70 .major = MLXSW_SP2_FWREV_MAJOR,
71 .minor = MLXSW_SP_FWREV_MINOR,
72 .subminor = MLXSW_SP_FWREV_SUBMINOR,
73 };
74
75 #define MLXSW_SP2_FW_FILENAME \
76 "mellanox/mlxsw_spectrum2-" __stringify(MLXSW_SP2_FWREV_MAJOR) \
77 "." __stringify(MLXSW_SP_FWREV_MINOR) \
78 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2"
79
80 #define MLXSW_SP3_FWREV_MAJOR 30
81
82 static const struct mlxsw_fw_rev mlxsw_sp3_fw_rev = {
83 .major = MLXSW_SP3_FWREV_MAJOR,
84 .minor = MLXSW_SP_FWREV_MINOR,
85 .subminor = MLXSW_SP_FWREV_SUBMINOR,
86 };
87
88 #define MLXSW_SP3_FW_FILENAME \
89 "mellanox/mlxsw_spectrum3-" __stringify(MLXSW_SP3_FWREV_MAJOR) \
90 "." __stringify(MLXSW_SP_FWREV_MINOR) \
91 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2"
92
93 #define MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME \
94 "mellanox/lc_ini_bundle_" \
95 __stringify(MLXSW_SP_FWREV_MINOR) "_" \
96 __stringify(MLXSW_SP_FWREV_SUBMINOR) ".bin"
97
98 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
99 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
100 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3";
101 static const char mlxsw_sp4_driver_name[] = "mlxsw_spectrum4";
102
103 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = {
104 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00
105 };
106 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = {
107 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00
108 };
109
110 /* tx_hdr_version
111 * Tx header version.
112 * Must be set to 1.
113 */
114 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
115
116 /* tx_hdr_ctl
117 * Packet control type.
118 * 0 - Ethernet control (e.g. EMADs, LACP)
119 * 1 - Ethernet data
120 */
121 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
122
123 /* tx_hdr_proto
124 * Packet protocol type. Must be set to 1 (Ethernet).
125 */
126 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
127
128 /* tx_hdr_rx_is_router
129 * Packet is sent from the router. Valid for data packets only.
130 */
131 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
132
133 /* tx_hdr_fid_valid
134 * Indicates if the 'fid' field is valid and should be used for
135 * forwarding lookup. Valid for data packets only.
136 */
137 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
138
139 /* tx_hdr_swid
140 * Switch partition ID. Must be set to 0.
141 */
142 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
143
144 /* tx_hdr_control_tclass
145 * Indicates if the packet should use the control TClass and not one
146 * of the data TClasses.
147 */
148 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
149
150 /* tx_hdr_etclass
151 * Egress TClass to be used on the egress device on the egress port.
152 */
153 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
154
155 /* tx_hdr_port_mid
156 * Destination local port for unicast packets.
157 * Destination multicast ID for multicast packets.
158 *
159 * Control packets are directed to a specific egress port, while data
160 * packets are transmitted through the CPU port (0) into the switch partition,
161 * where forwarding rules are applied.
162 */
163 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
164
165 /* tx_hdr_fid
166 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
167 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
168 * Valid for data packets only.
169 */
170 MLXSW_ITEM32(tx, hdr, fid, 0x08, 16, 16);
171
172 /* tx_hdr_type
173 * 0 - Data packets
174 * 6 - Control packets
175 */
176 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
177
mlxsw_sp_flow_counter_get(struct mlxsw_sp * mlxsw_sp,unsigned int counter_index,u64 * packets,u64 * bytes)178 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
179 unsigned int counter_index, u64 *packets,
180 u64 *bytes)
181 {
182 char mgpc_pl[MLXSW_REG_MGPC_LEN];
183 int err;
184
185 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
186 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
187 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
188 if (err)
189 return err;
190 if (packets)
191 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
192 if (bytes)
193 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
194 return 0;
195 }
196
mlxsw_sp_flow_counter_clear(struct mlxsw_sp * mlxsw_sp,unsigned int counter_index)197 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
198 unsigned int counter_index)
199 {
200 char mgpc_pl[MLXSW_REG_MGPC_LEN];
201
202 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
203 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
204 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
205 }
206
mlxsw_sp_flow_counter_alloc(struct mlxsw_sp * mlxsw_sp,unsigned int * p_counter_index)207 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
208 unsigned int *p_counter_index)
209 {
210 int err;
211
212 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
213 p_counter_index);
214 if (err)
215 return err;
216 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
217 if (err)
218 goto err_counter_clear;
219 return 0;
220
221 err_counter_clear:
222 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
223 *p_counter_index);
224 return err;
225 }
226
mlxsw_sp_flow_counter_free(struct mlxsw_sp * mlxsw_sp,unsigned int counter_index)227 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
228 unsigned int counter_index)
229 {
230 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
231 counter_index);
232 }
233
mlxsw_sp_txhdr_construct(struct sk_buff * skb,const struct mlxsw_tx_info * tx_info)234 void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
235 const struct mlxsw_tx_info *tx_info)
236 {
237 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
238
239 memset(txhdr, 0, MLXSW_TXHDR_LEN);
240
241 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
242 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
243 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
244 mlxsw_tx_hdr_swid_set(txhdr, 0);
245 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
246 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
247 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
248 }
249
250 int
mlxsw_sp_txhdr_ptp_data_construct(struct mlxsw_core * mlxsw_core,struct mlxsw_sp_port * mlxsw_sp_port,struct sk_buff * skb,const struct mlxsw_tx_info * tx_info)251 mlxsw_sp_txhdr_ptp_data_construct(struct mlxsw_core *mlxsw_core,
252 struct mlxsw_sp_port *mlxsw_sp_port,
253 struct sk_buff *skb,
254 const struct mlxsw_tx_info *tx_info)
255 {
256 char *txhdr;
257 u16 max_fid;
258 int err;
259
260 if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
261 err = -ENOMEM;
262 goto err_skb_cow_head;
263 }
264
265 if (!MLXSW_CORE_RES_VALID(mlxsw_core, FID)) {
266 err = -EIO;
267 goto err_res_valid;
268 }
269 max_fid = MLXSW_CORE_RES_GET(mlxsw_core, FID);
270
271 txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
272 memset(txhdr, 0, MLXSW_TXHDR_LEN);
273
274 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
275 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
276 mlxsw_tx_hdr_rx_is_router_set(txhdr, true);
277 mlxsw_tx_hdr_fid_valid_set(txhdr, true);
278 mlxsw_tx_hdr_fid_set(txhdr, max_fid + tx_info->local_port - 1);
279 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_DATA);
280 return 0;
281
282 err_res_valid:
283 err_skb_cow_head:
284 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
285 dev_kfree_skb_any(skb);
286 return err;
287 }
288
mlxsw_sp_skb_requires_ts(struct sk_buff * skb)289 static bool mlxsw_sp_skb_requires_ts(struct sk_buff *skb)
290 {
291 unsigned int type;
292
293 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
294 return false;
295
296 type = ptp_classify_raw(skb);
297 return !!ptp_parse_header(skb, type);
298 }
299
mlxsw_sp_txhdr_handle(struct mlxsw_core * mlxsw_core,struct mlxsw_sp_port * mlxsw_sp_port,struct sk_buff * skb,const struct mlxsw_tx_info * tx_info)300 static int mlxsw_sp_txhdr_handle(struct mlxsw_core *mlxsw_core,
301 struct mlxsw_sp_port *mlxsw_sp_port,
302 struct sk_buff *skb,
303 const struct mlxsw_tx_info *tx_info)
304 {
305 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
306
307 /* In Spectrum-2 and Spectrum-3, PTP events that require a time stamp
308 * need special handling and cannot be transmitted as regular control
309 * packets.
310 */
311 if (unlikely(mlxsw_sp_skb_requires_ts(skb)))
312 return mlxsw_sp->ptp_ops->txhdr_construct(mlxsw_core,
313 mlxsw_sp_port, skb,
314 tx_info);
315
316 if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
317 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
318 dev_kfree_skb_any(skb);
319 return -ENOMEM;
320 }
321
322 mlxsw_sp_txhdr_construct(skb, tx_info);
323 return 0;
324 }
325
mlxsw_sp_stp_spms_state(u8 state)326 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
327 {
328 switch (state) {
329 case BR_STATE_FORWARDING:
330 return MLXSW_REG_SPMS_STATE_FORWARDING;
331 case BR_STATE_LEARNING:
332 return MLXSW_REG_SPMS_STATE_LEARNING;
333 case BR_STATE_LISTENING:
334 case BR_STATE_DISABLED:
335 case BR_STATE_BLOCKING:
336 return MLXSW_REG_SPMS_STATE_DISCARDING;
337 default:
338 BUG();
339 }
340 }
341
mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid,u8 state)342 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
343 u8 state)
344 {
345 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
346 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
347 char *spms_pl;
348 int err;
349
350 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
351 if (!spms_pl)
352 return -ENOMEM;
353 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
354 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
355
356 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
357 kfree(spms_pl);
358 return err;
359 }
360
mlxsw_sp_base_mac_get(struct mlxsw_sp * mlxsw_sp)361 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
362 {
363 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
364 int err;
365
366 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
367 if (err)
368 return err;
369 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
370 return 0;
371 }
372
mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port * mlxsw_sp_port,bool is_up)373 int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
374 bool is_up)
375 {
376 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
377 char paos_pl[MLXSW_REG_PAOS_LEN];
378
379 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
380 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
381 MLXSW_PORT_ADMIN_STATUS_DOWN);
382 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
383 }
384
mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port * mlxsw_sp_port,const unsigned char * addr)385 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
386 const unsigned char *addr)
387 {
388 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
389 char ppad_pl[MLXSW_REG_PPAD_LEN];
390
391 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
392 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
393 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
394 }
395
mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port * mlxsw_sp_port)396 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
397 {
398 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
399
400 eth_hw_addr_gen(mlxsw_sp_port->dev, mlxsw_sp->base_mac,
401 mlxsw_sp_port->local_port);
402 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port,
403 mlxsw_sp_port->dev->dev_addr);
404 }
405
mlxsw_sp_port_max_mtu_get(struct mlxsw_sp_port * mlxsw_sp_port,int * p_max_mtu)406 static int mlxsw_sp_port_max_mtu_get(struct mlxsw_sp_port *mlxsw_sp_port, int *p_max_mtu)
407 {
408 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
409 char pmtu_pl[MLXSW_REG_PMTU_LEN];
410 int err;
411
412 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
413 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
414 if (err)
415 return err;
416
417 *p_max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
418 return 0;
419 }
420
mlxsw_sp_port_mtu_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 mtu)421 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
422 {
423 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
424 char pmtu_pl[MLXSW_REG_PMTU_LEN];
425
426 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
427 if (mtu > mlxsw_sp_port->max_mtu)
428 return -EINVAL;
429
430 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
431 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
432 }
433
mlxsw_sp_port_swid_set(struct mlxsw_sp * mlxsw_sp,u16 local_port,u8 swid)434 static int mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp,
435 u16 local_port, u8 swid)
436 {
437 char pspa_pl[MLXSW_REG_PSPA_LEN];
438
439 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
440 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
441 }
442
mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable)443 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
444 {
445 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
446 char svpe_pl[MLXSW_REG_SVPE_LEN];
447
448 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
449 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
450 }
451
mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid,bool learn_enable)452 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
453 bool learn_enable)
454 {
455 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
456 char *spvmlr_pl;
457 int err;
458
459 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
460 if (!spvmlr_pl)
461 return -ENOMEM;
462 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
463 learn_enable);
464 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
465 kfree(spvmlr_pl);
466 return err;
467 }
468
mlxsw_sp_ethtype_to_sver_type(u16 ethtype,u8 * p_sver_type)469 int mlxsw_sp_ethtype_to_sver_type(u16 ethtype, u8 *p_sver_type)
470 {
471 switch (ethtype) {
472 case ETH_P_8021Q:
473 *p_sver_type = 0;
474 break;
475 case ETH_P_8021AD:
476 *p_sver_type = 1;
477 break;
478 default:
479 return -EINVAL;
480 }
481
482 return 0;
483 }
484
mlxsw_sp_port_egress_ethtype_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 ethtype)485 int mlxsw_sp_port_egress_ethtype_set(struct mlxsw_sp_port *mlxsw_sp_port,
486 u16 ethtype)
487 {
488 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
489 char spevet_pl[MLXSW_REG_SPEVET_LEN];
490 u8 sver_type;
491 int err;
492
493 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type);
494 if (err)
495 return err;
496
497 mlxsw_reg_spevet_pack(spevet_pl, mlxsw_sp_port->local_port, sver_type);
498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spevet), spevet_pl);
499 }
500
__mlxsw_sp_port_pvid_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid,u16 ethtype)501 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
502 u16 vid, u16 ethtype)
503 {
504 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
505 char spvid_pl[MLXSW_REG_SPVID_LEN];
506 u8 sver_type;
507 int err;
508
509 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type);
510 if (err)
511 return err;
512
513 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid,
514 sver_type);
515
516 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
517 }
518
mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port * mlxsw_sp_port,bool allow)519 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
520 bool allow)
521 {
522 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
523 char spaft_pl[MLXSW_REG_SPAFT_LEN];
524
525 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
526 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
527 }
528
mlxsw_sp_port_pvid_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid,u16 ethtype)529 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
530 u16 ethtype)
531 {
532 int err;
533
534 if (!vid) {
535 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
536 if (err)
537 return err;
538 } else {
539 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid, ethtype);
540 if (err)
541 return err;
542 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
543 if (err)
544 goto err_port_allow_untagged_set;
545 }
546
547 mlxsw_sp_port->pvid = vid;
548 return 0;
549
550 err_port_allow_untagged_set:
551 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid, ethtype);
552 return err;
553 }
554
555 static int
mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port * mlxsw_sp_port)556 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
557 {
558 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
559 char sspr_pl[MLXSW_REG_SSPR_LEN];
560
561 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
562 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
563 }
564
565 static int
mlxsw_sp_port_module_info_parse(struct mlxsw_sp * mlxsw_sp,u16 local_port,char * pmlp_pl,struct mlxsw_sp_port_mapping * port_mapping)566 mlxsw_sp_port_module_info_parse(struct mlxsw_sp *mlxsw_sp,
567 u16 local_port, char *pmlp_pl,
568 struct mlxsw_sp_port_mapping *port_mapping)
569 {
570 bool separate_rxtx;
571 u8 first_lane;
572 u8 slot_index;
573 u8 module;
574 u8 width;
575 int i;
576
577 module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
578 slot_index = mlxsw_reg_pmlp_slot_index_get(pmlp_pl, 0);
579 width = mlxsw_reg_pmlp_width_get(pmlp_pl);
580 separate_rxtx = mlxsw_reg_pmlp_rxtx_get(pmlp_pl);
581 first_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
582
583 if (width && !is_power_of_2(width)) {
584 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: width value is not power of 2\n",
585 local_port);
586 return -EINVAL;
587 }
588
589 for (i = 0; i < width; i++) {
590 if (mlxsw_reg_pmlp_module_get(pmlp_pl, i) != module) {
591 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple modules\n",
592 local_port);
593 return -EINVAL;
594 }
595 if (mlxsw_reg_pmlp_slot_index_get(pmlp_pl, i) != slot_index) {
596 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple slot indexes\n",
597 local_port);
598 return -EINVAL;
599 }
600 if (separate_rxtx &&
601 mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) !=
602 mlxsw_reg_pmlp_rx_lane_get(pmlp_pl, i)) {
603 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are different\n",
604 local_port);
605 return -EINVAL;
606 }
607 if (mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != i + first_lane) {
608 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are not sequential\n",
609 local_port);
610 return -EINVAL;
611 }
612 }
613
614 port_mapping->module = module;
615 port_mapping->slot_index = slot_index;
616 port_mapping->width = width;
617 port_mapping->module_width = width;
618 port_mapping->lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
619 return 0;
620 }
621
622 static int
mlxsw_sp_port_module_info_get(struct mlxsw_sp * mlxsw_sp,u16 local_port,struct mlxsw_sp_port_mapping * port_mapping)623 mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, u16 local_port,
624 struct mlxsw_sp_port_mapping *port_mapping)
625 {
626 char pmlp_pl[MLXSW_REG_PMLP_LEN];
627 int err;
628
629 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
630 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
631 if (err)
632 return err;
633 return mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port,
634 pmlp_pl, port_mapping);
635 }
636
637 static int
mlxsw_sp_port_module_map(struct mlxsw_sp * mlxsw_sp,u16 local_port,const struct mlxsw_sp_port_mapping * port_mapping)638 mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u16 local_port,
639 const struct mlxsw_sp_port_mapping *port_mapping)
640 {
641 char pmlp_pl[MLXSW_REG_PMLP_LEN];
642 int i, err;
643
644 mlxsw_env_module_port_map(mlxsw_sp->core, port_mapping->slot_index,
645 port_mapping->module);
646
647 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
648 mlxsw_reg_pmlp_width_set(pmlp_pl, port_mapping->width);
649 for (i = 0; i < port_mapping->width; i++) {
650 mlxsw_reg_pmlp_slot_index_set(pmlp_pl, i,
651 port_mapping->slot_index);
652 mlxsw_reg_pmlp_module_set(pmlp_pl, i, port_mapping->module);
653 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, port_mapping->lane + i); /* Rx & Tx */
654 }
655
656 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
657 if (err)
658 goto err_pmlp_write;
659 return 0;
660
661 err_pmlp_write:
662 mlxsw_env_module_port_unmap(mlxsw_sp->core, port_mapping->slot_index,
663 port_mapping->module);
664 return err;
665 }
666
mlxsw_sp_port_module_unmap(struct mlxsw_sp * mlxsw_sp,u16 local_port,u8 slot_index,u8 module)667 static void mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u16 local_port,
668 u8 slot_index, u8 module)
669 {
670 char pmlp_pl[MLXSW_REG_PMLP_LEN];
671
672 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
673 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
674 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
675 mlxsw_env_module_port_unmap(mlxsw_sp->core, slot_index, module);
676 }
677
mlxsw_sp_port_open(struct net_device * dev)678 static int mlxsw_sp_port_open(struct net_device *dev)
679 {
680 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
682 int err;
683
684 err = mlxsw_env_module_port_up(mlxsw_sp->core,
685 mlxsw_sp_port->mapping.slot_index,
686 mlxsw_sp_port->mapping.module);
687 if (err)
688 return err;
689 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
690 if (err)
691 goto err_port_admin_status_set;
692 netif_start_queue(dev);
693 return 0;
694
695 err_port_admin_status_set:
696 mlxsw_env_module_port_down(mlxsw_sp->core,
697 mlxsw_sp_port->mapping.slot_index,
698 mlxsw_sp_port->mapping.module);
699 return err;
700 }
701
mlxsw_sp_port_stop(struct net_device * dev)702 static int mlxsw_sp_port_stop(struct net_device *dev)
703 {
704 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
705 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
706
707 netif_stop_queue(dev);
708 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
709 mlxsw_env_module_port_down(mlxsw_sp->core,
710 mlxsw_sp_port->mapping.slot_index,
711 mlxsw_sp_port->mapping.module);
712 return 0;
713 }
714
mlxsw_sp_port_xmit(struct sk_buff * skb,struct net_device * dev)715 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
716 struct net_device *dev)
717 {
718 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
719 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
720 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
721 const struct mlxsw_tx_info tx_info = {
722 .local_port = mlxsw_sp_port->local_port,
723 .is_emad = false,
724 };
725 u64 len;
726 int err;
727
728 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
729
730 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
731 return NETDEV_TX_BUSY;
732
733 if (eth_skb_pad(skb)) {
734 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
735 return NETDEV_TX_OK;
736 }
737
738 err = mlxsw_sp_txhdr_handle(mlxsw_sp->core, mlxsw_sp_port, skb,
739 &tx_info);
740 if (err)
741 return NETDEV_TX_OK;
742
743 /* TX header is consumed by HW on the way so we shouldn't count its
744 * bytes as being sent.
745 */
746 len = skb->len - MLXSW_TXHDR_LEN;
747
748 /* Due to a race we might fail here because of a full queue. In that
749 * unlikely case we simply drop the packet.
750 */
751 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
752
753 if (!err) {
754 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
755 u64_stats_update_begin(&pcpu_stats->syncp);
756 pcpu_stats->tx_packets++;
757 pcpu_stats->tx_bytes += len;
758 u64_stats_update_end(&pcpu_stats->syncp);
759 } else {
760 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
761 dev_kfree_skb_any(skb);
762 }
763 return NETDEV_TX_OK;
764 }
765
mlxsw_sp_set_rx_mode(struct net_device * dev)766 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
767 {
768 }
769
mlxsw_sp_port_set_mac_address(struct net_device * dev,void * p)770 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
771 {
772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
773 struct sockaddr *addr = p;
774 int err;
775
776 if (!is_valid_ether_addr(addr->sa_data))
777 return -EADDRNOTAVAIL;
778
779 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
780 if (err)
781 return err;
782 eth_hw_addr_set(dev, addr->sa_data);
783 return 0;
784 }
785
mlxsw_sp_port_change_mtu(struct net_device * dev,int mtu)786 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
787 {
788 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
789 struct mlxsw_sp_hdroom orig_hdroom;
790 struct mlxsw_sp_hdroom hdroom;
791 int err;
792
793 orig_hdroom = *mlxsw_sp_port->hdroom;
794
795 hdroom = orig_hdroom;
796 hdroom.mtu = mtu;
797 mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom);
798
799 err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom);
800 if (err) {
801 netdev_err(dev, "Failed to configure port's headroom\n");
802 return err;
803 }
804
805 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
806 if (err)
807 goto err_port_mtu_set;
808 dev->mtu = mtu;
809 return 0;
810
811 err_port_mtu_set:
812 mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom);
813 return err;
814 }
815
816 static int
mlxsw_sp_port_get_sw_stats64(const struct net_device * dev,struct rtnl_link_stats64 * stats)817 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
818 struct rtnl_link_stats64 *stats)
819 {
820 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
821 struct mlxsw_sp_port_pcpu_stats *p;
822 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
823 u32 tx_dropped = 0;
824 unsigned int start;
825 int i;
826
827 for_each_possible_cpu(i) {
828 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
829 do {
830 start = u64_stats_fetch_begin_irq(&p->syncp);
831 rx_packets = p->rx_packets;
832 rx_bytes = p->rx_bytes;
833 tx_packets = p->tx_packets;
834 tx_bytes = p->tx_bytes;
835 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
836
837 stats->rx_packets += rx_packets;
838 stats->rx_bytes += rx_bytes;
839 stats->tx_packets += tx_packets;
840 stats->tx_bytes += tx_bytes;
841 /* tx_dropped is u32, updated without syncp protection. */
842 tx_dropped += p->tx_dropped;
843 }
844 stats->tx_dropped = tx_dropped;
845 return 0;
846 }
847
mlxsw_sp_port_has_offload_stats(const struct net_device * dev,int attr_id)848 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
849 {
850 switch (attr_id) {
851 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
852 return true;
853 }
854
855 return false;
856 }
857
mlxsw_sp_port_get_offload_stats(int attr_id,const struct net_device * dev,void * sp)858 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
859 void *sp)
860 {
861 switch (attr_id) {
862 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
863 return mlxsw_sp_port_get_sw_stats64(dev, sp);
864 }
865
866 return -EINVAL;
867 }
868
mlxsw_sp_port_get_stats_raw(struct net_device * dev,int grp,int prio,char * ppcnt_pl)869 int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
870 int prio, char *ppcnt_pl)
871 {
872 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
873 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
874
875 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
876 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
877 }
878
mlxsw_sp_port_get_hw_stats(struct net_device * dev,struct rtnl_link_stats64 * stats)879 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
880 struct rtnl_link_stats64 *stats)
881 {
882 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
883 int err;
884
885 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
886 0, ppcnt_pl);
887 if (err)
888 goto out;
889
890 stats->tx_packets =
891 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
892 stats->rx_packets =
893 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
894 stats->tx_bytes =
895 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
896 stats->rx_bytes =
897 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
898 stats->multicast =
899 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
900
901 stats->rx_crc_errors =
902 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
903 stats->rx_frame_errors =
904 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
905
906 stats->rx_length_errors = (
907 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
908 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
909 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
910
911 stats->rx_errors = (stats->rx_crc_errors +
912 stats->rx_frame_errors + stats->rx_length_errors);
913
914 out:
915 return err;
916 }
917
918 static void
mlxsw_sp_port_get_hw_xstats(struct net_device * dev,struct mlxsw_sp_port_xstats * xstats)919 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
920 struct mlxsw_sp_port_xstats *xstats)
921 {
922 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
923 int err, i;
924
925 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
926 ppcnt_pl);
927 if (!err)
928 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
929
930 for (i = 0; i < TC_MAX_QUEUE; i++) {
931 err = mlxsw_sp_port_get_stats_raw(dev,
932 MLXSW_REG_PPCNT_TC_CONG_CNT,
933 i, ppcnt_pl);
934 if (err)
935 goto tc_cnt;
936
937 xstats->wred_drop[i] =
938 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
939 xstats->tc_ecn[i] = mlxsw_reg_ppcnt_ecn_marked_tc_get(ppcnt_pl);
940
941 tc_cnt:
942 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
943 i, ppcnt_pl);
944 if (err)
945 continue;
946
947 xstats->backlog[i] =
948 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
949 xstats->tail_drop[i] =
950 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
951 }
952
953 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
954 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
955 i, ppcnt_pl);
956 if (err)
957 continue;
958
959 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
960 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
961 }
962 }
963
update_stats_cache(struct work_struct * work)964 static void update_stats_cache(struct work_struct *work)
965 {
966 struct mlxsw_sp_port *mlxsw_sp_port =
967 container_of(work, struct mlxsw_sp_port,
968 periodic_hw_stats.update_dw.work);
969
970 if (!netif_carrier_ok(mlxsw_sp_port->dev))
971 /* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as
972 * necessary when port goes down.
973 */
974 goto out;
975
976 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
977 &mlxsw_sp_port->periodic_hw_stats.stats);
978 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
979 &mlxsw_sp_port->periodic_hw_stats.xstats);
980
981 out:
982 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
983 MLXSW_HW_STATS_UPDATE_TIME);
984 }
985
986 /* Return the stats from a cache that is updated periodically,
987 * as this function might get called in an atomic context.
988 */
989 static void
mlxsw_sp_port_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)990 mlxsw_sp_port_get_stats64(struct net_device *dev,
991 struct rtnl_link_stats64 *stats)
992 {
993 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
994
995 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
996 }
997
__mlxsw_sp_port_vlan_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid_begin,u16 vid_end,bool is_member,bool untagged)998 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
999 u16 vid_begin, u16 vid_end,
1000 bool is_member, bool untagged)
1001 {
1002 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1003 char *spvm_pl;
1004 int err;
1005
1006 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1007 if (!spvm_pl)
1008 return -ENOMEM;
1009
1010 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1011 vid_end, is_member, untagged);
1012 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1013 kfree(spvm_pl);
1014 return err;
1015 }
1016
mlxsw_sp_port_vlan_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid_begin,u16 vid_end,bool is_member,bool untagged)1017 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1018 u16 vid_end, bool is_member, bool untagged)
1019 {
1020 u16 vid, vid_e;
1021 int err;
1022
1023 for (vid = vid_begin; vid <= vid_end;
1024 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1025 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1026 vid_end);
1027
1028 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1029 is_member, untagged);
1030 if (err)
1031 return err;
1032 }
1033
1034 return 0;
1035 }
1036
mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port * mlxsw_sp_port,bool flush_default)1037 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port,
1038 bool flush_default)
1039 {
1040 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1041
1042 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1043 &mlxsw_sp_port->vlans_list, list) {
1044 if (!flush_default &&
1045 mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID)
1046 continue;
1047 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1048 }
1049 }
1050
1051 static void
mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan * mlxsw_sp_port_vlan)1052 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1053 {
1054 if (mlxsw_sp_port_vlan->bridge_port)
1055 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1056 else if (mlxsw_sp_port_vlan->fid)
1057 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1058 }
1059
1060 struct mlxsw_sp_port_vlan *
mlxsw_sp_port_vlan_create(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid)1061 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1062 {
1063 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1064 bool untagged = vid == MLXSW_SP_DEFAULT_VID;
1065 int err;
1066
1067 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1068 if (mlxsw_sp_port_vlan)
1069 return ERR_PTR(-EEXIST);
1070
1071 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1072 if (err)
1073 return ERR_PTR(err);
1074
1075 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1076 if (!mlxsw_sp_port_vlan) {
1077 err = -ENOMEM;
1078 goto err_port_vlan_alloc;
1079 }
1080
1081 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1082 mlxsw_sp_port_vlan->vid = vid;
1083 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1084
1085 return mlxsw_sp_port_vlan;
1086
1087 err_port_vlan_alloc:
1088 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1089 return ERR_PTR(err);
1090 }
1091
mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan * mlxsw_sp_port_vlan)1092 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1093 {
1094 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1095 u16 vid = mlxsw_sp_port_vlan->vid;
1096
1097 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan);
1098 list_del(&mlxsw_sp_port_vlan->list);
1099 kfree(mlxsw_sp_port_vlan);
1100 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1101 }
1102
mlxsw_sp_port_add_vid(struct net_device * dev,__be16 __always_unused proto,u16 vid)1103 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1104 __be16 __always_unused proto, u16 vid)
1105 {
1106 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1107
1108 /* VLAN 0 is added to HW filter when device goes up, but it is
1109 * reserved in our case, so simply return.
1110 */
1111 if (!vid)
1112 return 0;
1113
1114 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid));
1115 }
1116
mlxsw_sp_port_kill_vid(struct net_device * dev,__be16 __always_unused proto,u16 vid)1117 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1118 __be16 __always_unused proto, u16 vid)
1119 {
1120 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1121 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1122
1123 /* VLAN 0 is removed from HW filter when device goes down, but
1124 * it is reserved in our case, so simply return.
1125 */
1126 if (!vid)
1127 return 0;
1128
1129 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1130 if (!mlxsw_sp_port_vlan)
1131 return 0;
1132 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1133
1134 return 0;
1135 }
1136
mlxsw_sp_setup_tc_block(struct mlxsw_sp_port * mlxsw_sp_port,struct flow_block_offload * f)1137 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1138 struct flow_block_offload *f)
1139 {
1140 switch (f->binder_type) {
1141 case FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS:
1142 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, true);
1143 case FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS:
1144 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, false);
1145 case FLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP:
1146 return mlxsw_sp_setup_tc_block_qevent_early_drop(mlxsw_sp_port, f);
1147 case FLOW_BLOCK_BINDER_TYPE_RED_MARK:
1148 return mlxsw_sp_setup_tc_block_qevent_mark(mlxsw_sp_port, f);
1149 default:
1150 return -EOPNOTSUPP;
1151 }
1152 }
1153
mlxsw_sp_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)1154 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1155 void *type_data)
1156 {
1157 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1158
1159 switch (type) {
1160 case TC_SETUP_BLOCK:
1161 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1162 case TC_SETUP_QDISC_RED:
1163 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1164 case TC_SETUP_QDISC_PRIO:
1165 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1166 case TC_SETUP_QDISC_ETS:
1167 return mlxsw_sp_setup_tc_ets(mlxsw_sp_port, type_data);
1168 case TC_SETUP_QDISC_TBF:
1169 return mlxsw_sp_setup_tc_tbf(mlxsw_sp_port, type_data);
1170 case TC_SETUP_QDISC_FIFO:
1171 return mlxsw_sp_setup_tc_fifo(mlxsw_sp_port, type_data);
1172 default:
1173 return -EOPNOTSUPP;
1174 }
1175 }
1176
mlxsw_sp_feature_hw_tc(struct net_device * dev,bool enable)1177 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1178 {
1179 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1180
1181 if (!enable) {
1182 if (mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->ing_flow_block) ||
1183 mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->eg_flow_block)) {
1184 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1185 return -EINVAL;
1186 }
1187 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->ing_flow_block);
1188 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->eg_flow_block);
1189 } else {
1190 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->ing_flow_block);
1191 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->eg_flow_block);
1192 }
1193 return 0;
1194 }
1195
mlxsw_sp_feature_loopback(struct net_device * dev,bool enable)1196 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable)
1197 {
1198 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1199 char pplr_pl[MLXSW_REG_PPLR_LEN];
1200 int err;
1201
1202 if (netif_running(dev))
1203 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1204
1205 mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable);
1206 err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr),
1207 pplr_pl);
1208
1209 if (netif_running(dev))
1210 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1211
1212 return err;
1213 }
1214
1215 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1216
mlxsw_sp_handle_feature(struct net_device * dev,netdev_features_t wanted_features,netdev_features_t feature,mlxsw_sp_feature_handler feature_handler)1217 static int mlxsw_sp_handle_feature(struct net_device *dev,
1218 netdev_features_t wanted_features,
1219 netdev_features_t feature,
1220 mlxsw_sp_feature_handler feature_handler)
1221 {
1222 netdev_features_t changes = wanted_features ^ dev->features;
1223 bool enable = !!(wanted_features & feature);
1224 int err;
1225
1226 if (!(changes & feature))
1227 return 0;
1228
1229 err = feature_handler(dev, enable);
1230 if (err) {
1231 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1232 enable ? "Enable" : "Disable", &feature, err);
1233 return err;
1234 }
1235
1236 if (enable)
1237 dev->features |= feature;
1238 else
1239 dev->features &= ~feature;
1240
1241 return 0;
1242 }
mlxsw_sp_set_features(struct net_device * dev,netdev_features_t features)1243 static int mlxsw_sp_set_features(struct net_device *dev,
1244 netdev_features_t features)
1245 {
1246 netdev_features_t oper_features = dev->features;
1247 int err = 0;
1248
1249 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1250 mlxsw_sp_feature_hw_tc);
1251 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK,
1252 mlxsw_sp_feature_loopback);
1253
1254 if (err) {
1255 dev->features = oper_features;
1256 return -EINVAL;
1257 }
1258
1259 return 0;
1260 }
1261
1262 static struct devlink_port *
mlxsw_sp_port_get_devlink_port(struct net_device * dev)1263 mlxsw_sp_port_get_devlink_port(struct net_device *dev)
1264 {
1265 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1266 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1267
1268 return mlxsw_core_port_devlink_port_get(mlxsw_sp->core,
1269 mlxsw_sp_port->local_port);
1270 }
1271
mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port * mlxsw_sp_port,struct ifreq * ifr)1272 static int mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port,
1273 struct ifreq *ifr)
1274 {
1275 struct hwtstamp_config config;
1276 int err;
1277
1278 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1279 return -EFAULT;
1280
1281 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port,
1282 &config);
1283 if (err)
1284 return err;
1285
1286 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1287 return -EFAULT;
1288
1289 return 0;
1290 }
1291
mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port * mlxsw_sp_port,struct ifreq * ifr)1292 static int mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port,
1293 struct ifreq *ifr)
1294 {
1295 struct hwtstamp_config config;
1296 int err;
1297
1298 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port,
1299 &config);
1300 if (err)
1301 return err;
1302
1303 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1304 return -EFAULT;
1305
1306 return 0;
1307 }
1308
mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port * mlxsw_sp_port)1309 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port)
1310 {
1311 struct hwtstamp_config config = {0};
1312
1313 mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config);
1314 }
1315
1316 static int
mlxsw_sp_port_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)1317 mlxsw_sp_port_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1318 {
1319 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1320
1321 switch (cmd) {
1322 case SIOCSHWTSTAMP:
1323 return mlxsw_sp_port_hwtstamp_set(mlxsw_sp_port, ifr);
1324 case SIOCGHWTSTAMP:
1325 return mlxsw_sp_port_hwtstamp_get(mlxsw_sp_port, ifr);
1326 default:
1327 return -EOPNOTSUPP;
1328 }
1329 }
1330
1331 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1332 .ndo_open = mlxsw_sp_port_open,
1333 .ndo_stop = mlxsw_sp_port_stop,
1334 .ndo_start_xmit = mlxsw_sp_port_xmit,
1335 .ndo_setup_tc = mlxsw_sp_setup_tc,
1336 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
1337 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1338 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1339 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
1340 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1341 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
1342 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1343 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1344 .ndo_set_features = mlxsw_sp_set_features,
1345 .ndo_get_devlink_port = mlxsw_sp_port_get_devlink_port,
1346 .ndo_eth_ioctl = mlxsw_sp_port_ioctl,
1347 };
1348
1349 static int
mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port * mlxsw_sp_port)1350 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port)
1351 {
1352 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1353 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
1354 const struct mlxsw_sp_port_type_speed_ops *ops;
1355 char ptys_pl[MLXSW_REG_PTYS_LEN];
1356 u32 eth_proto_cap_masked;
1357 int err;
1358
1359 ops = mlxsw_sp->port_type_speed_ops;
1360
1361 /* Set advertised speeds to speeds supported by both the driver
1362 * and the device.
1363 */
1364 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
1365 0, false);
1366 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1367 if (err)
1368 return err;
1369
1370 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap,
1371 ð_proto_admin, ð_proto_oper);
1372 eth_proto_cap_masked = ops->ptys_proto_cap_masked_get(eth_proto_cap);
1373 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
1374 eth_proto_cap_masked,
1375 mlxsw_sp_port->link.autoneg);
1376 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1377 }
1378
mlxsw_sp_port_speed_get(struct mlxsw_sp_port * mlxsw_sp_port,u32 * speed)1379 int mlxsw_sp_port_speed_get(struct mlxsw_sp_port *mlxsw_sp_port, u32 *speed)
1380 {
1381 const struct mlxsw_sp_port_type_speed_ops *port_type_speed_ops;
1382 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1383 char ptys_pl[MLXSW_REG_PTYS_LEN];
1384 u32 eth_proto_oper;
1385 int err;
1386
1387 port_type_speed_ops = mlxsw_sp->port_type_speed_ops;
1388 port_type_speed_ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl,
1389 mlxsw_sp_port->local_port, 0,
1390 false);
1391 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1392 if (err)
1393 return err;
1394 port_type_speed_ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, NULL, NULL,
1395 ð_proto_oper);
1396 *speed = port_type_speed_ops->from_ptys_speed(mlxsw_sp, eth_proto_oper);
1397 return 0;
1398 }
1399
mlxsw_sp_port_ets_set(struct mlxsw_sp_port * mlxsw_sp_port,enum mlxsw_reg_qeec_hr hr,u8 index,u8 next_index,bool dwrr,u8 dwrr_weight)1400 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1401 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1402 bool dwrr, u8 dwrr_weight)
1403 {
1404 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1405 char qeec_pl[MLXSW_REG_QEEC_LEN];
1406
1407 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1408 next_index);
1409 mlxsw_reg_qeec_de_set(qeec_pl, true);
1410 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1411 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1412 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1413 }
1414
mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port * mlxsw_sp_port,enum mlxsw_reg_qeec_hr hr,u8 index,u8 next_index,u32 maxrate,u8 burst_size)1415 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1416 enum mlxsw_reg_qeec_hr hr, u8 index,
1417 u8 next_index, u32 maxrate, u8 burst_size)
1418 {
1419 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1420 char qeec_pl[MLXSW_REG_QEEC_LEN];
1421
1422 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1423 next_index);
1424 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1425 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1426 mlxsw_reg_qeec_max_shaper_bs_set(qeec_pl, burst_size);
1427 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1428 }
1429
mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port * mlxsw_sp_port,enum mlxsw_reg_qeec_hr hr,u8 index,u8 next_index,u32 minrate)1430 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
1431 enum mlxsw_reg_qeec_hr hr, u8 index,
1432 u8 next_index, u32 minrate)
1433 {
1434 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1435 char qeec_pl[MLXSW_REG_QEEC_LEN];
1436
1437 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1438 next_index);
1439 mlxsw_reg_qeec_mise_set(qeec_pl, true);
1440 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
1441
1442 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1443 }
1444
mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port * mlxsw_sp_port,u8 switch_prio,u8 tclass)1445 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1446 u8 switch_prio, u8 tclass)
1447 {
1448 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1449 char qtct_pl[MLXSW_REG_QTCT_LEN];
1450
1451 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1452 tclass);
1453 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1454 }
1455
mlxsw_sp_port_ets_init(struct mlxsw_sp_port * mlxsw_sp_port)1456 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1457 {
1458 int err, i;
1459
1460 /* Setup the elements hierarcy, so that each TC is linked to
1461 * one subgroup, which are all member in the same group.
1462 */
1463 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1464 MLXSW_REG_QEEC_HR_GROUP, 0, 0, false, 0);
1465 if (err)
1466 return err;
1467 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1468 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1469 MLXSW_REG_QEEC_HR_SUBGROUP, i,
1470 0, false, 0);
1471 if (err)
1472 return err;
1473 }
1474 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1475 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1476 MLXSW_REG_QEEC_HR_TC, i, i,
1477 false, 0);
1478 if (err)
1479 return err;
1480
1481 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1482 MLXSW_REG_QEEC_HR_TC,
1483 i + 8, i,
1484 true, 100);
1485 if (err)
1486 return err;
1487 }
1488
1489 /* Make sure the max shaper is disabled in all hierarchies that support
1490 * it. Note that this disables ptps (PTP shaper), but that is intended
1491 * for the initial configuration.
1492 */
1493 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1494 MLXSW_REG_QEEC_HR_PORT, 0, 0,
1495 MLXSW_REG_QEEC_MAS_DIS, 0);
1496 if (err)
1497 return err;
1498 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1499 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1500 MLXSW_REG_QEEC_HR_SUBGROUP,
1501 i, 0,
1502 MLXSW_REG_QEEC_MAS_DIS, 0);
1503 if (err)
1504 return err;
1505 }
1506 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1507 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1508 MLXSW_REG_QEEC_HR_TC,
1509 i, i,
1510 MLXSW_REG_QEEC_MAS_DIS, 0);
1511 if (err)
1512 return err;
1513
1514 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1515 MLXSW_REG_QEEC_HR_TC,
1516 i + 8, i,
1517 MLXSW_REG_QEEC_MAS_DIS, 0);
1518 if (err)
1519 return err;
1520 }
1521
1522 /* Configure the min shaper for multicast TCs. */
1523 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1524 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
1525 MLXSW_REG_QEEC_HR_TC,
1526 i + 8, i,
1527 MLXSW_REG_QEEC_MIS_MIN);
1528 if (err)
1529 return err;
1530 }
1531
1532 /* Map all priorities to traffic class 0. */
1533 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1534 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1535 if (err)
1536 return err;
1537 }
1538
1539 return 0;
1540 }
1541
mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable)1542 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
1543 bool enable)
1544 {
1545 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1546 char qtctm_pl[MLXSW_REG_QTCTM_LEN];
1547
1548 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
1549 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
1550 }
1551
mlxsw_sp_port_overheat_init_val_set(struct mlxsw_sp_port * mlxsw_sp_port)1552 static int mlxsw_sp_port_overheat_init_val_set(struct mlxsw_sp_port *mlxsw_sp_port)
1553 {
1554 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1555 u8 slot_index = mlxsw_sp_port->mapping.slot_index;
1556 u8 module = mlxsw_sp_port->mapping.module;
1557 u64 overheat_counter;
1558 int err;
1559
1560 err = mlxsw_env_module_overheat_counter_get(mlxsw_sp->core, slot_index,
1561 module, &overheat_counter);
1562 if (err)
1563 return err;
1564
1565 mlxsw_sp_port->module_overheat_initial_val = overheat_counter;
1566 return 0;
1567 }
1568
1569 int
mlxsw_sp_port_vlan_classification_set(struct mlxsw_sp_port * mlxsw_sp_port,bool is_8021ad_tagged,bool is_8021q_tagged)1570 mlxsw_sp_port_vlan_classification_set(struct mlxsw_sp_port *mlxsw_sp_port,
1571 bool is_8021ad_tagged,
1572 bool is_8021q_tagged)
1573 {
1574 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1575 char spvc_pl[MLXSW_REG_SPVC_LEN];
1576
1577 mlxsw_reg_spvc_pack(spvc_pl, mlxsw_sp_port->local_port,
1578 is_8021ad_tagged, is_8021q_tagged);
1579 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvc), spvc_pl);
1580 }
1581
mlxsw_sp_port_label_info_get(struct mlxsw_sp * mlxsw_sp,u16 local_port,u8 * port_number,u8 * split_port_subnumber,u8 * slot_index)1582 static int mlxsw_sp_port_label_info_get(struct mlxsw_sp *mlxsw_sp,
1583 u16 local_port, u8 *port_number,
1584 u8 *split_port_subnumber,
1585 u8 *slot_index)
1586 {
1587 char pllp_pl[MLXSW_REG_PLLP_LEN];
1588 int err;
1589
1590 mlxsw_reg_pllp_pack(pllp_pl, local_port);
1591 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pllp), pllp_pl);
1592 if (err)
1593 return err;
1594 mlxsw_reg_pllp_unpack(pllp_pl, port_number,
1595 split_port_subnumber, slot_index);
1596 return 0;
1597 }
1598
mlxsw_sp_port_create(struct mlxsw_sp * mlxsw_sp,u16 local_port,bool split,struct mlxsw_sp_port_mapping * port_mapping)1599 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u16 local_port,
1600 bool split,
1601 struct mlxsw_sp_port_mapping *port_mapping)
1602 {
1603 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1604 struct mlxsw_sp_port *mlxsw_sp_port;
1605 u32 lanes = port_mapping->width;
1606 u8 split_port_subnumber;
1607 struct net_device *dev;
1608 u8 port_number;
1609 u8 slot_index;
1610 bool splittable;
1611 int err;
1612
1613 err = mlxsw_sp_port_module_map(mlxsw_sp, local_port, port_mapping);
1614 if (err) {
1615 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
1616 local_port);
1617 return err;
1618 }
1619
1620 err = mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 0);
1621 if (err) {
1622 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1623 local_port);
1624 goto err_port_swid_set;
1625 }
1626
1627 err = mlxsw_sp_port_label_info_get(mlxsw_sp, local_port, &port_number,
1628 &split_port_subnumber, &slot_index);
1629 if (err) {
1630 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get port label information\n",
1631 local_port);
1632 goto err_port_label_info_get;
1633 }
1634
1635 splittable = lanes > 1 && !split;
1636 err = mlxsw_core_port_init(mlxsw_sp->core, local_port, slot_index,
1637 port_number, split, split_port_subnumber,
1638 splittable, lanes, mlxsw_sp->base_mac,
1639 sizeof(mlxsw_sp->base_mac));
1640 if (err) {
1641 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1642 local_port);
1643 goto err_core_port_init;
1644 }
1645
1646 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1647 if (!dev) {
1648 err = -ENOMEM;
1649 goto err_alloc_etherdev;
1650 }
1651 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
1652 dev_net_set(dev, mlxsw_sp_net(mlxsw_sp));
1653 mlxsw_sp_port = netdev_priv(dev);
1654 mlxsw_sp_port->dev = dev;
1655 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1656 mlxsw_sp_port->local_port = local_port;
1657 mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID;
1658 mlxsw_sp_port->split = split;
1659 mlxsw_sp_port->mapping = *port_mapping;
1660 mlxsw_sp_port->link.autoneg = 1;
1661 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
1662
1663 mlxsw_sp_port->pcpu_stats =
1664 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1665 if (!mlxsw_sp_port->pcpu_stats) {
1666 err = -ENOMEM;
1667 goto err_alloc_stats;
1668 }
1669
1670 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1671 &update_stats_cache);
1672
1673 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1674 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1675
1676 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1677 if (err) {
1678 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1679 mlxsw_sp_port->local_port);
1680 goto err_dev_addr_init;
1681 }
1682
1683 netif_carrier_off(dev);
1684
1685 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1686 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
1687 dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK;
1688
1689 dev->min_mtu = 0;
1690 dev->max_mtu = ETH_MAX_MTU;
1691
1692 /* Each packet needs to have a Tx header (metadata) on top all other
1693 * headers.
1694 */
1695 dev->needed_headroom = MLXSW_TXHDR_LEN;
1696
1697 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1698 if (err) {
1699 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1700 mlxsw_sp_port->local_port);
1701 goto err_port_system_port_mapping_set;
1702 }
1703
1704 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port);
1705 if (err) {
1706 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1707 mlxsw_sp_port->local_port);
1708 goto err_port_speed_by_width_set;
1709 }
1710
1711 err = mlxsw_sp->port_type_speed_ops->ptys_max_speed(mlxsw_sp_port,
1712 &mlxsw_sp_port->max_speed);
1713 if (err) {
1714 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum speed\n",
1715 mlxsw_sp_port->local_port);
1716 goto err_max_speed_get;
1717 }
1718
1719 err = mlxsw_sp_port_max_mtu_get(mlxsw_sp_port, &mlxsw_sp_port->max_mtu);
1720 if (err) {
1721 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum MTU\n",
1722 mlxsw_sp_port->local_port);
1723 goto err_port_max_mtu_get;
1724 }
1725
1726 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1727 if (err) {
1728 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1729 mlxsw_sp_port->local_port);
1730 goto err_port_mtu_set;
1731 }
1732
1733 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1734 if (err)
1735 goto err_port_admin_status_set;
1736
1737 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1738 if (err) {
1739 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1740 mlxsw_sp_port->local_port);
1741 goto err_port_buffers_init;
1742 }
1743
1744 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1745 if (err) {
1746 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1747 mlxsw_sp_port->local_port);
1748 goto err_port_ets_init;
1749 }
1750
1751 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
1752 if (err) {
1753 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
1754 mlxsw_sp_port->local_port);
1755 goto err_port_tc_mc_mode;
1756 }
1757
1758 /* ETS and buffers must be initialized before DCB. */
1759 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1760 if (err) {
1761 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1762 mlxsw_sp_port->local_port);
1763 goto err_port_dcb_init;
1764 }
1765
1766 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
1767 if (err) {
1768 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
1769 mlxsw_sp_port->local_port);
1770 goto err_port_fids_init;
1771 }
1772
1773 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
1774 if (err) {
1775 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
1776 mlxsw_sp_port->local_port);
1777 goto err_port_qdiscs_init;
1778 }
1779
1780 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false,
1781 false);
1782 if (err) {
1783 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n",
1784 mlxsw_sp_port->local_port);
1785 goto err_port_vlan_clear;
1786 }
1787
1788 err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
1789 if (err) {
1790 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
1791 mlxsw_sp_port->local_port);
1792 goto err_port_nve_init;
1793 }
1794
1795 err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID,
1796 ETH_P_8021Q);
1797 if (err) {
1798 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n",
1799 mlxsw_sp_port->local_port);
1800 goto err_port_pvid_set;
1801 }
1802
1803 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port,
1804 MLXSW_SP_DEFAULT_VID);
1805 if (IS_ERR(mlxsw_sp_port_vlan)) {
1806 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
1807 mlxsw_sp_port->local_port);
1808 err = PTR_ERR(mlxsw_sp_port_vlan);
1809 goto err_port_vlan_create;
1810 }
1811 mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan;
1812
1813 /* Set SPVC.et0=true and SPVC.et1=false to make the local port to treat
1814 * only packets with 802.1q header as tagged packets.
1815 */
1816 err = mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, false, true);
1817 if (err) {
1818 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set default VLAN classification\n",
1819 local_port);
1820 goto err_port_vlan_classification_set;
1821 }
1822
1823 INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw,
1824 mlxsw_sp->ptp_ops->shaper_work);
1825
1826 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1827
1828 err = mlxsw_sp_port_overheat_init_val_set(mlxsw_sp_port);
1829 if (err) {
1830 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set overheat initial value\n",
1831 mlxsw_sp_port->local_port);
1832 goto err_port_overheat_init_val_set;
1833 }
1834
1835 err = register_netdev(dev);
1836 if (err) {
1837 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1838 mlxsw_sp_port->local_port);
1839 goto err_register_netdev;
1840 }
1841
1842 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
1843 mlxsw_sp_port, dev);
1844 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
1845 return 0;
1846
1847 err_register_netdev:
1848 err_port_overheat_init_val_set:
1849 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true);
1850 err_port_vlan_classification_set:
1851 mlxsw_sp->ports[local_port] = NULL;
1852 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1853 err_port_vlan_create:
1854 err_port_pvid_set:
1855 mlxsw_sp_port_nve_fini(mlxsw_sp_port);
1856 err_port_nve_init:
1857 err_port_vlan_clear:
1858 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
1859 err_port_qdiscs_init:
1860 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
1861 err_port_fids_init:
1862 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
1863 err_port_dcb_init:
1864 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
1865 err_port_tc_mc_mode:
1866 err_port_ets_init:
1867 mlxsw_sp_port_buffers_fini(mlxsw_sp_port);
1868 err_port_buffers_init:
1869 err_port_admin_status_set:
1870 err_port_mtu_set:
1871 err_port_max_mtu_get:
1872 err_max_speed_get:
1873 err_port_speed_by_width_set:
1874 err_port_system_port_mapping_set:
1875 err_dev_addr_init:
1876 free_percpu(mlxsw_sp_port->pcpu_stats);
1877 err_alloc_stats:
1878 free_netdev(dev);
1879 err_alloc_etherdev:
1880 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
1881 err_core_port_init:
1882 err_port_label_info_get:
1883 mlxsw_sp_port_swid_set(mlxsw_sp, local_port,
1884 MLXSW_PORT_SWID_DISABLED_PORT);
1885 err_port_swid_set:
1886 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port,
1887 port_mapping->slot_index,
1888 port_mapping->module);
1889 return err;
1890 }
1891
mlxsw_sp_port_remove(struct mlxsw_sp * mlxsw_sp,u16 local_port)1892 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u16 local_port)
1893 {
1894 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1895 u8 slot_index = mlxsw_sp_port->mapping.slot_index;
1896 u8 module = mlxsw_sp_port->mapping.module;
1897
1898 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
1899 cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw);
1900 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
1901 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
1902 mlxsw_sp_port_ptp_clear(mlxsw_sp_port);
1903 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true);
1904 mlxsw_sp->ports[local_port] = NULL;
1905 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true);
1906 mlxsw_sp_port_nve_fini(mlxsw_sp_port);
1907 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
1908 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
1909 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
1910 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
1911 mlxsw_sp_port_buffers_fini(mlxsw_sp_port);
1912 free_percpu(mlxsw_sp_port->pcpu_stats);
1913 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
1914 free_netdev(mlxsw_sp_port->dev);
1915 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
1916 mlxsw_sp_port_swid_set(mlxsw_sp, local_port,
1917 MLXSW_PORT_SWID_DISABLED_PORT);
1918 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, slot_index, module);
1919 }
1920
mlxsw_sp_cpu_port_create(struct mlxsw_sp * mlxsw_sp)1921 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp)
1922 {
1923 struct mlxsw_sp_port *mlxsw_sp_port;
1924 int err;
1925
1926 mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL);
1927 if (!mlxsw_sp_port)
1928 return -ENOMEM;
1929
1930 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1931 mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT;
1932
1933 err = mlxsw_core_cpu_port_init(mlxsw_sp->core,
1934 mlxsw_sp_port,
1935 mlxsw_sp->base_mac,
1936 sizeof(mlxsw_sp->base_mac));
1937 if (err) {
1938 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n");
1939 goto err_core_cpu_port_init;
1940 }
1941
1942 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port;
1943 return 0;
1944
1945 err_core_cpu_port_init:
1946 kfree(mlxsw_sp_port);
1947 return err;
1948 }
1949
mlxsw_sp_cpu_port_remove(struct mlxsw_sp * mlxsw_sp)1950 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp)
1951 {
1952 struct mlxsw_sp_port *mlxsw_sp_port =
1953 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT];
1954
1955 mlxsw_core_cpu_port_fini(mlxsw_sp->core);
1956 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL;
1957 kfree(mlxsw_sp_port);
1958 }
1959
mlxsw_sp_local_port_valid(u16 local_port)1960 static bool mlxsw_sp_local_port_valid(u16 local_port)
1961 {
1962 return local_port != MLXSW_PORT_CPU_PORT;
1963 }
1964
mlxsw_sp_port_created(struct mlxsw_sp * mlxsw_sp,u16 local_port)1965 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u16 local_port)
1966 {
1967 if (!mlxsw_sp_local_port_valid(local_port))
1968 return false;
1969 return mlxsw_sp->ports[local_port] != NULL;
1970 }
1971
mlxsw_sp_port_mapping_event_set(struct mlxsw_sp * mlxsw_sp,u16 local_port,bool enable)1972 static int mlxsw_sp_port_mapping_event_set(struct mlxsw_sp *mlxsw_sp,
1973 u16 local_port, bool enable)
1974 {
1975 char pmecr_pl[MLXSW_REG_PMECR_LEN];
1976
1977 mlxsw_reg_pmecr_pack(pmecr_pl, local_port,
1978 enable ? MLXSW_REG_PMECR_E_GENERATE_EVENT :
1979 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT);
1980 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmecr), pmecr_pl);
1981 }
1982
1983 struct mlxsw_sp_port_mapping_event {
1984 struct list_head list;
1985 char pmlp_pl[MLXSW_REG_PMLP_LEN];
1986 };
1987
mlxsw_sp_port_mapping_events_work(struct work_struct * work)1988 static void mlxsw_sp_port_mapping_events_work(struct work_struct *work)
1989 {
1990 struct mlxsw_sp_port_mapping_event *event, *next_event;
1991 struct mlxsw_sp_port_mapping_events *events;
1992 struct mlxsw_sp_port_mapping port_mapping;
1993 struct mlxsw_sp *mlxsw_sp;
1994 struct devlink *devlink;
1995 LIST_HEAD(event_queue);
1996 u16 local_port;
1997 int err;
1998
1999 events = container_of(work, struct mlxsw_sp_port_mapping_events, work);
2000 mlxsw_sp = container_of(events, struct mlxsw_sp, port_mapping_events);
2001 devlink = priv_to_devlink(mlxsw_sp->core);
2002
2003 spin_lock_bh(&events->queue_lock);
2004 list_splice_init(&events->queue, &event_queue);
2005 spin_unlock_bh(&events->queue_lock);
2006
2007 list_for_each_entry_safe(event, next_event, &event_queue, list) {
2008 local_port = mlxsw_reg_pmlp_local_port_get(event->pmlp_pl);
2009 err = mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port,
2010 event->pmlp_pl, &port_mapping);
2011 if (err)
2012 goto out;
2013
2014 if (WARN_ON_ONCE(!port_mapping.width))
2015 goto out;
2016
2017 devl_lock(devlink);
2018
2019 if (!mlxsw_sp_port_created(mlxsw_sp, local_port))
2020 mlxsw_sp_port_create(mlxsw_sp, local_port,
2021 false, &port_mapping);
2022 else
2023 WARN_ON_ONCE(1);
2024
2025 devl_unlock(devlink);
2026
2027 mlxsw_sp->port_mapping[local_port] = port_mapping;
2028
2029 out:
2030 kfree(event);
2031 }
2032 }
2033
2034 static void
mlxsw_sp_port_mapping_listener_func(const struct mlxsw_reg_info * reg,char * pmlp_pl,void * priv)2035 mlxsw_sp_port_mapping_listener_func(const struct mlxsw_reg_info *reg,
2036 char *pmlp_pl, void *priv)
2037 {
2038 struct mlxsw_sp_port_mapping_events *events;
2039 struct mlxsw_sp_port_mapping_event *event;
2040 struct mlxsw_sp *mlxsw_sp = priv;
2041 u16 local_port;
2042
2043 local_port = mlxsw_reg_pmlp_local_port_get(pmlp_pl);
2044 if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port)))
2045 return;
2046
2047 events = &mlxsw_sp->port_mapping_events;
2048 event = kmalloc(sizeof(*event), GFP_ATOMIC);
2049 if (!event)
2050 return;
2051 memcpy(event->pmlp_pl, pmlp_pl, sizeof(event->pmlp_pl));
2052 spin_lock(&events->queue_lock);
2053 list_add_tail(&event->list, &events->queue);
2054 spin_unlock(&events->queue_lock);
2055 mlxsw_core_schedule_work(&events->work);
2056 }
2057
2058 static void
__mlxsw_sp_port_mapping_events_cancel(struct mlxsw_sp * mlxsw_sp)2059 __mlxsw_sp_port_mapping_events_cancel(struct mlxsw_sp *mlxsw_sp)
2060 {
2061 struct mlxsw_sp_port_mapping_event *event, *next_event;
2062 struct mlxsw_sp_port_mapping_events *events;
2063
2064 events = &mlxsw_sp->port_mapping_events;
2065
2066 /* Caller needs to make sure that no new event is going to appear. */
2067 cancel_work_sync(&events->work);
2068 list_for_each_entry_safe(event, next_event, &events->queue, list) {
2069 list_del(&event->list);
2070 kfree(event);
2071 }
2072 }
2073
mlxsw_sp_ports_remove(struct mlxsw_sp * mlxsw_sp)2074 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2075 {
2076 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
2077 int i;
2078
2079 for (i = 1; i < max_ports; i++)
2080 mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false);
2081 /* Make sure all scheduled events are processed */
2082 __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp);
2083
2084 for (i = 1; i < max_ports; i++)
2085 if (mlxsw_sp_port_created(mlxsw_sp, i))
2086 mlxsw_sp_port_remove(mlxsw_sp, i);
2087 mlxsw_sp_cpu_port_remove(mlxsw_sp);
2088 kfree(mlxsw_sp->ports);
2089 mlxsw_sp->ports = NULL;
2090 }
2091
2092 static void
mlxsw_sp_ports_remove_selected(struct mlxsw_core * mlxsw_core,bool (* selector)(void * priv,u16 local_port),void * priv)2093 mlxsw_sp_ports_remove_selected(struct mlxsw_core *mlxsw_core,
2094 bool (*selector)(void *priv, u16 local_port),
2095 void *priv)
2096 {
2097 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2098 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_core);
2099 int i;
2100
2101 for (i = 1; i < max_ports; i++)
2102 if (mlxsw_sp_port_created(mlxsw_sp, i) && selector(priv, i))
2103 mlxsw_sp_port_remove(mlxsw_sp, i);
2104 }
2105
mlxsw_sp_ports_create(struct mlxsw_sp * mlxsw_sp)2106 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2107 {
2108 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
2109 struct mlxsw_sp_port_mapping_events *events;
2110 struct mlxsw_sp_port_mapping *port_mapping;
2111 size_t alloc_size;
2112 int i;
2113 int err;
2114
2115 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
2116 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2117 if (!mlxsw_sp->ports)
2118 return -ENOMEM;
2119
2120 events = &mlxsw_sp->port_mapping_events;
2121 INIT_LIST_HEAD(&events->queue);
2122 spin_lock_init(&events->queue_lock);
2123 INIT_WORK(&events->work, mlxsw_sp_port_mapping_events_work);
2124
2125 for (i = 1; i < max_ports; i++) {
2126 err = mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, true);
2127 if (err)
2128 goto err_event_enable;
2129 }
2130
2131 err = mlxsw_sp_cpu_port_create(mlxsw_sp);
2132 if (err)
2133 goto err_cpu_port_create;
2134
2135 for (i = 1; i < max_ports; i++) {
2136 port_mapping = &mlxsw_sp->port_mapping[i];
2137 if (!port_mapping->width)
2138 continue;
2139 err = mlxsw_sp_port_create(mlxsw_sp, i, false, port_mapping);
2140 if (err)
2141 goto err_port_create;
2142 }
2143 return 0;
2144
2145 err_port_create:
2146 for (i--; i >= 1; i--)
2147 if (mlxsw_sp_port_created(mlxsw_sp, i))
2148 mlxsw_sp_port_remove(mlxsw_sp, i);
2149 i = max_ports;
2150 mlxsw_sp_cpu_port_remove(mlxsw_sp);
2151 err_cpu_port_create:
2152 err_event_enable:
2153 for (i--; i >= 1; i--)
2154 mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false);
2155 /* Make sure all scheduled events are processed */
2156 __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp);
2157 kfree(mlxsw_sp->ports);
2158 mlxsw_sp->ports = NULL;
2159 return err;
2160 }
2161
mlxsw_sp_port_module_info_init(struct mlxsw_sp * mlxsw_sp)2162 static int mlxsw_sp_port_module_info_init(struct mlxsw_sp *mlxsw_sp)
2163 {
2164 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
2165 struct mlxsw_sp_port_mapping *port_mapping;
2166 int i;
2167 int err;
2168
2169 mlxsw_sp->port_mapping = kcalloc(max_ports,
2170 sizeof(struct mlxsw_sp_port_mapping),
2171 GFP_KERNEL);
2172 if (!mlxsw_sp->port_mapping)
2173 return -ENOMEM;
2174
2175 for (i = 1; i < max_ports; i++) {
2176 port_mapping = &mlxsw_sp->port_mapping[i];
2177 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, port_mapping);
2178 if (err)
2179 goto err_port_module_info_get;
2180 }
2181 return 0;
2182
2183 err_port_module_info_get:
2184 kfree(mlxsw_sp->port_mapping);
2185 return err;
2186 }
2187
mlxsw_sp_port_module_info_fini(struct mlxsw_sp * mlxsw_sp)2188 static void mlxsw_sp_port_module_info_fini(struct mlxsw_sp *mlxsw_sp)
2189 {
2190 kfree(mlxsw_sp->port_mapping);
2191 }
2192
2193 static int
mlxsw_sp_port_split_create(struct mlxsw_sp * mlxsw_sp,struct mlxsw_sp_port_mapping * port_mapping,unsigned int count,const char * pmtdb_pl)2194 mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp,
2195 struct mlxsw_sp_port_mapping *port_mapping,
2196 unsigned int count, const char *pmtdb_pl)
2197 {
2198 struct mlxsw_sp_port_mapping split_port_mapping;
2199 int err, i;
2200
2201 split_port_mapping = *port_mapping;
2202 split_port_mapping.width /= count;
2203 for (i = 0; i < count; i++) {
2204 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2205
2206 if (!mlxsw_sp_local_port_valid(s_local_port))
2207 continue;
2208
2209 err = mlxsw_sp_port_create(mlxsw_sp, s_local_port,
2210 true, &split_port_mapping);
2211 if (err)
2212 goto err_port_create;
2213 split_port_mapping.lane += split_port_mapping.width;
2214 }
2215
2216 return 0;
2217
2218 err_port_create:
2219 for (i--; i >= 0; i--) {
2220 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2221
2222 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
2223 mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
2224 }
2225 return err;
2226 }
2227
mlxsw_sp_port_unsplit_create(struct mlxsw_sp * mlxsw_sp,unsigned int count,const char * pmtdb_pl)2228 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
2229 unsigned int count,
2230 const char *pmtdb_pl)
2231 {
2232 struct mlxsw_sp_port_mapping *port_mapping;
2233 int i;
2234
2235 /* Go over original unsplit ports in the gap and recreate them. */
2236 for (i = 0; i < count; i++) {
2237 u16 local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2238
2239 port_mapping = &mlxsw_sp->port_mapping[local_port];
2240 if (!port_mapping->width || !mlxsw_sp_local_port_valid(local_port))
2241 continue;
2242 mlxsw_sp_port_create(mlxsw_sp, local_port,
2243 false, port_mapping);
2244 }
2245 }
2246
2247 static struct mlxsw_sp_port *
mlxsw_sp_port_get_by_local_port(struct mlxsw_sp * mlxsw_sp,u16 local_port)2248 mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u16 local_port)
2249 {
2250 if (mlxsw_sp->ports && mlxsw_sp->ports[local_port])
2251 return mlxsw_sp->ports[local_port];
2252 return NULL;
2253 }
2254
mlxsw_sp_port_split(struct mlxsw_core * mlxsw_core,u16 local_port,unsigned int count,struct netlink_ext_ack * extack)2255 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u16 local_port,
2256 unsigned int count,
2257 struct netlink_ext_ack *extack)
2258 {
2259 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2260 struct mlxsw_sp_port_mapping port_mapping;
2261 struct mlxsw_sp_port *mlxsw_sp_port;
2262 enum mlxsw_reg_pmtdb_status status;
2263 char pmtdb_pl[MLXSW_REG_PMTDB_LEN];
2264 int i;
2265 int err;
2266
2267 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
2268 if (!mlxsw_sp_port) {
2269 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2270 local_port);
2271 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
2272 return -EINVAL;
2273 }
2274
2275 if (mlxsw_sp_port->split) {
2276 NL_SET_ERR_MSG_MOD(extack, "Port is already split");
2277 return -EINVAL;
2278 }
2279
2280 mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index,
2281 mlxsw_sp_port->mapping.module,
2282 mlxsw_sp_port->mapping.module_width / count,
2283 count);
2284 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl);
2285 if (err) {
2286 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info");
2287 return err;
2288 }
2289
2290 status = mlxsw_reg_pmtdb_status_get(pmtdb_pl);
2291 if (status != MLXSW_REG_PMTDB_STATUS_SUCCESS) {
2292 NL_SET_ERR_MSG_MOD(extack, "Unsupported split configuration");
2293 return -EINVAL;
2294 }
2295
2296 port_mapping = mlxsw_sp_port->mapping;
2297
2298 for (i = 0; i < count; i++) {
2299 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2300
2301 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
2302 mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
2303 }
2304
2305 err = mlxsw_sp_port_split_create(mlxsw_sp, &port_mapping,
2306 count, pmtdb_pl);
2307 if (err) {
2308 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2309 goto err_port_split_create;
2310 }
2311
2312 return 0;
2313
2314 err_port_split_create:
2315 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl);
2316
2317 return err;
2318 }
2319
mlxsw_sp_port_unsplit(struct mlxsw_core * mlxsw_core,u16 local_port,struct netlink_ext_ack * extack)2320 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u16 local_port,
2321 struct netlink_ext_ack *extack)
2322 {
2323 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2324 struct mlxsw_sp_port *mlxsw_sp_port;
2325 char pmtdb_pl[MLXSW_REG_PMTDB_LEN];
2326 unsigned int count;
2327 int i;
2328 int err;
2329
2330 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
2331 if (!mlxsw_sp_port) {
2332 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2333 local_port);
2334 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
2335 return -EINVAL;
2336 }
2337
2338 if (!mlxsw_sp_port->split) {
2339 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
2340 return -EINVAL;
2341 }
2342
2343 count = mlxsw_sp_port->mapping.module_width /
2344 mlxsw_sp_port->mapping.width;
2345
2346 mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index,
2347 mlxsw_sp_port->mapping.module,
2348 mlxsw_sp_port->mapping.module_width / count,
2349 count);
2350 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl);
2351 if (err) {
2352 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info");
2353 return err;
2354 }
2355
2356 for (i = 0; i < count; i++) {
2357 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2358
2359 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
2360 mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
2361 }
2362
2363 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl);
2364
2365 return 0;
2366 }
2367
2368 static void
mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port * mlxsw_sp_port)2369 mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port)
2370 {
2371 int i;
2372
2373 for (i = 0; i < TC_MAX_QUEUE; i++)
2374 mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0;
2375 }
2376
mlxsw_sp_pude_event_func(const struct mlxsw_reg_info * reg,char * pude_pl,void * priv)2377 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2378 char *pude_pl, void *priv)
2379 {
2380 struct mlxsw_sp *mlxsw_sp = priv;
2381 struct mlxsw_sp_port *mlxsw_sp_port;
2382 enum mlxsw_reg_pude_oper_status status;
2383 u16 local_port;
2384
2385 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2386
2387 if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port)))
2388 return;
2389 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2390 if (!mlxsw_sp_port)
2391 return;
2392
2393 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2394 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2395 netdev_info(mlxsw_sp_port->dev, "link up\n");
2396 netif_carrier_on(mlxsw_sp_port->dev);
2397 mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0);
2398 } else {
2399 netdev_info(mlxsw_sp_port->dev, "link down\n");
2400 netif_carrier_off(mlxsw_sp_port->dev);
2401 mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port);
2402 }
2403 }
2404
mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp * mlxsw_sp,char * mtpptr_pl,bool ingress)2405 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp,
2406 char *mtpptr_pl, bool ingress)
2407 {
2408 u16 local_port;
2409 u8 num_rec;
2410 int i;
2411
2412 local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl);
2413 num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl);
2414 for (i = 0; i < num_rec; i++) {
2415 u8 domain_number;
2416 u8 message_type;
2417 u16 sequence_id;
2418 u64 timestamp;
2419
2420 mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type,
2421 &domain_number, &sequence_id,
2422 ×tamp);
2423 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port,
2424 message_type, domain_number,
2425 sequence_id, timestamp);
2426 }
2427 }
2428
mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info * reg,char * mtpptr_pl,void * priv)2429 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg,
2430 char *mtpptr_pl, void *priv)
2431 {
2432 struct mlxsw_sp *mlxsw_sp = priv;
2433
2434 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true);
2435 }
2436
mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info * reg,char * mtpptr_pl,void * priv)2437 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg,
2438 char *mtpptr_pl, void *priv)
2439 {
2440 struct mlxsw_sp *mlxsw_sp = priv;
2441
2442 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false);
2443 }
2444
mlxsw_sp_rx_listener_no_mark_func(struct sk_buff * skb,u16 local_port,void * priv)2445 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
2446 u16 local_port, void *priv)
2447 {
2448 struct mlxsw_sp *mlxsw_sp = priv;
2449 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2450 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2451
2452 if (unlikely(!mlxsw_sp_port)) {
2453 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2454 local_port);
2455 return;
2456 }
2457
2458 skb->dev = mlxsw_sp_port->dev;
2459
2460 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2461 u64_stats_update_begin(&pcpu_stats->syncp);
2462 pcpu_stats->rx_packets++;
2463 pcpu_stats->rx_bytes += skb->len;
2464 u64_stats_update_end(&pcpu_stats->syncp);
2465
2466 skb->protocol = eth_type_trans(skb, skb->dev);
2467 netif_receive_skb(skb);
2468 }
2469
mlxsw_sp_rx_listener_mark_func(struct sk_buff * skb,u16 local_port,void * priv)2470 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u16 local_port,
2471 void *priv)
2472 {
2473 skb->offload_fwd_mark = 1;
2474 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
2475 }
2476
mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff * skb,u16 local_port,void * priv)2477 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb,
2478 u16 local_port, void *priv)
2479 {
2480 skb->offload_l3_fwd_mark = 1;
2481 skb->offload_fwd_mark = 1;
2482 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
2483 }
2484
mlxsw_sp_ptp_receive(struct mlxsw_sp * mlxsw_sp,struct sk_buff * skb,u16 local_port)2485 void mlxsw_sp_ptp_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
2486 u16 local_port)
2487 {
2488 mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port);
2489 }
2490
2491 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
2492 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
2493 _is_ctrl, SP_##_trap_group, DISCARD)
2494
2495 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
2496 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
2497 _is_ctrl, SP_##_trap_group, DISCARD)
2498
2499 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
2500 MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \
2501 _is_ctrl, SP_##_trap_group, DISCARD)
2502
2503 #define MLXSW_SP_EVENTL(_func, _trap_id) \
2504 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
2505
2506 static const struct mlxsw_listener mlxsw_sp_listener[] = {
2507 /* Events */
2508 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
2509 /* L2 traps */
2510 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, FID_MISS, false),
2511 /* L3 traps */
2512 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
2513 false),
2514 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
2515 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
2516 false),
2517 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_CLASS_E, FORWARD,
2518 ROUTER_EXP, false),
2519 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_MC_DMAC, FORWARD,
2520 ROUTER_EXP, false),
2521 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_DIP, FORWARD,
2522 ROUTER_EXP, false),
2523 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_DIP_LINK_LOCAL, FORWARD,
2524 ROUTER_EXP, false),
2525 /* Multicast Router Traps */
2526 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
2527 MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
2528 /* NVE traps */
2529 MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, NEIGH_DISCOVERY, false),
2530 };
2531
2532 static const struct mlxsw_listener mlxsw_sp1_listener[] = {
2533 /* Events */
2534 MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0),
2535 MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0),
2536 };
2537
2538 static const struct mlxsw_listener mlxsw_sp2_listener[] = {
2539 /* Events */
2540 MLXSW_SP_EVENTL(mlxsw_sp_port_mapping_listener_func, PMLPE),
2541 };
2542
mlxsw_sp_cpu_policers_set(struct mlxsw_core * mlxsw_core)2543 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
2544 {
2545 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2546 char qpcr_pl[MLXSW_REG_QPCR_LEN];
2547 enum mlxsw_reg_qpcr_ir_units ir_units;
2548 int max_cpu_policers;
2549 bool is_bytes;
2550 u8 burst_size;
2551 u32 rate;
2552 int i, err;
2553
2554 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
2555 return -EIO;
2556
2557 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
2558
2559 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
2560 for (i = 0; i < max_cpu_policers; i++) {
2561 is_bytes = false;
2562 switch (i) {
2563 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2564 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
2565 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS:
2566 rate = 1024;
2567 burst_size = 7;
2568 break;
2569 default:
2570 continue;
2571 }
2572
2573 __set_bit(i, mlxsw_sp->trap->policers_usage);
2574 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
2575 burst_size);
2576 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
2577 if (err)
2578 return err;
2579 }
2580
2581 return 0;
2582 }
2583
mlxsw_sp_trap_groups_set(struct mlxsw_core * mlxsw_core)2584 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
2585 {
2586 char htgt_pl[MLXSW_REG_HTGT_LEN];
2587 enum mlxsw_reg_htgt_trap_group i;
2588 int max_cpu_policers;
2589 int max_trap_groups;
2590 u8 priority, tc;
2591 u16 policer_id;
2592 int err;
2593
2594 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
2595 return -EIO;
2596
2597 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
2598 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
2599
2600 for (i = 0; i < max_trap_groups; i++) {
2601 policer_id = i;
2602 switch (i) {
2603 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2604 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
2605 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS:
2606 priority = 1;
2607 tc = 1;
2608 break;
2609 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
2610 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
2611 tc = MLXSW_REG_HTGT_DEFAULT_TC;
2612 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
2613 break;
2614 default:
2615 continue;
2616 }
2617
2618 if (max_cpu_policers <= policer_id &&
2619 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
2620 return -EIO;
2621
2622 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
2623 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
2624 if (err)
2625 return err;
2626 }
2627
2628 return 0;
2629 }
2630
mlxsw_sp_traps_init(struct mlxsw_sp * mlxsw_sp)2631 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2632 {
2633 struct mlxsw_sp_trap *trap;
2634 u64 max_policers;
2635 int err;
2636
2637 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_CPU_POLICERS))
2638 return -EIO;
2639 max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS);
2640 trap = kzalloc(struct_size(trap, policers_usage,
2641 BITS_TO_LONGS(max_policers)), GFP_KERNEL);
2642 if (!trap)
2643 return -ENOMEM;
2644 trap->max_policers = max_policers;
2645 mlxsw_sp->trap = trap;
2646
2647 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
2648 if (err)
2649 goto err_cpu_policers_set;
2650
2651 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
2652 if (err)
2653 goto err_trap_groups_set;
2654
2655 err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp_listener,
2656 ARRAY_SIZE(mlxsw_sp_listener),
2657 mlxsw_sp);
2658 if (err)
2659 goto err_traps_register;
2660
2661 err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp->listeners,
2662 mlxsw_sp->listeners_count, mlxsw_sp);
2663 if (err)
2664 goto err_extra_traps_init;
2665
2666 return 0;
2667
2668 err_extra_traps_init:
2669 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener,
2670 ARRAY_SIZE(mlxsw_sp_listener),
2671 mlxsw_sp);
2672 err_traps_register:
2673 err_trap_groups_set:
2674 err_cpu_policers_set:
2675 kfree(trap);
2676 return err;
2677 }
2678
mlxsw_sp_traps_fini(struct mlxsw_sp * mlxsw_sp)2679 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2680 {
2681 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp->listeners,
2682 mlxsw_sp->listeners_count,
2683 mlxsw_sp);
2684 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener,
2685 ARRAY_SIZE(mlxsw_sp_listener), mlxsw_sp);
2686 kfree(mlxsw_sp->trap);
2687 }
2688
2689 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe
2690
mlxsw_sp_lag_init(struct mlxsw_sp * mlxsw_sp)2691 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2692 {
2693 char slcr_pl[MLXSW_REG_SLCR_LEN];
2694 u16 max_lag;
2695 u32 seed;
2696 int err;
2697
2698 seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac),
2699 MLXSW_SP_LAG_SEED_INIT);
2700 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2701 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2702 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2703 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2704 MLXSW_REG_SLCR_LAG_HASH_SIP |
2705 MLXSW_REG_SLCR_LAG_HASH_DIP |
2706 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2707 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2708 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
2709 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2710 if (err)
2711 return err;
2712
2713 err = mlxsw_core_max_lag(mlxsw_sp->core, &max_lag);
2714 if (err)
2715 return err;
2716
2717 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
2718 return -EIO;
2719
2720 mlxsw_sp->lags = kcalloc(max_lag, sizeof(struct mlxsw_sp_upper),
2721 GFP_KERNEL);
2722 if (!mlxsw_sp->lags)
2723 return -ENOMEM;
2724
2725 return 0;
2726 }
2727
mlxsw_sp_lag_fini(struct mlxsw_sp * mlxsw_sp)2728 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
2729 {
2730 kfree(mlxsw_sp->lags);
2731 }
2732
2733 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = {
2734 .clock_init = mlxsw_sp1_ptp_clock_init,
2735 .clock_fini = mlxsw_sp1_ptp_clock_fini,
2736 .init = mlxsw_sp1_ptp_init,
2737 .fini = mlxsw_sp1_ptp_fini,
2738 .receive = mlxsw_sp1_ptp_receive,
2739 .transmitted = mlxsw_sp1_ptp_transmitted,
2740 .hwtstamp_get = mlxsw_sp1_ptp_hwtstamp_get,
2741 .hwtstamp_set = mlxsw_sp1_ptp_hwtstamp_set,
2742 .shaper_work = mlxsw_sp1_ptp_shaper_work,
2743 .get_ts_info = mlxsw_sp1_ptp_get_ts_info,
2744 .get_stats_count = mlxsw_sp1_get_stats_count,
2745 .get_stats_strings = mlxsw_sp1_get_stats_strings,
2746 .get_stats = mlxsw_sp1_get_stats,
2747 .txhdr_construct = mlxsw_sp_ptp_txhdr_construct,
2748 };
2749
2750 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = {
2751 .clock_init = mlxsw_sp2_ptp_clock_init,
2752 .clock_fini = mlxsw_sp2_ptp_clock_fini,
2753 .init = mlxsw_sp2_ptp_init,
2754 .fini = mlxsw_sp2_ptp_fini,
2755 .receive = mlxsw_sp2_ptp_receive,
2756 .transmitted = mlxsw_sp2_ptp_transmitted,
2757 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get,
2758 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set,
2759 .shaper_work = mlxsw_sp2_ptp_shaper_work,
2760 .get_ts_info = mlxsw_sp2_ptp_get_ts_info,
2761 .get_stats_count = mlxsw_sp2_get_stats_count,
2762 .get_stats_strings = mlxsw_sp2_get_stats_strings,
2763 .get_stats = mlxsw_sp2_get_stats,
2764 .txhdr_construct = mlxsw_sp2_ptp_txhdr_construct,
2765 };
2766
2767 static const struct mlxsw_sp_ptp_ops mlxsw_sp4_ptp_ops = {
2768 .clock_init = mlxsw_sp2_ptp_clock_init,
2769 .clock_fini = mlxsw_sp2_ptp_clock_fini,
2770 .init = mlxsw_sp2_ptp_init,
2771 .fini = mlxsw_sp2_ptp_fini,
2772 .receive = mlxsw_sp2_ptp_receive,
2773 .transmitted = mlxsw_sp2_ptp_transmitted,
2774 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get,
2775 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set,
2776 .shaper_work = mlxsw_sp2_ptp_shaper_work,
2777 .get_ts_info = mlxsw_sp2_ptp_get_ts_info,
2778 .get_stats_count = mlxsw_sp2_get_stats_count,
2779 .get_stats_strings = mlxsw_sp2_get_stats_strings,
2780 .get_stats = mlxsw_sp2_get_stats,
2781 .txhdr_construct = mlxsw_sp_ptp_txhdr_construct,
2782 };
2783
2784 struct mlxsw_sp_sample_trigger_node {
2785 struct mlxsw_sp_sample_trigger trigger;
2786 struct mlxsw_sp_sample_params params;
2787 struct rhash_head ht_node;
2788 struct rcu_head rcu;
2789 refcount_t refcount;
2790 };
2791
2792 static const struct rhashtable_params mlxsw_sp_sample_trigger_ht_params = {
2793 .key_offset = offsetof(struct mlxsw_sp_sample_trigger_node, trigger),
2794 .head_offset = offsetof(struct mlxsw_sp_sample_trigger_node, ht_node),
2795 .key_len = sizeof(struct mlxsw_sp_sample_trigger),
2796 .automatic_shrinking = true,
2797 };
2798
2799 static void
mlxsw_sp_sample_trigger_key_init(struct mlxsw_sp_sample_trigger * key,const struct mlxsw_sp_sample_trigger * trigger)2800 mlxsw_sp_sample_trigger_key_init(struct mlxsw_sp_sample_trigger *key,
2801 const struct mlxsw_sp_sample_trigger *trigger)
2802 {
2803 memset(key, 0, sizeof(*key));
2804 key->type = trigger->type;
2805 key->local_port = trigger->local_port;
2806 }
2807
2808 /* RCU read lock must be held */
2809 struct mlxsw_sp_sample_params *
mlxsw_sp_sample_trigger_params_lookup(struct mlxsw_sp * mlxsw_sp,const struct mlxsw_sp_sample_trigger * trigger)2810 mlxsw_sp_sample_trigger_params_lookup(struct mlxsw_sp *mlxsw_sp,
2811 const struct mlxsw_sp_sample_trigger *trigger)
2812 {
2813 struct mlxsw_sp_sample_trigger_node *trigger_node;
2814 struct mlxsw_sp_sample_trigger key;
2815
2816 mlxsw_sp_sample_trigger_key_init(&key, trigger);
2817 trigger_node = rhashtable_lookup(&mlxsw_sp->sample_trigger_ht, &key,
2818 mlxsw_sp_sample_trigger_ht_params);
2819 if (!trigger_node)
2820 return NULL;
2821
2822 return &trigger_node->params;
2823 }
2824
2825 static int
mlxsw_sp_sample_trigger_node_init(struct mlxsw_sp * mlxsw_sp,const struct mlxsw_sp_sample_trigger * trigger,const struct mlxsw_sp_sample_params * params)2826 mlxsw_sp_sample_trigger_node_init(struct mlxsw_sp *mlxsw_sp,
2827 const struct mlxsw_sp_sample_trigger *trigger,
2828 const struct mlxsw_sp_sample_params *params)
2829 {
2830 struct mlxsw_sp_sample_trigger_node *trigger_node;
2831 int err;
2832
2833 trigger_node = kzalloc(sizeof(*trigger_node), GFP_KERNEL);
2834 if (!trigger_node)
2835 return -ENOMEM;
2836
2837 trigger_node->trigger = *trigger;
2838 trigger_node->params = *params;
2839 refcount_set(&trigger_node->refcount, 1);
2840
2841 err = rhashtable_insert_fast(&mlxsw_sp->sample_trigger_ht,
2842 &trigger_node->ht_node,
2843 mlxsw_sp_sample_trigger_ht_params);
2844 if (err)
2845 goto err_rhashtable_insert;
2846
2847 return 0;
2848
2849 err_rhashtable_insert:
2850 kfree(trigger_node);
2851 return err;
2852 }
2853
2854 static void
mlxsw_sp_sample_trigger_node_fini(struct mlxsw_sp * mlxsw_sp,struct mlxsw_sp_sample_trigger_node * trigger_node)2855 mlxsw_sp_sample_trigger_node_fini(struct mlxsw_sp *mlxsw_sp,
2856 struct mlxsw_sp_sample_trigger_node *trigger_node)
2857 {
2858 rhashtable_remove_fast(&mlxsw_sp->sample_trigger_ht,
2859 &trigger_node->ht_node,
2860 mlxsw_sp_sample_trigger_ht_params);
2861 kfree_rcu(trigger_node, rcu);
2862 }
2863
2864 int
mlxsw_sp_sample_trigger_params_set(struct mlxsw_sp * mlxsw_sp,const struct mlxsw_sp_sample_trigger * trigger,const struct mlxsw_sp_sample_params * params,struct netlink_ext_ack * extack)2865 mlxsw_sp_sample_trigger_params_set(struct mlxsw_sp *mlxsw_sp,
2866 const struct mlxsw_sp_sample_trigger *trigger,
2867 const struct mlxsw_sp_sample_params *params,
2868 struct netlink_ext_ack *extack)
2869 {
2870 struct mlxsw_sp_sample_trigger_node *trigger_node;
2871 struct mlxsw_sp_sample_trigger key;
2872
2873 ASSERT_RTNL();
2874
2875 mlxsw_sp_sample_trigger_key_init(&key, trigger);
2876
2877 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht,
2878 &key,
2879 mlxsw_sp_sample_trigger_ht_params);
2880 if (!trigger_node)
2881 return mlxsw_sp_sample_trigger_node_init(mlxsw_sp, &key,
2882 params);
2883
2884 if (trigger_node->trigger.local_port) {
2885 NL_SET_ERR_MSG_MOD(extack, "Sampling already enabled on port");
2886 return -EINVAL;
2887 }
2888
2889 if (trigger_node->params.psample_group != params->psample_group ||
2890 trigger_node->params.truncate != params->truncate ||
2891 trigger_node->params.rate != params->rate ||
2892 trigger_node->params.trunc_size != params->trunc_size) {
2893 NL_SET_ERR_MSG_MOD(extack, "Sampling parameters do not match for an existing sampling trigger");
2894 return -EINVAL;
2895 }
2896
2897 refcount_inc(&trigger_node->refcount);
2898
2899 return 0;
2900 }
2901
2902 void
mlxsw_sp_sample_trigger_params_unset(struct mlxsw_sp * mlxsw_sp,const struct mlxsw_sp_sample_trigger * trigger)2903 mlxsw_sp_sample_trigger_params_unset(struct mlxsw_sp *mlxsw_sp,
2904 const struct mlxsw_sp_sample_trigger *trigger)
2905 {
2906 struct mlxsw_sp_sample_trigger_node *trigger_node;
2907 struct mlxsw_sp_sample_trigger key;
2908
2909 ASSERT_RTNL();
2910
2911 mlxsw_sp_sample_trigger_key_init(&key, trigger);
2912
2913 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht,
2914 &key,
2915 mlxsw_sp_sample_trigger_ht_params);
2916 if (!trigger_node)
2917 return;
2918
2919 if (!refcount_dec_and_test(&trigger_node->refcount))
2920 return;
2921
2922 mlxsw_sp_sample_trigger_node_fini(mlxsw_sp, trigger_node);
2923 }
2924
2925 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
2926 unsigned long event, void *ptr);
2927
2928 #define MLXSW_SP_DEFAULT_PARSING_DEPTH 96
2929 #define MLXSW_SP_INCREASED_PARSING_DEPTH 128
2930 #define MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT 4789
2931
mlxsw_sp_parsing_init(struct mlxsw_sp * mlxsw_sp)2932 static void mlxsw_sp_parsing_init(struct mlxsw_sp *mlxsw_sp)
2933 {
2934 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH;
2935 mlxsw_sp->parsing.vxlan_udp_dport = MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT;
2936 mutex_init(&mlxsw_sp->parsing.lock);
2937 }
2938
mlxsw_sp_parsing_fini(struct mlxsw_sp * mlxsw_sp)2939 static void mlxsw_sp_parsing_fini(struct mlxsw_sp *mlxsw_sp)
2940 {
2941 mutex_destroy(&mlxsw_sp->parsing.lock);
2942 }
2943
2944 struct mlxsw_sp_ipv6_addr_node {
2945 struct in6_addr key;
2946 struct rhash_head ht_node;
2947 u32 kvdl_index;
2948 refcount_t refcount;
2949 };
2950
2951 static const struct rhashtable_params mlxsw_sp_ipv6_addr_ht_params = {
2952 .key_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, key),
2953 .head_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, ht_node),
2954 .key_len = sizeof(struct in6_addr),
2955 .automatic_shrinking = true,
2956 };
2957
2958 static int
mlxsw_sp_ipv6_addr_init(struct mlxsw_sp * mlxsw_sp,const struct in6_addr * addr6,u32 * p_kvdl_index)2959 mlxsw_sp_ipv6_addr_init(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6,
2960 u32 *p_kvdl_index)
2961 {
2962 struct mlxsw_sp_ipv6_addr_node *node;
2963 char rips_pl[MLXSW_REG_RIPS_LEN];
2964 int err;
2965
2966 err = mlxsw_sp_kvdl_alloc(mlxsw_sp,
2967 MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1,
2968 p_kvdl_index);
2969 if (err)
2970 return err;
2971
2972 mlxsw_reg_rips_pack(rips_pl, *p_kvdl_index, addr6);
2973 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rips), rips_pl);
2974 if (err)
2975 goto err_rips_write;
2976
2977 node = kzalloc(sizeof(*node), GFP_KERNEL);
2978 if (!node) {
2979 err = -ENOMEM;
2980 goto err_node_alloc;
2981 }
2982
2983 node->key = *addr6;
2984 node->kvdl_index = *p_kvdl_index;
2985 refcount_set(&node->refcount, 1);
2986
2987 err = rhashtable_insert_fast(&mlxsw_sp->ipv6_addr_ht,
2988 &node->ht_node,
2989 mlxsw_sp_ipv6_addr_ht_params);
2990 if (err)
2991 goto err_rhashtable_insert;
2992
2993 return 0;
2994
2995 err_rhashtable_insert:
2996 kfree(node);
2997 err_node_alloc:
2998 err_rips_write:
2999 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1,
3000 *p_kvdl_index);
3001 return err;
3002 }
3003
mlxsw_sp_ipv6_addr_fini(struct mlxsw_sp * mlxsw_sp,struct mlxsw_sp_ipv6_addr_node * node)3004 static void mlxsw_sp_ipv6_addr_fini(struct mlxsw_sp *mlxsw_sp,
3005 struct mlxsw_sp_ipv6_addr_node *node)
3006 {
3007 u32 kvdl_index = node->kvdl_index;
3008
3009 rhashtable_remove_fast(&mlxsw_sp->ipv6_addr_ht, &node->ht_node,
3010 mlxsw_sp_ipv6_addr_ht_params);
3011 kfree(node);
3012 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1,
3013 kvdl_index);
3014 }
3015
mlxsw_sp_ipv6_addr_kvdl_index_get(struct mlxsw_sp * mlxsw_sp,const struct in6_addr * addr6,u32 * p_kvdl_index)3016 int mlxsw_sp_ipv6_addr_kvdl_index_get(struct mlxsw_sp *mlxsw_sp,
3017 const struct in6_addr *addr6,
3018 u32 *p_kvdl_index)
3019 {
3020 struct mlxsw_sp_ipv6_addr_node *node;
3021 int err = 0;
3022
3023 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock);
3024 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6,
3025 mlxsw_sp_ipv6_addr_ht_params);
3026 if (node) {
3027 refcount_inc(&node->refcount);
3028 *p_kvdl_index = node->kvdl_index;
3029 goto out_unlock;
3030 }
3031
3032 err = mlxsw_sp_ipv6_addr_init(mlxsw_sp, addr6, p_kvdl_index);
3033
3034 out_unlock:
3035 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock);
3036 return err;
3037 }
3038
3039 void
mlxsw_sp_ipv6_addr_put(struct mlxsw_sp * mlxsw_sp,const struct in6_addr * addr6)3040 mlxsw_sp_ipv6_addr_put(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6)
3041 {
3042 struct mlxsw_sp_ipv6_addr_node *node;
3043
3044 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock);
3045 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6,
3046 mlxsw_sp_ipv6_addr_ht_params);
3047 if (WARN_ON(!node))
3048 goto out_unlock;
3049
3050 if (!refcount_dec_and_test(&node->refcount))
3051 goto out_unlock;
3052
3053 mlxsw_sp_ipv6_addr_fini(mlxsw_sp, node);
3054
3055 out_unlock:
3056 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock);
3057 }
3058
mlxsw_sp_ipv6_addr_ht_init(struct mlxsw_sp * mlxsw_sp)3059 static int mlxsw_sp_ipv6_addr_ht_init(struct mlxsw_sp *mlxsw_sp)
3060 {
3061 int err;
3062
3063 err = rhashtable_init(&mlxsw_sp->ipv6_addr_ht,
3064 &mlxsw_sp_ipv6_addr_ht_params);
3065 if (err)
3066 return err;
3067
3068 mutex_init(&mlxsw_sp->ipv6_addr_ht_lock);
3069 return 0;
3070 }
3071
mlxsw_sp_ipv6_addr_ht_fini(struct mlxsw_sp * mlxsw_sp)3072 static void mlxsw_sp_ipv6_addr_ht_fini(struct mlxsw_sp *mlxsw_sp)
3073 {
3074 mutex_destroy(&mlxsw_sp->ipv6_addr_ht_lock);
3075 rhashtable_destroy(&mlxsw_sp->ipv6_addr_ht);
3076 }
3077
mlxsw_sp_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info,struct netlink_ext_ack * extack)3078 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
3079 const struct mlxsw_bus_info *mlxsw_bus_info,
3080 struct netlink_ext_ack *extack)
3081 {
3082 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3083 int err;
3084
3085 mlxsw_sp->core = mlxsw_core;
3086 mlxsw_sp->bus_info = mlxsw_bus_info;
3087
3088 mlxsw_sp_parsing_init(mlxsw_sp);
3089 mlxsw_core_emad_string_tlv_enable(mlxsw_core);
3090
3091 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3092 if (err) {
3093 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3094 return err;
3095 }
3096
3097 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3098 if (err) {
3099 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3100 return err;
3101 }
3102
3103 err = mlxsw_sp_pgt_init(mlxsw_sp);
3104 if (err) {
3105 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PGT\n");
3106 goto err_pgt_init;
3107 }
3108
3109 err = mlxsw_sp_fids_init(mlxsw_sp);
3110 if (err) {
3111 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
3112 goto err_fids_init;
3113 }
3114
3115 err = mlxsw_sp_policers_init(mlxsw_sp);
3116 if (err) {
3117 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize policers\n");
3118 goto err_policers_init;
3119 }
3120
3121 err = mlxsw_sp_traps_init(mlxsw_sp);
3122 if (err) {
3123 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3124 goto err_traps_init;
3125 }
3126
3127 err = mlxsw_sp_devlink_traps_init(mlxsw_sp);
3128 if (err) {
3129 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n");
3130 goto err_devlink_traps_init;
3131 }
3132
3133 err = mlxsw_sp_buffers_init(mlxsw_sp);
3134 if (err) {
3135 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3136 goto err_buffers_init;
3137 }
3138
3139 err = mlxsw_sp_lag_init(mlxsw_sp);
3140 if (err) {
3141 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3142 goto err_lag_init;
3143 }
3144
3145 /* Initialize SPAN before router and switchdev, so that those components
3146 * can call mlxsw_sp_span_respin().
3147 */
3148 err = mlxsw_sp_span_init(mlxsw_sp);
3149 if (err) {
3150 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3151 goto err_span_init;
3152 }
3153
3154 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3155 if (err) {
3156 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3157 goto err_switchdev_init;
3158 }
3159
3160 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3161 if (err) {
3162 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3163 goto err_counter_pool_init;
3164 }
3165
3166 err = mlxsw_sp_afa_init(mlxsw_sp);
3167 if (err) {
3168 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3169 goto err_afa_init;
3170 }
3171
3172 err = mlxsw_sp_ipv6_addr_ht_init(mlxsw_sp);
3173 if (err) {
3174 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize hash table for IPv6 addresses\n");
3175 goto err_ipv6_addr_ht_init;
3176 }
3177
3178 err = mlxsw_sp_nve_init(mlxsw_sp);
3179 if (err) {
3180 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
3181 goto err_nve_init;
3182 }
3183
3184 err = mlxsw_sp_acl_init(mlxsw_sp);
3185 if (err) {
3186 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3187 goto err_acl_init;
3188 }
3189
3190 err = mlxsw_sp_router_init(mlxsw_sp, extack);
3191 if (err) {
3192 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3193 goto err_router_init;
3194 }
3195
3196 if (mlxsw_sp->bus_info->read_clock_capable) {
3197 /* NULL is a valid return value from clock_init */
3198 mlxsw_sp->clock =
3199 mlxsw_sp->ptp_ops->clock_init(mlxsw_sp,
3200 mlxsw_sp->bus_info->dev);
3201 if (IS_ERR(mlxsw_sp->clock)) {
3202 err = PTR_ERR(mlxsw_sp->clock);
3203 dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n");
3204 goto err_ptp_clock_init;
3205 }
3206 }
3207
3208 if (mlxsw_sp->clock) {
3209 /* NULL is a valid return value from ptp_ops->init */
3210 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp);
3211 if (IS_ERR(mlxsw_sp->ptp_state)) {
3212 err = PTR_ERR(mlxsw_sp->ptp_state);
3213 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n");
3214 goto err_ptp_init;
3215 }
3216 }
3217
3218 /* Initialize netdevice notifier after SPAN is initialized, so that the
3219 * event handler can call SPAN respin.
3220 */
3221 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3222 err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
3223 &mlxsw_sp->netdevice_nb);
3224 if (err) {
3225 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3226 goto err_netdev_notifier;
3227 }
3228
3229 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3230 if (err) {
3231 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3232 goto err_dpipe_init;
3233 }
3234
3235 err = mlxsw_sp_port_module_info_init(mlxsw_sp);
3236 if (err) {
3237 dev_err(mlxsw_sp->bus_info->dev, "Failed to init port module info\n");
3238 goto err_port_module_info_init;
3239 }
3240
3241 err = rhashtable_init(&mlxsw_sp->sample_trigger_ht,
3242 &mlxsw_sp_sample_trigger_ht_params);
3243 if (err) {
3244 dev_err(mlxsw_sp->bus_info->dev, "Failed to init sampling trigger hashtable\n");
3245 goto err_sample_trigger_init;
3246 }
3247
3248 err = mlxsw_sp_ports_create(mlxsw_sp);
3249 if (err) {
3250 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3251 goto err_ports_create;
3252 }
3253
3254 return 0;
3255
3256 err_ports_create:
3257 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht);
3258 err_sample_trigger_init:
3259 mlxsw_sp_port_module_info_fini(mlxsw_sp);
3260 err_port_module_info_init:
3261 mlxsw_sp_dpipe_fini(mlxsw_sp);
3262 err_dpipe_init:
3263 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
3264 &mlxsw_sp->netdevice_nb);
3265 err_netdev_notifier:
3266 if (mlxsw_sp->clock)
3267 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
3268 err_ptp_init:
3269 if (mlxsw_sp->clock)
3270 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
3271 err_ptp_clock_init:
3272 mlxsw_sp_router_fini(mlxsw_sp);
3273 err_router_init:
3274 mlxsw_sp_acl_fini(mlxsw_sp);
3275 err_acl_init:
3276 mlxsw_sp_nve_fini(mlxsw_sp);
3277 err_nve_init:
3278 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp);
3279 err_ipv6_addr_ht_init:
3280 mlxsw_sp_afa_fini(mlxsw_sp);
3281 err_afa_init:
3282 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3283 err_counter_pool_init:
3284 mlxsw_sp_switchdev_fini(mlxsw_sp);
3285 err_switchdev_init:
3286 mlxsw_sp_span_fini(mlxsw_sp);
3287 err_span_init:
3288 mlxsw_sp_lag_fini(mlxsw_sp);
3289 err_lag_init:
3290 mlxsw_sp_buffers_fini(mlxsw_sp);
3291 err_buffers_init:
3292 mlxsw_sp_devlink_traps_fini(mlxsw_sp);
3293 err_devlink_traps_init:
3294 mlxsw_sp_traps_fini(mlxsw_sp);
3295 err_traps_init:
3296 mlxsw_sp_policers_fini(mlxsw_sp);
3297 err_policers_init:
3298 mlxsw_sp_fids_fini(mlxsw_sp);
3299 err_fids_init:
3300 mlxsw_sp_pgt_fini(mlxsw_sp);
3301 err_pgt_init:
3302 mlxsw_sp_kvdl_fini(mlxsw_sp);
3303 mlxsw_sp_parsing_fini(mlxsw_sp);
3304 return err;
3305 }
3306
mlxsw_sp1_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info,struct netlink_ext_ack * extack)3307 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
3308 const struct mlxsw_bus_info *mlxsw_bus_info,
3309 struct netlink_ext_ack *extack)
3310 {
3311 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3312
3313 mlxsw_sp->switchdev_ops = &mlxsw_sp1_switchdev_ops;
3314 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
3315 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
3316 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
3317 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
3318 mlxsw_sp->acl_rulei_ops = &mlxsw_sp1_acl_rulei_ops;
3319 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
3320 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
3321 mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask;
3322 mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals;
3323 mlxsw_sp->sb_ops = &mlxsw_sp1_sb_ops;
3324 mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops;
3325 mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops;
3326 mlxsw_sp->span_ops = &mlxsw_sp1_span_ops;
3327 mlxsw_sp->policer_core_ops = &mlxsw_sp1_policer_core_ops;
3328 mlxsw_sp->trap_ops = &mlxsw_sp1_trap_ops;
3329 mlxsw_sp->mall_ops = &mlxsw_sp1_mall_ops;
3330 mlxsw_sp->router_ops = &mlxsw_sp1_router_ops;
3331 mlxsw_sp->listeners = mlxsw_sp1_listener;
3332 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener);
3333 mlxsw_sp->fid_family_arr = mlxsw_sp1_fid_family_arr;
3334 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1;
3335 mlxsw_sp->pgt_smpe_index_valid = true;
3336
3337 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
3338 }
3339
mlxsw_sp2_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info,struct netlink_ext_ack * extack)3340 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
3341 const struct mlxsw_bus_info *mlxsw_bus_info,
3342 struct netlink_ext_ack *extack)
3343 {
3344 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3345
3346 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
3347 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3348 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3349 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
3350 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3351 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
3352 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3353 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops;
3354 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
3355 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
3356 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
3357 mlxsw_sp->sb_ops = &mlxsw_sp2_sb_ops;
3358 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
3359 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
3360 mlxsw_sp->span_ops = &mlxsw_sp2_span_ops;
3361 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
3362 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
3363 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
3364 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
3365 mlxsw_sp->listeners = mlxsw_sp2_listener;
3366 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
3367 mlxsw_sp->fid_family_arr = mlxsw_sp2_fid_family_arr;
3368 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2;
3369 mlxsw_sp->pgt_smpe_index_valid = false;
3370
3371 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
3372 }
3373
mlxsw_sp3_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info,struct netlink_ext_ack * extack)3374 static int mlxsw_sp3_init(struct mlxsw_core *mlxsw_core,
3375 const struct mlxsw_bus_info *mlxsw_bus_info,
3376 struct netlink_ext_ack *extack)
3377 {
3378 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3379
3380 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
3381 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3382 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3383 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
3384 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3385 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
3386 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3387 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops;
3388 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
3389 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
3390 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
3391 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops;
3392 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
3393 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
3394 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops;
3395 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
3396 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
3397 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
3398 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
3399 mlxsw_sp->listeners = mlxsw_sp2_listener;
3400 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
3401 mlxsw_sp->fid_family_arr = mlxsw_sp2_fid_family_arr;
3402 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3;
3403 mlxsw_sp->pgt_smpe_index_valid = false;
3404
3405 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
3406 }
3407
mlxsw_sp4_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info,struct netlink_ext_ack * extack)3408 static int mlxsw_sp4_init(struct mlxsw_core *mlxsw_core,
3409 const struct mlxsw_bus_info *mlxsw_bus_info,
3410 struct netlink_ext_ack *extack)
3411 {
3412 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3413
3414 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
3415 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3416 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3417 mlxsw_sp->afk_ops = &mlxsw_sp4_afk_ops;
3418 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3419 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
3420 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3421 mlxsw_sp->acl_bf_ops = &mlxsw_sp4_acl_bf_ops;
3422 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
3423 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
3424 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
3425 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops;
3426 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
3427 mlxsw_sp->ptp_ops = &mlxsw_sp4_ptp_ops;
3428 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops;
3429 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
3430 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
3431 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
3432 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
3433 mlxsw_sp->listeners = mlxsw_sp2_listener;
3434 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
3435 mlxsw_sp->fid_family_arr = mlxsw_sp2_fid_family_arr;
3436 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4;
3437 mlxsw_sp->pgt_smpe_index_valid = false;
3438
3439 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
3440 }
3441
mlxsw_sp_fini(struct mlxsw_core * mlxsw_core)3442 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
3443 {
3444 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3445
3446 mlxsw_sp_ports_remove(mlxsw_sp);
3447 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht);
3448 mlxsw_sp_port_module_info_fini(mlxsw_sp);
3449 mlxsw_sp_dpipe_fini(mlxsw_sp);
3450 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
3451 &mlxsw_sp->netdevice_nb);
3452 if (mlxsw_sp->clock) {
3453 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
3454 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
3455 }
3456 mlxsw_sp_router_fini(mlxsw_sp);
3457 mlxsw_sp_acl_fini(mlxsw_sp);
3458 mlxsw_sp_nve_fini(mlxsw_sp);
3459 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp);
3460 mlxsw_sp_afa_fini(mlxsw_sp);
3461 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3462 mlxsw_sp_switchdev_fini(mlxsw_sp);
3463 mlxsw_sp_span_fini(mlxsw_sp);
3464 mlxsw_sp_lag_fini(mlxsw_sp);
3465 mlxsw_sp_buffers_fini(mlxsw_sp);
3466 mlxsw_sp_devlink_traps_fini(mlxsw_sp);
3467 mlxsw_sp_traps_fini(mlxsw_sp);
3468 mlxsw_sp_policers_fini(mlxsw_sp);
3469 mlxsw_sp_fids_fini(mlxsw_sp);
3470 mlxsw_sp_pgt_fini(mlxsw_sp);
3471 mlxsw_sp_kvdl_fini(mlxsw_sp);
3472 mlxsw_sp_parsing_fini(mlxsw_sp);
3473 }
3474
3475 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
3476 .used_flood_mode = 1,
3477 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED,
3478 .used_max_ib_mc = 1,
3479 .max_ib_mc = 0,
3480 .used_max_pkey = 1,
3481 .max_pkey = 0,
3482 .used_ubridge = 1,
3483 .ubridge = 1,
3484 .used_kvd_sizes = 1,
3485 .kvd_hash_single_parts = 59,
3486 .kvd_hash_double_parts = 41,
3487 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
3488 .swid_config = {
3489 {
3490 .used_type = 1,
3491 .type = MLXSW_PORT_SWID_TYPE_ETH,
3492 }
3493 },
3494 };
3495
3496 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
3497 .used_flood_mode = 1,
3498 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED,
3499 .used_max_ib_mc = 1,
3500 .max_ib_mc = 0,
3501 .used_max_pkey = 1,
3502 .max_pkey = 0,
3503 .used_ubridge = 1,
3504 .ubridge = 1,
3505 .swid_config = {
3506 {
3507 .used_type = 1,
3508 .type = MLXSW_PORT_SWID_TYPE_ETH,
3509 }
3510 },
3511 .used_cqe_time_stamp_type = 1,
3512 .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,
3513 };
3514
3515 /* Reduce number of LAGs from full capacity (256) to the maximum supported LAGs
3516 * in Spectrum-2/3, to avoid regression in number of free entries in the PGT
3517 * table.
3518 */
3519 #define MLXSW_SP4_CONFIG_PROFILE_MAX_LAG 128
3520
3521 static const struct mlxsw_config_profile mlxsw_sp4_config_profile = {
3522 .used_max_lag = 1,
3523 .max_lag = MLXSW_SP4_CONFIG_PROFILE_MAX_LAG,
3524 .used_flood_mode = 1,
3525 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED,
3526 .used_max_ib_mc = 1,
3527 .max_ib_mc = 0,
3528 .used_max_pkey = 1,
3529 .max_pkey = 0,
3530 .used_ubridge = 1,
3531 .ubridge = 1,
3532 .swid_config = {
3533 {
3534 .used_type = 1,
3535 .type = MLXSW_PORT_SWID_TYPE_ETH,
3536 }
3537 },
3538 .used_cqe_time_stamp_type = 1,
3539 .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,
3540 };
3541
3542 static void
mlxsw_sp_resource_size_params_prepare(struct mlxsw_core * mlxsw_core,struct devlink_resource_size_params * kvd_size_params,struct devlink_resource_size_params * linear_size_params,struct devlink_resource_size_params * hash_double_size_params,struct devlink_resource_size_params * hash_single_size_params)3543 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
3544 struct devlink_resource_size_params *kvd_size_params,
3545 struct devlink_resource_size_params *linear_size_params,
3546 struct devlink_resource_size_params *hash_double_size_params,
3547 struct devlink_resource_size_params *hash_single_size_params)
3548 {
3549 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3550 KVD_SINGLE_MIN_SIZE);
3551 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3552 KVD_DOUBLE_MIN_SIZE);
3553 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3554 u32 linear_size_min = 0;
3555
3556 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
3557 MLXSW_SP_KVD_GRANULARITY,
3558 DEVLINK_RESOURCE_UNIT_ENTRY);
3559 devlink_resource_size_params_init(linear_size_params, linear_size_min,
3560 kvd_size - single_size_min -
3561 double_size_min,
3562 MLXSW_SP_KVD_GRANULARITY,
3563 DEVLINK_RESOURCE_UNIT_ENTRY);
3564 devlink_resource_size_params_init(hash_double_size_params,
3565 double_size_min,
3566 kvd_size - single_size_min -
3567 linear_size_min,
3568 MLXSW_SP_KVD_GRANULARITY,
3569 DEVLINK_RESOURCE_UNIT_ENTRY);
3570 devlink_resource_size_params_init(hash_single_size_params,
3571 single_size_min,
3572 kvd_size - double_size_min -
3573 linear_size_min,
3574 MLXSW_SP_KVD_GRANULARITY,
3575 DEVLINK_RESOURCE_UNIT_ENTRY);
3576 }
3577
mlxsw_sp1_resources_kvd_register(struct mlxsw_core * mlxsw_core)3578 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
3579 {
3580 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3581 struct devlink_resource_size_params hash_single_size_params;
3582 struct devlink_resource_size_params hash_double_size_params;
3583 struct devlink_resource_size_params linear_size_params;
3584 struct devlink_resource_size_params kvd_size_params;
3585 u32 kvd_size, single_size, double_size, linear_size;
3586 const struct mlxsw_config_profile *profile;
3587 int err;
3588
3589 profile = &mlxsw_sp1_config_profile;
3590 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3591 return -EIO;
3592
3593 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
3594 &linear_size_params,
3595 &hash_double_size_params,
3596 &hash_single_size_params);
3597
3598 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3599 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
3600 kvd_size, MLXSW_SP_RESOURCE_KVD,
3601 DEVLINK_RESOURCE_ID_PARENT_TOP,
3602 &kvd_size_params);
3603 if (err)
3604 return err;
3605
3606 linear_size = profile->kvd_linear_size;
3607 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
3608 linear_size,
3609 MLXSW_SP_RESOURCE_KVD_LINEAR,
3610 MLXSW_SP_RESOURCE_KVD,
3611 &linear_size_params);
3612 if (err)
3613 return err;
3614
3615 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
3616 if (err)
3617 return err;
3618
3619 double_size = kvd_size - linear_size;
3620 double_size *= profile->kvd_hash_double_parts;
3621 double_size /= profile->kvd_hash_double_parts +
3622 profile->kvd_hash_single_parts;
3623 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
3624 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
3625 double_size,
3626 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3627 MLXSW_SP_RESOURCE_KVD,
3628 &hash_double_size_params);
3629 if (err)
3630 return err;
3631
3632 single_size = kvd_size - double_size - linear_size;
3633 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
3634 single_size,
3635 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3636 MLXSW_SP_RESOURCE_KVD,
3637 &hash_single_size_params);
3638 if (err)
3639 return err;
3640
3641 return 0;
3642 }
3643
mlxsw_sp2_resources_kvd_register(struct mlxsw_core * mlxsw_core)3644 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core)
3645 {
3646 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3647 struct devlink_resource_size_params kvd_size_params;
3648 u32 kvd_size;
3649
3650 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3651 return -EIO;
3652
3653 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3654 devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size,
3655 MLXSW_SP_KVD_GRANULARITY,
3656 DEVLINK_RESOURCE_UNIT_ENTRY);
3657
3658 return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
3659 kvd_size, MLXSW_SP_RESOURCE_KVD,
3660 DEVLINK_RESOURCE_ID_PARENT_TOP,
3661 &kvd_size_params);
3662 }
3663
mlxsw_sp_resources_span_register(struct mlxsw_core * mlxsw_core)3664 static int mlxsw_sp_resources_span_register(struct mlxsw_core *mlxsw_core)
3665 {
3666 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3667 struct devlink_resource_size_params span_size_params;
3668 u32 max_span;
3669
3670 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SPAN))
3671 return -EIO;
3672
3673 max_span = MLXSW_CORE_RES_GET(mlxsw_core, MAX_SPAN);
3674 devlink_resource_size_params_init(&span_size_params, max_span, max_span,
3675 1, DEVLINK_RESOURCE_UNIT_ENTRY);
3676
3677 return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_SPAN,
3678 max_span, MLXSW_SP_RESOURCE_SPAN,
3679 DEVLINK_RESOURCE_ID_PARENT_TOP,
3680 &span_size_params);
3681 }
3682
3683 static int
mlxsw_sp_resources_rif_mac_profile_register(struct mlxsw_core * mlxsw_core)3684 mlxsw_sp_resources_rif_mac_profile_register(struct mlxsw_core *mlxsw_core)
3685 {
3686 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3687 struct devlink_resource_size_params size_params;
3688 u8 max_rif_mac_profiles;
3689
3690 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIF_MAC_PROFILES))
3691 max_rif_mac_profiles = 1;
3692 else
3693 max_rif_mac_profiles = MLXSW_CORE_RES_GET(mlxsw_core,
3694 MAX_RIF_MAC_PROFILES);
3695 devlink_resource_size_params_init(&size_params, max_rif_mac_profiles,
3696 max_rif_mac_profiles, 1,
3697 DEVLINK_RESOURCE_UNIT_ENTRY);
3698
3699 return devl_resource_register(devlink,
3700 "rif_mac_profiles",
3701 max_rif_mac_profiles,
3702 MLXSW_SP_RESOURCE_RIF_MAC_PROFILES,
3703 DEVLINK_RESOURCE_ID_PARENT_TOP,
3704 &size_params);
3705 }
3706
mlxsw_sp_resources_rifs_register(struct mlxsw_core * mlxsw_core)3707 static int mlxsw_sp_resources_rifs_register(struct mlxsw_core *mlxsw_core)
3708 {
3709 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3710 struct devlink_resource_size_params size_params;
3711 u64 max_rifs;
3712
3713 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIFS))
3714 return -EIO;
3715
3716 max_rifs = MLXSW_CORE_RES_GET(mlxsw_core, MAX_RIFS);
3717 devlink_resource_size_params_init(&size_params, max_rifs, max_rifs,
3718 1, DEVLINK_RESOURCE_UNIT_ENTRY);
3719
3720 return devl_resource_register(devlink, "rifs", max_rifs,
3721 MLXSW_SP_RESOURCE_RIFS,
3722 DEVLINK_RESOURCE_ID_PARENT_TOP,
3723 &size_params);
3724 }
3725
mlxsw_sp1_resources_register(struct mlxsw_core * mlxsw_core)3726 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
3727 {
3728 int err;
3729
3730 err = mlxsw_sp1_resources_kvd_register(mlxsw_core);
3731 if (err)
3732 return err;
3733
3734 err = mlxsw_sp_resources_span_register(mlxsw_core);
3735 if (err)
3736 goto err_resources_span_register;
3737
3738 err = mlxsw_sp_counter_resources_register(mlxsw_core);
3739 if (err)
3740 goto err_resources_counter_register;
3741
3742 err = mlxsw_sp_policer_resources_register(mlxsw_core);
3743 if (err)
3744 goto err_policer_resources_register;
3745
3746 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core);
3747 if (err)
3748 goto err_resources_rif_mac_profile_register;
3749
3750 err = mlxsw_sp_resources_rifs_register(mlxsw_core);
3751 if (err)
3752 goto err_resources_rifs_register;
3753
3754 return 0;
3755
3756 err_resources_rifs_register:
3757 err_resources_rif_mac_profile_register:
3758 err_policer_resources_register:
3759 err_resources_counter_register:
3760 err_resources_span_register:
3761 devl_resources_unregister(priv_to_devlink(mlxsw_core));
3762 return err;
3763 }
3764
mlxsw_sp2_resources_register(struct mlxsw_core * mlxsw_core)3765 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
3766 {
3767 int err;
3768
3769 err = mlxsw_sp2_resources_kvd_register(mlxsw_core);
3770 if (err)
3771 return err;
3772
3773 err = mlxsw_sp_resources_span_register(mlxsw_core);
3774 if (err)
3775 goto err_resources_span_register;
3776
3777 err = mlxsw_sp_counter_resources_register(mlxsw_core);
3778 if (err)
3779 goto err_resources_counter_register;
3780
3781 err = mlxsw_sp_policer_resources_register(mlxsw_core);
3782 if (err)
3783 goto err_policer_resources_register;
3784
3785 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core);
3786 if (err)
3787 goto err_resources_rif_mac_profile_register;
3788
3789 err = mlxsw_sp_resources_rifs_register(mlxsw_core);
3790 if (err)
3791 goto err_resources_rifs_register;
3792
3793 return 0;
3794
3795 err_resources_rifs_register:
3796 err_resources_rif_mac_profile_register:
3797 err_policer_resources_register:
3798 err_resources_counter_register:
3799 err_resources_span_register:
3800 devl_resources_unregister(priv_to_devlink(mlxsw_core));
3801 return err;
3802 }
3803
mlxsw_sp_kvd_sizes_get(struct mlxsw_core * mlxsw_core,const struct mlxsw_config_profile * profile,u64 * p_single_size,u64 * p_double_size,u64 * p_linear_size)3804 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
3805 const struct mlxsw_config_profile *profile,
3806 u64 *p_single_size, u64 *p_double_size,
3807 u64 *p_linear_size)
3808 {
3809 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3810 u32 double_size;
3811 int err;
3812
3813 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3814 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
3815 return -EIO;
3816
3817 /* The hash part is what left of the kvd without the
3818 * linear part. It is split to the single size and
3819 * double size by the parts ratio from the profile.
3820 * Both sizes must be a multiplications of the
3821 * granularity from the profile. In case the user
3822 * provided the sizes they are obtained via devlink.
3823 */
3824 err = devl_resource_size_get(devlink,
3825 MLXSW_SP_RESOURCE_KVD_LINEAR,
3826 p_linear_size);
3827 if (err)
3828 *p_linear_size = profile->kvd_linear_size;
3829
3830 err = devl_resource_size_get(devlink,
3831 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3832 p_double_size);
3833 if (err) {
3834 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3835 *p_linear_size;
3836 double_size *= profile->kvd_hash_double_parts;
3837 double_size /= profile->kvd_hash_double_parts +
3838 profile->kvd_hash_single_parts;
3839 *p_double_size = rounddown(double_size,
3840 MLXSW_SP_KVD_GRANULARITY);
3841 }
3842
3843 err = devl_resource_size_get(devlink,
3844 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3845 p_single_size);
3846 if (err)
3847 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3848 *p_double_size - *p_linear_size;
3849
3850 /* Check results are legal. */
3851 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3852 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3853 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
3854 return -EIO;
3855
3856 return 0;
3857 }
3858
3859 static int
mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx)3860 mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink *devlink, u32 id,
3861 struct devlink_param_gset_ctx *ctx)
3862 {
3863 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
3864 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3865
3866 ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp);
3867 return 0;
3868 }
3869
3870 static int
mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx)3871 mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink *devlink, u32 id,
3872 struct devlink_param_gset_ctx *ctx)
3873 {
3874 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
3875 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3876
3877 return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32);
3878 }
3879
3880 static const struct devlink_param mlxsw_sp2_devlink_params[] = {
3881 DEVLINK_PARAM_DRIVER(MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
3882 "acl_region_rehash_interval",
3883 DEVLINK_PARAM_TYPE_U32,
3884 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
3885 mlxsw_sp_params_acl_region_rehash_intrvl_get,
3886 mlxsw_sp_params_acl_region_rehash_intrvl_set,
3887 NULL),
3888 };
3889
mlxsw_sp2_params_register(struct mlxsw_core * mlxsw_core)3890 static int mlxsw_sp2_params_register(struct mlxsw_core *mlxsw_core)
3891 {
3892 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3893 union devlink_param_value value;
3894 int err;
3895
3896 err = devlink_params_register(devlink, mlxsw_sp2_devlink_params,
3897 ARRAY_SIZE(mlxsw_sp2_devlink_params));
3898 if (err)
3899 return err;
3900
3901 value.vu32 = 0;
3902 devlink_param_driverinit_value_set(devlink,
3903 MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
3904 value);
3905 return 0;
3906 }
3907
mlxsw_sp2_params_unregister(struct mlxsw_core * mlxsw_core)3908 static void mlxsw_sp2_params_unregister(struct mlxsw_core *mlxsw_core)
3909 {
3910 devlink_params_unregister(priv_to_devlink(mlxsw_core),
3911 mlxsw_sp2_devlink_params,
3912 ARRAY_SIZE(mlxsw_sp2_devlink_params));
3913 }
3914
mlxsw_sp_ptp_transmitted(struct mlxsw_core * mlxsw_core,struct sk_buff * skb,u16 local_port)3915 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core,
3916 struct sk_buff *skb, u16 local_port)
3917 {
3918 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3919
3920 skb_pull(skb, MLXSW_TXHDR_LEN);
3921 mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port);
3922 }
3923
3924 static struct mlxsw_driver mlxsw_sp1_driver = {
3925 .kind = mlxsw_sp1_driver_name,
3926 .priv_size = sizeof(struct mlxsw_sp),
3927 .fw_req_rev = &mlxsw_sp1_fw_rev,
3928 .fw_filename = MLXSW_SP1_FW_FILENAME,
3929 .init = mlxsw_sp1_init,
3930 .fini = mlxsw_sp_fini,
3931 .port_split = mlxsw_sp_port_split,
3932 .port_unsplit = mlxsw_sp_port_unsplit,
3933 .sb_pool_get = mlxsw_sp_sb_pool_get,
3934 .sb_pool_set = mlxsw_sp_sb_pool_set,
3935 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3936 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3937 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3938 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3939 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3940 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3941 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3942 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3943 .trap_init = mlxsw_sp_trap_init,
3944 .trap_fini = mlxsw_sp_trap_fini,
3945 .trap_action_set = mlxsw_sp_trap_action_set,
3946 .trap_group_init = mlxsw_sp_trap_group_init,
3947 .trap_group_set = mlxsw_sp_trap_group_set,
3948 .trap_policer_init = mlxsw_sp_trap_policer_init,
3949 .trap_policer_fini = mlxsw_sp_trap_policer_fini,
3950 .trap_policer_set = mlxsw_sp_trap_policer_set,
3951 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
3952 .txhdr_construct = mlxsw_sp_txhdr_construct,
3953 .resources_register = mlxsw_sp1_resources_register,
3954 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
3955 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
3956 .txhdr_len = MLXSW_TXHDR_LEN,
3957 .profile = &mlxsw_sp1_config_profile,
3958 .sdq_supports_cqe_v2 = false,
3959 };
3960
3961 static struct mlxsw_driver mlxsw_sp2_driver = {
3962 .kind = mlxsw_sp2_driver_name,
3963 .priv_size = sizeof(struct mlxsw_sp),
3964 .fw_req_rev = &mlxsw_sp2_fw_rev,
3965 .fw_filename = MLXSW_SP2_FW_FILENAME,
3966 .init = mlxsw_sp2_init,
3967 .fini = mlxsw_sp_fini,
3968 .port_split = mlxsw_sp_port_split,
3969 .port_unsplit = mlxsw_sp_port_unsplit,
3970 .ports_remove_selected = mlxsw_sp_ports_remove_selected,
3971 .sb_pool_get = mlxsw_sp_sb_pool_get,
3972 .sb_pool_set = mlxsw_sp_sb_pool_set,
3973 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3974 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3975 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3976 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3977 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3978 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3979 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3980 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3981 .trap_init = mlxsw_sp_trap_init,
3982 .trap_fini = mlxsw_sp_trap_fini,
3983 .trap_action_set = mlxsw_sp_trap_action_set,
3984 .trap_group_init = mlxsw_sp_trap_group_init,
3985 .trap_group_set = mlxsw_sp_trap_group_set,
3986 .trap_policer_init = mlxsw_sp_trap_policer_init,
3987 .trap_policer_fini = mlxsw_sp_trap_policer_fini,
3988 .trap_policer_set = mlxsw_sp_trap_policer_set,
3989 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
3990 .txhdr_construct = mlxsw_sp_txhdr_construct,
3991 .resources_register = mlxsw_sp2_resources_register,
3992 .params_register = mlxsw_sp2_params_register,
3993 .params_unregister = mlxsw_sp2_params_unregister,
3994 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
3995 .txhdr_len = MLXSW_TXHDR_LEN,
3996 .profile = &mlxsw_sp2_config_profile,
3997 .sdq_supports_cqe_v2 = true,
3998 };
3999
4000 static struct mlxsw_driver mlxsw_sp3_driver = {
4001 .kind = mlxsw_sp3_driver_name,
4002 .priv_size = sizeof(struct mlxsw_sp),
4003 .fw_req_rev = &mlxsw_sp3_fw_rev,
4004 .fw_filename = MLXSW_SP3_FW_FILENAME,
4005 .init = mlxsw_sp3_init,
4006 .fini = mlxsw_sp_fini,
4007 .port_split = mlxsw_sp_port_split,
4008 .port_unsplit = mlxsw_sp_port_unsplit,
4009 .ports_remove_selected = mlxsw_sp_ports_remove_selected,
4010 .sb_pool_get = mlxsw_sp_sb_pool_get,
4011 .sb_pool_set = mlxsw_sp_sb_pool_set,
4012 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4013 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4014 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4015 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4016 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4017 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4018 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4019 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4020 .trap_init = mlxsw_sp_trap_init,
4021 .trap_fini = mlxsw_sp_trap_fini,
4022 .trap_action_set = mlxsw_sp_trap_action_set,
4023 .trap_group_init = mlxsw_sp_trap_group_init,
4024 .trap_group_set = mlxsw_sp_trap_group_set,
4025 .trap_policer_init = mlxsw_sp_trap_policer_init,
4026 .trap_policer_fini = mlxsw_sp_trap_policer_fini,
4027 .trap_policer_set = mlxsw_sp_trap_policer_set,
4028 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
4029 .txhdr_construct = mlxsw_sp_txhdr_construct,
4030 .resources_register = mlxsw_sp2_resources_register,
4031 .params_register = mlxsw_sp2_params_register,
4032 .params_unregister = mlxsw_sp2_params_unregister,
4033 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
4034 .txhdr_len = MLXSW_TXHDR_LEN,
4035 .profile = &mlxsw_sp2_config_profile,
4036 .sdq_supports_cqe_v2 = true,
4037 };
4038
4039 static struct mlxsw_driver mlxsw_sp4_driver = {
4040 .kind = mlxsw_sp4_driver_name,
4041 .priv_size = sizeof(struct mlxsw_sp),
4042 .init = mlxsw_sp4_init,
4043 .fini = mlxsw_sp_fini,
4044 .port_split = mlxsw_sp_port_split,
4045 .port_unsplit = mlxsw_sp_port_unsplit,
4046 .ports_remove_selected = mlxsw_sp_ports_remove_selected,
4047 .sb_pool_get = mlxsw_sp_sb_pool_get,
4048 .sb_pool_set = mlxsw_sp_sb_pool_set,
4049 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4050 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4051 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4052 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4053 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4054 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4055 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4056 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4057 .trap_init = mlxsw_sp_trap_init,
4058 .trap_fini = mlxsw_sp_trap_fini,
4059 .trap_action_set = mlxsw_sp_trap_action_set,
4060 .trap_group_init = mlxsw_sp_trap_group_init,
4061 .trap_group_set = mlxsw_sp_trap_group_set,
4062 .trap_policer_init = mlxsw_sp_trap_policer_init,
4063 .trap_policer_fini = mlxsw_sp_trap_policer_fini,
4064 .trap_policer_set = mlxsw_sp_trap_policer_set,
4065 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
4066 .txhdr_construct = mlxsw_sp_txhdr_construct,
4067 .resources_register = mlxsw_sp2_resources_register,
4068 .params_register = mlxsw_sp2_params_register,
4069 .params_unregister = mlxsw_sp2_params_unregister,
4070 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
4071 .txhdr_len = MLXSW_TXHDR_LEN,
4072 .profile = &mlxsw_sp4_config_profile,
4073 .sdq_supports_cqe_v2 = true,
4074 };
4075
mlxsw_sp_port_dev_check(const struct net_device * dev)4076 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
4077 {
4078 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4079 }
4080
mlxsw_sp_lower_dev_walk(struct net_device * lower_dev,struct netdev_nested_priv * priv)4081 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev,
4082 struct netdev_nested_priv *priv)
4083 {
4084 int ret = 0;
4085
4086 if (mlxsw_sp_port_dev_check(lower_dev)) {
4087 priv->data = (void *)netdev_priv(lower_dev);
4088 ret = 1;
4089 }
4090
4091 return ret;
4092 }
4093
mlxsw_sp_port_dev_lower_find(struct net_device * dev)4094 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
4095 {
4096 struct netdev_nested_priv priv = {
4097 .data = NULL,
4098 };
4099
4100 if (mlxsw_sp_port_dev_check(dev))
4101 return netdev_priv(dev);
4102
4103 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &priv);
4104
4105 return (struct mlxsw_sp_port *)priv.data;
4106 }
4107
mlxsw_sp_lower_get(struct net_device * dev)4108 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
4109 {
4110 struct mlxsw_sp_port *mlxsw_sp_port;
4111
4112 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4113 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4114 }
4115
mlxsw_sp_port_dev_lower_find_rcu(struct net_device * dev)4116 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
4117 {
4118 struct netdev_nested_priv priv = {
4119 .data = NULL,
4120 };
4121
4122 if (mlxsw_sp_port_dev_check(dev))
4123 return netdev_priv(dev);
4124
4125 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4126 &priv);
4127
4128 return (struct mlxsw_sp_port *)priv.data;
4129 }
4130
mlxsw_sp_port_lower_dev_hold(struct net_device * dev)4131 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4132 {
4133 struct mlxsw_sp_port *mlxsw_sp_port;
4134
4135 rcu_read_lock();
4136 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4137 if (mlxsw_sp_port)
4138 dev_hold(mlxsw_sp_port->dev);
4139 rcu_read_unlock();
4140 return mlxsw_sp_port;
4141 }
4142
mlxsw_sp_port_dev_put(struct mlxsw_sp_port * mlxsw_sp_port)4143 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4144 {
4145 dev_put(mlxsw_sp_port->dev);
4146 }
4147
mlxsw_sp_parsing_depth_inc(struct mlxsw_sp * mlxsw_sp)4148 int mlxsw_sp_parsing_depth_inc(struct mlxsw_sp *mlxsw_sp)
4149 {
4150 char mprs_pl[MLXSW_REG_MPRS_LEN];
4151 int err = 0;
4152
4153 mutex_lock(&mlxsw_sp->parsing.lock);
4154
4155 if (refcount_inc_not_zero(&mlxsw_sp->parsing.parsing_depth_ref))
4156 goto out_unlock;
4157
4158 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_INCREASED_PARSING_DEPTH,
4159 mlxsw_sp->parsing.vxlan_udp_dport);
4160 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
4161 if (err)
4162 goto out_unlock;
4163
4164 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_INCREASED_PARSING_DEPTH;
4165 refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 1);
4166
4167 out_unlock:
4168 mutex_unlock(&mlxsw_sp->parsing.lock);
4169 return err;
4170 }
4171
mlxsw_sp_parsing_depth_dec(struct mlxsw_sp * mlxsw_sp)4172 void mlxsw_sp_parsing_depth_dec(struct mlxsw_sp *mlxsw_sp)
4173 {
4174 char mprs_pl[MLXSW_REG_MPRS_LEN];
4175
4176 mutex_lock(&mlxsw_sp->parsing.lock);
4177
4178 if (!refcount_dec_and_test(&mlxsw_sp->parsing.parsing_depth_ref))
4179 goto out_unlock;
4180
4181 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_DEFAULT_PARSING_DEPTH,
4182 mlxsw_sp->parsing.vxlan_udp_dport);
4183 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
4184 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH;
4185
4186 out_unlock:
4187 mutex_unlock(&mlxsw_sp->parsing.lock);
4188 }
4189
mlxsw_sp_parsing_vxlan_udp_dport_set(struct mlxsw_sp * mlxsw_sp,__be16 udp_dport)4190 int mlxsw_sp_parsing_vxlan_udp_dport_set(struct mlxsw_sp *mlxsw_sp,
4191 __be16 udp_dport)
4192 {
4193 char mprs_pl[MLXSW_REG_MPRS_LEN];
4194 int err;
4195
4196 mutex_lock(&mlxsw_sp->parsing.lock);
4197
4198 mlxsw_reg_mprs_pack(mprs_pl, mlxsw_sp->parsing.parsing_depth,
4199 be16_to_cpu(udp_dport));
4200 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
4201 if (err)
4202 goto out_unlock;
4203
4204 mlxsw_sp->parsing.vxlan_udp_dport = be16_to_cpu(udp_dport);
4205
4206 out_unlock:
4207 mutex_unlock(&mlxsw_sp->parsing.lock);
4208 return err;
4209 }
4210
4211 static void
mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port * mlxsw_sp_port,struct net_device * lag_dev)4212 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
4213 struct net_device *lag_dev)
4214 {
4215 struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
4216 struct net_device *upper_dev;
4217 struct list_head *iter;
4218
4219 if (netif_is_bridge_port(lag_dev))
4220 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
4221
4222 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
4223 if (!netif_is_bridge_port(upper_dev))
4224 continue;
4225 br_dev = netdev_master_upper_dev_get(upper_dev);
4226 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
4227 }
4228 }
4229
mlxsw_sp_lag_create(struct mlxsw_sp * mlxsw_sp,u16 lag_id)4230 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4231 {
4232 char sldr_pl[MLXSW_REG_SLDR_LEN];
4233
4234 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4235 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4236 }
4237
mlxsw_sp_lag_destroy(struct mlxsw_sp * mlxsw_sp,u16 lag_id)4238 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4239 {
4240 char sldr_pl[MLXSW_REG_SLDR_LEN];
4241
4242 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4243 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4244 }
4245
mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id,u8 port_index)4246 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4247 u16 lag_id, u8 port_index)
4248 {
4249 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4250 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4251
4252 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4253 lag_id, port_index);
4254 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4255 }
4256
mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4257 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4258 u16 lag_id)
4259 {
4260 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4261 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4262
4263 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4264 lag_id);
4265 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4266 }
4267
mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4268 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4269 u16 lag_id)
4270 {
4271 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4272 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4273
4274 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4275 lag_id);
4276 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4277 }
4278
mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4279 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4280 u16 lag_id)
4281 {
4282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4283 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4284
4285 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4286 lag_id);
4287 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4288 }
4289
mlxsw_sp_lag_index_get(struct mlxsw_sp * mlxsw_sp,struct net_device * lag_dev,u16 * p_lag_id)4290 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4291 struct net_device *lag_dev,
4292 u16 *p_lag_id)
4293 {
4294 struct mlxsw_sp_upper *lag;
4295 int free_lag_id = -1;
4296 u16 max_lag;
4297 int err, i;
4298
4299 err = mlxsw_core_max_lag(mlxsw_sp->core, &max_lag);
4300 if (err)
4301 return err;
4302
4303 for (i = 0; i < max_lag; i++) {
4304 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4305 if (lag->ref_count) {
4306 if (lag->dev == lag_dev) {
4307 *p_lag_id = i;
4308 return 0;
4309 }
4310 } else if (free_lag_id < 0) {
4311 free_lag_id = i;
4312 }
4313 }
4314 if (free_lag_id < 0)
4315 return -EBUSY;
4316 *p_lag_id = free_lag_id;
4317 return 0;
4318 }
4319
4320 static bool
mlxsw_sp_master_lag_check(struct mlxsw_sp * mlxsw_sp,struct net_device * lag_dev,struct netdev_lag_upper_info * lag_upper_info,struct netlink_ext_ack * extack)4321 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4322 struct net_device *lag_dev,
4323 struct netdev_lag_upper_info *lag_upper_info,
4324 struct netlink_ext_ack *extack)
4325 {
4326 u16 lag_id;
4327
4328 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4329 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
4330 return false;
4331 }
4332 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4333 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
4334 return false;
4335 }
4336 return true;
4337 }
4338
mlxsw_sp_port_lag_index_get(struct mlxsw_sp * mlxsw_sp,u16 lag_id,u8 * p_port_index)4339 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4340 u16 lag_id, u8 *p_port_index)
4341 {
4342 u64 max_lag_members;
4343 int i;
4344
4345 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4346 MAX_LAG_MEMBERS);
4347 for (i = 0; i < max_lag_members; i++) {
4348 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4349 *p_port_index = i;
4350 return 0;
4351 }
4352 }
4353 return -EBUSY;
4354 }
4355
mlxsw_sp_port_lag_join(struct mlxsw_sp_port * mlxsw_sp_port,struct net_device * lag_dev,struct netlink_ext_ack * extack)4356 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4357 struct net_device *lag_dev,
4358 struct netlink_ext_ack *extack)
4359 {
4360 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4361 struct mlxsw_sp_upper *lag;
4362 u16 lag_id;
4363 u8 port_index;
4364 int err;
4365
4366 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4367 if (err)
4368 return err;
4369 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4370 if (!lag->ref_count) {
4371 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4372 if (err)
4373 return err;
4374 lag->dev = lag_dev;
4375 }
4376
4377 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4378 if (err)
4379 return err;
4380 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4381 if (err)
4382 goto err_col_port_add;
4383
4384 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4385 mlxsw_sp_port->local_port);
4386 mlxsw_sp_port->lag_id = lag_id;
4387 mlxsw_sp_port->lagged = 1;
4388 lag->ref_count++;
4389
4390 /* Port is no longer usable as a router interface */
4391 if (mlxsw_sp_port->default_vlan->fid)
4392 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan);
4393
4394 /* Join a router interface configured on the LAG, if exists */
4395 err = mlxsw_sp_port_vlan_router_join(mlxsw_sp_port->default_vlan,
4396 lag_dev, extack);
4397 if (err)
4398 goto err_router_join;
4399
4400 return 0;
4401
4402 err_router_join:
4403 lag->ref_count--;
4404 mlxsw_sp_port->lagged = 0;
4405 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4406 mlxsw_sp_port->local_port);
4407 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4408 err_col_port_add:
4409 if (!lag->ref_count)
4410 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4411 return err;
4412 }
4413
mlxsw_sp_port_lag_leave(struct mlxsw_sp_port * mlxsw_sp_port,struct net_device * lag_dev)4414 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4415 struct net_device *lag_dev)
4416 {
4417 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4418 u16 lag_id = mlxsw_sp_port->lag_id;
4419 struct mlxsw_sp_upper *lag;
4420
4421 if (!mlxsw_sp_port->lagged)
4422 return;
4423 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4424 WARN_ON(lag->ref_count == 0);
4425
4426 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4427
4428 /* Any VLANs configured on the port are no longer valid */
4429 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false);
4430 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan);
4431 /* Make the LAG and its directly linked uppers leave bridges they
4432 * are memeber in
4433 */
4434 mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
4435
4436 if (lag->ref_count == 1)
4437 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4438
4439 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4440 mlxsw_sp_port->local_port);
4441 mlxsw_sp_port->lagged = 0;
4442 lag->ref_count--;
4443
4444 /* Make sure untagged frames are allowed to ingress */
4445 mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID,
4446 ETH_P_8021Q);
4447 }
4448
mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4449 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4450 u16 lag_id)
4451 {
4452 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4453 char sldr_pl[MLXSW_REG_SLDR_LEN];
4454
4455 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4456 mlxsw_sp_port->local_port);
4457 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4458 }
4459
mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4460 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4461 u16 lag_id)
4462 {
4463 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4464 char sldr_pl[MLXSW_REG_SLDR_LEN];
4465
4466 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4467 mlxsw_sp_port->local_port);
4468 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4469 }
4470
4471 static int
mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port * mlxsw_sp_port)4472 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port)
4473 {
4474 int err;
4475
4476 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port,
4477 mlxsw_sp_port->lag_id);
4478 if (err)
4479 return err;
4480
4481 err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
4482 if (err)
4483 goto err_dist_port_add;
4484
4485 return 0;
4486
4487 err_dist_port_add:
4488 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id);
4489 return err;
4490 }
4491
4492 static int
mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port * mlxsw_sp_port)4493 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port)
4494 {
4495 int err;
4496
4497 err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4498 mlxsw_sp_port->lag_id);
4499 if (err)
4500 return err;
4501
4502 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port,
4503 mlxsw_sp_port->lag_id);
4504 if (err)
4505 goto err_col_port_disable;
4506
4507 return 0;
4508
4509 err_col_port_disable:
4510 mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
4511 return err;
4512 }
4513
mlxsw_sp_port_lag_changed(struct mlxsw_sp_port * mlxsw_sp_port,struct netdev_lag_lower_state_info * info)4514 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4515 struct netdev_lag_lower_state_info *info)
4516 {
4517 if (info->tx_enabled)
4518 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port);
4519 else
4520 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
4521 }
4522
mlxsw_sp_port_stp_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable)4523 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4524 bool enable)
4525 {
4526 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4527 enum mlxsw_reg_spms_state spms_state;
4528 char *spms_pl;
4529 u16 vid;
4530 int err;
4531
4532 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4533 MLXSW_REG_SPMS_STATE_DISCARDING;
4534
4535 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4536 if (!spms_pl)
4537 return -ENOMEM;
4538 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4539
4540 for (vid = 0; vid < VLAN_N_VID; vid++)
4541 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4542
4543 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4544 kfree(spms_pl);
4545 return err;
4546 }
4547
mlxsw_sp_port_ovs_join(struct mlxsw_sp_port * mlxsw_sp_port)4548 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4549 {
4550 u16 vid = 1;
4551 int err;
4552
4553 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
4554 if (err)
4555 return err;
4556 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4557 if (err)
4558 goto err_port_stp_set;
4559 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
4560 true, false);
4561 if (err)
4562 goto err_port_vlan_set;
4563
4564 for (; vid <= VLAN_N_VID - 1; vid++) {
4565 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4566 vid, false);
4567 if (err)
4568 goto err_vid_learning_set;
4569 }
4570
4571 return 0;
4572
4573 err_vid_learning_set:
4574 for (vid--; vid >= 1; vid--)
4575 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
4576 err_port_vlan_set:
4577 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4578 err_port_stp_set:
4579 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4580 return err;
4581 }
4582
mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port * mlxsw_sp_port)4583 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4584 {
4585 u16 vid;
4586
4587 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4588 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4589 vid, true);
4590
4591 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
4592 false, false);
4593 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4594 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4595 }
4596
mlxsw_sp_bridge_has_multiple_vxlans(struct net_device * br_dev)4597 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
4598 {
4599 unsigned int num_vxlans = 0;
4600 struct net_device *dev;
4601 struct list_head *iter;
4602
4603 netdev_for_each_lower_dev(br_dev, dev, iter) {
4604 if (netif_is_vxlan(dev))
4605 num_vxlans++;
4606 }
4607
4608 return num_vxlans > 1;
4609 }
4610
mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device * br_dev)4611 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev)
4612 {
4613 DECLARE_BITMAP(vlans, VLAN_N_VID) = {0};
4614 struct net_device *dev;
4615 struct list_head *iter;
4616
4617 netdev_for_each_lower_dev(br_dev, dev, iter) {
4618 u16 pvid;
4619 int err;
4620
4621 if (!netif_is_vxlan(dev))
4622 continue;
4623
4624 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid);
4625 if (err || !pvid)
4626 continue;
4627
4628 if (test_and_set_bit(pvid, vlans))
4629 return false;
4630 }
4631
4632 return true;
4633 }
4634
mlxsw_sp_bridge_vxlan_is_valid(struct net_device * br_dev,struct netlink_ext_ack * extack)4635 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
4636 struct netlink_ext_ack *extack)
4637 {
4638 if (br_multicast_enabled(br_dev)) {
4639 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
4640 return false;
4641 }
4642
4643 if (!br_vlan_enabled(br_dev) &&
4644 mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
4645 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
4646 return false;
4647 }
4648
4649 if (br_vlan_enabled(br_dev) &&
4650 !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) {
4651 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged");
4652 return false;
4653 }
4654
4655 return true;
4656 }
4657
mlxsw_sp_netdevice_port_upper_event(struct net_device * lower_dev,struct net_device * dev,unsigned long event,void * ptr)4658 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4659 struct net_device *dev,
4660 unsigned long event, void *ptr)
4661 {
4662 struct netdev_notifier_changeupper_info *info;
4663 struct mlxsw_sp_port *mlxsw_sp_port;
4664 struct netlink_ext_ack *extack;
4665 struct net_device *upper_dev;
4666 struct mlxsw_sp *mlxsw_sp;
4667 int err = 0;
4668 u16 proto;
4669
4670 mlxsw_sp_port = netdev_priv(dev);
4671 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4672 info = ptr;
4673 extack = netdev_notifier_info_to_extack(&info->info);
4674
4675 switch (event) {
4676 case NETDEV_PRECHANGEUPPER:
4677 upper_dev = info->upper_dev;
4678 if (!is_vlan_dev(upper_dev) &&
4679 !netif_is_lag_master(upper_dev) &&
4680 !netif_is_bridge_master(upper_dev) &&
4681 !netif_is_ovs_master(upper_dev) &&
4682 !netif_is_macvlan(upper_dev) &&
4683 !netif_is_l3_master(upper_dev)) {
4684 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4685 return -EINVAL;
4686 }
4687 if (!info->linking)
4688 break;
4689 if (netif_is_bridge_master(upper_dev) &&
4690 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
4691 mlxsw_sp_bridge_has_vxlan(upper_dev) &&
4692 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4693 return -EOPNOTSUPP;
4694 if (netdev_has_any_upper_dev(upper_dev) &&
4695 (!netif_is_bridge_master(upper_dev) ||
4696 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4697 upper_dev))) {
4698 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
4699 return -EINVAL;
4700 }
4701 if (netif_is_lag_master(upper_dev) &&
4702 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4703 info->upper_info, extack))
4704 return -EINVAL;
4705 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4706 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
4707 return -EINVAL;
4708 }
4709 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4710 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4711 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
4712 return -EINVAL;
4713 }
4714 if (netif_is_macvlan(upper_dev) &&
4715 !mlxsw_sp_rif_exists(mlxsw_sp, lower_dev)) {
4716 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4717 return -EOPNOTSUPP;
4718 }
4719 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4720 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
4721 return -EINVAL;
4722 }
4723 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4724 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
4725 return -EINVAL;
4726 }
4727 if (netif_is_bridge_master(upper_dev)) {
4728 br_vlan_get_proto(upper_dev, &proto);
4729 if (br_vlan_enabled(upper_dev) &&
4730 proto != ETH_P_8021Q && proto != ETH_P_8021AD) {
4731 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a bridge with unknown VLAN protocol is not supported");
4732 return -EOPNOTSUPP;
4733 }
4734 if (vlan_uses_dev(lower_dev) &&
4735 br_vlan_enabled(upper_dev) &&
4736 proto == ETH_P_8021AD) {
4737 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port that already has a VLAN upper to an 802.1ad bridge is not supported");
4738 return -EOPNOTSUPP;
4739 }
4740 }
4741 if (netif_is_bridge_port(lower_dev) && is_vlan_dev(upper_dev)) {
4742 struct net_device *br_dev = netdev_master_upper_dev_get(lower_dev);
4743
4744 if (br_vlan_enabled(br_dev)) {
4745 br_vlan_get_proto(br_dev, &proto);
4746 if (proto == ETH_P_8021AD) {
4747 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a port enslaved to an 802.1ad bridge");
4748 return -EOPNOTSUPP;
4749 }
4750 }
4751 }
4752 if (is_vlan_dev(upper_dev) &&
4753 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) {
4754 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol");
4755 return -EOPNOTSUPP;
4756 }
4757 break;
4758 case NETDEV_CHANGEUPPER:
4759 upper_dev = info->upper_dev;
4760 if (netif_is_bridge_master(upper_dev)) {
4761 if (info->linking)
4762 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4763 lower_dev,
4764 upper_dev,
4765 extack);
4766 else
4767 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4768 lower_dev,
4769 upper_dev);
4770 } else if (netif_is_lag_master(upper_dev)) {
4771 if (info->linking) {
4772 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4773 upper_dev, extack);
4774 } else {
4775 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
4776 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4777 upper_dev);
4778 }
4779 } else if (netif_is_ovs_master(upper_dev)) {
4780 if (info->linking)
4781 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4782 else
4783 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
4784 } else if (netif_is_macvlan(upper_dev)) {
4785 if (!info->linking)
4786 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4787 } else if (is_vlan_dev(upper_dev)) {
4788 struct net_device *br_dev;
4789
4790 if (!netif_is_bridge_port(upper_dev))
4791 break;
4792 if (info->linking)
4793 break;
4794 br_dev = netdev_master_upper_dev_get(upper_dev);
4795 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
4796 br_dev);
4797 }
4798 break;
4799 }
4800
4801 return err;
4802 }
4803
mlxsw_sp_netdevice_port_lower_event(struct net_device * dev,unsigned long event,void * ptr)4804 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4805 unsigned long event, void *ptr)
4806 {
4807 struct netdev_notifier_changelowerstate_info *info;
4808 struct mlxsw_sp_port *mlxsw_sp_port;
4809 int err;
4810
4811 mlxsw_sp_port = netdev_priv(dev);
4812 info = ptr;
4813
4814 switch (event) {
4815 case NETDEV_CHANGELOWERSTATE:
4816 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4817 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4818 info->lower_state_info);
4819 if (err)
4820 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4821 }
4822 break;
4823 }
4824
4825 return 0;
4826 }
4827
mlxsw_sp_netdevice_port_event(struct net_device * lower_dev,struct net_device * port_dev,unsigned long event,void * ptr)4828 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4829 struct net_device *port_dev,
4830 unsigned long event, void *ptr)
4831 {
4832 switch (event) {
4833 case NETDEV_PRECHANGEUPPER:
4834 case NETDEV_CHANGEUPPER:
4835 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4836 event, ptr);
4837 case NETDEV_CHANGELOWERSTATE:
4838 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4839 ptr);
4840 }
4841
4842 return 0;
4843 }
4844
mlxsw_sp_netdevice_lag_event(struct net_device * lag_dev,unsigned long event,void * ptr)4845 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4846 unsigned long event, void *ptr)
4847 {
4848 struct net_device *dev;
4849 struct list_head *iter;
4850 int ret;
4851
4852 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4853 if (mlxsw_sp_port_dev_check(dev)) {
4854 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4855 ptr);
4856 if (ret)
4857 return ret;
4858 }
4859 }
4860
4861 return 0;
4862 }
4863
mlxsw_sp_netdevice_port_vlan_event(struct net_device * vlan_dev,struct net_device * dev,unsigned long event,void * ptr,u16 vid)4864 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4865 struct net_device *dev,
4866 unsigned long event, void *ptr,
4867 u16 vid)
4868 {
4869 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4870 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4871 struct netdev_notifier_changeupper_info *info = ptr;
4872 struct netlink_ext_ack *extack;
4873 struct net_device *upper_dev;
4874 int err = 0;
4875
4876 extack = netdev_notifier_info_to_extack(&info->info);
4877
4878 switch (event) {
4879 case NETDEV_PRECHANGEUPPER:
4880 upper_dev = info->upper_dev;
4881 if (!netif_is_bridge_master(upper_dev) &&
4882 !netif_is_macvlan(upper_dev) &&
4883 !netif_is_l3_master(upper_dev)) {
4884 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4885 return -EINVAL;
4886 }
4887 if (!info->linking)
4888 break;
4889 if (netif_is_bridge_master(upper_dev) &&
4890 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
4891 mlxsw_sp_bridge_has_vxlan(upper_dev) &&
4892 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4893 return -EOPNOTSUPP;
4894 if (netdev_has_any_upper_dev(upper_dev) &&
4895 (!netif_is_bridge_master(upper_dev) ||
4896 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4897 upper_dev))) {
4898 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
4899 return -EINVAL;
4900 }
4901 if (netif_is_macvlan(upper_dev) &&
4902 !mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) {
4903 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4904 return -EOPNOTSUPP;
4905 }
4906 break;
4907 case NETDEV_CHANGEUPPER:
4908 upper_dev = info->upper_dev;
4909 if (netif_is_bridge_master(upper_dev)) {
4910 if (info->linking)
4911 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4912 vlan_dev,
4913 upper_dev,
4914 extack);
4915 else
4916 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4917 vlan_dev,
4918 upper_dev);
4919 } else if (netif_is_macvlan(upper_dev)) {
4920 if (!info->linking)
4921 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4922 }
4923 break;
4924 }
4925
4926 return err;
4927 }
4928
mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device * vlan_dev,struct net_device * lag_dev,unsigned long event,void * ptr,u16 vid)4929 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4930 struct net_device *lag_dev,
4931 unsigned long event,
4932 void *ptr, u16 vid)
4933 {
4934 struct net_device *dev;
4935 struct list_head *iter;
4936 int ret;
4937
4938 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4939 if (mlxsw_sp_port_dev_check(dev)) {
4940 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4941 event, ptr,
4942 vid);
4943 if (ret)
4944 return ret;
4945 }
4946 }
4947
4948 return 0;
4949 }
4950
mlxsw_sp_netdevice_bridge_vlan_event(struct net_device * vlan_dev,struct net_device * br_dev,unsigned long event,void * ptr,u16 vid)4951 static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev,
4952 struct net_device *br_dev,
4953 unsigned long event, void *ptr,
4954 u16 vid)
4955 {
4956 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
4957 struct netdev_notifier_changeupper_info *info = ptr;
4958 struct netlink_ext_ack *extack;
4959 struct net_device *upper_dev;
4960
4961 if (!mlxsw_sp)
4962 return 0;
4963
4964 extack = netdev_notifier_info_to_extack(&info->info);
4965
4966 switch (event) {
4967 case NETDEV_PRECHANGEUPPER:
4968 upper_dev = info->upper_dev;
4969 if (!netif_is_macvlan(upper_dev) &&
4970 !netif_is_l3_master(upper_dev)) {
4971 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4972 return -EOPNOTSUPP;
4973 }
4974 if (!info->linking)
4975 break;
4976 if (netif_is_macvlan(upper_dev) &&
4977 !mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) {
4978 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4979 return -EOPNOTSUPP;
4980 }
4981 break;
4982 case NETDEV_CHANGEUPPER:
4983 upper_dev = info->upper_dev;
4984 if (info->linking)
4985 break;
4986 if (netif_is_macvlan(upper_dev))
4987 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4988 break;
4989 }
4990
4991 return 0;
4992 }
4993
mlxsw_sp_netdevice_vlan_event(struct net_device * vlan_dev,unsigned long event,void * ptr)4994 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4995 unsigned long event, void *ptr)
4996 {
4997 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4998 u16 vid = vlan_dev_vlan_id(vlan_dev);
4999
5000 if (mlxsw_sp_port_dev_check(real_dev))
5001 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
5002 event, ptr, vid);
5003 else if (netif_is_lag_master(real_dev))
5004 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
5005 real_dev, event,
5006 ptr, vid);
5007 else if (netif_is_bridge_master(real_dev))
5008 return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev,
5009 event, ptr, vid);
5010
5011 return 0;
5012 }
5013
mlxsw_sp_netdevice_bridge_event(struct net_device * br_dev,unsigned long event,void * ptr)5014 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
5015 unsigned long event, void *ptr)
5016 {
5017 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
5018 struct netdev_notifier_changeupper_info *info = ptr;
5019 struct netlink_ext_ack *extack;
5020 struct net_device *upper_dev;
5021 u16 proto;
5022
5023 if (!mlxsw_sp)
5024 return 0;
5025
5026 extack = netdev_notifier_info_to_extack(&info->info);
5027
5028 switch (event) {
5029 case NETDEV_PRECHANGEUPPER:
5030 upper_dev = info->upper_dev;
5031 if (!is_vlan_dev(upper_dev) &&
5032 !netif_is_macvlan(upper_dev) &&
5033 !netif_is_l3_master(upper_dev)) {
5034 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5035 return -EOPNOTSUPP;
5036 }
5037 if (!info->linking)
5038 break;
5039 if (br_vlan_enabled(br_dev)) {
5040 br_vlan_get_proto(br_dev, &proto);
5041 if (proto == ETH_P_8021AD) {
5042 NL_SET_ERR_MSG_MOD(extack, "Upper devices are not supported on top of an 802.1ad bridge");
5043 return -EOPNOTSUPP;
5044 }
5045 }
5046 if (is_vlan_dev(upper_dev) &&
5047 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) {
5048 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol");
5049 return -EOPNOTSUPP;
5050 }
5051 if (netif_is_macvlan(upper_dev) &&
5052 !mlxsw_sp_rif_exists(mlxsw_sp, br_dev)) {
5053 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
5054 return -EOPNOTSUPP;
5055 }
5056 break;
5057 case NETDEV_CHANGEUPPER:
5058 upper_dev = info->upper_dev;
5059 if (info->linking)
5060 break;
5061 if (is_vlan_dev(upper_dev))
5062 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
5063 if (netif_is_macvlan(upper_dev))
5064 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
5065 break;
5066 }
5067
5068 return 0;
5069 }
5070
mlxsw_sp_netdevice_macvlan_event(struct net_device * macvlan_dev,unsigned long event,void * ptr)5071 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
5072 unsigned long event, void *ptr)
5073 {
5074 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
5075 struct netdev_notifier_changeupper_info *info = ptr;
5076 struct netlink_ext_ack *extack;
5077 struct net_device *upper_dev;
5078
5079 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
5080 return 0;
5081
5082 extack = netdev_notifier_info_to_extack(&info->info);
5083 upper_dev = info->upper_dev;
5084
5085 if (!netif_is_l3_master(upper_dev)) {
5086 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5087 return -EOPNOTSUPP;
5088 }
5089
5090 return 0;
5091 }
5092
mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp * mlxsw_sp,struct net_device * dev,unsigned long event,void * ptr)5093 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
5094 struct net_device *dev,
5095 unsigned long event, void *ptr)
5096 {
5097 struct netdev_notifier_changeupper_info *cu_info;
5098 struct netdev_notifier_info *info = ptr;
5099 struct netlink_ext_ack *extack;
5100 struct net_device *upper_dev;
5101
5102 extack = netdev_notifier_info_to_extack(info);
5103
5104 switch (event) {
5105 case NETDEV_CHANGEUPPER:
5106 cu_info = container_of(info,
5107 struct netdev_notifier_changeupper_info,
5108 info);
5109 upper_dev = cu_info->upper_dev;
5110 if (!netif_is_bridge_master(upper_dev))
5111 return 0;
5112 if (!mlxsw_sp_lower_get(upper_dev))
5113 return 0;
5114 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
5115 return -EOPNOTSUPP;
5116 if (cu_info->linking) {
5117 if (!netif_running(dev))
5118 return 0;
5119 /* When the bridge is VLAN-aware, the VNI of the VxLAN
5120 * device needs to be mapped to a VLAN, but at this
5121 * point no VLANs are configured on the VxLAN device
5122 */
5123 if (br_vlan_enabled(upper_dev))
5124 return 0;
5125 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
5126 dev, 0, extack);
5127 } else {
5128 /* VLANs were already flushed, which triggered the
5129 * necessary cleanup
5130 */
5131 if (br_vlan_enabled(upper_dev))
5132 return 0;
5133 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
5134 }
5135 break;
5136 case NETDEV_PRE_UP:
5137 upper_dev = netdev_master_upper_dev_get(dev);
5138 if (!upper_dev)
5139 return 0;
5140 if (!netif_is_bridge_master(upper_dev))
5141 return 0;
5142 if (!mlxsw_sp_lower_get(upper_dev))
5143 return 0;
5144 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0,
5145 extack);
5146 case NETDEV_DOWN:
5147 upper_dev = netdev_master_upper_dev_get(dev);
5148 if (!upper_dev)
5149 return 0;
5150 if (!netif_is_bridge_master(upper_dev))
5151 return 0;
5152 if (!mlxsw_sp_lower_get(upper_dev))
5153 return 0;
5154 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
5155 break;
5156 }
5157
5158 return 0;
5159 }
5160
mlxsw_sp_netdevice_event(struct notifier_block * nb,unsigned long event,void * ptr)5161 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
5162 unsigned long event, void *ptr)
5163 {
5164 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
5165 struct mlxsw_sp_span_entry *span_entry;
5166 struct mlxsw_sp *mlxsw_sp;
5167 int err = 0;
5168
5169 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
5170 if (event == NETDEV_UNREGISTER) {
5171 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
5172 if (span_entry)
5173 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
5174 }
5175 mlxsw_sp_span_respin(mlxsw_sp);
5176
5177 if (netif_is_vxlan(dev))
5178 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
5179 else if (mlxsw_sp_port_dev_check(dev))
5180 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
5181 else if (netif_is_lag_master(dev))
5182 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
5183 else if (is_vlan_dev(dev))
5184 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
5185 else if (netif_is_bridge_master(dev))
5186 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
5187 else if (netif_is_macvlan(dev))
5188 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
5189
5190 return notifier_from_errno(err);
5191 }
5192
5193 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
5194 .notifier_call = mlxsw_sp_inetaddr_valid_event,
5195 };
5196
5197 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
5198 .notifier_call = mlxsw_sp_inet6addr_valid_event,
5199 };
5200
5201 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
5202 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
5203 {0, },
5204 };
5205
5206 static struct pci_driver mlxsw_sp1_pci_driver = {
5207 .name = mlxsw_sp1_driver_name,
5208 .id_table = mlxsw_sp1_pci_id_table,
5209 };
5210
5211 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
5212 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
5213 {0, },
5214 };
5215
5216 static struct pci_driver mlxsw_sp2_pci_driver = {
5217 .name = mlxsw_sp2_driver_name,
5218 .id_table = mlxsw_sp2_pci_id_table,
5219 };
5220
5221 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = {
5222 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0},
5223 {0, },
5224 };
5225
5226 static struct pci_driver mlxsw_sp3_pci_driver = {
5227 .name = mlxsw_sp3_driver_name,
5228 .id_table = mlxsw_sp3_pci_id_table,
5229 };
5230
5231 static const struct pci_device_id mlxsw_sp4_pci_id_table[] = {
5232 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM4), 0},
5233 {0, },
5234 };
5235
5236 static struct pci_driver mlxsw_sp4_pci_driver = {
5237 .name = mlxsw_sp4_driver_name,
5238 .id_table = mlxsw_sp4_pci_id_table,
5239 };
5240
mlxsw_sp_module_init(void)5241 static int __init mlxsw_sp_module_init(void)
5242 {
5243 int err;
5244
5245 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5246 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5247
5248 err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
5249 if (err)
5250 goto err_sp1_core_driver_register;
5251
5252 err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
5253 if (err)
5254 goto err_sp2_core_driver_register;
5255
5256 err = mlxsw_core_driver_register(&mlxsw_sp3_driver);
5257 if (err)
5258 goto err_sp3_core_driver_register;
5259
5260 err = mlxsw_core_driver_register(&mlxsw_sp4_driver);
5261 if (err)
5262 goto err_sp4_core_driver_register;
5263
5264 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
5265 if (err)
5266 goto err_sp1_pci_driver_register;
5267
5268 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
5269 if (err)
5270 goto err_sp2_pci_driver_register;
5271
5272 err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver);
5273 if (err)
5274 goto err_sp3_pci_driver_register;
5275
5276 err = mlxsw_pci_driver_register(&mlxsw_sp4_pci_driver);
5277 if (err)
5278 goto err_sp4_pci_driver_register;
5279
5280 return 0;
5281
5282 err_sp4_pci_driver_register:
5283 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
5284 err_sp3_pci_driver_register:
5285 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5286 err_sp2_pci_driver_register:
5287 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
5288 err_sp1_pci_driver_register:
5289 mlxsw_core_driver_unregister(&mlxsw_sp4_driver);
5290 err_sp4_core_driver_register:
5291 mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
5292 err_sp3_core_driver_register:
5293 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5294 err_sp2_core_driver_register:
5295 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5296 err_sp1_core_driver_register:
5297 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5298 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5299 return err;
5300 }
5301
mlxsw_sp_module_exit(void)5302 static void __exit mlxsw_sp_module_exit(void)
5303 {
5304 mlxsw_pci_driver_unregister(&mlxsw_sp4_pci_driver);
5305 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
5306 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5307 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
5308 mlxsw_core_driver_unregister(&mlxsw_sp4_driver);
5309 mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
5310 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5311 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5312 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5313 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5314 }
5315
5316 module_init(mlxsw_sp_module_init);
5317 module_exit(mlxsw_sp_module_exit);
5318
5319 MODULE_LICENSE("Dual BSD/GPL");
5320 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5321 MODULE_DESCRIPTION("Mellanox Spectrum driver");
5322 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
5323 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
5324 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table);
5325 MODULE_DEVICE_TABLE(pci, mlxsw_sp4_pci_id_table);
5326 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);
5327 MODULE_FIRMWARE(MLXSW_SP2_FW_FILENAME);
5328 MODULE_FIRMWARE(MLXSW_SP3_FW_FILENAME);
5329 MODULE_FIRMWARE(MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME);
5330