1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3
4 #ifndef _MLXSW_REG_H
5 #define _MLXSW_REG_H
6
7 #include <linux/kernel.h>
8 #include <linux/string.h>
9 #include <linux/bitops.h>
10 #include <linux/if_vlan.h>
11
12 #include "item.h"
13 #include "port.h"
14
15 struct mlxsw_reg_info {
16 u16 id;
17 u16 len; /* In u8 */
18 const char *name;
19 };
20
21 #define MLXSW_REG_DEFINE(_name, _id, _len) \
22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \
23 .id = _id, \
24 .len = _len, \
25 .name = #_name, \
26 }
27
28 #define MLXSW_REG(type) (&mlxsw_reg_##type)
29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
31
32 /* SGCR - Switch General Configuration Register
33 * --------------------------------------------
34 * This register is used for configuration of the switch capabilities.
35 */
36 #define MLXSW_REG_SGCR_ID 0x2000
37 #define MLXSW_REG_SGCR_LEN 0x10
38
39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
40
41 /* reg_sgcr_llb
42 * Link Local Broadcast (Default=0)
43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
44 * packets and ignore the IGMP snooping entries.
45 * Access: RW
46 */
47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
48
mlxsw_reg_sgcr_pack(char * payload,bool llb)49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
50 {
51 MLXSW_REG_ZERO(sgcr, payload);
52 mlxsw_reg_sgcr_llb_set(payload, !!llb);
53 }
54
55 /* SPAD - Switch Physical Address Register
56 * ---------------------------------------
57 * The SPAD register configures the switch physical MAC address.
58 */
59 #define MLXSW_REG_SPAD_ID 0x2002
60 #define MLXSW_REG_SPAD_LEN 0x10
61
62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
63
64 /* reg_spad_base_mac
65 * Base MAC address for the switch partitions.
66 * Per switch partition MAC address is equal to:
67 * base_mac + swid
68 * Access: RW
69 */
70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
71
72 /* SSPR - Switch System Port Record Register
73 * -----------------------------------------
74 * Configures the system port to local port mapping.
75 */
76 #define MLXSW_REG_SSPR_ID 0x2008
77 #define MLXSW_REG_SSPR_LEN 0x8
78
79 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
80
81 /* reg_sspr_m
82 * Master - if set, then the record describes the master system port.
83 * This is needed in case a local port is mapped into several system ports
84 * (for multipathing). That number will be reported as the source system
85 * port when packets are forwarded to the CPU. Only one master port is allowed
86 * per local port.
87 *
88 * Note: Must be set for Spectrum.
89 * Access: RW
90 */
91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
92
93 /* reg_sspr_local_port
94 * Local port number.
95 *
96 * Access: RW
97 */
98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12);
99
100 /* reg_sspr_sub_port
101 * Virtual port within the physical port.
102 * Should be set to 0 when virtual ports are not enabled on the port.
103 *
104 * Access: RW
105 */
106 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
107
108 /* reg_sspr_system_port
109 * Unique identifier within the stacking domain that represents all the ports
110 * that are available in the system (external ports).
111 *
112 * Currently, only single-ASIC configurations are supported, so we default to
113 * 1:1 mapping between system ports and local ports.
114 * Access: Index
115 */
116 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
117
mlxsw_reg_sspr_pack(char * payload,u16 local_port)118 static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port)
119 {
120 MLXSW_REG_ZERO(sspr, payload);
121 mlxsw_reg_sspr_m_set(payload, 1);
122 mlxsw_reg_sspr_local_port_set(payload, local_port);
123 mlxsw_reg_sspr_sub_port_set(payload, 0);
124 mlxsw_reg_sspr_system_port_set(payload, local_port);
125 }
126
127 /* SFDAT - Switch Filtering Database Aging Time
128 * --------------------------------------------
129 * Controls the Switch aging time. Aging time is able to be set per Switch
130 * Partition.
131 */
132 #define MLXSW_REG_SFDAT_ID 0x2009
133 #define MLXSW_REG_SFDAT_LEN 0x8
134
135 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
136
137 /* reg_sfdat_swid
138 * Switch partition ID.
139 * Access: Index
140 */
141 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
142
143 /* reg_sfdat_age_time
144 * Aging time in seconds
145 * Min - 10 seconds
146 * Max - 1,000,000 seconds
147 * Default is 300 seconds.
148 * Access: RW
149 */
150 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
151
mlxsw_reg_sfdat_pack(char * payload,u32 age_time)152 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
153 {
154 MLXSW_REG_ZERO(sfdat, payload);
155 mlxsw_reg_sfdat_swid_set(payload, 0);
156 mlxsw_reg_sfdat_age_time_set(payload, age_time);
157 }
158
159 /* SFD - Switch Filtering Database
160 * -------------------------------
161 * The following register defines the access to the filtering database.
162 * The register supports querying, adding, removing and modifying the database.
163 * The access is optimized for bulk updates in which case more than one
164 * FDB record is present in the same command.
165 */
166 #define MLXSW_REG_SFD_ID 0x200A
167 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
168 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
169 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
170 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
171 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
172
173 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
174
175 /* reg_sfd_swid
176 * Switch partition ID for queries. Reserved on Write.
177 * Access: Index
178 */
179 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
180
181 enum mlxsw_reg_sfd_op {
182 /* Dump entire FDB a (process according to record_locator) */
183 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
184 /* Query records by {MAC, VID/FID} value */
185 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
186 /* Query and clear activity. Query records by {MAC, VID/FID} value */
187 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
188 /* Test. Response indicates if each of the records could be
189 * added to the FDB.
190 */
191 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
192 /* Add/modify. Aged-out records cannot be added. This command removes
193 * the learning notification of the {MAC, VID/FID}. Response includes
194 * the entries that were added to the FDB.
195 */
196 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
197 /* Remove record by {MAC, VID/FID}. This command also removes
198 * the learning notification and aged-out notifications
199 * of the {MAC, VID/FID}. The response provides current (pre-removal)
200 * entries as non-aged-out.
201 */
202 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
203 /* Remove learned notification by {MAC, VID/FID}. The response provides
204 * the removed learning notification.
205 */
206 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
207 };
208
209 /* reg_sfd_op
210 * Operation.
211 * Access: OP
212 */
213 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
214
215 /* reg_sfd_record_locator
216 * Used for querying the FDB. Use record_locator=0 to initiate the
217 * query. When a record is returned, a new record_locator is
218 * returned to be used in the subsequent query.
219 * Reserved for database update.
220 * Access: Index
221 */
222 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
223
224 /* reg_sfd_num_rec
225 * Request: Number of records to read/add/modify/remove
226 * Response: Number of records read/added/replaced/removed
227 * See above description for more details.
228 * Ranges 0..64
229 * Access: RW
230 */
231 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
232
mlxsw_reg_sfd_pack(char * payload,enum mlxsw_reg_sfd_op op,u32 record_locator)233 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
234 u32 record_locator)
235 {
236 MLXSW_REG_ZERO(sfd, payload);
237 mlxsw_reg_sfd_op_set(payload, op);
238 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
239 }
240
241 /* reg_sfd_rec_swid
242 * Switch partition ID.
243 * Access: Index
244 */
245 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
246 MLXSW_REG_SFD_REC_LEN, 0x00, false);
247
248 enum mlxsw_reg_sfd_rec_type {
249 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
250 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
251 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
252 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
253 };
254
255 /* reg_sfd_rec_type
256 * FDB record type.
257 * Access: RW
258 */
259 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
260 MLXSW_REG_SFD_REC_LEN, 0x00, false);
261
262 enum mlxsw_reg_sfd_rec_policy {
263 /* Replacement disabled, aging disabled. */
264 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
265 /* (mlag remote): Replacement enabled, aging disabled,
266 * learning notification enabled on this port.
267 */
268 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
269 /* (ingress device): Replacement enabled, aging enabled. */
270 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
271 };
272
273 /* reg_sfd_rec_policy
274 * Policy.
275 * Access: RW
276 */
277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
278 MLXSW_REG_SFD_REC_LEN, 0x00, false);
279
280 /* reg_sfd_rec_a
281 * Activity. Set for new static entries. Set for static entries if a frame SMAC
282 * lookup hits on the entry.
283 * To clear the a bit, use "query and clear activity" op.
284 * Access: RO
285 */
286 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
287 MLXSW_REG_SFD_REC_LEN, 0x00, false);
288
289 /* reg_sfd_rec_mac
290 * MAC address.
291 * Access: Index
292 */
293 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
294 MLXSW_REG_SFD_REC_LEN, 0x02);
295
296 enum mlxsw_reg_sfd_rec_action {
297 /* forward */
298 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
299 /* forward and trap, trap_id is FDB_TRAP */
300 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
301 /* trap and do not forward, trap_id is FDB_TRAP */
302 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
303 /* forward to IP router */
304 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
305 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
306 };
307
308 /* reg_sfd_rec_action
309 * Action to apply on the packet.
310 * Note: Dynamic entries can only be configured with NOP action.
311 * Access: RW
312 */
313 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
314 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
315
316 /* reg_sfd_uc_sub_port
317 * VEPA channel on local port.
318 * Valid only if local port is a non-stacking port. Must be 0 if multichannel
319 * VEPA is not enabled.
320 * Access: RW
321 */
322 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
323 MLXSW_REG_SFD_REC_LEN, 0x08, false);
324
325 /* reg_sfd_uc_fid_vid
326 * Filtering ID or VLAN ID
327 * For SwitchX and SwitchX-2:
328 * - Dynamic entries (policy 2,3) use FID
329 * - Static entries (policy 0) use VID
330 * - When independent learning is configured, VID=FID
331 * For Spectrum: use FID for both Dynamic and Static entries.
332 * VID should not be used.
333 * Access: Index
334 */
335 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
336 MLXSW_REG_SFD_REC_LEN, 0x08, false);
337
338 /* reg_sfd_uc_system_port
339 * Unique port identifier for the final destination of the packet.
340 * Access: RW
341 */
342 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
343 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
344
mlxsw_reg_sfd_rec_pack(char * payload,int rec_index,enum mlxsw_reg_sfd_rec_type rec_type,const char * mac,enum mlxsw_reg_sfd_rec_action action)345 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
346 enum mlxsw_reg_sfd_rec_type rec_type,
347 const char *mac,
348 enum mlxsw_reg_sfd_rec_action action)
349 {
350 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
351
352 if (rec_index >= num_rec)
353 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
354 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
355 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
356 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
357 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
358 }
359
mlxsw_reg_sfd_uc_pack(char * payload,int rec_index,enum mlxsw_reg_sfd_rec_policy policy,const char * mac,u16 fid_vid,enum mlxsw_reg_sfd_rec_action action,u16 local_port)360 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
361 enum mlxsw_reg_sfd_rec_policy policy,
362 const char *mac, u16 fid_vid,
363 enum mlxsw_reg_sfd_rec_action action,
364 u16 local_port)
365 {
366 mlxsw_reg_sfd_rec_pack(payload, rec_index,
367 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
368 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
369 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
370 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
371 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
372 }
373
374 /* reg_sfd_uc_lag_sub_port
375 * LAG sub port.
376 * Must be 0 if multichannel VEPA is not enabled.
377 * Access: RW
378 */
379 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
380 MLXSW_REG_SFD_REC_LEN, 0x08, false);
381
382 /* reg_sfd_uc_lag_fid_vid
383 * Filtering ID or VLAN ID
384 * For SwitchX and SwitchX-2:
385 * - Dynamic entries (policy 2,3) use FID
386 * - Static entries (policy 0) use VID
387 * - When independent learning is configured, VID=FID
388 * For Spectrum: use FID for both Dynamic and Static entries.
389 * VID should not be used.
390 * Access: Index
391 */
392 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
393 MLXSW_REG_SFD_REC_LEN, 0x08, false);
394
395 /* reg_sfd_uc_lag_lag_vid
396 * Indicates VID in case of vFIDs. Reserved for FIDs.
397 * Access: RW
398 */
399 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
400 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
401
402 /* reg_sfd_uc_lag_lag_id
403 * LAG Identifier - pointer into the LAG descriptor table.
404 * Access: RW
405 */
406 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
407 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
408
409 static inline void
mlxsw_reg_sfd_uc_lag_pack(char * payload,int rec_index,enum mlxsw_reg_sfd_rec_policy policy,const char * mac,u16 fid_vid,enum mlxsw_reg_sfd_rec_action action,u16 lag_vid,u16 lag_id)410 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
411 enum mlxsw_reg_sfd_rec_policy policy,
412 const char *mac, u16 fid_vid,
413 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
414 u16 lag_id)
415 {
416 mlxsw_reg_sfd_rec_pack(payload, rec_index,
417 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
418 mac, action);
419 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
420 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
421 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
422 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
423 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
424 }
425
426 /* reg_sfd_mc_pgi
427 *
428 * Multicast port group index - index into the port group table.
429 * Value 0x1FFF indicates the pgi should point to the MID entry.
430 * For Spectrum this value must be set to 0x1FFF
431 * Access: RW
432 */
433 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
434 MLXSW_REG_SFD_REC_LEN, 0x08, false);
435
436 /* reg_sfd_mc_fid_vid
437 *
438 * Filtering ID or VLAN ID
439 * Access: Index
440 */
441 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
442 MLXSW_REG_SFD_REC_LEN, 0x08, false);
443
444 /* reg_sfd_mc_mid
445 *
446 * Multicast identifier - global identifier that represents the multicast
447 * group across all devices.
448 * Access: RW
449 */
450 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
451 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
452
453 static inline void
mlxsw_reg_sfd_mc_pack(char * payload,int rec_index,const char * mac,u16 fid_vid,enum mlxsw_reg_sfd_rec_action action,u16 mid)454 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
455 const char *mac, u16 fid_vid,
456 enum mlxsw_reg_sfd_rec_action action, u16 mid)
457 {
458 mlxsw_reg_sfd_rec_pack(payload, rec_index,
459 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
460 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
461 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
462 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
463 }
464
465 /* reg_sfd_uc_tunnel_uip_msb
466 * When protocol is IPv4, the most significant byte of the underlay IPv4
467 * destination IP.
468 * When protocol is IPv6, reserved.
469 * Access: RW
470 */
471 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
472 8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
473
474 /* reg_sfd_uc_tunnel_fid
475 * Filtering ID.
476 * Access: Index
477 */
478 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
479 MLXSW_REG_SFD_REC_LEN, 0x08, false);
480
481 enum mlxsw_reg_sfd_uc_tunnel_protocol {
482 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
483 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
484 };
485
486 /* reg_sfd_uc_tunnel_protocol
487 * IP protocol.
488 * Access: RW
489 */
490 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
491 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
492
493 /* reg_sfd_uc_tunnel_uip_lsb
494 * When protocol is IPv4, the least significant bytes of the underlay
495 * IPv4 destination IP.
496 * When protocol is IPv6, pointer to the underlay IPv6 destination IP
497 * which is configured by RIPS.
498 * Access: RW
499 */
500 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
501 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
502
503 static inline void
mlxsw_reg_sfd_uc_tunnel_pack(char * payload,int rec_index,enum mlxsw_reg_sfd_rec_policy policy,const char * mac,u16 fid,enum mlxsw_reg_sfd_rec_action action,enum mlxsw_reg_sfd_uc_tunnel_protocol proto)504 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
505 enum mlxsw_reg_sfd_rec_policy policy,
506 const char *mac, u16 fid,
507 enum mlxsw_reg_sfd_rec_action action,
508 enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
509 {
510 mlxsw_reg_sfd_rec_pack(payload, rec_index,
511 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
512 action);
513 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
514 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
515 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
516 }
517
518 static inline void
mlxsw_reg_sfd_uc_tunnel_pack4(char * payload,int rec_index,enum mlxsw_reg_sfd_rec_policy policy,const char * mac,u16 fid,enum mlxsw_reg_sfd_rec_action action,u32 uip)519 mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index,
520 enum mlxsw_reg_sfd_rec_policy policy,
521 const char *mac, u16 fid,
522 enum mlxsw_reg_sfd_rec_action action, u32 uip)
523 {
524 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
525 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
526 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid,
527 action,
528 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4);
529 }
530
531 static inline void
mlxsw_reg_sfd_uc_tunnel_pack6(char * payload,int rec_index,const char * mac,u16 fid,enum mlxsw_reg_sfd_rec_action action,u32 uip_ptr)532 mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac,
533 u16 fid, enum mlxsw_reg_sfd_rec_action action,
534 u32 uip_ptr)
535 {
536 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr);
537 /* Only static policy is supported for IPv6 unicast tunnel entry. */
538 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index,
539 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY,
540 mac, fid, action,
541 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6);
542 }
543
544 enum mlxsw_reg_tunnel_port {
545 MLXSW_REG_TUNNEL_PORT_NVE,
546 MLXSW_REG_TUNNEL_PORT_VPLS,
547 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0,
548 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1,
549 };
550
551 /* SFN - Switch FDB Notification Register
552 * -------------------------------------------
553 * The switch provides notifications on newly learned FDB entries and
554 * aged out entries. The notifications can be polled by software.
555 */
556 #define MLXSW_REG_SFN_ID 0x200B
557 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
558 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
559 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
560 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
561 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
562
563 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
564
565 /* reg_sfn_swid
566 * Switch partition ID.
567 * Access: Index
568 */
569 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
570
571 /* reg_sfn_end
572 * Forces the current session to end.
573 * Access: OP
574 */
575 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
576
577 /* reg_sfn_num_rec
578 * Request: Number of learned notifications and aged-out notification
579 * records requested.
580 * Response: Number of notification records returned (must be smaller
581 * than or equal to the value requested)
582 * Ranges 0..64
583 * Access: OP
584 */
585 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
586
mlxsw_reg_sfn_pack(char * payload)587 static inline void mlxsw_reg_sfn_pack(char *payload)
588 {
589 MLXSW_REG_ZERO(sfn, payload);
590 mlxsw_reg_sfn_swid_set(payload, 0);
591 mlxsw_reg_sfn_end_set(payload, 0);
592 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
593 }
594
595 /* reg_sfn_rec_swid
596 * Switch partition ID.
597 * Access: RO
598 */
599 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
600 MLXSW_REG_SFN_REC_LEN, 0x00, false);
601
602 enum mlxsw_reg_sfn_rec_type {
603 /* MAC addresses learned on a regular port. */
604 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
605 /* MAC addresses learned on a LAG port. */
606 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
607 /* Aged-out MAC address on a regular port. */
608 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
609 /* Aged-out MAC address on a LAG port. */
610 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
611 /* Learned unicast tunnel record. */
612 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
613 /* Aged-out unicast tunnel record. */
614 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
615 };
616
617 /* reg_sfn_rec_type
618 * Notification record type.
619 * Access: RO
620 */
621 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
622 MLXSW_REG_SFN_REC_LEN, 0x00, false);
623
624 /* reg_sfn_rec_mac
625 * MAC address.
626 * Access: RO
627 */
628 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
629 MLXSW_REG_SFN_REC_LEN, 0x02);
630
631 /* reg_sfn_mac_sub_port
632 * VEPA channel on the local port.
633 * 0 if multichannel VEPA is not enabled.
634 * Access: RO
635 */
636 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
637 MLXSW_REG_SFN_REC_LEN, 0x08, false);
638
639 /* reg_sfn_mac_fid
640 * Filtering identifier.
641 * Access: RO
642 */
643 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
644 MLXSW_REG_SFN_REC_LEN, 0x08, false);
645
646 /* reg_sfn_mac_system_port
647 * Unique port identifier for the final destination of the packet.
648 * Access: RO
649 */
650 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
651 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
652
mlxsw_reg_sfn_mac_unpack(char * payload,int rec_index,char * mac,u16 * p_vid,u16 * p_local_port)653 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
654 char *mac, u16 *p_vid,
655 u16 *p_local_port)
656 {
657 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
658 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
659 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
660 }
661
662 /* reg_sfn_mac_lag_lag_id
663 * LAG ID (pointer into the LAG descriptor table).
664 * Access: RO
665 */
666 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
667 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
668
mlxsw_reg_sfn_mac_lag_unpack(char * payload,int rec_index,char * mac,u16 * p_vid,u16 * p_lag_id)669 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
670 char *mac, u16 *p_vid,
671 u16 *p_lag_id)
672 {
673 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
674 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
675 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
676 }
677
678 /* reg_sfn_uc_tunnel_uip_msb
679 * When protocol is IPv4, the most significant byte of the underlay IPv4
680 * address of the remote VTEP.
681 * When protocol is IPv6, reserved.
682 * Access: RO
683 */
684 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
685 8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
686
687 enum mlxsw_reg_sfn_uc_tunnel_protocol {
688 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
689 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
690 };
691
692 /* reg_sfn_uc_tunnel_protocol
693 * IP protocol.
694 * Access: RO
695 */
696 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
697 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
698
699 /* reg_sfn_uc_tunnel_uip_lsb
700 * When protocol is IPv4, the least significant bytes of the underlay
701 * IPv4 address of the remote VTEP.
702 * When protocol is IPv6, ipv6_id to be queried from TNIPSD.
703 * Access: RO
704 */
705 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
706 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
707
708 /* reg_sfn_uc_tunnel_port
709 * Tunnel port.
710 * Reserved on Spectrum.
711 * Access: RO
712 */
713 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
714 MLXSW_REG_SFN_REC_LEN, 0x10, false);
715
716 static inline void
mlxsw_reg_sfn_uc_tunnel_unpack(char * payload,int rec_index,char * mac,u16 * p_fid,u32 * p_uip,enum mlxsw_reg_sfn_uc_tunnel_protocol * p_proto)717 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,
718 u16 *p_fid, u32 *p_uip,
719 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
720 {
721 u32 uip_msb, uip_lsb;
722
723 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
724 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
725 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);
726 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);
727 *p_uip = uip_msb << 24 | uip_lsb;
728 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);
729 }
730
731 /* SPMS - Switch Port MSTP/RSTP State Register
732 * -------------------------------------------
733 * Configures the spanning tree state of a physical port.
734 */
735 #define MLXSW_REG_SPMS_ID 0x200D
736 #define MLXSW_REG_SPMS_LEN 0x404
737
738 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
739
740 /* reg_spms_local_port
741 * Local port number.
742 * Access: Index
743 */
744 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12);
745
746 enum mlxsw_reg_spms_state {
747 MLXSW_REG_SPMS_STATE_NO_CHANGE,
748 MLXSW_REG_SPMS_STATE_DISCARDING,
749 MLXSW_REG_SPMS_STATE_LEARNING,
750 MLXSW_REG_SPMS_STATE_FORWARDING,
751 };
752
753 /* reg_spms_state
754 * Spanning tree state of each VLAN ID (VID) of the local port.
755 * 0 - Do not change spanning tree state (used only when writing).
756 * 1 - Discarding. No learning or forwarding to/from this port (default).
757 * 2 - Learning. Port is learning, but not forwarding.
758 * 3 - Forwarding. Port is learning and forwarding.
759 * Access: RW
760 */
761 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
762
mlxsw_reg_spms_pack(char * payload,u16 local_port)763 static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port)
764 {
765 MLXSW_REG_ZERO(spms, payload);
766 mlxsw_reg_spms_local_port_set(payload, local_port);
767 }
768
mlxsw_reg_spms_vid_pack(char * payload,u16 vid,enum mlxsw_reg_spms_state state)769 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
770 enum mlxsw_reg_spms_state state)
771 {
772 mlxsw_reg_spms_state_set(payload, vid, state);
773 }
774
775 /* SPVID - Switch Port VID
776 * -----------------------
777 * The switch port VID configures the default VID for a port.
778 */
779 #define MLXSW_REG_SPVID_ID 0x200E
780 #define MLXSW_REG_SPVID_LEN 0x08
781
782 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
783
784 /* reg_spvid_tport
785 * Port is tunnel port.
786 * Reserved when SwitchX/-2 or Spectrum-1.
787 * Access: Index
788 */
789 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1);
790
791 /* reg_spvid_local_port
792 * When tport = 0: Local port number. Not supported for CPU port.
793 * When tport = 1: Tunnel port.
794 * Access: Index
795 */
796 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12);
797
798 /* reg_spvid_sub_port
799 * Virtual port within the physical port.
800 * Should be set to 0 when virtual ports are not enabled on the port.
801 * Access: Index
802 */
803 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
804
805 /* reg_spvid_egr_et_set
806 * When VLAN is pushed at ingress (for untagged packets or for
807 * QinQ push mode) then the EtherType is decided at the egress port.
808 * Reserved when Spectrum-1.
809 * Access: RW
810 */
811 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1);
812
813 /* reg_spvid_et_vlan
814 * EtherType used for when VLAN is pushed at ingress (for untagged
815 * packets or for QinQ push mode).
816 * 0: ether_type0 - (default)
817 * 1: ether_type1
818 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2
819 * Ethertype IDs are configured by SVER.
820 * Reserved when egr_et_set = 1.
821 * Access: RW
822 */
823 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2);
824
825 /* reg_spvid_pvid
826 * Port default VID
827 * Access: RW
828 */
829 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
830
mlxsw_reg_spvid_pack(char * payload,u16 local_port,u16 pvid,u8 et_vlan)831 static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid,
832 u8 et_vlan)
833 {
834 MLXSW_REG_ZERO(spvid, payload);
835 mlxsw_reg_spvid_local_port_set(payload, local_port);
836 mlxsw_reg_spvid_pvid_set(payload, pvid);
837 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan);
838 }
839
840 /* SPVM - Switch Port VLAN Membership
841 * ----------------------------------
842 * The Switch Port VLAN Membership register configures the VLAN membership
843 * of a port in a VLAN denoted by VID. VLAN membership is managed per
844 * virtual port. The register can be used to add and remove VID(s) from a port.
845 */
846 #define MLXSW_REG_SPVM_ID 0x200F
847 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
848 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
849 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255
850 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
851 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
852
853 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
854
855 /* reg_spvm_pt
856 * Priority tagged. If this bit is set, packets forwarded to the port with
857 * untagged VLAN membership (u bit is set) will be tagged with priority tag
858 * (VID=0)
859 * Access: RW
860 */
861 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
862
863 /* reg_spvm_pte
864 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
865 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
866 * Access: WO
867 */
868 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
869
870 /* reg_spvm_local_port
871 * Local port number.
872 * Access: Index
873 */
874 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12);
875
876 /* reg_spvm_sub_port
877 * Virtual port within the physical port.
878 * Should be set to 0 when virtual ports are not enabled on the port.
879 * Access: Index
880 */
881 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
882
883 /* reg_spvm_num_rec
884 * Number of records to update. Each record contains: i, e, u, vid.
885 * Access: OP
886 */
887 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
888
889 /* reg_spvm_rec_i
890 * Ingress membership in VLAN ID.
891 * Access: Index
892 */
893 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
894 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
895 MLXSW_REG_SPVM_REC_LEN, 0, false);
896
897 /* reg_spvm_rec_e
898 * Egress membership in VLAN ID.
899 * Access: Index
900 */
901 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
902 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
903 MLXSW_REG_SPVM_REC_LEN, 0, false);
904
905 /* reg_spvm_rec_u
906 * Untagged - port is an untagged member - egress transmission uses untagged
907 * frames on VID<n>
908 * Access: Index
909 */
910 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
911 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
912 MLXSW_REG_SPVM_REC_LEN, 0, false);
913
914 /* reg_spvm_rec_vid
915 * Egress membership in VLAN ID.
916 * Access: Index
917 */
918 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
919 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
920 MLXSW_REG_SPVM_REC_LEN, 0, false);
921
mlxsw_reg_spvm_pack(char * payload,u16 local_port,u16 vid_begin,u16 vid_end,bool is_member,bool untagged)922 static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port,
923 u16 vid_begin, u16 vid_end,
924 bool is_member, bool untagged)
925 {
926 int size = vid_end - vid_begin + 1;
927 int i;
928
929 MLXSW_REG_ZERO(spvm, payload);
930 mlxsw_reg_spvm_local_port_set(payload, local_port);
931 mlxsw_reg_spvm_num_rec_set(payload, size);
932
933 for (i = 0; i < size; i++) {
934 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
935 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
936 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
937 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
938 }
939 }
940
941 /* SPAFT - Switch Port Acceptable Frame Types
942 * ------------------------------------------
943 * The Switch Port Acceptable Frame Types register configures the frame
944 * admittance of the port.
945 */
946 #define MLXSW_REG_SPAFT_ID 0x2010
947 #define MLXSW_REG_SPAFT_LEN 0x08
948
949 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
950
951 /* reg_spaft_local_port
952 * Local port number.
953 * Access: Index
954 *
955 * Note: CPU port is not supported (all tag types are allowed).
956 */
957 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12);
958
959 /* reg_spaft_sub_port
960 * Virtual port within the physical port.
961 * Should be set to 0 when virtual ports are not enabled on the port.
962 * Access: RW
963 */
964 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
965
966 /* reg_spaft_allow_untagged
967 * When set, untagged frames on the ingress are allowed (default).
968 * Access: RW
969 */
970 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
971
972 /* reg_spaft_allow_prio_tagged
973 * When set, priority tagged frames on the ingress are allowed (default).
974 * Access: RW
975 */
976 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
977
978 /* reg_spaft_allow_tagged
979 * When set, tagged frames on the ingress are allowed (default).
980 * Access: RW
981 */
982 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
983
mlxsw_reg_spaft_pack(char * payload,u16 local_port,bool allow_untagged)984 static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port,
985 bool allow_untagged)
986 {
987 MLXSW_REG_ZERO(spaft, payload);
988 mlxsw_reg_spaft_local_port_set(payload, local_port);
989 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
990 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);
991 mlxsw_reg_spaft_allow_tagged_set(payload, true);
992 }
993
994 /* SFGC - Switch Flooding Group Configuration
995 * ------------------------------------------
996 * The following register controls the association of flooding tables and MIDs
997 * to packet types used for flooding.
998 */
999 #define MLXSW_REG_SFGC_ID 0x2011
1000 #define MLXSW_REG_SFGC_LEN 0x10
1001
1002 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
1003
1004 enum mlxsw_reg_sfgc_type {
1005 MLXSW_REG_SFGC_TYPE_BROADCAST,
1006 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1007 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1008 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1009 MLXSW_REG_SFGC_TYPE_RESERVED,
1010 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1011 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
1012 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
1013 MLXSW_REG_SFGC_TYPE_MAX,
1014 };
1015
1016 /* reg_sfgc_type
1017 * The traffic type to reach the flooding table.
1018 * Access: Index
1019 */
1020 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1021
1022 enum mlxsw_reg_sfgc_bridge_type {
1023 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
1024 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
1025 };
1026
1027 /* reg_sfgc_bridge_type
1028 * Access: Index
1029 *
1030 * Note: SwitchX-2 only supports 802.1Q mode.
1031 */
1032 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1033
1034 enum mlxsw_flood_table_type {
1035 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
1036 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
1037 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
1038 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
1039 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
1040 };
1041
1042 /* reg_sfgc_table_type
1043 * See mlxsw_flood_table_type
1044 * Access: RW
1045 *
1046 * Note: FID offset and FID types are not supported in SwitchX-2.
1047 */
1048 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1049
1050 /* reg_sfgc_flood_table
1051 * Flooding table index to associate with the specific type on the specific
1052 * switch partition.
1053 * Access: RW
1054 */
1055 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1056
1057 /* reg_sfgc_mid
1058 * The multicast ID for the swid. Not supported for Spectrum
1059 * Access: RW
1060 */
1061 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1062
1063 /* reg_sfgc_counter_set_type
1064 * Counter Set Type for flow counters.
1065 * Access: RW
1066 */
1067 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1068
1069 /* reg_sfgc_counter_index
1070 * Counter Index for flow counters.
1071 * Access: RW
1072 */
1073 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1074
1075 static inline void
mlxsw_reg_sfgc_pack(char * payload,enum mlxsw_reg_sfgc_type type,enum mlxsw_reg_sfgc_bridge_type bridge_type,enum mlxsw_flood_table_type table_type,unsigned int flood_table)1076 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1077 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1078 enum mlxsw_flood_table_type table_type,
1079 unsigned int flood_table)
1080 {
1081 MLXSW_REG_ZERO(sfgc, payload);
1082 mlxsw_reg_sfgc_type_set(payload, type);
1083 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1084 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1085 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1086 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1087 }
1088
1089 /* SFDF - Switch Filtering DB Flush
1090 * --------------------------------
1091 * The switch filtering DB flush register is used to flush the FDB.
1092 * Note that FDB notifications are flushed as well.
1093 */
1094 #define MLXSW_REG_SFDF_ID 0x2013
1095 #define MLXSW_REG_SFDF_LEN 0x14
1096
1097 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1098
1099 /* reg_sfdf_swid
1100 * Switch partition ID.
1101 * Access: Index
1102 */
1103 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1104
1105 enum mlxsw_reg_sfdf_flush_type {
1106 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1107 MLXSW_REG_SFDF_FLUSH_PER_FID,
1108 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1109 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1110 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1111 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1112 MLXSW_REG_SFDF_FLUSH_PER_NVE,
1113 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1114 };
1115
1116 /* reg_sfdf_flush_type
1117 * Flush type.
1118 * 0 - All SWID dynamic entries are flushed.
1119 * 1 - All FID dynamic entries are flushed.
1120 * 2 - All dynamic entries pointing to port are flushed.
1121 * 3 - All FID dynamic entries pointing to port are flushed.
1122 * 4 - All dynamic entries pointing to LAG are flushed.
1123 * 5 - All FID dynamic entries pointing to LAG are flushed.
1124 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1125 * flushed.
1126 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1127 * flushed, per FID.
1128 * Access: RW
1129 */
1130 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1131
1132 /* reg_sfdf_flush_static
1133 * Static.
1134 * 0 - Flush only dynamic entries.
1135 * 1 - Flush both dynamic and static entries.
1136 * Access: RW
1137 */
1138 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1139
mlxsw_reg_sfdf_pack(char * payload,enum mlxsw_reg_sfdf_flush_type type)1140 static inline void mlxsw_reg_sfdf_pack(char *payload,
1141 enum mlxsw_reg_sfdf_flush_type type)
1142 {
1143 MLXSW_REG_ZERO(sfdf, payload);
1144 mlxsw_reg_sfdf_flush_type_set(payload, type);
1145 mlxsw_reg_sfdf_flush_static_set(payload, true);
1146 }
1147
1148 /* reg_sfdf_fid
1149 * FID to flush.
1150 * Access: RW
1151 */
1152 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1153
1154 /* reg_sfdf_system_port
1155 * Port to flush.
1156 * Access: RW
1157 */
1158 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1159
1160 /* reg_sfdf_port_fid_system_port
1161 * Port to flush, pointed to by FID.
1162 * Access: RW
1163 */
1164 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1165
1166 /* reg_sfdf_lag_id
1167 * LAG ID to flush.
1168 * Access: RW
1169 */
1170 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1171
1172 /* reg_sfdf_lag_fid_lag_id
1173 * LAG ID to flush, pointed to by FID.
1174 * Access: RW
1175 */
1176 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1177
1178 /* SLDR - Switch LAG Descriptor Register
1179 * -----------------------------------------
1180 * The switch LAG descriptor register is populated by LAG descriptors.
1181 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1182 * max_lag-1.
1183 */
1184 #define MLXSW_REG_SLDR_ID 0x2014
1185 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1186
1187 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1188
1189 enum mlxsw_reg_sldr_op {
1190 /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1191 MLXSW_REG_SLDR_OP_LAG_CREATE,
1192 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1193 /* Ports that appear in the list have the Distributor enabled */
1194 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1195 /* Removes ports from the disributor list */
1196 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1197 };
1198
1199 /* reg_sldr_op
1200 * Operation.
1201 * Access: RW
1202 */
1203 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1204
1205 /* reg_sldr_lag_id
1206 * LAG identifier. The lag_id is the index into the LAG descriptor table.
1207 * Access: Index
1208 */
1209 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1210
mlxsw_reg_sldr_lag_create_pack(char * payload,u8 lag_id)1211 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1212 {
1213 MLXSW_REG_ZERO(sldr, payload);
1214 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1215 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1216 }
1217
mlxsw_reg_sldr_lag_destroy_pack(char * payload,u8 lag_id)1218 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1219 {
1220 MLXSW_REG_ZERO(sldr, payload);
1221 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1222 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1223 }
1224
1225 /* reg_sldr_num_ports
1226 * The number of member ports of the LAG.
1227 * Reserved for Create / Destroy operations
1228 * For Add / Remove operations - indicates the number of ports in the list.
1229 * Access: RW
1230 */
1231 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1232
1233 /* reg_sldr_system_port
1234 * System port.
1235 * Access: RW
1236 */
1237 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1238
mlxsw_reg_sldr_lag_add_port_pack(char * payload,u8 lag_id,u16 local_port)1239 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1240 u16 local_port)
1241 {
1242 MLXSW_REG_ZERO(sldr, payload);
1243 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1244 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1245 mlxsw_reg_sldr_num_ports_set(payload, 1);
1246 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1247 }
1248
mlxsw_reg_sldr_lag_remove_port_pack(char * payload,u8 lag_id,u16 local_port)1249 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1250 u16 local_port)
1251 {
1252 MLXSW_REG_ZERO(sldr, payload);
1253 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1254 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1255 mlxsw_reg_sldr_num_ports_set(payload, 1);
1256 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1257 }
1258
1259 /* SLCR - Switch LAG Configuration 2 Register
1260 * -------------------------------------------
1261 * The Switch LAG Configuration register is used for configuring the
1262 * LAG properties of the switch.
1263 */
1264 #define MLXSW_REG_SLCR_ID 0x2015
1265 #define MLXSW_REG_SLCR_LEN 0x10
1266
1267 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1268
1269 enum mlxsw_reg_slcr_pp {
1270 /* Global Configuration (for all ports) */
1271 MLXSW_REG_SLCR_PP_GLOBAL,
1272 /* Per port configuration, based on local_port field */
1273 MLXSW_REG_SLCR_PP_PER_PORT,
1274 };
1275
1276 /* reg_slcr_pp
1277 * Per Port Configuration
1278 * Note: Reading at Global mode results in reading port 1 configuration.
1279 * Access: Index
1280 */
1281 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1282
1283 /* reg_slcr_local_port
1284 * Local port number
1285 * Supported from CPU port
1286 * Not supported from router port
1287 * Reserved when pp = Global Configuration
1288 * Access: Index
1289 */
1290 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12);
1291
1292 enum mlxsw_reg_slcr_type {
1293 MLXSW_REG_SLCR_TYPE_CRC, /* default */
1294 MLXSW_REG_SLCR_TYPE_XOR,
1295 MLXSW_REG_SLCR_TYPE_RANDOM,
1296 };
1297
1298 /* reg_slcr_type
1299 * Hash type
1300 * Access: RW
1301 */
1302 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1303
1304 /* Ingress port */
1305 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1306 /* SMAC - for IPv4 and IPv6 packets */
1307 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1308 /* SMAC - for non-IP packets */
1309 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1310 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1311 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1312 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1313 /* DMAC - for IPv4 and IPv6 packets */
1314 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1315 /* DMAC - for non-IP packets */
1316 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1317 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1318 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1319 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1320 /* Ethertype - for IPv4 and IPv6 packets */
1321 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1322 /* Ethertype - for non-IP packets */
1323 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1324 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1325 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1326 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1327 /* VLAN ID - for IPv4 and IPv6 packets */
1328 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1329 /* VLAN ID - for non-IP packets */
1330 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1331 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1332 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1333 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1334 /* Source IP address (can be IPv4 or IPv6) */
1335 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1336 /* Destination IP address (can be IPv4 or IPv6) */
1337 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1338 /* TCP/UDP source port */
1339 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1340 /* TCP/UDP destination port*/
1341 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1342 /* IPv4 Protocol/IPv6 Next Header */
1343 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1344 /* IPv6 Flow label */
1345 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1346 /* SID - FCoE source ID */
1347 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1348 /* DID - FCoE destination ID */
1349 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1350 /* OXID - FCoE originator exchange ID */
1351 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1352 /* Destination QP number - for RoCE packets */
1353 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1354
1355 /* reg_slcr_lag_hash
1356 * LAG hashing configuration. This is a bitmask, in which each set
1357 * bit includes the corresponding item in the LAG hash calculation.
1358 * The default lag_hash contains SMAC, DMAC, VLANID and
1359 * Ethertype (for all packet types).
1360 * Access: RW
1361 */
1362 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1363
1364 /* reg_slcr_seed
1365 * LAG seed value. The seed is the same for all ports.
1366 * Access: RW
1367 */
1368 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1369
mlxsw_reg_slcr_pack(char * payload,u16 lag_hash,u32 seed)1370 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1371 {
1372 MLXSW_REG_ZERO(slcr, payload);
1373 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1374 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1375 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1376 mlxsw_reg_slcr_seed_set(payload, seed);
1377 }
1378
1379 /* SLCOR - Switch LAG Collector Register
1380 * -------------------------------------
1381 * The Switch LAG Collector register controls the Local Port membership
1382 * in a LAG and enablement of the collector.
1383 */
1384 #define MLXSW_REG_SLCOR_ID 0x2016
1385 #define MLXSW_REG_SLCOR_LEN 0x10
1386
1387 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1388
1389 enum mlxsw_reg_slcor_col {
1390 /* Port is added with collector disabled */
1391 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1392 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1393 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1394 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1395 };
1396
1397 /* reg_slcor_col
1398 * Collector configuration
1399 * Access: RW
1400 */
1401 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1402
1403 /* reg_slcor_local_port
1404 * Local port number
1405 * Not supported for CPU port
1406 * Access: Index
1407 */
1408 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12);
1409
1410 /* reg_slcor_lag_id
1411 * LAG Identifier. Index into the LAG descriptor table.
1412 * Access: Index
1413 */
1414 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1415
1416 /* reg_slcor_port_index
1417 * Port index in the LAG list. Only valid on Add Port to LAG col.
1418 * Valid range is from 0 to cap_max_lag_members-1
1419 * Access: RW
1420 */
1421 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1422
mlxsw_reg_slcor_pack(char * payload,u16 local_port,u16 lag_id,enum mlxsw_reg_slcor_col col)1423 static inline void mlxsw_reg_slcor_pack(char *payload,
1424 u16 local_port, u16 lag_id,
1425 enum mlxsw_reg_slcor_col col)
1426 {
1427 MLXSW_REG_ZERO(slcor, payload);
1428 mlxsw_reg_slcor_col_set(payload, col);
1429 mlxsw_reg_slcor_local_port_set(payload, local_port);
1430 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1431 }
1432
mlxsw_reg_slcor_port_add_pack(char * payload,u16 local_port,u16 lag_id,u8 port_index)1433 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1434 u16 local_port, u16 lag_id,
1435 u8 port_index)
1436 {
1437 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1438 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1439 mlxsw_reg_slcor_port_index_set(payload, port_index);
1440 }
1441
mlxsw_reg_slcor_port_remove_pack(char * payload,u16 local_port,u16 lag_id)1442 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1443 u16 local_port, u16 lag_id)
1444 {
1445 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1446 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1447 }
1448
mlxsw_reg_slcor_col_enable_pack(char * payload,u16 local_port,u16 lag_id)1449 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1450 u16 local_port, u16 lag_id)
1451 {
1452 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1453 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1454 }
1455
mlxsw_reg_slcor_col_disable_pack(char * payload,u16 local_port,u16 lag_id)1456 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1457 u16 local_port, u16 lag_id)
1458 {
1459 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1460 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1461 }
1462
1463 /* SPMLR - Switch Port MAC Learning Register
1464 * -----------------------------------------
1465 * Controls the Switch MAC learning policy per port.
1466 */
1467 #define MLXSW_REG_SPMLR_ID 0x2018
1468 #define MLXSW_REG_SPMLR_LEN 0x8
1469
1470 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1471
1472 /* reg_spmlr_local_port
1473 * Local port number.
1474 * Access: Index
1475 */
1476 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12);
1477
1478 /* reg_spmlr_sub_port
1479 * Virtual port within the physical port.
1480 * Should be set to 0 when virtual ports are not enabled on the port.
1481 * Access: Index
1482 */
1483 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1484
1485 enum mlxsw_reg_spmlr_learn_mode {
1486 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1487 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1488 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1489 };
1490
1491 /* reg_spmlr_learn_mode
1492 * Learning mode on the port.
1493 * 0 - Learning disabled.
1494 * 2 - Learning enabled.
1495 * 3 - Security mode.
1496 *
1497 * In security mode the switch does not learn MACs on the port, but uses the
1498 * SMAC to see if it exists on another ingress port. If so, the packet is
1499 * classified as a bad packet and is discarded unless the software registers
1500 * to receive port security error packets usign HPKT.
1501 */
1502 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1503
mlxsw_reg_spmlr_pack(char * payload,u16 local_port,enum mlxsw_reg_spmlr_learn_mode mode)1504 static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port,
1505 enum mlxsw_reg_spmlr_learn_mode mode)
1506 {
1507 MLXSW_REG_ZERO(spmlr, payload);
1508 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1509 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1510 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1511 }
1512
1513 /* SVFA - Switch VID to FID Allocation Register
1514 * --------------------------------------------
1515 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1516 * virtualized ports.
1517 */
1518 #define MLXSW_REG_SVFA_ID 0x201C
1519 #define MLXSW_REG_SVFA_LEN 0x10
1520
1521 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1522
1523 /* reg_svfa_swid
1524 * Switch partition ID.
1525 * Access: Index
1526 */
1527 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1528
1529 /* reg_svfa_local_port
1530 * Local port number.
1531 * Access: Index
1532 *
1533 * Note: Reserved for 802.1Q FIDs.
1534 */
1535 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12);
1536
1537 enum mlxsw_reg_svfa_mt {
1538 MLXSW_REG_SVFA_MT_VID_TO_FID,
1539 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1540 };
1541
1542 /* reg_svfa_mapping_table
1543 * Mapping table:
1544 * 0 - VID to FID
1545 * 1 - {Port, VID} to FID
1546 * Access: Index
1547 *
1548 * Note: Reserved for SwitchX-2.
1549 */
1550 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1551
1552 /* reg_svfa_v
1553 * Valid.
1554 * Valid if set.
1555 * Access: RW
1556 *
1557 * Note: Reserved for SwitchX-2.
1558 */
1559 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1560
1561 /* reg_svfa_fid
1562 * Filtering ID.
1563 * Access: RW
1564 */
1565 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1566
1567 /* reg_svfa_vid
1568 * VLAN ID.
1569 * Access: Index
1570 */
1571 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1572
1573 /* reg_svfa_counter_set_type
1574 * Counter set type for flow counters.
1575 * Access: RW
1576 *
1577 * Note: Reserved for SwitchX-2.
1578 */
1579 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1580
1581 /* reg_svfa_counter_index
1582 * Counter index for flow counters.
1583 * Access: RW
1584 *
1585 * Note: Reserved for SwitchX-2.
1586 */
1587 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1588
mlxsw_reg_svfa_pack(char * payload,u16 local_port,enum mlxsw_reg_svfa_mt mt,bool valid,u16 fid,u16 vid)1589 static inline void mlxsw_reg_svfa_pack(char *payload, u16 local_port,
1590 enum mlxsw_reg_svfa_mt mt, bool valid,
1591 u16 fid, u16 vid)
1592 {
1593 MLXSW_REG_ZERO(svfa, payload);
1594 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1595 mlxsw_reg_svfa_swid_set(payload, 0);
1596 mlxsw_reg_svfa_local_port_set(payload, local_port);
1597 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1598 mlxsw_reg_svfa_v_set(payload, valid);
1599 mlxsw_reg_svfa_fid_set(payload, fid);
1600 mlxsw_reg_svfa_vid_set(payload, vid);
1601 }
1602
1603 /* SPVTR - Switch Port VLAN Stacking Register
1604 * ------------------------------------------
1605 * The Switch Port VLAN Stacking register configures the VLAN mode of the port
1606 * to enable VLAN stacking.
1607 */
1608 #define MLXSW_REG_SPVTR_ID 0x201D
1609 #define MLXSW_REG_SPVTR_LEN 0x10
1610
1611 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN);
1612
1613 /* reg_spvtr_tport
1614 * Port is tunnel port.
1615 * Access: Index
1616 *
1617 * Note: Reserved when SwitchX/-2 or Spectrum-1.
1618 */
1619 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1);
1620
1621 /* reg_spvtr_local_port
1622 * When tport = 0: local port number (Not supported from/to CPU).
1623 * When tport = 1: tunnel port.
1624 * Access: Index
1625 */
1626 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12);
1627
1628 /* reg_spvtr_ippe
1629 * Ingress Port Prio Mode Update Enable.
1630 * When set, the Port Prio Mode is updated with the provided ipprio_mode field.
1631 * Reserved on Get operations.
1632 * Access: OP
1633 */
1634 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1);
1635
1636 /* reg_spvtr_ipve
1637 * Ingress Port VID Mode Update Enable.
1638 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode
1639 * field.
1640 * Reserved on Get operations.
1641 * Access: OP
1642 */
1643 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1);
1644
1645 /* reg_spvtr_epve
1646 * Egress Port VID Mode Update Enable.
1647 * When set, the Egress Port VID Mode is updated with the provided epvid_mode
1648 * field.
1649 * Access: OP
1650 */
1651 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1);
1652
1653 /* reg_spvtr_ipprio_mode
1654 * Ingress Port Priority Mode.
1655 * This controls the PCP and DEI of the new outer VLAN
1656 * Note: for SwitchX/-2 the DEI is not affected.
1657 * 0: use port default PCP and DEI (configured by QPDPC).
1658 * 1: use C-VLAN PCP and DEI.
1659 * Has no effect when ipvid_mode = 0.
1660 * Reserved when tport = 1.
1661 * Access: RW
1662 */
1663 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4);
1664
1665 enum mlxsw_reg_spvtr_ipvid_mode {
1666 /* IEEE Compliant PVID (default) */
1667 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID,
1668 /* Push VLAN (for VLAN stacking, except prio tagged packets) */
1669 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET,
1670 /* Always push VLAN (also for prio tagged packets) */
1671 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN,
1672 };
1673
1674 /* reg_spvtr_ipvid_mode
1675 * Ingress Port VLAN-ID Mode.
1676 * For Spectrum family, this affects the values of SPVM.i
1677 * Access: RW
1678 */
1679 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4);
1680
1681 enum mlxsw_reg_spvtr_epvid_mode {
1682 /* IEEE Compliant VLAN membership */
1683 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP,
1684 /* Pop VLAN (for VLAN stacking) */
1685 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN,
1686 };
1687
1688 /* reg_spvtr_epvid_mode
1689 * Egress Port VLAN-ID Mode.
1690 * For Spectrum family, this affects the values of SPVM.e,u,pt.
1691 * Access: WO
1692 */
1693 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4);
1694
mlxsw_reg_spvtr_pack(char * payload,bool tport,u16 local_port,enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode)1695 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport,
1696 u16 local_port,
1697 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode)
1698 {
1699 MLXSW_REG_ZERO(spvtr, payload);
1700 mlxsw_reg_spvtr_tport_set(payload, tport);
1701 mlxsw_reg_spvtr_local_port_set(payload, local_port);
1702 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode);
1703 mlxsw_reg_spvtr_ipve_set(payload, true);
1704 }
1705
1706 /* SVPE - Switch Virtual-Port Enabling Register
1707 * --------------------------------------------
1708 * Enables port virtualization.
1709 */
1710 #define MLXSW_REG_SVPE_ID 0x201E
1711 #define MLXSW_REG_SVPE_LEN 0x4
1712
1713 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1714
1715 /* reg_svpe_local_port
1716 * Local port number
1717 * Access: Index
1718 *
1719 * Note: CPU port is not supported (uses VLAN mode only).
1720 */
1721 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12);
1722
1723 /* reg_svpe_vp_en
1724 * Virtual port enable.
1725 * 0 - Disable, VLAN mode (VID to FID).
1726 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1727 * Access: RW
1728 */
1729 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1730
mlxsw_reg_svpe_pack(char * payload,u16 local_port,bool enable)1731 static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port,
1732 bool enable)
1733 {
1734 MLXSW_REG_ZERO(svpe, payload);
1735 mlxsw_reg_svpe_local_port_set(payload, local_port);
1736 mlxsw_reg_svpe_vp_en_set(payload, enable);
1737 }
1738
1739 /* SFMR - Switch FID Management Register
1740 * -------------------------------------
1741 * Creates and configures FIDs.
1742 */
1743 #define MLXSW_REG_SFMR_ID 0x201F
1744 #define MLXSW_REG_SFMR_LEN 0x18
1745
1746 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1747
1748 enum mlxsw_reg_sfmr_op {
1749 MLXSW_REG_SFMR_OP_CREATE_FID,
1750 MLXSW_REG_SFMR_OP_DESTROY_FID,
1751 };
1752
1753 /* reg_sfmr_op
1754 * Operation.
1755 * 0 - Create or edit FID.
1756 * 1 - Destroy FID.
1757 * Access: WO
1758 */
1759 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1760
1761 /* reg_sfmr_fid
1762 * Filtering ID.
1763 * Access: Index
1764 */
1765 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1766
1767 /* reg_sfmr_fid_offset
1768 * FID offset.
1769 * Used to point into the flooding table selected by SFGC register if
1770 * the table is of type FID-Offset. Otherwise, this field is reserved.
1771 * Access: RW
1772 */
1773 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1774
1775 /* reg_sfmr_vtfp
1776 * Valid Tunnel Flood Pointer.
1777 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1778 * Access: RW
1779 *
1780 * Note: Reserved for 802.1Q FIDs.
1781 */
1782 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1783
1784 /* reg_sfmr_nve_tunnel_flood_ptr
1785 * Underlay Flooding and BC Pointer.
1786 * Used as a pointer to the first entry of the group based link lists of
1787 * flooding or BC entries (for NVE tunnels).
1788 * Access: RW
1789 */
1790 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1791
1792 /* reg_sfmr_vv
1793 * VNI Valid.
1794 * If not set, then vni is reserved.
1795 * Access: RW
1796 *
1797 * Note: Reserved for 802.1Q FIDs.
1798 */
1799 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1800
1801 /* reg_sfmr_vni
1802 * Virtual Network Identifier.
1803 * Access: RW
1804 *
1805 * Note: A given VNI can only be assigned to one FID.
1806 */
1807 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1808
mlxsw_reg_sfmr_pack(char * payload,enum mlxsw_reg_sfmr_op op,u16 fid,u16 fid_offset)1809 static inline void mlxsw_reg_sfmr_pack(char *payload,
1810 enum mlxsw_reg_sfmr_op op, u16 fid,
1811 u16 fid_offset)
1812 {
1813 MLXSW_REG_ZERO(sfmr, payload);
1814 mlxsw_reg_sfmr_op_set(payload, op);
1815 mlxsw_reg_sfmr_fid_set(payload, fid);
1816 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1817 mlxsw_reg_sfmr_vtfp_set(payload, false);
1818 mlxsw_reg_sfmr_vv_set(payload, false);
1819 }
1820
1821 /* SPVMLR - Switch Port VLAN MAC Learning Register
1822 * -----------------------------------------------
1823 * Controls the switch MAC learning policy per {Port, VID}.
1824 */
1825 #define MLXSW_REG_SPVMLR_ID 0x2020
1826 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1827 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1828 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1829 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1830 MLXSW_REG_SPVMLR_REC_LEN * \
1831 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1832
1833 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1834
1835 /* reg_spvmlr_local_port
1836 * Local ingress port.
1837 * Access: Index
1838 *
1839 * Note: CPU port is not supported.
1840 */
1841 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12);
1842
1843 /* reg_spvmlr_num_rec
1844 * Number of records to update.
1845 * Access: OP
1846 */
1847 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1848
1849 /* reg_spvmlr_rec_learn_enable
1850 * 0 - Disable learning for {Port, VID}.
1851 * 1 - Enable learning for {Port, VID}.
1852 * Access: RW
1853 */
1854 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1855 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1856
1857 /* reg_spvmlr_rec_vid
1858 * VLAN ID to be added/removed from port or for querying.
1859 * Access: Index
1860 */
1861 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1862 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1863
mlxsw_reg_spvmlr_pack(char * payload,u16 local_port,u16 vid_begin,u16 vid_end,bool learn_enable)1864 static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port,
1865 u16 vid_begin, u16 vid_end,
1866 bool learn_enable)
1867 {
1868 int num_rec = vid_end - vid_begin + 1;
1869 int i;
1870
1871 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1872
1873 MLXSW_REG_ZERO(spvmlr, payload);
1874 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1875 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1876
1877 for (i = 0; i < num_rec; i++) {
1878 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1879 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1880 }
1881 }
1882
1883 /* SPVC - Switch Port VLAN Classification Register
1884 * -----------------------------------------------
1885 * Configures the port to identify packets as untagged / single tagged /
1886 * double packets based on the packet EtherTypes.
1887 * Ethertype IDs are configured by SVER.
1888 */
1889 #define MLXSW_REG_SPVC_ID 0x2026
1890 #define MLXSW_REG_SPVC_LEN 0x0C
1891
1892 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN);
1893
1894 /* reg_spvc_local_port
1895 * Local port.
1896 * Access: Index
1897 *
1898 * Note: applies both to Rx port and Tx port, so if a packet traverses
1899 * through Rx port i and a Tx port j then port i and port j must have the
1900 * same configuration.
1901 */
1902 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12);
1903
1904 /* reg_spvc_inner_et2
1905 * Vlan Tag1 EtherType2 enable.
1906 * Packet is initially classified as double VLAN Tag if in addition to
1907 * being classified with a tag0 VLAN Tag its tag1 EtherType value is
1908 * equal to ether_type2.
1909 * 0: disable (default)
1910 * 1: enable
1911 * Access: RW
1912 */
1913 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1);
1914
1915 /* reg_spvc_et2
1916 * Vlan Tag0 EtherType2 enable.
1917 * Packet is initially classified as VLAN Tag if its tag0 EtherType is
1918 * equal to ether_type2.
1919 * 0: disable (default)
1920 * 1: enable
1921 * Access: RW
1922 */
1923 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1);
1924
1925 /* reg_spvc_inner_et1
1926 * Vlan Tag1 EtherType1 enable.
1927 * Packet is initially classified as double VLAN Tag if in addition to
1928 * being classified with a tag0 VLAN Tag its tag1 EtherType value is
1929 * equal to ether_type1.
1930 * 0: disable
1931 * 1: enable (default)
1932 * Access: RW
1933 */
1934 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1);
1935
1936 /* reg_spvc_et1
1937 * Vlan Tag0 EtherType1 enable.
1938 * Packet is initially classified as VLAN Tag if its tag0 EtherType is
1939 * equal to ether_type1.
1940 * 0: disable
1941 * 1: enable (default)
1942 * Access: RW
1943 */
1944 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1);
1945
1946 /* reg_inner_et0
1947 * Vlan Tag1 EtherType0 enable.
1948 * Packet is initially classified as double VLAN Tag if in addition to
1949 * being classified with a tag0 VLAN Tag its tag1 EtherType value is
1950 * equal to ether_type0.
1951 * 0: disable
1952 * 1: enable (default)
1953 * Access: RW
1954 */
1955 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1);
1956
1957 /* reg_et0
1958 * Vlan Tag0 EtherType0 enable.
1959 * Packet is initially classified as VLAN Tag if its tag0 EtherType is
1960 * equal to ether_type0.
1961 * 0: disable
1962 * 1: enable (default)
1963 * Access: RW
1964 */
1965 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1);
1966
mlxsw_reg_spvc_pack(char * payload,u16 local_port,bool et1,bool et0)1967 static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1,
1968 bool et0)
1969 {
1970 MLXSW_REG_ZERO(spvc, payload);
1971 mlxsw_reg_spvc_local_port_set(payload, local_port);
1972 /* Enable inner_et1 and inner_et0 to enable identification of double
1973 * tagged packets.
1974 */
1975 mlxsw_reg_spvc_inner_et1_set(payload, 1);
1976 mlxsw_reg_spvc_inner_et0_set(payload, 1);
1977 mlxsw_reg_spvc_et1_set(payload, et1);
1978 mlxsw_reg_spvc_et0_set(payload, et0);
1979 }
1980
1981 /* SPEVET - Switch Port Egress VLAN EtherType
1982 * ------------------------------------------
1983 * The switch port egress VLAN EtherType configures which EtherType to push at
1984 * egress for packets incoming through a local port for which 'SPVID.egr_et_set'
1985 * is set.
1986 */
1987 #define MLXSW_REG_SPEVET_ID 0x202A
1988 #define MLXSW_REG_SPEVET_LEN 0x08
1989
1990 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN);
1991
1992 /* reg_spevet_local_port
1993 * Egress Local port number.
1994 * Not supported to CPU port.
1995 * Access: Index
1996 */
1997 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12);
1998
1999 /* reg_spevet_et_vlan
2000 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet:
2001 * 0: ether_type0 - (default)
2002 * 1: ether_type1
2003 * 2: ether_type2
2004 * Access: RW
2005 */
2006 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2);
2007
mlxsw_reg_spevet_pack(char * payload,u16 local_port,u8 et_vlan)2008 static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port,
2009 u8 et_vlan)
2010 {
2011 MLXSW_REG_ZERO(spevet, payload);
2012 mlxsw_reg_spevet_local_port_set(payload, local_port);
2013 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan);
2014 }
2015
2016 /* SFTR-V2 - Switch Flooding Table Version 2 Register
2017 * --------------------------------------------------
2018 * The switch flooding table is used for flooding packet replication. The table
2019 * defines a bit mask of ports for packet replication.
2020 */
2021 #define MLXSW_REG_SFTR2_ID 0x202F
2022 #define MLXSW_REG_SFTR2_LEN 0x120
2023
2024 MLXSW_REG_DEFINE(sftr2, MLXSW_REG_SFTR2_ID, MLXSW_REG_SFTR2_LEN);
2025
2026 /* reg_sftr2_swid
2027 * Switch partition ID with which to associate the port.
2028 * Access: Index
2029 */
2030 MLXSW_ITEM32(reg, sftr2, swid, 0x00, 24, 8);
2031
2032 /* reg_sftr2_flood_table
2033 * Flooding table index to associate with the specific type on the specific
2034 * switch partition.
2035 * Access: Index
2036 */
2037 MLXSW_ITEM32(reg, sftr2, flood_table, 0x00, 16, 6);
2038
2039 /* reg_sftr2_index
2040 * Index. Used as an index into the Flooding Table in case the table is
2041 * configured to use VID / FID or FID Offset.
2042 * Access: Index
2043 */
2044 MLXSW_ITEM32(reg, sftr2, index, 0x00, 0, 16);
2045
2046 /* reg_sftr2_table_type
2047 * See mlxsw_flood_table_type
2048 * Access: RW
2049 */
2050 MLXSW_ITEM32(reg, sftr2, table_type, 0x04, 16, 3);
2051
2052 /* reg_sftr2_range
2053 * Range of entries to update
2054 * Access: Index
2055 */
2056 MLXSW_ITEM32(reg, sftr2, range, 0x04, 0, 16);
2057
2058 /* reg_sftr2_port
2059 * Local port membership (1 bit per port).
2060 * Access: RW
2061 */
2062 MLXSW_ITEM_BIT_ARRAY(reg, sftr2, port, 0x20, 0x80, 1);
2063
2064 /* reg_sftr2_port_mask
2065 * Local port mask (1 bit per port).
2066 * Access: WO
2067 */
2068 MLXSW_ITEM_BIT_ARRAY(reg, sftr2, port_mask, 0xA0, 0x80, 1);
2069
mlxsw_reg_sftr2_pack(char * payload,unsigned int flood_table,unsigned int index,enum mlxsw_flood_table_type table_type,unsigned int range,u16 port,bool set)2070 static inline void mlxsw_reg_sftr2_pack(char *payload,
2071 unsigned int flood_table,
2072 unsigned int index,
2073 enum mlxsw_flood_table_type table_type,
2074 unsigned int range, u16 port, bool set)
2075 {
2076 MLXSW_REG_ZERO(sftr2, payload);
2077 mlxsw_reg_sftr2_swid_set(payload, 0);
2078 mlxsw_reg_sftr2_flood_table_set(payload, flood_table);
2079 mlxsw_reg_sftr2_index_set(payload, index);
2080 mlxsw_reg_sftr2_table_type_set(payload, table_type);
2081 mlxsw_reg_sftr2_range_set(payload, range);
2082 mlxsw_reg_sftr2_port_set(payload, port, set);
2083 mlxsw_reg_sftr2_port_mask_set(payload, port, 1);
2084 }
2085
2086 /* SMID-V2 - Switch Multicast ID Version 2 Register
2087 * ------------------------------------------------
2088 * The MID record maps from a MID (Multicast ID), which is a unique identifier
2089 * of the multicast group within the stacking domain, into a list of local
2090 * ports into which the packet is replicated.
2091 */
2092 #define MLXSW_REG_SMID2_ID 0x2034
2093 #define MLXSW_REG_SMID2_LEN 0x120
2094
2095 MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN);
2096
2097 /* reg_smid2_swid
2098 * Switch partition ID.
2099 * Access: Index
2100 */
2101 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8);
2102
2103 /* reg_smid2_mid
2104 * Multicast identifier - global identifier that represents the multicast group
2105 * across all devices.
2106 * Access: Index
2107 */
2108 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16);
2109
2110 /* reg_smid2_port
2111 * Local port memebership (1 bit per port).
2112 * Access: RW
2113 */
2114 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1);
2115
2116 /* reg_smid2_port_mask
2117 * Local port mask (1 bit per port).
2118 * Access: WO
2119 */
2120 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1);
2121
mlxsw_reg_smid2_pack(char * payload,u16 mid,u16 port,bool set)2122 static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port,
2123 bool set)
2124 {
2125 MLXSW_REG_ZERO(smid2, payload);
2126 mlxsw_reg_smid2_swid_set(payload, 0);
2127 mlxsw_reg_smid2_mid_set(payload, mid);
2128 mlxsw_reg_smid2_port_set(payload, port, set);
2129 mlxsw_reg_smid2_port_mask_set(payload, port, 1);
2130 }
2131
2132 /* CWTP - Congetion WRED ECN TClass Profile
2133 * ----------------------------------------
2134 * Configures the profiles for queues of egress port and traffic class
2135 */
2136 #define MLXSW_REG_CWTP_ID 0x2802
2137 #define MLXSW_REG_CWTP_BASE_LEN 0x28
2138 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
2139 #define MLXSW_REG_CWTP_LEN 0x40
2140
2141 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
2142
2143 /* reg_cwtp_local_port
2144 * Local port number
2145 * Not supported for CPU port
2146 * Access: Index
2147 */
2148 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12);
2149
2150 /* reg_cwtp_traffic_class
2151 * Traffic Class to configure
2152 * Access: Index
2153 */
2154 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
2155
2156 /* reg_cwtp_profile_min
2157 * Minimum Average Queue Size of the profile in cells.
2158 * Access: RW
2159 */
2160 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
2161 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
2162
2163 /* reg_cwtp_profile_percent
2164 * Percentage of WRED and ECN marking for maximum Average Queue size
2165 * Range is 0 to 100, units of integer percentage
2166 * Access: RW
2167 */
2168 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
2169 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
2170
2171 /* reg_cwtp_profile_max
2172 * Maximum Average Queue size of the profile in cells
2173 * Access: RW
2174 */
2175 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
2176 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
2177
2178 #define MLXSW_REG_CWTP_MIN_VALUE 64
2179 #define MLXSW_REG_CWTP_MAX_PROFILE 2
2180 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
2181
mlxsw_reg_cwtp_pack(char * payload,u16 local_port,u8 traffic_class)2182 static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port,
2183 u8 traffic_class)
2184 {
2185 int i;
2186
2187 MLXSW_REG_ZERO(cwtp, payload);
2188 mlxsw_reg_cwtp_local_port_set(payload, local_port);
2189 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
2190
2191 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
2192 mlxsw_reg_cwtp_profile_min_set(payload, i,
2193 MLXSW_REG_CWTP_MIN_VALUE);
2194 mlxsw_reg_cwtp_profile_max_set(payload, i,
2195 MLXSW_REG_CWTP_MIN_VALUE);
2196 }
2197 }
2198
2199 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
2200
2201 static inline void
mlxsw_reg_cwtp_profile_pack(char * payload,u8 profile,u32 min,u32 max,u32 probability)2202 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
2203 u32 probability)
2204 {
2205 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
2206
2207 mlxsw_reg_cwtp_profile_min_set(payload, index, min);
2208 mlxsw_reg_cwtp_profile_max_set(payload, index, max);
2209 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
2210 }
2211
2212 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping
2213 * ---------------------------------------------------
2214 * The CWTPM register maps each egress port and traffic class to profile num.
2215 */
2216 #define MLXSW_REG_CWTPM_ID 0x2803
2217 #define MLXSW_REG_CWTPM_LEN 0x44
2218
2219 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
2220
2221 /* reg_cwtpm_local_port
2222 * Local port number
2223 * Not supported for CPU port
2224 * Access: Index
2225 */
2226 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12);
2227
2228 /* reg_cwtpm_traffic_class
2229 * Traffic Class to configure
2230 * Access: Index
2231 */
2232 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
2233
2234 /* reg_cwtpm_ew
2235 * Control enablement of WRED for traffic class:
2236 * 0 - Disable
2237 * 1 - Enable
2238 * Access: RW
2239 */
2240 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
2241
2242 /* reg_cwtpm_ee
2243 * Control enablement of ECN for traffic class:
2244 * 0 - Disable
2245 * 1 - Enable
2246 * Access: RW
2247 */
2248 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
2249
2250 /* reg_cwtpm_tcp_g
2251 * TCP Green Profile.
2252 * Index of the profile within {port, traffic class} to use.
2253 * 0 for disabling both WRED and ECN for this type of traffic.
2254 * Access: RW
2255 */
2256 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
2257
2258 /* reg_cwtpm_tcp_y
2259 * TCP Yellow Profile.
2260 * Index of the profile within {port, traffic class} to use.
2261 * 0 for disabling both WRED and ECN for this type of traffic.
2262 * Access: RW
2263 */
2264 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
2265
2266 /* reg_cwtpm_tcp_r
2267 * TCP Red Profile.
2268 * Index of the profile within {port, traffic class} to use.
2269 * 0 for disabling both WRED and ECN for this type of traffic.
2270 * Access: RW
2271 */
2272 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2273
2274 /* reg_cwtpm_ntcp_g
2275 * Non-TCP Green Profile.
2276 * Index of the profile within {port, traffic class} to use.
2277 * 0 for disabling both WRED and ECN for this type of traffic.
2278 * Access: RW
2279 */
2280 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2281
2282 /* reg_cwtpm_ntcp_y
2283 * Non-TCP Yellow Profile.
2284 * Index of the profile within {port, traffic class} to use.
2285 * 0 for disabling both WRED and ECN for this type of traffic.
2286 * Access: RW
2287 */
2288 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2289
2290 /* reg_cwtpm_ntcp_r
2291 * Non-TCP Red Profile.
2292 * Index of the profile within {port, traffic class} to use.
2293 * 0 for disabling both WRED and ECN for this type of traffic.
2294 * Access: RW
2295 */
2296 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2297
2298 #define MLXSW_REG_CWTPM_RESET_PROFILE 0
2299
mlxsw_reg_cwtpm_pack(char * payload,u16 local_port,u8 traffic_class,u8 profile,bool wred,bool ecn)2300 static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port,
2301 u8 traffic_class, u8 profile,
2302 bool wred, bool ecn)
2303 {
2304 MLXSW_REG_ZERO(cwtpm, payload);
2305 mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2306 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2307 mlxsw_reg_cwtpm_ew_set(payload, wred);
2308 mlxsw_reg_cwtpm_ee_set(payload, ecn);
2309 mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
2310 mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
2311 mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
2312 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
2313 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
2314 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
2315 }
2316
2317 /* PGCR - Policy-Engine General Configuration Register
2318 * ---------------------------------------------------
2319 * This register configures general Policy-Engine settings.
2320 */
2321 #define MLXSW_REG_PGCR_ID 0x3001
2322 #define MLXSW_REG_PGCR_LEN 0x20
2323
2324 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
2325
2326 /* reg_pgcr_default_action_pointer_base
2327 * Default action pointer base. Each region has a default action pointer
2328 * which is equal to default_action_pointer_base + region_id.
2329 * Access: RW
2330 */
2331 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2332
mlxsw_reg_pgcr_pack(char * payload,u32 pointer_base)2333 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
2334 {
2335 MLXSW_REG_ZERO(pgcr, payload);
2336 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2337 }
2338
2339 /* PPBT - Policy-Engine Port Binding Table
2340 * ---------------------------------------
2341 * This register is used for configuration of the Port Binding Table.
2342 */
2343 #define MLXSW_REG_PPBT_ID 0x3002
2344 #define MLXSW_REG_PPBT_LEN 0x14
2345
2346 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2347
2348 enum mlxsw_reg_pxbt_e {
2349 MLXSW_REG_PXBT_E_IACL,
2350 MLXSW_REG_PXBT_E_EACL,
2351 };
2352
2353 /* reg_ppbt_e
2354 * Access: Index
2355 */
2356 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2357
2358 enum mlxsw_reg_pxbt_op {
2359 MLXSW_REG_PXBT_OP_BIND,
2360 MLXSW_REG_PXBT_OP_UNBIND,
2361 };
2362
2363 /* reg_ppbt_op
2364 * Access: RW
2365 */
2366 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2367
2368 /* reg_ppbt_local_port
2369 * Local port. Not including CPU port.
2370 * Access: Index
2371 */
2372 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12);
2373
2374 /* reg_ppbt_g
2375 * group - When set, the binding is of an ACL group. When cleared,
2376 * the binding is of an ACL.
2377 * Must be set to 1 for Spectrum.
2378 * Access: RW
2379 */
2380 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2381
2382 /* reg_ppbt_acl_info
2383 * ACL/ACL group identifier. If the g bit is set, this field should hold
2384 * the acl_group_id, else it should hold the acl_id.
2385 * Access: RW
2386 */
2387 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2388
mlxsw_reg_ppbt_pack(char * payload,enum mlxsw_reg_pxbt_e e,enum mlxsw_reg_pxbt_op op,u16 local_port,u16 acl_info)2389 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2390 enum mlxsw_reg_pxbt_op op,
2391 u16 local_port, u16 acl_info)
2392 {
2393 MLXSW_REG_ZERO(ppbt, payload);
2394 mlxsw_reg_ppbt_e_set(payload, e);
2395 mlxsw_reg_ppbt_op_set(payload, op);
2396 mlxsw_reg_ppbt_local_port_set(payload, local_port);
2397 mlxsw_reg_ppbt_g_set(payload, true);
2398 mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2399 }
2400
2401 /* PACL - Policy-Engine ACL Register
2402 * ---------------------------------
2403 * This register is used for configuration of the ACL.
2404 */
2405 #define MLXSW_REG_PACL_ID 0x3004
2406 #define MLXSW_REG_PACL_LEN 0x70
2407
2408 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2409
2410 /* reg_pacl_v
2411 * Valid. Setting the v bit makes the ACL valid. It should not be cleared
2412 * while the ACL is bounded to either a port, VLAN or ACL rule.
2413 * Access: RW
2414 */
2415 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2416
2417 /* reg_pacl_acl_id
2418 * An identifier representing the ACL (managed by software)
2419 * Range 0 .. cap_max_acl_regions - 1
2420 * Access: Index
2421 */
2422 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2423
2424 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2425
2426 /* reg_pacl_tcam_region_info
2427 * Opaque object that represents a TCAM region.
2428 * Obtained through PTAR register.
2429 * Access: RW
2430 */
2431 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2432 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2433
mlxsw_reg_pacl_pack(char * payload,u16 acl_id,bool valid,const char * tcam_region_info)2434 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2435 bool valid, const char *tcam_region_info)
2436 {
2437 MLXSW_REG_ZERO(pacl, payload);
2438 mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2439 mlxsw_reg_pacl_v_set(payload, valid);
2440 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2441 }
2442
2443 /* PAGT - Policy-Engine ACL Group Table
2444 * ------------------------------------
2445 * This register is used for configuration of the ACL Group Table.
2446 */
2447 #define MLXSW_REG_PAGT_ID 0x3005
2448 #define MLXSW_REG_PAGT_BASE_LEN 0x30
2449 #define MLXSW_REG_PAGT_ACL_LEN 4
2450 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2451 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2452 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2453
2454 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2455
2456 /* reg_pagt_size
2457 * Number of ACLs in the group.
2458 * Size 0 invalidates a group.
2459 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)
2460 * Total number of ACLs in all groups must be lower or equal
2461 * to cap_max_acl_tot_groups
2462 * Note: a group which is binded must not be invalidated
2463 * Access: Index
2464 */
2465 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2466
2467 /* reg_pagt_acl_group_id
2468 * An identifier (numbered from 0..cap_max_acl_groups-1) representing
2469 * the ACL Group identifier (managed by software).
2470 * Access: Index
2471 */
2472 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2473
2474 /* reg_pagt_multi
2475 * Multi-ACL
2476 * 0 - This ACL is the last ACL in the multi-ACL
2477 * 1 - This ACL is part of a multi-ACL
2478 * Access: RW
2479 */
2480 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2481
2482 /* reg_pagt_acl_id
2483 * ACL identifier
2484 * Access: RW
2485 */
2486 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2487
mlxsw_reg_pagt_pack(char * payload,u16 acl_group_id)2488 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2489 {
2490 MLXSW_REG_ZERO(pagt, payload);
2491 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2492 }
2493
mlxsw_reg_pagt_acl_id_pack(char * payload,int index,u16 acl_id,bool multi)2494 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2495 u16 acl_id, bool multi)
2496 {
2497 u8 size = mlxsw_reg_pagt_size_get(payload);
2498
2499 if (index >= size)
2500 mlxsw_reg_pagt_size_set(payload, index + 1);
2501 mlxsw_reg_pagt_multi_set(payload, index, multi);
2502 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2503 }
2504
2505 /* PTAR - Policy-Engine TCAM Allocation Register
2506 * ---------------------------------------------
2507 * This register is used for allocation of regions in the TCAM.
2508 * Note: Query method is not supported on this register.
2509 */
2510 #define MLXSW_REG_PTAR_ID 0x3006
2511 #define MLXSW_REG_PTAR_BASE_LEN 0x20
2512 #define MLXSW_REG_PTAR_KEY_ID_LEN 1
2513 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2514 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2515 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2516
2517 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2518
2519 enum mlxsw_reg_ptar_op {
2520 /* allocate a TCAM region */
2521 MLXSW_REG_PTAR_OP_ALLOC,
2522 /* resize a TCAM region */
2523 MLXSW_REG_PTAR_OP_RESIZE,
2524 /* deallocate TCAM region */
2525 MLXSW_REG_PTAR_OP_FREE,
2526 /* test allocation */
2527 MLXSW_REG_PTAR_OP_TEST,
2528 };
2529
2530 /* reg_ptar_op
2531 * Access: OP
2532 */
2533 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2534
2535 /* reg_ptar_action_set_type
2536 * Type of action set to be used on this region.
2537 * For Spectrum and Spectrum-2, this is always type 2 - "flexible"
2538 * Access: WO
2539 */
2540 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2541
2542 enum mlxsw_reg_ptar_key_type {
2543 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */
2544 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */
2545 };
2546
2547 /* reg_ptar_key_type
2548 * TCAM key type for the region.
2549 * Access: WO
2550 */
2551 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2552
2553 /* reg_ptar_region_size
2554 * TCAM region size. When allocating/resizing this is the requested size,
2555 * the response is the actual size. Note that actual size may be
2556 * larger than requested.
2557 * Allowed range 1 .. cap_max_rules-1
2558 * Reserved during op deallocate.
2559 * Access: WO
2560 */
2561 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2562
2563 /* reg_ptar_region_id
2564 * Region identifier
2565 * Range 0 .. cap_max_regions-1
2566 * Access: Index
2567 */
2568 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2569
2570 /* reg_ptar_tcam_region_info
2571 * Opaque object that represents the TCAM region.
2572 * Returned when allocating a region.
2573 * Provided by software for ACL generation and region deallocation and resize.
2574 * Access: RW
2575 */
2576 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2577 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2578
2579 /* reg_ptar_flexible_key_id
2580 * Identifier of the Flexible Key.
2581 * Only valid if key_type == "FLEX_KEY"
2582 * The key size will be rounded up to one of the following values:
2583 * 9B, 18B, 36B, 54B.
2584 * This field is reserved for in resize operation.
2585 * Access: WO
2586 */
2587 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2588 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2589
mlxsw_reg_ptar_pack(char * payload,enum mlxsw_reg_ptar_op op,enum mlxsw_reg_ptar_key_type key_type,u16 region_size,u16 region_id,const char * tcam_region_info)2590 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2591 enum mlxsw_reg_ptar_key_type key_type,
2592 u16 region_size, u16 region_id,
2593 const char *tcam_region_info)
2594 {
2595 MLXSW_REG_ZERO(ptar, payload);
2596 mlxsw_reg_ptar_op_set(payload, op);
2597 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */
2598 mlxsw_reg_ptar_key_type_set(payload, key_type);
2599 mlxsw_reg_ptar_region_size_set(payload, region_size);
2600 mlxsw_reg_ptar_region_id_set(payload, region_id);
2601 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2602 }
2603
mlxsw_reg_ptar_key_id_pack(char * payload,int index,u16 key_id)2604 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2605 u16 key_id)
2606 {
2607 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2608 }
2609
mlxsw_reg_ptar_unpack(char * payload,char * tcam_region_info)2610 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2611 {
2612 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2613 }
2614
2615 /* PPBS - Policy-Engine Policy Based Switching Register
2616 * ----------------------------------------------------
2617 * This register retrieves and sets Policy Based Switching Table entries.
2618 */
2619 #define MLXSW_REG_PPBS_ID 0x300C
2620 #define MLXSW_REG_PPBS_LEN 0x14
2621
2622 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2623
2624 /* reg_ppbs_pbs_ptr
2625 * Index into the PBS table.
2626 * For Spectrum, the index points to the KVD Linear.
2627 * Access: Index
2628 */
2629 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2630
2631 /* reg_ppbs_system_port
2632 * Unique port identifier for the final destination of the packet.
2633 * Access: RW
2634 */
2635 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2636
mlxsw_reg_ppbs_pack(char * payload,u32 pbs_ptr,u16 system_port)2637 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2638 u16 system_port)
2639 {
2640 MLXSW_REG_ZERO(ppbs, payload);
2641 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2642 mlxsw_reg_ppbs_system_port_set(payload, system_port);
2643 }
2644
2645 /* PRCR - Policy-Engine Rules Copy Register
2646 * ----------------------------------------
2647 * This register is used for accessing rules within a TCAM region.
2648 */
2649 #define MLXSW_REG_PRCR_ID 0x300D
2650 #define MLXSW_REG_PRCR_LEN 0x40
2651
2652 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2653
2654 enum mlxsw_reg_prcr_op {
2655 /* Move rules. Moves the rules from "tcam_region_info" starting
2656 * at offset "offset" to "dest_tcam_region_info"
2657 * at offset "dest_offset."
2658 */
2659 MLXSW_REG_PRCR_OP_MOVE,
2660 /* Copy rules. Copies the rules from "tcam_region_info" starting
2661 * at offset "offset" to "dest_tcam_region_info"
2662 * at offset "dest_offset."
2663 */
2664 MLXSW_REG_PRCR_OP_COPY,
2665 };
2666
2667 /* reg_prcr_op
2668 * Access: OP
2669 */
2670 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2671
2672 /* reg_prcr_offset
2673 * Offset within the source region to copy/move from.
2674 * Access: Index
2675 */
2676 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2677
2678 /* reg_prcr_size
2679 * The number of rules to copy/move.
2680 * Access: WO
2681 */
2682 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2683
2684 /* reg_prcr_tcam_region_info
2685 * Opaque object that represents the source TCAM region.
2686 * Access: Index
2687 */
2688 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2689 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2690
2691 /* reg_prcr_dest_offset
2692 * Offset within the source region to copy/move to.
2693 * Access: Index
2694 */
2695 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2696
2697 /* reg_prcr_dest_tcam_region_info
2698 * Opaque object that represents the destination TCAM region.
2699 * Access: Index
2700 */
2701 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2702 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2703
mlxsw_reg_prcr_pack(char * payload,enum mlxsw_reg_prcr_op op,const char * src_tcam_region_info,u16 src_offset,const char * dest_tcam_region_info,u16 dest_offset,u16 size)2704 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2705 const char *src_tcam_region_info,
2706 u16 src_offset,
2707 const char *dest_tcam_region_info,
2708 u16 dest_offset, u16 size)
2709 {
2710 MLXSW_REG_ZERO(prcr, payload);
2711 mlxsw_reg_prcr_op_set(payload, op);
2712 mlxsw_reg_prcr_offset_set(payload, src_offset);
2713 mlxsw_reg_prcr_size_set(payload, size);
2714 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2715 src_tcam_region_info);
2716 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2717 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2718 dest_tcam_region_info);
2719 }
2720
2721 /* PEFA - Policy-Engine Extended Flexible Action Register
2722 * ------------------------------------------------------
2723 * This register is used for accessing an extended flexible action entry
2724 * in the central KVD Linear Database.
2725 */
2726 #define MLXSW_REG_PEFA_ID 0x300F
2727 #define MLXSW_REG_PEFA_LEN 0xB0
2728
2729 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2730
2731 /* reg_pefa_index
2732 * Index in the KVD Linear Centralized Database.
2733 * Access: Index
2734 */
2735 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2736
2737 /* reg_pefa_a
2738 * Index in the KVD Linear Centralized Database.
2739 * Activity
2740 * For a new entry: set if ca=0, clear if ca=1
2741 * Set if a packet lookup has hit on the specific entry
2742 * Access: RO
2743 */
2744 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2745
2746 /* reg_pefa_ca
2747 * Clear activity
2748 * When write: activity is according to this field
2749 * When read: after reading the activity is cleared according to ca
2750 * Access: OP
2751 */
2752 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2753
2754 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2755
2756 /* reg_pefa_flex_action_set
2757 * Action-set to perform when rule is matched.
2758 * Must be zero padded if action set is shorter.
2759 * Access: RW
2760 */
2761 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2762
mlxsw_reg_pefa_pack(char * payload,u32 index,bool ca,const char * flex_action_set)2763 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2764 const char *flex_action_set)
2765 {
2766 MLXSW_REG_ZERO(pefa, payload);
2767 mlxsw_reg_pefa_index_set(payload, index);
2768 mlxsw_reg_pefa_ca_set(payload, ca);
2769 if (flex_action_set)
2770 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2771 flex_action_set);
2772 }
2773
mlxsw_reg_pefa_unpack(char * payload,bool * p_a)2774 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2775 {
2776 *p_a = mlxsw_reg_pefa_a_get(payload);
2777 }
2778
2779 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register
2780 * --------------------------------------------------------------
2781 * This register is used for binding Multicast router to an ACL group
2782 * that serves the MC router.
2783 * This register is not supported by SwitchX/-2 and Spectrum.
2784 */
2785 #define MLXSW_REG_PEMRBT_ID 0x3014
2786 #define MLXSW_REG_PEMRBT_LEN 0x14
2787
2788 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
2789
2790 enum mlxsw_reg_pemrbt_protocol {
2791 MLXSW_REG_PEMRBT_PROTO_IPV4,
2792 MLXSW_REG_PEMRBT_PROTO_IPV6,
2793 };
2794
2795 /* reg_pemrbt_protocol
2796 * Access: Index
2797 */
2798 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
2799
2800 /* reg_pemrbt_group_id
2801 * ACL group identifier.
2802 * Range 0..cap_max_acl_groups-1
2803 * Access: RW
2804 */
2805 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
2806
2807 static inline void
mlxsw_reg_pemrbt_pack(char * payload,enum mlxsw_reg_pemrbt_protocol protocol,u16 group_id)2808 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
2809 u16 group_id)
2810 {
2811 MLXSW_REG_ZERO(pemrbt, payload);
2812 mlxsw_reg_pemrbt_protocol_set(payload, protocol);
2813 mlxsw_reg_pemrbt_group_id_set(payload, group_id);
2814 }
2815
2816 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
2817 * -----------------------------------------------------
2818 * This register is used for accessing rules within a TCAM region.
2819 * It is a new version of PTCE in order to support wider key,
2820 * mask and action within a TCAM region. This register is not supported
2821 * by SwitchX and SwitchX-2.
2822 */
2823 #define MLXSW_REG_PTCE2_ID 0x3017
2824 #define MLXSW_REG_PTCE2_LEN 0x1D8
2825
2826 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2827
2828 /* reg_ptce2_v
2829 * Valid.
2830 * Access: RW
2831 */
2832 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2833
2834 /* reg_ptce2_a
2835 * Activity. Set if a packet lookup has hit on the specific entry.
2836 * To clear the "a" bit, use "clear activity" op or "clear on read" op.
2837 * Access: RO
2838 */
2839 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2840
2841 enum mlxsw_reg_ptce2_op {
2842 /* Read operation. */
2843 MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2844 /* clear on read operation. Used to read entry
2845 * and clear Activity bit.
2846 */
2847 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2848 /* Write operation. Used to write a new entry to the table.
2849 * All R/W fields are relevant for new entry. Activity bit is set
2850 * for new entries - Note write with v = 0 will delete the entry.
2851 */
2852 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2853 /* Update action. Only action set will be updated. */
2854 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2855 /* Clear activity. A bit is cleared for the entry. */
2856 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2857 };
2858
2859 /* reg_ptce2_op
2860 * Access: OP
2861 */
2862 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2863
2864 /* reg_ptce2_offset
2865 * Access: Index
2866 */
2867 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2868
2869 /* reg_ptce2_priority
2870 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1.
2871 * Note: priority does not have to be unique per rule.
2872 * Within a region, higher priority should have lower offset (no limitation
2873 * between regions in a multi-region).
2874 * Access: RW
2875 */
2876 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
2877
2878 /* reg_ptce2_tcam_region_info
2879 * Opaque object that represents the TCAM region.
2880 * Access: Index
2881 */
2882 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2883 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2884
2885 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
2886
2887 /* reg_ptce2_flex_key_blocks
2888 * ACL Key.
2889 * Access: RW
2890 */
2891 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2892 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2893
2894 /* reg_ptce2_mask
2895 * mask- in the same size as key. A bit that is set directs the TCAM
2896 * to compare the corresponding bit in key. A bit that is clear directs
2897 * the TCAM to ignore the corresponding bit in key.
2898 * Access: RW
2899 */
2900 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2901 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2902
2903 /* reg_ptce2_flex_action_set
2904 * ACL action set.
2905 * Access: RW
2906 */
2907 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2908 MLXSW_REG_FLEX_ACTION_SET_LEN);
2909
mlxsw_reg_ptce2_pack(char * payload,bool valid,enum mlxsw_reg_ptce2_op op,const char * tcam_region_info,u16 offset,u32 priority)2910 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2911 enum mlxsw_reg_ptce2_op op,
2912 const char *tcam_region_info,
2913 u16 offset, u32 priority)
2914 {
2915 MLXSW_REG_ZERO(ptce2, payload);
2916 mlxsw_reg_ptce2_v_set(payload, valid);
2917 mlxsw_reg_ptce2_op_set(payload, op);
2918 mlxsw_reg_ptce2_offset_set(payload, offset);
2919 mlxsw_reg_ptce2_priority_set(payload, priority);
2920 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2921 }
2922
2923 /* PERPT - Policy-Engine ERP Table Register
2924 * ----------------------------------------
2925 * This register adds and removes eRPs from the eRP table.
2926 */
2927 #define MLXSW_REG_PERPT_ID 0x3021
2928 #define MLXSW_REG_PERPT_LEN 0x80
2929
2930 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
2931
2932 /* reg_perpt_erpt_bank
2933 * eRP table bank.
2934 * Range 0 .. cap_max_erp_table_banks - 1
2935 * Access: Index
2936 */
2937 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
2938
2939 /* reg_perpt_erpt_index
2940 * Index to eRP table within the eRP bank.
2941 * Range is 0 .. cap_max_erp_table_bank_size - 1
2942 * Access: Index
2943 */
2944 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
2945
2946 enum mlxsw_reg_perpt_key_size {
2947 MLXSW_REG_PERPT_KEY_SIZE_2KB,
2948 MLXSW_REG_PERPT_KEY_SIZE_4KB,
2949 MLXSW_REG_PERPT_KEY_SIZE_8KB,
2950 MLXSW_REG_PERPT_KEY_SIZE_12KB,
2951 };
2952
2953 /* reg_perpt_key_size
2954 * Access: OP
2955 */
2956 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
2957
2958 /* reg_perpt_bf_bypass
2959 * 0 - The eRP is used only if bloom filter state is set for the given
2960 * rule.
2961 * 1 - The eRP is used regardless of bloom filter state.
2962 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass
2963 * Access: RW
2964 */
2965 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
2966
2967 /* reg_perpt_erp_id
2968 * eRP ID for use by the rules.
2969 * Access: RW
2970 */
2971 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
2972
2973 /* reg_perpt_erpt_base_bank
2974 * Base eRP table bank, points to head of erp_vector
2975 * Range is 0 .. cap_max_erp_table_banks - 1
2976 * Access: OP
2977 */
2978 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
2979
2980 /* reg_perpt_erpt_base_index
2981 * Base index to eRP table within the eRP bank
2982 * Range is 0 .. cap_max_erp_table_bank_size - 1
2983 * Access: OP
2984 */
2985 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
2986
2987 /* reg_perpt_erp_index_in_vector
2988 * eRP index in the vector.
2989 * Access: OP
2990 */
2991 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
2992
2993 /* reg_perpt_erp_vector
2994 * eRP vector.
2995 * Access: OP
2996 */
2997 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
2998
2999 /* reg_perpt_mask
3000 * Mask
3001 * 0 - A-TCAM will ignore the bit in key
3002 * 1 - A-TCAM will compare the bit in key
3003 * Access: RW
3004 */
3005 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3006
mlxsw_reg_perpt_erp_vector_pack(char * payload,unsigned long * erp_vector,unsigned long size)3007 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
3008 unsigned long *erp_vector,
3009 unsigned long size)
3010 {
3011 unsigned long bit;
3012
3013 for_each_set_bit(bit, erp_vector, size)
3014 mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
3015 }
3016
3017 static inline void
mlxsw_reg_perpt_pack(char * payload,u8 erpt_bank,u8 erpt_index,enum mlxsw_reg_perpt_key_size key_size,u8 erp_id,u8 erpt_base_bank,u8 erpt_base_index,u8 erp_index,char * mask)3018 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
3019 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
3020 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
3021 char *mask)
3022 {
3023 MLXSW_REG_ZERO(perpt, payload);
3024 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
3025 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
3026 mlxsw_reg_perpt_key_size_set(payload, key_size);
3027 mlxsw_reg_perpt_bf_bypass_set(payload, false);
3028 mlxsw_reg_perpt_erp_id_set(payload, erp_id);
3029 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
3030 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
3031 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
3032 mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
3033 }
3034
3035 /* PERAR - Policy-Engine Region Association Register
3036 * -------------------------------------------------
3037 * This register associates a hw region for region_id's. Changing on the fly
3038 * is supported by the device.
3039 */
3040 #define MLXSW_REG_PERAR_ID 0x3026
3041 #define MLXSW_REG_PERAR_LEN 0x08
3042
3043 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
3044
3045 /* reg_perar_region_id
3046 * Region identifier
3047 * Range 0 .. cap_max_regions-1
3048 * Access: Index
3049 */
3050 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
3051
3052 static inline unsigned int
mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)3053 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
3054 {
3055 return DIV_ROUND_UP(block_num, 4);
3056 }
3057
3058 /* reg_perar_hw_region
3059 * HW Region
3060 * Range 0 .. cap_max_regions-1
3061 * Default: hw_region = region_id
3062 * For a 8 key block region, 2 consecutive regions are used
3063 * For a 12 key block region, 3 consecutive regions are used
3064 * Access: RW
3065 */
3066 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
3067
mlxsw_reg_perar_pack(char * payload,u16 region_id,u16 hw_region)3068 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
3069 u16 hw_region)
3070 {
3071 MLXSW_REG_ZERO(perar, payload);
3072 mlxsw_reg_perar_region_id_set(payload, region_id);
3073 mlxsw_reg_perar_hw_region_set(payload, hw_region);
3074 }
3075
3076 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3
3077 * -----------------------------------------------------
3078 * This register is a new version of PTCE-V2 in order to support the
3079 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.
3080 */
3081 #define MLXSW_REG_PTCE3_ID 0x3027
3082 #define MLXSW_REG_PTCE3_LEN 0xF0
3083
3084 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
3085
3086 /* reg_ptce3_v
3087 * Valid.
3088 * Access: RW
3089 */
3090 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
3091
3092 enum mlxsw_reg_ptce3_op {
3093 /* Write operation. Used to write a new entry to the table.
3094 * All R/W fields are relevant for new entry. Activity bit is set
3095 * for new entries. Write with v = 0 will delete the entry. Must
3096 * not be used if an entry exists.
3097 */
3098 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
3099 /* Update operation */
3100 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
3101 /* Read operation */
3102 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
3103 };
3104
3105 /* reg_ptce3_op
3106 * Access: OP
3107 */
3108 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
3109
3110 /* reg_ptce3_priority
3111 * Priority of the rule. Higher values win.
3112 * For Spectrum-2 range is 1..cap_kvd_size - 1
3113 * Note: Priority does not have to be unique per rule.
3114 * Access: RW
3115 */
3116 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
3117
3118 /* reg_ptce3_tcam_region_info
3119 * Opaque object that represents the TCAM region.
3120 * Access: Index
3121 */
3122 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
3123 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
3124
3125 /* reg_ptce3_flex2_key_blocks
3126 * ACL key. The key must be masked according to eRP (if exists) or
3127 * according to master mask.
3128 * Access: Index
3129 */
3130 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
3131 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3132
3133 /* reg_ptce3_erp_id
3134 * eRP ID.
3135 * Access: Index
3136 */
3137 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
3138
3139 /* reg_ptce3_delta_start
3140 * Start point of delta_value and delta_mask, in bits. Must not exceed
3141 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0.
3142 * Access: Index
3143 */
3144 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
3145
3146 /* reg_ptce3_delta_mask
3147 * Delta mask.
3148 * 0 - Ignore relevant bit in delta_value
3149 * 1 - Compare relevant bit in delta_value
3150 * Delta mask must not be set for reserved fields in the key blocks.
3151 * Note: No delta when no eRPs. Thus, for regions with
3152 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0.
3153 * Access: Index
3154 */
3155 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
3156
3157 /* reg_ptce3_delta_value
3158 * Delta value.
3159 * Bits which are masked by delta_mask must be 0.
3160 * Access: Index
3161 */
3162 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
3163
3164 /* reg_ptce3_prune_vector
3165 * Pruning vector relative to the PERPT.erp_id.
3166 * Used for reducing lookups.
3167 * 0 - NEED: Do a lookup using the eRP.
3168 * 1 - PRUNE: Do not perform a lookup using the eRP.
3169 * Maybe be modified by PEAPBL and PEAPBM.
3170 * Note: In Spectrum-2, a region of 8 key blocks must be set to either
3171 * all 1's or all 0's.
3172 * Access: RW
3173 */
3174 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
3175
3176 /* reg_ptce3_prune_ctcam
3177 * Pruning on C-TCAM. Used for reducing lookups.
3178 * 0 - NEED: Do a lookup in the C-TCAM.
3179 * 1 - PRUNE: Do not perform a lookup in the C-TCAM.
3180 * Access: RW
3181 */
3182 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
3183
3184 /* reg_ptce3_large_exists
3185 * Large entry key ID exists.
3186 * Within the region:
3187 * 0 - SINGLE: The large_entry_key_id is not currently in use.
3188 * For rule insert: The MSB of the key (blocks 6..11) will be added.
3189 * For rule delete: The MSB of the key will be removed.
3190 * 1 - NON_SINGLE: The large_entry_key_id is currently in use.
3191 * For rule insert: The MSB of the key (blocks 6..11) will not be added.
3192 * For rule delete: The MSB of the key will not be removed.
3193 * Access: WO
3194 */
3195 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
3196
3197 /* reg_ptce3_large_entry_key_id
3198 * Large entry key ID.
3199 * A key for 12 key blocks rules. Reserved when region has less than 12 key
3200 * blocks. Must be different for different keys which have the same common
3201 * 6 key blocks (MSB, blocks 6..11) key within a region.
3202 * Range is 0..cap_max_pe_large_key_id - 1
3203 * Access: RW
3204 */
3205 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
3206
3207 /* reg_ptce3_action_pointer
3208 * Pointer to action.
3209 * Range is 0..cap_max_kvd_action_sets - 1
3210 * Access: RW
3211 */
3212 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
3213
mlxsw_reg_ptce3_pack(char * payload,bool valid,enum mlxsw_reg_ptce3_op op,u32 priority,const char * tcam_region_info,const char * key,u8 erp_id,u16 delta_start,u8 delta_mask,u8 delta_value,bool large_exists,u32 lkey_id,u32 action_pointer)3214 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
3215 enum mlxsw_reg_ptce3_op op,
3216 u32 priority,
3217 const char *tcam_region_info,
3218 const char *key, u8 erp_id,
3219 u16 delta_start, u8 delta_mask,
3220 u8 delta_value, bool large_exists,
3221 u32 lkey_id, u32 action_pointer)
3222 {
3223 MLXSW_REG_ZERO(ptce3, payload);
3224 mlxsw_reg_ptce3_v_set(payload, valid);
3225 mlxsw_reg_ptce3_op_set(payload, op);
3226 mlxsw_reg_ptce3_priority_set(payload, priority);
3227 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
3228 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
3229 mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
3230 mlxsw_reg_ptce3_delta_start_set(payload, delta_start);
3231 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);
3232 mlxsw_reg_ptce3_delta_value_set(payload, delta_value);
3233 mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
3234 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
3235 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
3236 }
3237
3238 /* PERCR - Policy-Engine Region Configuration Register
3239 * ---------------------------------------------------
3240 * This register configures the region parameters. The region_id must be
3241 * allocated.
3242 */
3243 #define MLXSW_REG_PERCR_ID 0x302A
3244 #define MLXSW_REG_PERCR_LEN 0x80
3245
3246 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
3247
3248 /* reg_percr_region_id
3249 * Region identifier.
3250 * Range 0..cap_max_regions-1
3251 * Access: Index
3252 */
3253 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
3254
3255 /* reg_percr_atcam_ignore_prune
3256 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule.
3257 * Access: RW
3258 */
3259 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
3260
3261 /* reg_percr_ctcam_ignore_prune
3262 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule.
3263 * Access: RW
3264 */
3265 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
3266
3267 /* reg_percr_bf_bypass
3268 * Bloom filter bypass.
3269 * 0 - Bloom filter is used (default)
3270 * 1 - Bloom filter is bypassed. The bypass is an OR condition of
3271 * region_id or eRP. See PERPT.bf_bypass
3272 * Access: RW
3273 */
3274 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3275
3276 /* reg_percr_master_mask
3277 * Master mask. Logical OR mask of all masks of all rules of a region
3278 * (both A-TCAM and C-TCAM). When there are no eRPs
3279 * (erpt_pointer_valid = 0), then this provides the mask.
3280 * Access: RW
3281 */
3282 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3283
mlxsw_reg_percr_pack(char * payload,u16 region_id)3284 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
3285 {
3286 MLXSW_REG_ZERO(percr, payload);
3287 mlxsw_reg_percr_region_id_set(payload, region_id);
3288 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
3289 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
3290 mlxsw_reg_percr_bf_bypass_set(payload, false);
3291 }
3292
3293 /* PERERP - Policy-Engine Region eRP Register
3294 * ------------------------------------------
3295 * This register configures the region eRP. The region_id must be
3296 * allocated.
3297 */
3298 #define MLXSW_REG_PERERP_ID 0x302B
3299 #define MLXSW_REG_PERERP_LEN 0x1C
3300
3301 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
3302
3303 /* reg_pererp_region_id
3304 * Region identifier.
3305 * Range 0..cap_max_regions-1
3306 * Access: Index
3307 */
3308 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3309
3310 /* reg_pererp_ctcam_le
3311 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.
3312 * Access: RW
3313 */
3314 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3315
3316 /* reg_pererp_erpt_pointer_valid
3317 * erpt_pointer is valid.
3318 * Access: RW
3319 */
3320 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3321
3322 /* reg_pererp_erpt_bank_pointer
3323 * Pointer to eRP table bank. May be modified at any time.
3324 * Range 0..cap_max_erp_table_banks-1
3325 * Reserved when erpt_pointer_valid = 0
3326 */
3327 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3328
3329 /* reg_pererp_erpt_pointer
3330 * Pointer to eRP table within the eRP bank. Can be changed for an
3331 * existing region.
3332 * Range 0..cap_max_erp_table_size-1
3333 * Reserved when erpt_pointer_valid = 0
3334 * Access: RW
3335 */
3336 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3337
3338 /* reg_pererp_erpt_vector
3339 * Vector of allowed eRP indexes starting from erpt_pointer within the
3340 * erpt_bank_pointer. Next entries will be in next bank.
3341 * Note that eRP index is used and not eRP ID.
3342 * Reserved when erpt_pointer_valid = 0
3343 * Access: RW
3344 */
3345 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3346
3347 /* reg_pererp_master_rp_id
3348 * Master RP ID. When there are no eRPs, then this provides the eRP ID
3349 * for the lookup. Can be changed for an existing region.
3350 * Reserved when erpt_pointer_valid = 1
3351 * Access: RW
3352 */
3353 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3354
mlxsw_reg_pererp_erp_vector_pack(char * payload,unsigned long * erp_vector,unsigned long size)3355 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
3356 unsigned long *erp_vector,
3357 unsigned long size)
3358 {
3359 unsigned long bit;
3360
3361 for_each_set_bit(bit, erp_vector, size)
3362 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
3363 }
3364
mlxsw_reg_pererp_pack(char * payload,u16 region_id,bool ctcam_le,bool erpt_pointer_valid,u8 erpt_bank_pointer,u8 erpt_pointer,u8 master_rp_id)3365 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
3366 bool ctcam_le, bool erpt_pointer_valid,
3367 u8 erpt_bank_pointer, u8 erpt_pointer,
3368 u8 master_rp_id)
3369 {
3370 MLXSW_REG_ZERO(pererp, payload);
3371 mlxsw_reg_pererp_region_id_set(payload, region_id);
3372 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
3373 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
3374 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
3375 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
3376 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
3377 }
3378
3379 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register
3380 * ----------------------------------------------------------------
3381 * This register configures the Bloom filter entries.
3382 */
3383 #define MLXSW_REG_PEABFE_ID 0x3022
3384 #define MLXSW_REG_PEABFE_BASE_LEN 0x10
3385 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
3386 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
3387 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
3388 MLXSW_REG_PEABFE_BF_REC_LEN * \
3389 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
3390
3391 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
3392
3393 /* reg_peabfe_size
3394 * Number of BF entries to be updated.
3395 * Range 1..256
3396 * Access: Op
3397 */
3398 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3399
3400 /* reg_peabfe_bf_entry_state
3401 * Bloom filter state
3402 * 0 - Clear
3403 * 1 - Set
3404 * Access: RW
3405 */
3406 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3407 MLXSW_REG_PEABFE_BASE_LEN, 31, 1,
3408 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3409
3410 /* reg_peabfe_bf_entry_bank
3411 * Bloom filter bank ID
3412 * Range 0..cap_max_erp_table_banks-1
3413 * Access: Index
3414 */
3415 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3416 MLXSW_REG_PEABFE_BASE_LEN, 24, 4,
3417 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3418
3419 /* reg_peabfe_bf_entry_index
3420 * Bloom filter entry index
3421 * Range 0..2^cap_max_bf_log-1
3422 * Access: Index
3423 */
3424 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3425 MLXSW_REG_PEABFE_BASE_LEN, 0, 24,
3426 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3427
mlxsw_reg_peabfe_pack(char * payload)3428 static inline void mlxsw_reg_peabfe_pack(char *payload)
3429 {
3430 MLXSW_REG_ZERO(peabfe, payload);
3431 }
3432
mlxsw_reg_peabfe_rec_pack(char * payload,int rec_index,u8 state,u8 bank,u32 bf_index)3433 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
3434 u8 state, u8 bank, u32 bf_index)
3435 {
3436 u8 num_rec = mlxsw_reg_peabfe_size_get(payload);
3437
3438 if (rec_index >= num_rec)
3439 mlxsw_reg_peabfe_size_set(payload, rec_index + 1);
3440 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);
3441 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);
3442 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);
3443 }
3444
3445 /* IEDR - Infrastructure Entry Delete Register
3446 * ----------------------------------------------------
3447 * This register is used for deleting entries from the entry tables.
3448 * It is legitimate to attempt to delete a nonexisting entry (the device will
3449 * respond as a good flow).
3450 */
3451 #define MLXSW_REG_IEDR_ID 0x3804
3452 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */
3453 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */
3454 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3455 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \
3456 MLXSW_REG_IEDR_REC_LEN * \
3457 MLXSW_REG_IEDR_REC_MAX_COUNT)
3458
3459 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3460
3461 /* reg_iedr_num_rec
3462 * Number of records.
3463 * Access: OP
3464 */
3465 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3466
3467 /* reg_iedr_rec_type
3468 * Resource type.
3469 * Access: OP
3470 */
3471 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3472 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3473
3474 /* reg_iedr_rec_size
3475 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type.
3476 * Access: OP
3477 */
3478 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13,
3479 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3480
3481 /* reg_iedr_rec_index_start
3482 * Resource index start.
3483 * Access: OP
3484 */
3485 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3486 MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3487
mlxsw_reg_iedr_pack(char * payload)3488 static inline void mlxsw_reg_iedr_pack(char *payload)
3489 {
3490 MLXSW_REG_ZERO(iedr, payload);
3491 }
3492
mlxsw_reg_iedr_rec_pack(char * payload,int rec_index,u8 rec_type,u16 rec_size,u32 rec_index_start)3493 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3494 u8 rec_type, u16 rec_size,
3495 u32 rec_index_start)
3496 {
3497 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3498
3499 if (rec_index >= num_rec)
3500 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3501 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3502 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3503 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3504 }
3505
3506 /* QPTS - QoS Priority Trust State Register
3507 * ----------------------------------------
3508 * This register controls the port policy to calculate the switch priority and
3509 * packet color based on incoming packet fields.
3510 */
3511 #define MLXSW_REG_QPTS_ID 0x4002
3512 #define MLXSW_REG_QPTS_LEN 0x8
3513
3514 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3515
3516 /* reg_qpts_local_port
3517 * Local port number.
3518 * Access: Index
3519 *
3520 * Note: CPU port is supported.
3521 */
3522 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12);
3523
3524 enum mlxsw_reg_qpts_trust_state {
3525 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3526 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */
3527 };
3528
3529 /* reg_qpts_trust_state
3530 * Trust state for a given port.
3531 * Access: RW
3532 */
3533 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3534
mlxsw_reg_qpts_pack(char * payload,u16 local_port,enum mlxsw_reg_qpts_trust_state ts)3535 static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port,
3536 enum mlxsw_reg_qpts_trust_state ts)
3537 {
3538 MLXSW_REG_ZERO(qpts, payload);
3539
3540 mlxsw_reg_qpts_local_port_set(payload, local_port);
3541 mlxsw_reg_qpts_trust_state_set(payload, ts);
3542 }
3543
3544 /* QPCR - QoS Policer Configuration Register
3545 * -----------------------------------------
3546 * The QPCR register is used to create policers - that limit
3547 * the rate of bytes or packets via some trap group.
3548 */
3549 #define MLXSW_REG_QPCR_ID 0x4004
3550 #define MLXSW_REG_QPCR_LEN 0x28
3551
3552 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3553
3554 enum mlxsw_reg_qpcr_g {
3555 MLXSW_REG_QPCR_G_GLOBAL = 2,
3556 MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3557 };
3558
3559 /* reg_qpcr_g
3560 * The policer type.
3561 * Access: Index
3562 */
3563 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3564
3565 /* reg_qpcr_pid
3566 * Policer ID.
3567 * Access: Index
3568 */
3569 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3570
3571 /* reg_qpcr_clear_counter
3572 * Clear counters.
3573 * Access: OP
3574 */
3575 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1);
3576
3577 /* reg_qpcr_color_aware
3578 * Is the policer aware of colors.
3579 * Must be 0 (unaware) for cpu port.
3580 * Access: RW for unbounded policer. RO for bounded policer.
3581 */
3582 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3583
3584 /* reg_qpcr_bytes
3585 * Is policer limit is for bytes per sec or packets per sec.
3586 * 0 - packets
3587 * 1 - bytes
3588 * Access: RW for unbounded policer. RO for bounded policer.
3589 */
3590 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3591
3592 enum mlxsw_reg_qpcr_ir_units {
3593 MLXSW_REG_QPCR_IR_UNITS_M,
3594 MLXSW_REG_QPCR_IR_UNITS_K,
3595 };
3596
3597 /* reg_qpcr_ir_units
3598 * Policer's units for cir and eir fields (for bytes limits only)
3599 * 1 - 10^3
3600 * 0 - 10^6
3601 * Access: OP
3602 */
3603 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3604
3605 enum mlxsw_reg_qpcr_rate_type {
3606 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3607 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3608 };
3609
3610 /* reg_qpcr_rate_type
3611 * Policer can have one limit (single rate) or 2 limits with specific operation
3612 * for packets that exceed the lower rate but not the upper one.
3613 * (For cpu port must be single rate)
3614 * Access: RW for unbounded policer. RO for bounded policer.
3615 */
3616 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3617
3618 /* reg_qpc_cbs
3619 * Policer's committed burst size.
3620 * The policer is working with time slices of 50 nano sec. By default every
3621 * slice is granted the proportionate share of the committed rate. If we want to
3622 * allow a slice to exceed that share (while still keeping the rate per sec) we
3623 * can allow burst. The burst size is between the default proportionate share
3624 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the
3625 * committed rate will result in exceeding the rate). The burst size must be a
3626 * log of 2 and will be determined by 2^cbs.
3627 * Access: RW
3628 */
3629 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3630
3631 /* reg_qpcr_cir
3632 * Policer's committed rate.
3633 * The rate used for sungle rate, the lower rate for double rate.
3634 * For bytes limits, the rate will be this value * the unit from ir_units.
3635 * (Resolution error is up to 1%).
3636 * Access: RW
3637 */
3638 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3639
3640 /* reg_qpcr_eir
3641 * Policer's exceed rate.
3642 * The higher rate for double rate, reserved for single rate.
3643 * Lower rate for double rate policer.
3644 * For bytes limits, the rate will be this value * the unit from ir_units.
3645 * (Resolution error is up to 1%).
3646 * Access: RW
3647 */
3648 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3649
3650 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3651
3652 /* reg_qpcr_exceed_action.
3653 * What to do with packets between the 2 limits for double rate.
3654 * Access: RW for unbounded policer. RO for bounded policer.
3655 */
3656 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3657
3658 enum mlxsw_reg_qpcr_action {
3659 /* Discard */
3660 MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3661 /* Forward and set color to red.
3662 * If the packet is intended to cpu port, it will be dropped.
3663 */
3664 MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3665 };
3666
3667 /* reg_qpcr_violate_action
3668 * What to do with packets that cross the cir limit (for single rate) or the eir
3669 * limit (for double rate).
3670 * Access: RW for unbounded policer. RO for bounded policer.
3671 */
3672 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3673
3674 /* reg_qpcr_violate_count
3675 * Counts the number of times violate_action happened on this PID.
3676 * Access: RW
3677 */
3678 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64);
3679
3680 /* Packets */
3681 #define MLXSW_REG_QPCR_LOWEST_CIR 1
3682 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */
3683 #define MLXSW_REG_QPCR_LOWEST_CBS 4
3684 #define MLXSW_REG_QPCR_HIGHEST_CBS 24
3685
3686 /* Bandwidth */
3687 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */
3688 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */
3689 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4
3690 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4
3691 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25
3692 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31
3693
mlxsw_reg_qpcr_pack(char * payload,u16 pid,enum mlxsw_reg_qpcr_ir_units ir_units,bool bytes,u32 cir,u16 cbs)3694 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3695 enum mlxsw_reg_qpcr_ir_units ir_units,
3696 bool bytes, u32 cir, u16 cbs)
3697 {
3698 MLXSW_REG_ZERO(qpcr, payload);
3699 mlxsw_reg_qpcr_pid_set(payload, pid);
3700 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3701 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3702 mlxsw_reg_qpcr_violate_action_set(payload,
3703 MLXSW_REG_QPCR_ACTION_DISCARD);
3704 mlxsw_reg_qpcr_cir_set(payload, cir);
3705 mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3706 mlxsw_reg_qpcr_bytes_set(payload, bytes);
3707 mlxsw_reg_qpcr_cbs_set(payload, cbs);
3708 }
3709
3710 /* QTCT - QoS Switch Traffic Class Table
3711 * -------------------------------------
3712 * Configures the mapping between the packet switch priority and the
3713 * traffic class on the transmit port.
3714 */
3715 #define MLXSW_REG_QTCT_ID 0x400A
3716 #define MLXSW_REG_QTCT_LEN 0x08
3717
3718 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3719
3720 /* reg_qtct_local_port
3721 * Local port number.
3722 * Access: Index
3723 *
3724 * Note: CPU port is not supported.
3725 */
3726 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12);
3727
3728 /* reg_qtct_sub_port
3729 * Virtual port within the physical port.
3730 * Should be set to 0 when virtual ports are not enabled on the port.
3731 * Access: Index
3732 */
3733 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3734
3735 /* reg_qtct_switch_prio
3736 * Switch priority.
3737 * Access: Index
3738 */
3739 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3740
3741 /* reg_qtct_tclass
3742 * Traffic class.
3743 * Default values:
3744 * switch_prio 0 : tclass 1
3745 * switch_prio 1 : tclass 0
3746 * switch_prio i : tclass i, for i > 1
3747 * Access: RW
3748 */
3749 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3750
mlxsw_reg_qtct_pack(char * payload,u16 local_port,u8 switch_prio,u8 tclass)3751 static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port,
3752 u8 switch_prio, u8 tclass)
3753 {
3754 MLXSW_REG_ZERO(qtct, payload);
3755 mlxsw_reg_qtct_local_port_set(payload, local_port);
3756 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3757 mlxsw_reg_qtct_tclass_set(payload, tclass);
3758 }
3759
3760 /* QEEC - QoS ETS Element Configuration Register
3761 * ---------------------------------------------
3762 * Configures the ETS elements.
3763 */
3764 #define MLXSW_REG_QEEC_ID 0x400D
3765 #define MLXSW_REG_QEEC_LEN 0x20
3766
3767 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3768
3769 /* reg_qeec_local_port
3770 * Local port number.
3771 * Access: Index
3772 *
3773 * Note: CPU port is supported.
3774 */
3775 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12);
3776
3777 enum mlxsw_reg_qeec_hr {
3778 MLXSW_REG_QEEC_HR_PORT,
3779 MLXSW_REG_QEEC_HR_GROUP,
3780 MLXSW_REG_QEEC_HR_SUBGROUP,
3781 MLXSW_REG_QEEC_HR_TC,
3782 };
3783
3784 /* reg_qeec_element_hierarchy
3785 * 0 - Port
3786 * 1 - Group
3787 * 2 - Subgroup
3788 * 3 - Traffic Class
3789 * Access: Index
3790 */
3791 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3792
3793 /* reg_qeec_element_index
3794 * The index of the element in the hierarchy.
3795 * Access: Index
3796 */
3797 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3798
3799 /* reg_qeec_next_element_index
3800 * The index of the next (lower) element in the hierarchy.
3801 * Access: RW
3802 *
3803 * Note: Reserved for element_hierarchy 0.
3804 */
3805 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3806
3807 /* reg_qeec_mise
3808 * Min shaper configuration enable. Enables configuration of the min
3809 * shaper on this ETS element
3810 * 0 - Disable
3811 * 1 - Enable
3812 * Access: RW
3813 */
3814 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
3815
3816 /* reg_qeec_ptps
3817 * PTP shaper
3818 * 0: regular shaper mode
3819 * 1: PTP oriented shaper
3820 * Allowed only for hierarchy 0
3821 * Not supported for CPU port
3822 * Note that ptps mode may affect the shaper rates of all hierarchies
3823 * Supported only on Spectrum-1
3824 * Access: RW
3825 */
3826 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
3827
3828 enum {
3829 MLXSW_REG_QEEC_BYTES_MODE,
3830 MLXSW_REG_QEEC_PACKETS_MODE,
3831 };
3832
3833 /* reg_qeec_pb
3834 * Packets or bytes mode.
3835 * 0 - Bytes mode
3836 * 1 - Packets mode
3837 * Access: RW
3838 *
3839 * Note: Used for max shaper configuration. For Spectrum, packets mode
3840 * is supported only for traffic classes of CPU port.
3841 */
3842 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3843
3844 /* The smallest permitted min shaper rate. */
3845 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */
3846
3847 /* reg_qeec_min_shaper_rate
3848 * Min shaper information rate.
3849 * For CPU port, can only be configured for port hierarchy.
3850 * When in bytes mode, value is specified in units of 1000bps.
3851 * Access: RW
3852 */
3853 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
3854
3855 /* reg_qeec_mase
3856 * Max shaper configuration enable. Enables configuration of the max
3857 * shaper on this ETS element.
3858 * 0 - Disable
3859 * 1 - Enable
3860 * Access: RW
3861 */
3862 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3863
3864 /* The largest max shaper value possible to disable the shaper. */
3865 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */
3866
3867 /* reg_qeec_max_shaper_rate
3868 * Max shaper information rate.
3869 * For CPU port, can only be configured for port hierarchy.
3870 * When in bytes mode, value is specified in units of 1000bps.
3871 * Access: RW
3872 */
3873 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31);
3874
3875 /* reg_qeec_de
3876 * DWRR configuration enable. Enables configuration of the dwrr and
3877 * dwrr_weight.
3878 * 0 - Disable
3879 * 1 - Enable
3880 * Access: RW
3881 */
3882 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
3883
3884 /* reg_qeec_dwrr
3885 * Transmission selection algorithm to use on the link going down from
3886 * the ETS element.
3887 * 0 - Strict priority
3888 * 1 - DWRR
3889 * Access: RW
3890 */
3891 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
3892
3893 /* reg_qeec_dwrr_weight
3894 * DWRR weight on the link going down from the ETS element. The
3895 * percentage of bandwidth guaranteed to an ETS element within
3896 * its hierarchy. The sum of all weights across all ETS elements
3897 * within one hierarchy should be equal to 100. Reserved when
3898 * transmission selection algorithm is strict priority.
3899 * Access: RW
3900 */
3901 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3902
3903 /* reg_qeec_max_shaper_bs
3904 * Max shaper burst size
3905 * Burst size is 2^max_shaper_bs * 512 bits
3906 * For Spectrum-1: Range is: 5..25
3907 * For Spectrum-2: Range is: 11..25
3908 * Reserved when ptps = 1
3909 * Access: RW
3910 */
3911 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6);
3912
3913 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25
3914 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5
3915 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11
3916 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11
3917 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4 11
3918
mlxsw_reg_qeec_pack(char * payload,u16 local_port,enum mlxsw_reg_qeec_hr hr,u8 index,u8 next_index)3919 static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port,
3920 enum mlxsw_reg_qeec_hr hr, u8 index,
3921 u8 next_index)
3922 {
3923 MLXSW_REG_ZERO(qeec, payload);
3924 mlxsw_reg_qeec_local_port_set(payload, local_port);
3925 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3926 mlxsw_reg_qeec_element_index_set(payload, index);
3927 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3928 }
3929
mlxsw_reg_qeec_ptps_pack(char * payload,u16 local_port,bool ptps)3930 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port,
3931 bool ptps)
3932 {
3933 MLXSW_REG_ZERO(qeec, payload);
3934 mlxsw_reg_qeec_local_port_set(payload, local_port);
3935 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT);
3936 mlxsw_reg_qeec_ptps_set(payload, ptps);
3937 }
3938
3939 /* QRWE - QoS ReWrite Enable
3940 * -------------------------
3941 * This register configures the rewrite enable per receive port.
3942 */
3943 #define MLXSW_REG_QRWE_ID 0x400F
3944 #define MLXSW_REG_QRWE_LEN 0x08
3945
3946 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
3947
3948 /* reg_qrwe_local_port
3949 * Local port number.
3950 * Access: Index
3951 *
3952 * Note: CPU port is supported. No support for router port.
3953 */
3954 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12);
3955
3956 /* reg_qrwe_dscp
3957 * Whether to enable DSCP rewrite (default is 0, don't rewrite).
3958 * Access: RW
3959 */
3960 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3961
3962 /* reg_qrwe_pcp
3963 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
3964 * Access: RW
3965 */
3966 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3967
mlxsw_reg_qrwe_pack(char * payload,u16 local_port,bool rewrite_pcp,bool rewrite_dscp)3968 static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port,
3969 bool rewrite_pcp, bool rewrite_dscp)
3970 {
3971 MLXSW_REG_ZERO(qrwe, payload);
3972 mlxsw_reg_qrwe_local_port_set(payload, local_port);
3973 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3974 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3975 }
3976
3977 /* QPDSM - QoS Priority to DSCP Mapping
3978 * ------------------------------------
3979 * QoS Priority to DSCP Mapping Register
3980 */
3981 #define MLXSW_REG_QPDSM_ID 0x4011
3982 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */
3983 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */
3984 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
3985 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \
3986 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \
3987 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
3988
3989 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
3990
3991 /* reg_qpdsm_local_port
3992 * Local Port. Supported for data packets from CPU port.
3993 * Access: Index
3994 */
3995 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12);
3996
3997 /* reg_qpdsm_prio_entry_color0_e
3998 * Enable update of the entry for color 0 and a given port.
3999 * Access: WO
4000 */
4001 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
4002 MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
4003 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4004
4005 /* reg_qpdsm_prio_entry_color0_dscp
4006 * DSCP field in the outer label of the packet for color 0 and a given port.
4007 * Reserved when e=0.
4008 * Access: RW
4009 */
4010 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
4011 MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
4012 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4013
4014 /* reg_qpdsm_prio_entry_color1_e
4015 * Enable update of the entry for color 1 and a given port.
4016 * Access: WO
4017 */
4018 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
4019 MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
4020 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4021
4022 /* reg_qpdsm_prio_entry_color1_dscp
4023 * DSCP field in the outer label of the packet for color 1 and a given port.
4024 * Reserved when e=0.
4025 * Access: RW
4026 */
4027 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
4028 MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
4029 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4030
4031 /* reg_qpdsm_prio_entry_color2_e
4032 * Enable update of the entry for color 2 and a given port.
4033 * Access: WO
4034 */
4035 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
4036 MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
4037 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4038
4039 /* reg_qpdsm_prio_entry_color2_dscp
4040 * DSCP field in the outer label of the packet for color 2 and a given port.
4041 * Reserved when e=0.
4042 * Access: RW
4043 */
4044 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
4045 MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
4046 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4047
mlxsw_reg_qpdsm_pack(char * payload,u16 local_port)4048 static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port)
4049 {
4050 MLXSW_REG_ZERO(qpdsm, payload);
4051 mlxsw_reg_qpdsm_local_port_set(payload, local_port);
4052 }
4053
4054 static inline void
mlxsw_reg_qpdsm_prio_pack(char * payload,unsigned short prio,u8 dscp)4055 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
4056 {
4057 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
4058 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
4059 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
4060 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
4061 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
4062 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
4063 }
4064
4065 /* QPDP - QoS Port DSCP to Priority Mapping Register
4066 * -------------------------------------------------
4067 * This register controls the port default Switch Priority and Color. The
4068 * default Switch Priority and Color are used for frames where the trust state
4069 * uses default values. All member ports of a LAG should be configured with the
4070 * same default values.
4071 */
4072 #define MLXSW_REG_QPDP_ID 0x4007
4073 #define MLXSW_REG_QPDP_LEN 0x8
4074
4075 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN);
4076
4077 /* reg_qpdp_local_port
4078 * Local Port. Supported for data packets from CPU port.
4079 * Access: Index
4080 */
4081 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12);
4082
4083 /* reg_qpdp_switch_prio
4084 * Default port Switch Priority (default 0)
4085 * Access: RW
4086 */
4087 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4);
4088
mlxsw_reg_qpdp_pack(char * payload,u16 local_port,u8 switch_prio)4089 static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port,
4090 u8 switch_prio)
4091 {
4092 MLXSW_REG_ZERO(qpdp, payload);
4093 mlxsw_reg_qpdp_local_port_set(payload, local_port);
4094 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio);
4095 }
4096
4097 /* QPDPM - QoS Port DSCP to Priority Mapping Register
4098 * --------------------------------------------------
4099 * This register controls the mapping from DSCP field to
4100 * Switch Priority for IP packets.
4101 */
4102 #define MLXSW_REG_QPDPM_ID 0x4013
4103 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */
4104 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */
4105 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
4106 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \
4107 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \
4108 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
4109
4110 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
4111
4112 /* reg_qpdpm_local_port
4113 * Local Port. Supported for data packets from CPU port.
4114 * Access: Index
4115 */
4116 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12);
4117
4118 /* reg_qpdpm_dscp_e
4119 * Enable update of the specific entry. When cleared, the switch_prio and color
4120 * fields are ignored and the previous switch_prio and color values are
4121 * preserved.
4122 * Access: WO
4123 */
4124 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
4125 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4126
4127 /* reg_qpdpm_dscp_prio
4128 * The new Switch Priority value for the relevant DSCP value.
4129 * Access: RW
4130 */
4131 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
4132 MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
4133 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4134
mlxsw_reg_qpdpm_pack(char * payload,u16 local_port)4135 static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port)
4136 {
4137 MLXSW_REG_ZERO(qpdpm, payload);
4138 mlxsw_reg_qpdpm_local_port_set(payload, local_port);
4139 }
4140
4141 static inline void
mlxsw_reg_qpdpm_dscp_pack(char * payload,unsigned short dscp,u8 prio)4142 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
4143 {
4144 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
4145 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
4146 }
4147
4148 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register
4149 * ------------------------------------------------------------------
4150 * This register configures if the Switch Priority to Traffic Class mapping is
4151 * based on Multicast packet indication. If so, then multicast packets will get
4152 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by
4153 * QTCT.
4154 * By default, Switch Priority to Traffic Class mapping is not based on
4155 * Multicast packet indication.
4156 */
4157 #define MLXSW_REG_QTCTM_ID 0x401A
4158 #define MLXSW_REG_QTCTM_LEN 0x08
4159
4160 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
4161
4162 /* reg_qtctm_local_port
4163 * Local port number.
4164 * No support for CPU port.
4165 * Access: Index
4166 */
4167 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12);
4168
4169 /* reg_qtctm_mc
4170 * Multicast Mode
4171 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
4172 * indication (default is 0, not based on Multicast packet indication).
4173 */
4174 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
4175
4176 static inline void
mlxsw_reg_qtctm_pack(char * payload,u16 local_port,bool mc)4177 mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc)
4178 {
4179 MLXSW_REG_ZERO(qtctm, payload);
4180 mlxsw_reg_qtctm_local_port_set(payload, local_port);
4181 mlxsw_reg_qtctm_mc_set(payload, mc);
4182 }
4183
4184 /* QPSC - QoS PTP Shaper Configuration Register
4185 * --------------------------------------------
4186 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1.
4187 * Supported only on Spectrum-1.
4188 */
4189 #define MLXSW_REG_QPSC_ID 0x401B
4190 #define MLXSW_REG_QPSC_LEN 0x28
4191
4192 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN);
4193
4194 enum mlxsw_reg_qpsc_port_speed {
4195 MLXSW_REG_QPSC_PORT_SPEED_100M,
4196 MLXSW_REG_QPSC_PORT_SPEED_1G,
4197 MLXSW_REG_QPSC_PORT_SPEED_10G,
4198 MLXSW_REG_QPSC_PORT_SPEED_25G,
4199 };
4200
4201 /* reg_qpsc_port_speed
4202 * Port speed.
4203 * Access: Index
4204 */
4205 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4);
4206
4207 /* reg_qpsc_shaper_time_exp
4208 * The base-time-interval for updating the shapers tokens (for all hierarchies).
4209 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
4210 * shaper_rate = 64bit * shaper_inc / shaper_update_rate
4211 * Access: RW
4212 */
4213 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4);
4214
4215 /* reg_qpsc_shaper_time_mantissa
4216 * The base-time-interval for updating the shapers tokens (for all hierarchies).
4217 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
4218 * shaper_rate = 64bit * shaper_inc / shaper_update_rate
4219 * Access: RW
4220 */
4221 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5);
4222
4223 /* reg_qpsc_shaper_inc
4224 * Number of tokens added to shaper on each update.
4225 * Units of 8B.
4226 * Access: RW
4227 */
4228 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);
4229
4230 /* reg_qpsc_shaper_bs
4231 * Max shaper Burst size.
4232 * Burst size is 2 ^ max_shaper_bs * 512 [bits]
4233 * Range is: 5..25 (from 2KB..2GB)
4234 * Access: RW
4235 */
4236 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);
4237
4238 /* reg_qpsc_ptsc_we
4239 * Write enable to port_to_shaper_credits.
4240 * Access: WO
4241 */
4242 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);
4243
4244 /* reg_qpsc_port_to_shaper_credits
4245 * For split ports: range 1..57
4246 * For non-split ports: range 1..112
4247 * Written only when ptsc_we is set.
4248 * Access: RW
4249 */
4250 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);
4251
4252 /* reg_qpsc_ing_timestamp_inc
4253 * Ingress timestamp increment.
4254 * 2's complement.
4255 * The timestamp of MTPPTR at ingress will be incremented by this value. Global
4256 * value for all ports.
4257 * Same units as used by MTPPTR.
4258 * Access: RW
4259 */
4260 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);
4261
4262 /* reg_qpsc_egr_timestamp_inc
4263 * Egress timestamp increment.
4264 * 2's complement.
4265 * The timestamp of MTPPTR at egress will be incremented by this value. Global
4266 * value for all ports.
4267 * Same units as used by MTPPTR.
4268 * Access: RW
4269 */
4270 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);
4271
4272 static inline void
mlxsw_reg_qpsc_pack(char * payload,enum mlxsw_reg_qpsc_port_speed port_speed,u8 shaper_time_exp,u8 shaper_time_mantissa,u8 shaper_inc,u8 shaper_bs,u8 port_to_shaper_credits,int ing_timestamp_inc,int egr_timestamp_inc)4273 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed,
4274 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc,
4275 u8 shaper_bs, u8 port_to_shaper_credits,
4276 int ing_timestamp_inc, int egr_timestamp_inc)
4277 {
4278 MLXSW_REG_ZERO(qpsc, payload);
4279 mlxsw_reg_qpsc_port_speed_set(payload, port_speed);
4280 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp);
4281 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa);
4282 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc);
4283 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs);
4284 mlxsw_reg_qpsc_ptsc_we_set(payload, true);
4285 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits);
4286 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc);
4287 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc);
4288 }
4289
4290 /* PMLP - Ports Module to Local Port Register
4291 * ------------------------------------------
4292 * Configures the assignment of modules to local ports.
4293 */
4294 #define MLXSW_REG_PMLP_ID 0x5002
4295 #define MLXSW_REG_PMLP_LEN 0x40
4296
4297 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
4298
4299 /* reg_pmlp_rxtx
4300 * 0 - Tx value is used for both Tx and Rx.
4301 * 1 - Rx value is taken from a separte field.
4302 * Access: RW
4303 */
4304 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
4305
4306 /* reg_pmlp_local_port
4307 * Local port number.
4308 * Access: Index
4309 */
4310 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12);
4311
4312 /* reg_pmlp_width
4313 * 0 - Unmap local port.
4314 * 1 - Lane 0 is used.
4315 * 2 - Lanes 0 and 1 are used.
4316 * 4 - Lanes 0, 1, 2 and 3 are used.
4317 * 8 - Lanes 0-7 are used.
4318 * Access: RW
4319 */
4320 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
4321
4322 /* reg_pmlp_module
4323 * Module number.
4324 * Access: RW
4325 */
4326 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
4327
4328 /* reg_pmlp_slot_index
4329 * Module number.
4330 * Slot_index
4331 * Slot_index = 0 represent the onboard (motherboard).
4332 * In case of non-modular system only slot_index = 0 is available.
4333 * Access: RW
4334 */
4335 MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false);
4336
4337 /* reg_pmlp_tx_lane
4338 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
4339 * Access: RW
4340 */
4341 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false);
4342
4343 /* reg_pmlp_rx_lane
4344 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
4345 * equal to Tx lane.
4346 * Access: RW
4347 */
4348 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);
4349
mlxsw_reg_pmlp_pack(char * payload,u16 local_port)4350 static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port)
4351 {
4352 MLXSW_REG_ZERO(pmlp, payload);
4353 mlxsw_reg_pmlp_local_port_set(payload, local_port);
4354 }
4355
4356 /* PMTU - Port MTU Register
4357 * ------------------------
4358 * Configures and reports the port MTU.
4359 */
4360 #define MLXSW_REG_PMTU_ID 0x5003
4361 #define MLXSW_REG_PMTU_LEN 0x10
4362
4363 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
4364
4365 /* reg_pmtu_local_port
4366 * Local port number.
4367 * Access: Index
4368 */
4369 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12);
4370
4371 /* reg_pmtu_max_mtu
4372 * Maximum MTU.
4373 * When port type (e.g. Ethernet) is configured, the relevant MTU is
4374 * reported, otherwise the minimum between the max_mtu of the different
4375 * types is reported.
4376 * Access: RO
4377 */
4378 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
4379
4380 /* reg_pmtu_admin_mtu
4381 * MTU value to set port to. Must be smaller or equal to max_mtu.
4382 * Note: If port type is Infiniband, then port must be disabled, when its
4383 * MTU is set.
4384 * Access: RW
4385 */
4386 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
4387
4388 /* reg_pmtu_oper_mtu
4389 * The actual MTU configured on the port. Packets exceeding this size
4390 * will be dropped.
4391 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
4392 * oper_mtu might be smaller than admin_mtu.
4393 * Access: RO
4394 */
4395 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
4396
mlxsw_reg_pmtu_pack(char * payload,u16 local_port,u16 new_mtu)4397 static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port,
4398 u16 new_mtu)
4399 {
4400 MLXSW_REG_ZERO(pmtu, payload);
4401 mlxsw_reg_pmtu_local_port_set(payload, local_port);
4402 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
4403 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
4404 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
4405 }
4406
4407 /* PTYS - Port Type and Speed Register
4408 * -----------------------------------
4409 * Configures and reports the port speed type.
4410 *
4411 * Note: When set while the link is up, the changes will not take effect
4412 * until the port transitions from down to up state.
4413 */
4414 #define MLXSW_REG_PTYS_ID 0x5004
4415 #define MLXSW_REG_PTYS_LEN 0x40
4416
4417 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
4418
4419 /* an_disable_admin
4420 * Auto negotiation disable administrative configuration
4421 * 0 - Device doesn't support AN disable.
4422 * 1 - Device supports AN disable.
4423 * Access: RW
4424 */
4425 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
4426
4427 /* reg_ptys_local_port
4428 * Local port number.
4429 * Access: Index
4430 */
4431 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12);
4432
4433 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0)
4434 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
4435
4436 /* reg_ptys_proto_mask
4437 * Protocol mask. Indicates which protocol is used.
4438 * 0 - Infiniband.
4439 * 1 - Fibre Channel.
4440 * 2 - Ethernet.
4441 * Access: Index
4442 */
4443 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
4444
4445 enum {
4446 MLXSW_REG_PTYS_AN_STATUS_NA,
4447 MLXSW_REG_PTYS_AN_STATUS_OK,
4448 MLXSW_REG_PTYS_AN_STATUS_FAIL,
4449 };
4450
4451 /* reg_ptys_an_status
4452 * Autonegotiation status.
4453 * Access: RO
4454 */
4455 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
4456
4457 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0)
4458 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1)
4459 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3)
4460 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4)
4461 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5)
4462 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6)
4463 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7)
4464 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8)
4465 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9)
4466 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10)
4467 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12)
4468 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15)
4469
4470 /* reg_ptys_ext_eth_proto_cap
4471 * Extended Ethernet port supported speeds and protocols.
4472 * Access: RO
4473 */
4474 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
4475
4476 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
4477 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
4478 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
4479 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
4480 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
4481 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
4482 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
4483 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
4484 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
4485 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
4486 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
4487 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
4488 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18)
4489 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
4490 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
4491 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
4492 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
4493 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
4494 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(24)
4495 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T BIT(25)
4496 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
4497 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
4498 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
4499 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
4500 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
4501
4502 /* reg_ptys_eth_proto_cap
4503 * Ethernet port supported speeds and protocols.
4504 * Access: RO
4505 */
4506 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
4507
4508 /* reg_ptys_ib_link_width_cap
4509 * IB port supported widths.
4510 * Access: RO
4511 */
4512 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
4513
4514 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0)
4515 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1)
4516 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2)
4517 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3)
4518 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4)
4519 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5)
4520
4521 /* reg_ptys_ib_proto_cap
4522 * IB port supported speeds and protocols.
4523 * Access: RO
4524 */
4525 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
4526
4527 /* reg_ptys_ext_eth_proto_admin
4528 * Extended speed and protocol to set port to.
4529 * Access: RW
4530 */
4531 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4532
4533 /* reg_ptys_eth_proto_admin
4534 * Speed and protocol to set port to.
4535 * Access: RW
4536 */
4537 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
4538
4539 /* reg_ptys_ib_link_width_admin
4540 * IB width to set port to.
4541 * Access: RW
4542 */
4543 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
4544
4545 /* reg_ptys_ib_proto_admin
4546 * IB speeds and protocols to set port to.
4547 * Access: RW
4548 */
4549 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
4550
4551 /* reg_ptys_ext_eth_proto_oper
4552 * The extended current speed and protocol configured for the port.
4553 * Access: RO
4554 */
4555 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4556
4557 /* reg_ptys_eth_proto_oper
4558 * The current speed and protocol configured for the port.
4559 * Access: RO
4560 */
4561 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
4562
4563 /* reg_ptys_ib_link_width_oper
4564 * The current IB width to set port to.
4565 * Access: RO
4566 */
4567 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
4568
4569 /* reg_ptys_ib_proto_oper
4570 * The current IB speed and protocol.
4571 * Access: RO
4572 */
4573 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
4574
4575 enum mlxsw_reg_ptys_connector_type {
4576 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
4577 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
4578 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
4579 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
4580 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
4581 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
4582 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
4583 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
4584 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
4585 };
4586
4587 /* reg_ptys_connector_type
4588 * Connector type indication.
4589 * Access: RO
4590 */
4591 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4592
mlxsw_reg_ptys_eth_pack(char * payload,u16 local_port,u32 proto_admin,bool autoneg)4593 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port,
4594 u32 proto_admin, bool autoneg)
4595 {
4596 MLXSW_REG_ZERO(ptys, payload);
4597 mlxsw_reg_ptys_local_port_set(payload, local_port);
4598 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4599 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4600 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4601 }
4602
mlxsw_reg_ptys_ext_eth_pack(char * payload,u16 local_port,u32 proto_admin,bool autoneg)4603 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port,
4604 u32 proto_admin, bool autoneg)
4605 {
4606 MLXSW_REG_ZERO(ptys, payload);
4607 mlxsw_reg_ptys_local_port_set(payload, local_port);
4608 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4609 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4610 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4611 }
4612
mlxsw_reg_ptys_eth_unpack(char * payload,u32 * p_eth_proto_cap,u32 * p_eth_proto_admin,u32 * p_eth_proto_oper)4613 static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
4614 u32 *p_eth_proto_cap,
4615 u32 *p_eth_proto_admin,
4616 u32 *p_eth_proto_oper)
4617 {
4618 if (p_eth_proto_cap)
4619 *p_eth_proto_cap =
4620 mlxsw_reg_ptys_eth_proto_cap_get(payload);
4621 if (p_eth_proto_admin)
4622 *p_eth_proto_admin =
4623 mlxsw_reg_ptys_eth_proto_admin_get(payload);
4624 if (p_eth_proto_oper)
4625 *p_eth_proto_oper =
4626 mlxsw_reg_ptys_eth_proto_oper_get(payload);
4627 }
4628
mlxsw_reg_ptys_ext_eth_unpack(char * payload,u32 * p_eth_proto_cap,u32 * p_eth_proto_admin,u32 * p_eth_proto_oper)4629 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
4630 u32 *p_eth_proto_cap,
4631 u32 *p_eth_proto_admin,
4632 u32 *p_eth_proto_oper)
4633 {
4634 if (p_eth_proto_cap)
4635 *p_eth_proto_cap =
4636 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
4637 if (p_eth_proto_admin)
4638 *p_eth_proto_admin =
4639 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4640 if (p_eth_proto_oper)
4641 *p_eth_proto_oper =
4642 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4643 }
4644
mlxsw_reg_ptys_ib_pack(char * payload,u16 local_port,u16 proto_admin,u16 link_width)4645 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u16 local_port,
4646 u16 proto_admin, u16 link_width)
4647 {
4648 MLXSW_REG_ZERO(ptys, payload);
4649 mlxsw_reg_ptys_local_port_set(payload, local_port);
4650 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
4651 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
4652 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
4653 }
4654
mlxsw_reg_ptys_ib_unpack(char * payload,u16 * p_ib_proto_cap,u16 * p_ib_link_width_cap,u16 * p_ib_proto_oper,u16 * p_ib_link_width_oper)4655 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
4656 u16 *p_ib_link_width_cap,
4657 u16 *p_ib_proto_oper,
4658 u16 *p_ib_link_width_oper)
4659 {
4660 if (p_ib_proto_cap)
4661 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
4662 if (p_ib_link_width_cap)
4663 *p_ib_link_width_cap =
4664 mlxsw_reg_ptys_ib_link_width_cap_get(payload);
4665 if (p_ib_proto_oper)
4666 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
4667 if (p_ib_link_width_oper)
4668 *p_ib_link_width_oper =
4669 mlxsw_reg_ptys_ib_link_width_oper_get(payload);
4670 }
4671
4672 /* PPAD - Port Physical Address Register
4673 * -------------------------------------
4674 * The PPAD register configures the per port physical MAC address.
4675 */
4676 #define MLXSW_REG_PPAD_ID 0x5005
4677 #define MLXSW_REG_PPAD_LEN 0x10
4678
4679 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
4680
4681 /* reg_ppad_single_base_mac
4682 * 0: base_mac, local port should be 0 and mac[7:0] is
4683 * reserved. HW will set incremental
4684 * 1: single_mac - mac of the local_port
4685 * Access: RW
4686 */
4687 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
4688
4689 /* reg_ppad_local_port
4690 * port number, if single_base_mac = 0 then local_port is reserved
4691 * Access: RW
4692 */
4693 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24);
4694
4695 /* reg_ppad_mac
4696 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
4697 * If single_base_mac = 1 - the per port MAC address
4698 * Access: RW
4699 */
4700 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4701
mlxsw_reg_ppad_pack(char * payload,bool single_base_mac,u16 local_port)4702 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4703 u16 local_port)
4704 {
4705 MLXSW_REG_ZERO(ppad, payload);
4706 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4707 mlxsw_reg_ppad_local_port_set(payload, local_port);
4708 }
4709
4710 /* PAOS - Ports Administrative and Operational Status Register
4711 * -----------------------------------------------------------
4712 * Configures and retrieves per port administrative and operational status.
4713 */
4714 #define MLXSW_REG_PAOS_ID 0x5006
4715 #define MLXSW_REG_PAOS_LEN 0x10
4716
4717 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
4718
4719 /* reg_paos_swid
4720 * Switch partition ID with which to associate the port.
4721 * Note: while external ports uses unique local port numbers (and thus swid is
4722 * redundant), router ports use the same local port number where swid is the
4723 * only indication for the relevant port.
4724 * Access: Index
4725 */
4726 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
4727
4728 /* reg_paos_local_port
4729 * Local port number.
4730 * Access: Index
4731 */
4732 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12);
4733
4734 /* reg_paos_admin_status
4735 * Port administrative state (the desired state of the port):
4736 * 1 - Up.
4737 * 2 - Down.
4738 * 3 - Up once. This means that in case of link failure, the port won't go
4739 * into polling mode, but will wait to be re-enabled by software.
4740 * 4 - Disabled by system. Can only be set by hardware.
4741 * Access: RW
4742 */
4743 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
4744
4745 /* reg_paos_oper_status
4746 * Port operational state (the current state):
4747 * 1 - Up.
4748 * 2 - Down.
4749 * 3 - Down by port failure. This means that the device will not let the
4750 * port up again until explicitly specified by software.
4751 * Access: RO
4752 */
4753 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4754
4755 /* reg_paos_ase
4756 * Admin state update enabled.
4757 * Access: WO
4758 */
4759 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4760
4761 /* reg_paos_ee
4762 * Event update enable. If this bit is set, event generation will be
4763 * updated based on the e field.
4764 * Access: WO
4765 */
4766 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4767
4768 /* reg_paos_e
4769 * Event generation on operational state change:
4770 * 0 - Do not generate event.
4771 * 1 - Generate Event.
4772 * 2 - Generate Single Event.
4773 * Access: RW
4774 */
4775 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4776
mlxsw_reg_paos_pack(char * payload,u16 local_port,enum mlxsw_port_admin_status status)4777 static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port,
4778 enum mlxsw_port_admin_status status)
4779 {
4780 MLXSW_REG_ZERO(paos, payload);
4781 mlxsw_reg_paos_swid_set(payload, 0);
4782 mlxsw_reg_paos_local_port_set(payload, local_port);
4783 mlxsw_reg_paos_admin_status_set(payload, status);
4784 mlxsw_reg_paos_oper_status_set(payload, 0);
4785 mlxsw_reg_paos_ase_set(payload, 1);
4786 mlxsw_reg_paos_ee_set(payload, 1);
4787 mlxsw_reg_paos_e_set(payload, 1);
4788 }
4789
4790 /* PFCC - Ports Flow Control Configuration Register
4791 * ------------------------------------------------
4792 * Configures and retrieves the per port flow control configuration.
4793 */
4794 #define MLXSW_REG_PFCC_ID 0x5007
4795 #define MLXSW_REG_PFCC_LEN 0x20
4796
4797 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
4798
4799 /* reg_pfcc_local_port
4800 * Local port number.
4801 * Access: Index
4802 */
4803 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12);
4804
4805 /* reg_pfcc_pnat
4806 * Port number access type. Determines the way local_port is interpreted:
4807 * 0 - Local port number.
4808 * 1 - IB / label port number.
4809 * Access: Index
4810 */
4811 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4812
4813 /* reg_pfcc_shl_cap
4814 * Send to higher layers capabilities:
4815 * 0 - No capability of sending Pause and PFC frames to higher layers.
4816 * 1 - Device has capability of sending Pause and PFC frames to higher
4817 * layers.
4818 * Access: RO
4819 */
4820 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4821
4822 /* reg_pfcc_shl_opr
4823 * Send to higher layers operation:
4824 * 0 - Pause and PFC frames are handled by the port (default).
4825 * 1 - Pause and PFC frames are handled by the port and also sent to
4826 * higher layers. Only valid if shl_cap = 1.
4827 * Access: RW
4828 */
4829 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4830
4831 /* reg_pfcc_ppan
4832 * Pause policy auto negotiation.
4833 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
4834 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
4835 * based on the auto-negotiation resolution.
4836 * Access: RW
4837 *
4838 * Note: The auto-negotiation advertisement is set according to pptx and
4839 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
4840 */
4841 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4842
4843 /* reg_pfcc_prio_mask_tx
4844 * Bit per priority indicating if Tx flow control policy should be
4845 * updated based on bit pfctx.
4846 * Access: WO
4847 */
4848 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4849
4850 /* reg_pfcc_prio_mask_rx
4851 * Bit per priority indicating if Rx flow control policy should be
4852 * updated based on bit pfcrx.
4853 * Access: WO
4854 */
4855 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4856
4857 /* reg_pfcc_pptx
4858 * Admin Pause policy on Tx.
4859 * 0 - Never generate Pause frames (default).
4860 * 1 - Generate Pause frames according to Rx buffer threshold.
4861 * Access: RW
4862 */
4863 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4864
4865 /* reg_pfcc_aptx
4866 * Active (operational) Pause policy on Tx.
4867 * 0 - Never generate Pause frames.
4868 * 1 - Generate Pause frames according to Rx buffer threshold.
4869 * Access: RO
4870 */
4871 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4872
4873 /* reg_pfcc_pfctx
4874 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
4875 * 0 - Never generate priority Pause frames on the specified priority
4876 * (default).
4877 * 1 - Generate priority Pause frames according to Rx buffer threshold on
4878 * the specified priority.
4879 * Access: RW
4880 *
4881 * Note: pfctx and pptx must be mutually exclusive.
4882 */
4883 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4884
4885 /* reg_pfcc_pprx
4886 * Admin Pause policy on Rx.
4887 * 0 - Ignore received Pause frames (default).
4888 * 1 - Respect received Pause frames.
4889 * Access: RW
4890 */
4891 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4892
4893 /* reg_pfcc_aprx
4894 * Active (operational) Pause policy on Rx.
4895 * 0 - Ignore received Pause frames.
4896 * 1 - Respect received Pause frames.
4897 * Access: RO
4898 */
4899 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4900
4901 /* reg_pfcc_pfcrx
4902 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
4903 * 0 - Ignore incoming priority Pause frames on the specified priority
4904 * (default).
4905 * 1 - Respect incoming priority Pause frames on the specified priority.
4906 * Access: RW
4907 */
4908 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4909
4910 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4911
mlxsw_reg_pfcc_prio_pack(char * payload,u8 pfc_en)4912 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4913 {
4914 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4915 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4916 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4917 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4918 }
4919
mlxsw_reg_pfcc_pack(char * payload,u16 local_port)4920 static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port)
4921 {
4922 MLXSW_REG_ZERO(pfcc, payload);
4923 mlxsw_reg_pfcc_local_port_set(payload, local_port);
4924 }
4925
4926 /* PPCNT - Ports Performance Counters Register
4927 * -------------------------------------------
4928 * The PPCNT register retrieves per port performance counters.
4929 */
4930 #define MLXSW_REG_PPCNT_ID 0x5008
4931 #define MLXSW_REG_PPCNT_LEN 0x100
4932 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
4933
4934 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
4935
4936 /* reg_ppcnt_swid
4937 * For HCA: must be always 0.
4938 * Switch partition ID to associate port with.
4939 * Switch partitions are numbered from 0 to 7 inclusively.
4940 * Switch partition 254 indicates stacking ports.
4941 * Switch partition 255 indicates all switch partitions.
4942 * Only valid on Set() operation with local_port=255.
4943 * Access: Index
4944 */
4945 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
4946
4947 /* reg_ppcnt_local_port
4948 * Local port number.
4949 * Access: Index
4950 */
4951 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12);
4952
4953 /* reg_ppcnt_pnat
4954 * Port number access type:
4955 * 0 - Local port number
4956 * 1 - IB port number
4957 * Access: Index
4958 */
4959 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
4960
4961 enum mlxsw_reg_ppcnt_grp {
4962 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
4963 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,
4964 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
4965 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,
4966 MLXSW_REG_PPCNT_EXT_CNT = 0x5,
4967 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,
4968 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4969 MLXSW_REG_PPCNT_TC_CNT = 0x11,
4970 MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13,
4971 };
4972
4973 /* reg_ppcnt_grp
4974 * Performance counter group.
4975 * Group 63 indicates all groups. Only valid on Set() operation with
4976 * clr bit set.
4977 * 0x0: IEEE 802.3 Counters
4978 * 0x1: RFC 2863 Counters
4979 * 0x2: RFC 2819 Counters
4980 * 0x3: RFC 3635 Counters
4981 * 0x5: Ethernet Extended Counters
4982 * 0x6: Ethernet Discard Counters
4983 * 0x8: Link Level Retransmission Counters
4984 * 0x10: Per Priority Counters
4985 * 0x11: Per Traffic Class Counters
4986 * 0x12: Physical Layer Counters
4987 * 0x13: Per Traffic Class Congestion Counters
4988 * Access: Index
4989 */
4990 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
4991
4992 /* reg_ppcnt_clr
4993 * Clear counters. Setting the clr bit will reset the counter value
4994 * for all counters in the counter group. This bit can be set
4995 * for both Set() and Get() operation.
4996 * Access: OP
4997 */
4998 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
4999
5000 /* reg_ppcnt_lp_gl
5001 * Local port global variable.
5002 * 0: local_port 255 = all ports of the device.
5003 * 1: local_port indicates local port number for all ports.
5004 * Access: OP
5005 */
5006 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1);
5007
5008 /* reg_ppcnt_prio_tc
5009 * Priority for counter set that support per priority, valid values: 0-7.
5010 * Traffic class for counter set that support per traffic class,
5011 * valid values: 0- cap_max_tclass-1 .
5012 * For HCA: cap_max_tclass is always 8.
5013 * Otherwise must be 0.
5014 * Access: Index
5015 */
5016 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
5017
5018 /* Ethernet IEEE 802.3 Counter Group */
5019
5020 /* reg_ppcnt_a_frames_transmitted_ok
5021 * Access: RO
5022 */
5023 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
5024 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5025
5026 /* reg_ppcnt_a_frames_received_ok
5027 * Access: RO
5028 */
5029 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
5030 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5031
5032 /* reg_ppcnt_a_frame_check_sequence_errors
5033 * Access: RO
5034 */
5035 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
5036 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5037
5038 /* reg_ppcnt_a_alignment_errors
5039 * Access: RO
5040 */
5041 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
5042 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
5043
5044 /* reg_ppcnt_a_octets_transmitted_ok
5045 * Access: RO
5046 */
5047 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
5048 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5049
5050 /* reg_ppcnt_a_octets_received_ok
5051 * Access: RO
5052 */
5053 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
5054 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5055
5056 /* reg_ppcnt_a_multicast_frames_xmitted_ok
5057 * Access: RO
5058 */
5059 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
5060 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5061
5062 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
5063 * Access: RO
5064 */
5065 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
5066 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5067
5068 /* reg_ppcnt_a_multicast_frames_received_ok
5069 * Access: RO
5070 */
5071 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
5072 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5073
5074 /* reg_ppcnt_a_broadcast_frames_received_ok
5075 * Access: RO
5076 */
5077 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
5078 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5079
5080 /* reg_ppcnt_a_in_range_length_errors
5081 * Access: RO
5082 */
5083 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
5084 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5085
5086 /* reg_ppcnt_a_out_of_range_length_field
5087 * Access: RO
5088 */
5089 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
5090 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5091
5092 /* reg_ppcnt_a_frame_too_long_errors
5093 * Access: RO
5094 */
5095 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
5096 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5097
5098 /* reg_ppcnt_a_symbol_error_during_carrier
5099 * Access: RO
5100 */
5101 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
5102 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5103
5104 /* reg_ppcnt_a_mac_control_frames_transmitted
5105 * Access: RO
5106 */
5107 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
5108 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5109
5110 /* reg_ppcnt_a_mac_control_frames_received
5111 * Access: RO
5112 */
5113 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
5114 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
5115
5116 /* reg_ppcnt_a_unsupported_opcodes_received
5117 * Access: RO
5118 */
5119 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
5120 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
5121
5122 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
5123 * Access: RO
5124 */
5125 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
5126 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
5127
5128 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
5129 * Access: RO
5130 */
5131 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
5132 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
5133
5134 /* Ethernet RFC 2863 Counter Group */
5135
5136 /* reg_ppcnt_if_in_discards
5137 * Access: RO
5138 */
5139 MLXSW_ITEM64(reg, ppcnt, if_in_discards,
5140 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5141
5142 /* reg_ppcnt_if_out_discards
5143 * Access: RO
5144 */
5145 MLXSW_ITEM64(reg, ppcnt, if_out_discards,
5146 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5147
5148 /* reg_ppcnt_if_out_errors
5149 * Access: RO
5150 */
5151 MLXSW_ITEM64(reg, ppcnt, if_out_errors,
5152 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5153
5154 /* Ethernet RFC 2819 Counter Group */
5155
5156 /* reg_ppcnt_ether_stats_undersize_pkts
5157 * Access: RO
5158 */
5159 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
5160 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5161
5162 /* reg_ppcnt_ether_stats_oversize_pkts
5163 * Access: RO
5164 */
5165 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
5166 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5167
5168 /* reg_ppcnt_ether_stats_fragments
5169 * Access: RO
5170 */
5171 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
5172 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5173
5174 /* reg_ppcnt_ether_stats_pkts64octets
5175 * Access: RO
5176 */
5177 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
5178 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5179
5180 /* reg_ppcnt_ether_stats_pkts65to127octets
5181 * Access: RO
5182 */
5183 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
5184 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5185
5186 /* reg_ppcnt_ether_stats_pkts128to255octets
5187 * Access: RO
5188 */
5189 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
5190 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5191
5192 /* reg_ppcnt_ether_stats_pkts256to511octets
5193 * Access: RO
5194 */
5195 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
5196 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5197
5198 /* reg_ppcnt_ether_stats_pkts512to1023octets
5199 * Access: RO
5200 */
5201 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
5202 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
5203
5204 /* reg_ppcnt_ether_stats_pkts1024to1518octets
5205 * Access: RO
5206 */
5207 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
5208 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
5209
5210 /* reg_ppcnt_ether_stats_pkts1519to2047octets
5211 * Access: RO
5212 */
5213 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
5214 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
5215
5216 /* reg_ppcnt_ether_stats_pkts2048to4095octets
5217 * Access: RO
5218 */
5219 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
5220 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
5221
5222 /* reg_ppcnt_ether_stats_pkts4096to8191octets
5223 * Access: RO
5224 */
5225 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
5226 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
5227
5228 /* reg_ppcnt_ether_stats_pkts8192to10239octets
5229 * Access: RO
5230 */
5231 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
5232 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
5233
5234 /* Ethernet RFC 3635 Counter Group */
5235
5236 /* reg_ppcnt_dot3stats_fcs_errors
5237 * Access: RO
5238 */
5239 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
5240 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5241
5242 /* reg_ppcnt_dot3stats_symbol_errors
5243 * Access: RO
5244 */
5245 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,
5246 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5247
5248 /* reg_ppcnt_dot3control_in_unknown_opcodes
5249 * Access: RO
5250 */
5251 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,
5252 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5253
5254 /* reg_ppcnt_dot3in_pause_frames
5255 * Access: RO
5256 */
5257 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,
5258 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5259
5260 /* Ethernet Extended Counter Group Counters */
5261
5262 /* reg_ppcnt_ecn_marked
5263 * Access: RO
5264 */
5265 MLXSW_ITEM64(reg, ppcnt, ecn_marked,
5266 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5267
5268 /* Ethernet Discard Counter Group Counters */
5269
5270 /* reg_ppcnt_ingress_general
5271 * Access: RO
5272 */
5273 MLXSW_ITEM64(reg, ppcnt, ingress_general,
5274 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5275
5276 /* reg_ppcnt_ingress_policy_engine
5277 * Access: RO
5278 */
5279 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,
5280 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5281
5282 /* reg_ppcnt_ingress_vlan_membership
5283 * Access: RO
5284 */
5285 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,
5286 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5287
5288 /* reg_ppcnt_ingress_tag_frame_type
5289 * Access: RO
5290 */
5291 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,
5292 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
5293
5294 /* reg_ppcnt_egress_vlan_membership
5295 * Access: RO
5296 */
5297 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,
5298 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5299
5300 /* reg_ppcnt_loopback_filter
5301 * Access: RO
5302 */
5303 MLXSW_ITEM64(reg, ppcnt, loopback_filter,
5304 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5305
5306 /* reg_ppcnt_egress_general
5307 * Access: RO
5308 */
5309 MLXSW_ITEM64(reg, ppcnt, egress_general,
5310 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5311
5312 /* reg_ppcnt_egress_hoq
5313 * Access: RO
5314 */
5315 MLXSW_ITEM64(reg, ppcnt, egress_hoq,
5316 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5317
5318 /* reg_ppcnt_egress_policy_engine
5319 * Access: RO
5320 */
5321 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,
5322 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5323
5324 /* reg_ppcnt_ingress_tx_link_down
5325 * Access: RO
5326 */
5327 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,
5328 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5329
5330 /* reg_ppcnt_egress_stp_filter
5331 * Access: RO
5332 */
5333 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,
5334 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5335
5336 /* reg_ppcnt_egress_sll
5337 * Access: RO
5338 */
5339 MLXSW_ITEM64(reg, ppcnt, egress_sll,
5340 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5341
5342 /* Ethernet Per Priority Group Counters */
5343
5344 /* reg_ppcnt_rx_octets
5345 * Access: RO
5346 */
5347 MLXSW_ITEM64(reg, ppcnt, rx_octets,
5348 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5349
5350 /* reg_ppcnt_rx_frames
5351 * Access: RO
5352 */
5353 MLXSW_ITEM64(reg, ppcnt, rx_frames,
5354 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5355
5356 /* reg_ppcnt_tx_octets
5357 * Access: RO
5358 */
5359 MLXSW_ITEM64(reg, ppcnt, tx_octets,
5360 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5361
5362 /* reg_ppcnt_tx_frames
5363 * Access: RO
5364 */
5365 MLXSW_ITEM64(reg, ppcnt, tx_frames,
5366 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5367
5368 /* reg_ppcnt_rx_pause
5369 * Access: RO
5370 */
5371 MLXSW_ITEM64(reg, ppcnt, rx_pause,
5372 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5373
5374 /* reg_ppcnt_rx_pause_duration
5375 * Access: RO
5376 */
5377 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
5378 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5379
5380 /* reg_ppcnt_tx_pause
5381 * Access: RO
5382 */
5383 MLXSW_ITEM64(reg, ppcnt, tx_pause,
5384 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5385
5386 /* reg_ppcnt_tx_pause_duration
5387 * Access: RO
5388 */
5389 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
5390 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5391
5392 /* reg_ppcnt_rx_pause_transition
5393 * Access: RO
5394 */
5395 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
5396 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5397
5398 /* Ethernet Per Traffic Class Counters */
5399
5400 /* reg_ppcnt_tc_transmit_queue
5401 * Contains the transmit queue depth in cells of traffic class
5402 * selected by prio_tc and the port selected by local_port.
5403 * The field cannot be cleared.
5404 * Access: RO
5405 */
5406 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
5407 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5408
5409 /* reg_ppcnt_tc_no_buffer_discard_uc
5410 * The number of unicast packets dropped due to lack of shared
5411 * buffer resources.
5412 * Access: RO
5413 */
5414 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
5415 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5416
5417 /* Ethernet Per Traffic Class Congestion Group Counters */
5418
5419 /* reg_ppcnt_wred_discard
5420 * Access: RO
5421 */
5422 MLXSW_ITEM64(reg, ppcnt, wred_discard,
5423 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5424
5425 /* reg_ppcnt_ecn_marked_tc
5426 * Access: RO
5427 */
5428 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc,
5429 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5430
mlxsw_reg_ppcnt_pack(char * payload,u16 local_port,enum mlxsw_reg_ppcnt_grp grp,u8 prio_tc)5431 static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port,
5432 enum mlxsw_reg_ppcnt_grp grp,
5433 u8 prio_tc)
5434 {
5435 MLXSW_REG_ZERO(ppcnt, payload);
5436 mlxsw_reg_ppcnt_swid_set(payload, 0);
5437 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
5438 mlxsw_reg_ppcnt_pnat_set(payload, 0);
5439 mlxsw_reg_ppcnt_grp_set(payload, grp);
5440 mlxsw_reg_ppcnt_clr_set(payload, 0);
5441 mlxsw_reg_ppcnt_lp_gl_set(payload, 1);
5442 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
5443 }
5444
5445 /* PLIB - Port Local to InfiniBand Port
5446 * ------------------------------------
5447 * The PLIB register performs mapping from Local Port into InfiniBand Port.
5448 */
5449 #define MLXSW_REG_PLIB_ID 0x500A
5450 #define MLXSW_REG_PLIB_LEN 0x10
5451
5452 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
5453
5454 /* reg_plib_local_port
5455 * Local port number.
5456 * Access: Index
5457 */
5458 MLXSW_ITEM32_LP(reg, plib, 0x00, 16, 0x00, 12);
5459
5460 /* reg_plib_ib_port
5461 * InfiniBand port remapping for local_port.
5462 * Access: RW
5463 */
5464 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
5465
5466 /* PPTB - Port Prio To Buffer Register
5467 * -----------------------------------
5468 * Configures the switch priority to buffer table.
5469 */
5470 #define MLXSW_REG_PPTB_ID 0x500B
5471 #define MLXSW_REG_PPTB_LEN 0x10
5472
5473 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
5474
5475 enum {
5476 MLXSW_REG_PPTB_MM_UM,
5477 MLXSW_REG_PPTB_MM_UNICAST,
5478 MLXSW_REG_PPTB_MM_MULTICAST,
5479 };
5480
5481 /* reg_pptb_mm
5482 * Mapping mode.
5483 * 0 - Map both unicast and multicast packets to the same buffer.
5484 * 1 - Map only unicast packets.
5485 * 2 - Map only multicast packets.
5486 * Access: Index
5487 *
5488 * Note: SwitchX-2 only supports the first option.
5489 */
5490 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
5491
5492 /* reg_pptb_local_port
5493 * Local port number.
5494 * Access: Index
5495 */
5496 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12);
5497
5498 /* reg_pptb_um
5499 * Enables the update of the untagged_buf field.
5500 * Access: RW
5501 */
5502 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
5503
5504 /* reg_pptb_pm
5505 * Enables the update of the prio_to_buff field.
5506 * Bit <i> is a flag for updating the mapping for switch priority <i>.
5507 * Access: RW
5508 */
5509 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
5510
5511 /* reg_pptb_prio_to_buff
5512 * Mapping of switch priority <i> to one of the allocated receive port
5513 * buffers.
5514 * Access: RW
5515 */
5516 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
5517
5518 /* reg_pptb_pm_msb
5519 * Enables the update of the prio_to_buff field.
5520 * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
5521 * Access: RW
5522 */
5523 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
5524
5525 /* reg_pptb_untagged_buff
5526 * Mapping of untagged frames to one of the allocated receive port buffers.
5527 * Access: RW
5528 *
5529 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
5530 * Spectrum, as it maps untagged packets based on the default switch priority.
5531 */
5532 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
5533
5534 /* reg_pptb_prio_to_buff_msb
5535 * Mapping of switch priority <i+8> to one of the allocated receive port
5536 * buffers.
5537 * Access: RW
5538 */
5539 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5540
5541 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
5542
mlxsw_reg_pptb_pack(char * payload,u16 local_port)5543 static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port)
5544 {
5545 MLXSW_REG_ZERO(pptb, payload);
5546 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
5547 mlxsw_reg_pptb_local_port_set(payload, local_port);
5548 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5549 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5550 }
5551
mlxsw_reg_pptb_prio_to_buff_pack(char * payload,u8 prio,u8 buff)5552 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
5553 u8 buff)
5554 {
5555 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
5556 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
5557 }
5558
5559 /* PBMC - Port Buffer Management Control Register
5560 * ----------------------------------------------
5561 * The PBMC register configures and retrieves the port packet buffer
5562 * allocation for different Prios, and the Pause threshold management.
5563 */
5564 #define MLXSW_REG_PBMC_ID 0x500C
5565 #define MLXSW_REG_PBMC_LEN 0x6C
5566
5567 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
5568
5569 /* reg_pbmc_local_port
5570 * Local port number.
5571 * Access: Index
5572 */
5573 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12);
5574
5575 /* reg_pbmc_xoff_timer_value
5576 * When device generates a pause frame, it uses this value as the pause
5577 * timer (time for the peer port to pause in quota-512 bit time).
5578 * Access: RW
5579 */
5580 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
5581
5582 /* reg_pbmc_xoff_refresh
5583 * The time before a new pause frame should be sent to refresh the pause RW
5584 * state. Using the same units as xoff_timer_value above (in quota-512 bit
5585 * time).
5586 * Access: RW
5587 */
5588 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
5589
5590 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
5591
5592 /* reg_pbmc_buf_lossy
5593 * The field indicates if the buffer is lossy.
5594 * 0 - Lossless
5595 * 1 - Lossy
5596 * Access: RW
5597 */
5598 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
5599
5600 /* reg_pbmc_buf_epsb
5601 * Eligible for Port Shared buffer.
5602 * If epsb is set, packets assigned to buffer are allowed to insert the port
5603 * shared buffer.
5604 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
5605 * Access: RW
5606 */
5607 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
5608
5609 /* reg_pbmc_buf_size
5610 * The part of the packet buffer array is allocated for the specific buffer.
5611 * Units are represented in cells.
5612 * Access: RW
5613 */
5614 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
5615
5616 /* reg_pbmc_buf_xoff_threshold
5617 * Once the amount of data in the buffer goes above this value, device
5618 * starts sending PFC frames for all priorities associated with the
5619 * buffer. Units are represented in cells. Reserved in case of lossy
5620 * buffer.
5621 * Access: RW
5622 *
5623 * Note: In Spectrum, reserved for buffer[9].
5624 */
5625 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
5626 0x08, 0x04, false);
5627
5628 /* reg_pbmc_buf_xon_threshold
5629 * When the amount of data in the buffer goes below this value, device
5630 * stops sending PFC frames for the priorities associated with the
5631 * buffer. Units are represented in cells. Reserved in case of lossy
5632 * buffer.
5633 * Access: RW
5634 *
5635 * Note: In Spectrum, reserved for buffer[9].
5636 */
5637 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5638 0x08, 0x04, false);
5639
mlxsw_reg_pbmc_pack(char * payload,u16 local_port,u16 xoff_timer_value,u16 xoff_refresh)5640 static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port,
5641 u16 xoff_timer_value, u16 xoff_refresh)
5642 {
5643 MLXSW_REG_ZERO(pbmc, payload);
5644 mlxsw_reg_pbmc_local_port_set(payload, local_port);
5645 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
5646 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
5647 }
5648
mlxsw_reg_pbmc_lossy_buffer_pack(char * payload,int buf_index,u16 size)5649 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
5650 int buf_index,
5651 u16 size)
5652 {
5653 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
5654 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5655 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5656 }
5657
mlxsw_reg_pbmc_lossless_buffer_pack(char * payload,int buf_index,u16 size,u16 threshold)5658 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
5659 int buf_index, u16 size,
5660 u16 threshold)
5661 {
5662 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
5663 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5664 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5665 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
5666 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
5667 }
5668
5669 /* PSPA - Port Switch Partition Allocation
5670 * ---------------------------------------
5671 * Controls the association of a port with a switch partition and enables
5672 * configuring ports as stacking ports.
5673 */
5674 #define MLXSW_REG_PSPA_ID 0x500D
5675 #define MLXSW_REG_PSPA_LEN 0x8
5676
5677 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
5678
5679 /* reg_pspa_swid
5680 * Switch partition ID.
5681 * Access: RW
5682 */
5683 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
5684
5685 /* reg_pspa_local_port
5686 * Local port number.
5687 * Access: Index
5688 */
5689 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0);
5690
5691 /* reg_pspa_sub_port
5692 * Virtual port within the local port. Set to 0 when virtual ports are
5693 * disabled on the local port.
5694 * Access: Index
5695 */
5696 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5697
mlxsw_reg_pspa_pack(char * payload,u8 swid,u16 local_port)5698 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port)
5699 {
5700 MLXSW_REG_ZERO(pspa, payload);
5701 mlxsw_reg_pspa_swid_set(payload, swid);
5702 mlxsw_reg_pspa_local_port_set(payload, local_port);
5703 mlxsw_reg_pspa_sub_port_set(payload, 0);
5704 }
5705
5706 /* PMAOS - Ports Module Administrative and Operational Status
5707 * ----------------------------------------------------------
5708 * This register configures and retrieves the per module status.
5709 */
5710 #define MLXSW_REG_PMAOS_ID 0x5012
5711 #define MLXSW_REG_PMAOS_LEN 0x10
5712
5713 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN);
5714
5715 /* reg_pmaos_rst
5716 * Module reset toggle.
5717 * Note: Setting reset while module is plugged-in will result in transition to
5718 * "initializing" operational state.
5719 * Access: OP
5720 */
5721 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1);
5722
5723 /* reg_pmaos_slot_index
5724 * Slot index.
5725 * Access: Index
5726 */
5727 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4);
5728
5729 /* reg_pmaos_module
5730 * Module number.
5731 * Access: Index
5732 */
5733 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8);
5734
5735 enum mlxsw_reg_pmaos_admin_status {
5736 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1,
5737 MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2,
5738 /* If the module is active and then unplugged, or experienced an error
5739 * event, the operational status should go to "disabled" and can only
5740 * be enabled upon explicit enable command.
5741 */
5742 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3,
5743 };
5744
5745 /* reg_pmaos_admin_status
5746 * Module administrative state (the desired state of the module).
5747 * Note: To disable a module, all ports associated with the port must be
5748 * administatively down first.
5749 * Access: RW
5750 */
5751 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4);
5752
5753 /* reg_pmaos_ase
5754 * Admin state update enable.
5755 * If this bit is set, admin state will be updated based on admin_state field.
5756 * Only relevant on Set() operations.
5757 * Access: WO
5758 */
5759 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1);
5760
5761 /* reg_pmaos_ee
5762 * Event update enable.
5763 * If this bit is set, event generation will be updated based on the e field.
5764 * Only relevant on Set operations.
5765 * Access: WO
5766 */
5767 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1);
5768
5769 enum mlxsw_reg_pmaos_e {
5770 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT,
5771 MLXSW_REG_PMAOS_E_GENERATE_EVENT,
5772 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT,
5773 };
5774
5775 /* reg_pmaos_e
5776 * Event Generation on operational state change.
5777 * Access: RW
5778 */
5779 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2);
5780
mlxsw_reg_pmaos_pack(char * payload,u8 slot_index,u8 module)5781 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 slot_index, u8 module)
5782 {
5783 MLXSW_REG_ZERO(pmaos, payload);
5784 mlxsw_reg_pmaos_slot_index_set(payload, slot_index);
5785 mlxsw_reg_pmaos_module_set(payload, module);
5786 }
5787
5788 /* PPLR - Port Physical Loopback Register
5789 * --------------------------------------
5790 * This register allows configuration of the port's loopback mode.
5791 */
5792 #define MLXSW_REG_PPLR_ID 0x5018
5793 #define MLXSW_REG_PPLR_LEN 0x8
5794
5795 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN);
5796
5797 /* reg_pplr_local_port
5798 * Local port number.
5799 * Access: Index
5800 */
5801 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12);
5802
5803 /* Phy local loopback. When set the port's egress traffic is looped back
5804 * to the receiver and the port transmitter is disabled.
5805 */
5806 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
5807
5808 /* reg_pplr_lb_en
5809 * Loopback enable.
5810 * Access: RW
5811 */
5812 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
5813
mlxsw_reg_pplr_pack(char * payload,u16 local_port,bool phy_local)5814 static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port,
5815 bool phy_local)
5816 {
5817 MLXSW_REG_ZERO(pplr, payload);
5818 mlxsw_reg_pplr_local_port_set(payload, local_port);
5819 mlxsw_reg_pplr_lb_en_set(payload,
5820 phy_local ?
5821 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
5822 }
5823
5824 /* PMTDB - Port Module To local DataBase Register
5825 * ----------------------------------------------
5826 * The PMTDB register allows to query the possible module<->local port
5827 * mapping than can be used in PMLP. It does not represent the actual/current
5828 * mapping of the local to module. Actual mapping is only defined by PMLP.
5829 */
5830 #define MLXSW_REG_PMTDB_ID 0x501A
5831 #define MLXSW_REG_PMTDB_LEN 0x40
5832
5833 MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN);
5834
5835 /* reg_pmtdb_slot_index
5836 * Slot index (0: Main board).
5837 * Access: Index
5838 */
5839 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4);
5840
5841 /* reg_pmtdb_module
5842 * Module number.
5843 * Access: Index
5844 */
5845 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8);
5846
5847 /* reg_pmtdb_ports_width
5848 * Port's width
5849 * Access: Index
5850 */
5851 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4);
5852
5853 /* reg_pmtdb_num_ports
5854 * Number of ports in a single module (split/breakout)
5855 * Access: Index
5856 */
5857 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4);
5858
5859 enum mlxsw_reg_pmtdb_status {
5860 MLXSW_REG_PMTDB_STATUS_SUCCESS,
5861 };
5862
5863 /* reg_pmtdb_status
5864 * Status
5865 * Access: RO
5866 */
5867 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4);
5868
5869 /* reg_pmtdb_port_num
5870 * The local_port value which can be assigned to the module.
5871 * In case of more than one port, port<x> represent the /<x> port of
5872 * the module.
5873 * Access: RO
5874 */
5875 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false);
5876
mlxsw_reg_pmtdb_pack(char * payload,u8 slot_index,u8 module,u8 ports_width,u8 num_ports)5877 static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module,
5878 u8 ports_width, u8 num_ports)
5879 {
5880 MLXSW_REG_ZERO(pmtdb, payload);
5881 mlxsw_reg_pmtdb_slot_index_set(payload, slot_index);
5882 mlxsw_reg_pmtdb_module_set(payload, module);
5883 mlxsw_reg_pmtdb_ports_width_set(payload, ports_width);
5884 mlxsw_reg_pmtdb_num_ports_set(payload, num_ports);
5885 }
5886
5887 /* PMECR - Ports Mapping Event Configuration Register
5888 * --------------------------------------------------
5889 * The PMECR register is used to enable/disable event triggering
5890 * in case of local port mapping change.
5891 */
5892 #define MLXSW_REG_PMECR_ID 0x501B
5893 #define MLXSW_REG_PMECR_LEN 0x20
5894
5895 MLXSW_REG_DEFINE(pmecr, MLXSW_REG_PMECR_ID, MLXSW_REG_PMECR_LEN);
5896
5897 /* reg_pmecr_local_port
5898 * Local port number.
5899 * Access: Index
5900 */
5901 MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12);
5902
5903 /* reg_pmecr_ee
5904 * Event update enable. If this bit is set, event generation will be updated
5905 * based on the e field. Only relevant on Set operations.
5906 * Access: WO
5907 */
5908 MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1);
5909
5910 /* reg_pmecr_eswi
5911 * Software ignore enable bit. If this bit is set, the value of swi is used.
5912 * If this bit is clear, the value of swi is ignored.
5913 * Only relevant on Set operations.
5914 * Access: WO
5915 */
5916 MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1);
5917
5918 /* reg_pmecr_swi
5919 * Software ignore. If this bit is set, the device shouldn't generate events
5920 * in case of PMLP SET operation but only upon self local port mapping change
5921 * (if applicable according to e configuration). This is supplementary
5922 * configuration on top of e value.
5923 * Access: RW
5924 */
5925 MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1);
5926
5927 enum mlxsw_reg_pmecr_e {
5928 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT,
5929 MLXSW_REG_PMECR_E_GENERATE_EVENT,
5930 MLXSW_REG_PMECR_E_GENERATE_SINGLE_EVENT,
5931 };
5932
5933 /* reg_pmecr_e
5934 * Event generation on local port mapping change.
5935 * Access: RW
5936 */
5937 MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2);
5938
mlxsw_reg_pmecr_pack(char * payload,u16 local_port,enum mlxsw_reg_pmecr_e e)5939 static inline void mlxsw_reg_pmecr_pack(char *payload, u16 local_port,
5940 enum mlxsw_reg_pmecr_e e)
5941 {
5942 MLXSW_REG_ZERO(pmecr, payload);
5943 mlxsw_reg_pmecr_local_port_set(payload, local_port);
5944 mlxsw_reg_pmecr_e_set(payload, e);
5945 mlxsw_reg_pmecr_ee_set(payload, true);
5946 mlxsw_reg_pmecr_swi_set(payload, true);
5947 mlxsw_reg_pmecr_eswi_set(payload, true);
5948 }
5949
5950 /* PMPE - Port Module Plug/Unplug Event Register
5951 * ---------------------------------------------
5952 * This register reports any operational status change of a module.
5953 * A change in the module’s state will generate an event only if the change
5954 * happens after arming the event mechanism. Any changes to the module state
5955 * while the event mechanism is not armed will not be reported. Software can
5956 * query the PMPE register for module status.
5957 */
5958 #define MLXSW_REG_PMPE_ID 0x5024
5959 #define MLXSW_REG_PMPE_LEN 0x10
5960
5961 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN);
5962
5963 /* reg_pmpe_slot_index
5964 * Slot index.
5965 * Access: Index
5966 */
5967 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4);
5968
5969 /* reg_pmpe_module
5970 * Module number.
5971 * Access: Index
5972 */
5973 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8);
5974
5975 enum mlxsw_reg_pmpe_module_status {
5976 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1,
5977 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED,
5978 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR,
5979 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED,
5980 };
5981
5982 /* reg_pmpe_module_status
5983 * Module status.
5984 * Access: RO
5985 */
5986 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4);
5987
5988 /* reg_pmpe_error_type
5989 * Module error details.
5990 * Access: RO
5991 */
5992 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4);
5993
5994 /* PDDR - Port Diagnostics Database Register
5995 * -----------------------------------------
5996 * The PDDR enables to read the Phy debug database
5997 */
5998 #define MLXSW_REG_PDDR_ID 0x5031
5999 #define MLXSW_REG_PDDR_LEN 0x100
6000
6001 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN);
6002
6003 /* reg_pddr_local_port
6004 * Local port number.
6005 * Access: Index
6006 */
6007 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12);
6008
6009 enum mlxsw_reg_pddr_page_select {
6010 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1,
6011 };
6012
6013 /* reg_pddr_page_select
6014 * Page select index.
6015 * Access: Index
6016 */
6017 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8);
6018
6019 enum mlxsw_reg_pddr_trblsh_group_opcode {
6020 /* Monitor opcodes */
6021 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR,
6022 };
6023
6024 /* reg_pddr_group_opcode
6025 * Group selector.
6026 * Access: Index
6027 */
6028 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16);
6029
6030 /* reg_pddr_status_opcode
6031 * Group selector.
6032 * Access: RO
6033 */
6034 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16);
6035
mlxsw_reg_pddr_pack(char * payload,u16 local_port,u8 page_select)6036 static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port,
6037 u8 page_select)
6038 {
6039 MLXSW_REG_ZERO(pddr, payload);
6040 mlxsw_reg_pddr_local_port_set(payload, local_port);
6041 mlxsw_reg_pddr_page_select_set(payload, page_select);
6042 }
6043
6044 /* PMMP - Port Module Memory Map Properties Register
6045 * -------------------------------------------------
6046 * The PMMP register allows to override the module memory map advertisement.
6047 * The register can only be set when the module is disabled by PMAOS register.
6048 */
6049 #define MLXSW_REG_PMMP_ID 0x5044
6050 #define MLXSW_REG_PMMP_LEN 0x2C
6051
6052 MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN);
6053
6054 /* reg_pmmp_module
6055 * Module number.
6056 * Access: Index
6057 */
6058 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8);
6059
6060 /* reg_pmmp_slot_index
6061 * Slot index.
6062 * Access: Index
6063 */
6064 MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4);
6065
6066 /* reg_pmmp_sticky
6067 * When set, will keep eeprom_override values after plug-out event.
6068 * Access: OP
6069 */
6070 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1);
6071
6072 /* reg_pmmp_eeprom_override_mask
6073 * Write mask bit (negative polarity).
6074 * 0 - Allow write
6075 * 1 - Ignore write
6076 * On write, indicates which of the bits from eeprom_override field are
6077 * updated.
6078 * Access: WO
6079 */
6080 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16);
6081
6082 enum {
6083 /* Set module to low power mode */
6084 MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8),
6085 };
6086
6087 /* reg_pmmp_eeprom_override
6088 * Override / ignore EEPROM advertisement properties bitmask
6089 * Access: RW
6090 */
6091 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16);
6092
mlxsw_reg_pmmp_pack(char * payload,u8 slot_index,u8 module)6093 static inline void mlxsw_reg_pmmp_pack(char *payload, u8 slot_index, u8 module)
6094 {
6095 MLXSW_REG_ZERO(pmmp, payload);
6096 mlxsw_reg_pmmp_slot_index_set(payload, slot_index);
6097 mlxsw_reg_pmmp_module_set(payload, module);
6098 }
6099
6100 /* PLLP - Port Local port to Label Port mapping Register
6101 * -----------------------------------------------------
6102 * The PLLP register returns the mapping from Local Port into Label Port.
6103 */
6104 #define MLXSW_REG_PLLP_ID 0x504A
6105 #define MLXSW_REG_PLLP_LEN 0x10
6106
6107 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN);
6108
6109 /* reg_pllp_local_port
6110 * Local port number.
6111 * Access: Index
6112 */
6113 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12);
6114
6115 /* reg_pllp_label_port
6116 * Front panel label of the port.
6117 * Access: RO
6118 */
6119 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8);
6120
6121 /* reg_pllp_split_num
6122 * Label split mapping for local_port.
6123 * Access: RO
6124 */
6125 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4);
6126
6127 /* reg_pllp_slot_index
6128 * Slot index (0: Main board).
6129 * Access: RO
6130 */
6131 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4);
6132
mlxsw_reg_pllp_pack(char * payload,u16 local_port)6133 static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port)
6134 {
6135 MLXSW_REG_ZERO(pllp, payload);
6136 mlxsw_reg_pllp_local_port_set(payload, local_port);
6137 }
6138
mlxsw_reg_pllp_unpack(char * payload,u8 * label_port,u8 * split_num,u8 * slot_index)6139 static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port,
6140 u8 *split_num, u8 *slot_index)
6141 {
6142 *label_port = mlxsw_reg_pllp_label_port_get(payload);
6143 *split_num = mlxsw_reg_pllp_split_num_get(payload);
6144 *slot_index = mlxsw_reg_pllp_slot_index_get(payload);
6145 }
6146
6147 /* PMTM - Port Module Type Mapping Register
6148 * ----------------------------------------
6149 * The PMTM register allows query or configuration of module types.
6150 * The register can only be set when the module is disabled by PMAOS register
6151 */
6152 #define MLXSW_REG_PMTM_ID 0x5067
6153 #define MLXSW_REG_PMTM_LEN 0x10
6154
6155 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN);
6156
6157 /* reg_pmtm_slot_index
6158 * Slot index.
6159 * Access: Index
6160 */
6161 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4);
6162
6163 /* reg_pmtm_module
6164 * Module number.
6165 * Access: Index
6166 */
6167 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8);
6168
6169 enum mlxsw_reg_pmtm_module_type {
6170 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0,
6171 MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1,
6172 MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2,
6173 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4,
6174 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8,
6175 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10,
6176 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11,
6177 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12,
6178 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14,
6179 MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15,
6180 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16,
6181 MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17,
6182 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18,
6183 MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19,
6184 };
6185
6186 /* reg_pmtm_module_type
6187 * Module type.
6188 * Access: RW
6189 */
6190 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5);
6191
mlxsw_reg_pmtm_pack(char * payload,u8 slot_index,u8 module)6192 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module)
6193 {
6194 MLXSW_REG_ZERO(pmtm, payload);
6195 mlxsw_reg_pmtm_slot_index_set(payload, slot_index);
6196 mlxsw_reg_pmtm_module_set(payload, module);
6197 }
6198
6199 /* HTGT - Host Trap Group Table
6200 * ----------------------------
6201 * Configures the properties for forwarding to CPU.
6202 */
6203 #define MLXSW_REG_HTGT_ID 0x7002
6204 #define MLXSW_REG_HTGT_LEN 0x20
6205
6206 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
6207
6208 /* reg_htgt_swid
6209 * Switch partition ID.
6210 * Access: Index
6211 */
6212 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
6213
6214 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
6215
6216 /* reg_htgt_type
6217 * CPU path type.
6218 * Access: RW
6219 */
6220 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
6221
6222 enum mlxsw_reg_htgt_trap_group {
6223 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
6224 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT,
6225 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
6226 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
6227 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
6228 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING,
6229 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
6230 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
6231 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
6232 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
6233 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY,
6234 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
6235 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE,
6236 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
6237 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
6238 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
6239 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6,
6240 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,
6241 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,
6242 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,
6243 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP,
6244 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE,
6245 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING,
6246 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS,
6247 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD,
6248 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY,
6249 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS,
6250 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS,
6251 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS,
6252 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS,
6253 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS,
6254 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS,
6255
6256 __MLXSW_REG_HTGT_TRAP_GROUP_MAX,
6257 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1
6258 };
6259
6260 /* reg_htgt_trap_group
6261 * Trap group number. User defined number specifying which trap groups
6262 * should be forwarded to the CPU. The mapping between trap IDs and trap
6263 * groups is configured using HPKT register.
6264 * Access: Index
6265 */
6266 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
6267
6268 enum {
6269 MLXSW_REG_HTGT_POLICER_DISABLE,
6270 MLXSW_REG_HTGT_POLICER_ENABLE,
6271 };
6272
6273 /* reg_htgt_pide
6274 * Enable policer ID specified using 'pid' field.
6275 * Access: RW
6276 */
6277 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
6278
6279 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff
6280
6281 /* reg_htgt_pid
6282 * Policer ID for the trap group.
6283 * Access: RW
6284 */
6285 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
6286
6287 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
6288
6289 /* reg_htgt_mirror_action
6290 * Mirror action to use.
6291 * 0 - Trap to CPU.
6292 * 1 - Trap to CPU and mirror to a mirroring agent.
6293 * 2 - Mirror to a mirroring agent and do not trap to CPU.
6294 * Access: RW
6295 *
6296 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
6297 */
6298 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
6299
6300 /* reg_htgt_mirroring_agent
6301 * Mirroring agent.
6302 * Access: RW
6303 */
6304 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
6305
6306 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
6307
6308 /* reg_htgt_priority
6309 * Trap group priority.
6310 * In case a packet matches multiple classification rules, the packet will
6311 * only be trapped once, based on the trap ID associated with the group (via
6312 * register HPKT) with the highest priority.
6313 * Supported values are 0-7, with 7 represnting the highest priority.
6314 * Access: RW
6315 *
6316 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
6317 * by the 'trap_group' field.
6318 */
6319 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
6320
6321 #define MLXSW_REG_HTGT_DEFAULT_TC 7
6322
6323 /* reg_htgt_local_path_cpu_tclass
6324 * CPU ingress traffic class for the trap group.
6325 * Access: RW
6326 */
6327 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
6328
6329 enum mlxsw_reg_htgt_local_path_rdq {
6330 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
6331 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
6332 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
6333 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
6334 };
6335 /* reg_htgt_local_path_rdq
6336 * Receive descriptor queue (RDQ) to use for the trap group.
6337 * Access: RW
6338 */
6339 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
6340
mlxsw_reg_htgt_pack(char * payload,u8 group,u8 policer_id,u8 priority,u8 tc)6341 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
6342 u8 priority, u8 tc)
6343 {
6344 MLXSW_REG_ZERO(htgt, payload);
6345
6346 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
6347 mlxsw_reg_htgt_pide_set(payload,
6348 MLXSW_REG_HTGT_POLICER_DISABLE);
6349 } else {
6350 mlxsw_reg_htgt_pide_set(payload,
6351 MLXSW_REG_HTGT_POLICER_ENABLE);
6352 mlxsw_reg_htgt_pid_set(payload, policer_id);
6353 }
6354
6355 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
6356 mlxsw_reg_htgt_trap_group_set(payload, group);
6357 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
6358 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
6359 mlxsw_reg_htgt_priority_set(payload, priority);
6360 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
6361 mlxsw_reg_htgt_local_path_rdq_set(payload, group);
6362 }
6363
6364 /* HPKT - Host Packet Trap
6365 * -----------------------
6366 * Configures trap IDs inside trap groups.
6367 */
6368 #define MLXSW_REG_HPKT_ID 0x7003
6369 #define MLXSW_REG_HPKT_LEN 0x10
6370
6371 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
6372
6373 enum {
6374 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
6375 MLXSW_REG_HPKT_ACK_REQUIRED,
6376 };
6377
6378 /* reg_hpkt_ack
6379 * Require acknowledgements from the host for events.
6380 * If set, then the device will wait for the event it sent to be acknowledged
6381 * by the host. This option is only relevant for event trap IDs.
6382 * Access: RW
6383 *
6384 * Note: Currently not supported by firmware.
6385 */
6386 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
6387
6388 enum mlxsw_reg_hpkt_action {
6389 MLXSW_REG_HPKT_ACTION_FORWARD,
6390 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
6391 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
6392 MLXSW_REG_HPKT_ACTION_DISCARD,
6393 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
6394 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
6395 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU,
6396 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15,
6397 };
6398
6399 /* reg_hpkt_action
6400 * Action to perform on packet when trapped.
6401 * 0 - No action. Forward to CPU based on switching rules.
6402 * 1 - Trap to CPU (CPU receives sole copy).
6403 * 2 - Mirror to CPU (CPU receives a replica of the packet).
6404 * 3 - Discard.
6405 * 4 - Soft discard (allow other traps to act on the packet).
6406 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
6407 * 6 - Trap to CPU (CPU receives sole copy) and count it as error.
6408 * 15 - Restore the firmware's default action.
6409 * Access: RW
6410 *
6411 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
6412 * addressed to the CPU.
6413 */
6414 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
6415
6416 /* reg_hpkt_trap_group
6417 * Trap group to associate the trap with.
6418 * Access: RW
6419 */
6420 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
6421
6422 /* reg_hpkt_trap_id
6423 * Trap ID.
6424 * Access: Index
6425 *
6426 * Note: A trap ID can only be associated with a single trap group. The device
6427 * will associate the trap ID with the last trap group configured.
6428 */
6429 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10);
6430
6431 enum {
6432 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
6433 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
6434 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
6435 };
6436
6437 /* reg_hpkt_ctrl
6438 * Configure dedicated buffer resources for control packets.
6439 * Ignored by SwitchX-2.
6440 * 0 - Keep factory defaults.
6441 * 1 - Do not use control buffer for this trap ID.
6442 * 2 - Use control buffer for this trap ID.
6443 * Access: RW
6444 */
6445 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
6446
mlxsw_reg_hpkt_pack(char * payload,u8 action,u16 trap_id,enum mlxsw_reg_htgt_trap_group trap_group,bool is_ctrl)6447 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
6448 enum mlxsw_reg_htgt_trap_group trap_group,
6449 bool is_ctrl)
6450 {
6451 MLXSW_REG_ZERO(hpkt, payload);
6452 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
6453 mlxsw_reg_hpkt_action_set(payload, action);
6454 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
6455 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
6456 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
6457 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
6458 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
6459 }
6460
6461 /* RGCR - Router General Configuration Register
6462 * --------------------------------------------
6463 * The register is used for setting up the router configuration.
6464 */
6465 #define MLXSW_REG_RGCR_ID 0x8001
6466 #define MLXSW_REG_RGCR_LEN 0x28
6467
6468 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
6469
6470 /* reg_rgcr_ipv4_en
6471 * IPv4 router enable.
6472 * Access: RW
6473 */
6474 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
6475
6476 /* reg_rgcr_ipv6_en
6477 * IPv6 router enable.
6478 * Access: RW
6479 */
6480 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
6481
6482 /* reg_rgcr_max_router_interfaces
6483 * Defines the maximum number of active router interfaces for all virtual
6484 * routers.
6485 * Access: RW
6486 */
6487 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
6488
6489 /* reg_rgcr_usp
6490 * Update switch priority and packet color.
6491 * 0 - Preserve the value of Switch Priority and packet color.
6492 * 1 - Recalculate the value of Switch Priority and packet color.
6493 * Access: RW
6494 *
6495 * Note: Not supported by SwitchX and SwitchX-2.
6496 */
6497 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
6498
6499 /* reg_rgcr_pcp_rw
6500 * Indicates how to handle the pcp_rewrite_en value:
6501 * 0 - Preserve the value of pcp_rewrite_en.
6502 * 2 - Disable PCP rewrite.
6503 * 3 - Enable PCP rewrite.
6504 * Access: RW
6505 *
6506 * Note: Not supported by SwitchX and SwitchX-2.
6507 */
6508 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
6509
6510 /* reg_rgcr_activity_dis
6511 * Activity disable:
6512 * 0 - Activity will be set when an entry is hit (default).
6513 * 1 - Activity will not be set when an entry is hit.
6514 *
6515 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
6516 * (RALUE).
6517 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
6518 * Entry (RAUHT).
6519 * Bits 2:7 are reserved.
6520 * Access: RW
6521 *
6522 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
6523 */
6524 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
6525
mlxsw_reg_rgcr_pack(char * payload,bool ipv4_en,bool ipv6_en)6526 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
6527 bool ipv6_en)
6528 {
6529 MLXSW_REG_ZERO(rgcr, payload);
6530 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
6531 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
6532 }
6533
6534 /* RITR - Router Interface Table Register
6535 * --------------------------------------
6536 * The register is used to configure the router interface table.
6537 */
6538 #define MLXSW_REG_RITR_ID 0x8002
6539 #define MLXSW_REG_RITR_LEN 0x40
6540
6541 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
6542
6543 /* reg_ritr_enable
6544 * Enables routing on the router interface.
6545 * Access: RW
6546 */
6547 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
6548
6549 /* reg_ritr_ipv4
6550 * IPv4 routing enable. Enables routing of IPv4 traffic on the router
6551 * interface.
6552 * Access: RW
6553 */
6554 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
6555
6556 /* reg_ritr_ipv6
6557 * IPv6 routing enable. Enables routing of IPv6 traffic on the router
6558 * interface.
6559 * Access: RW
6560 */
6561 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
6562
6563 /* reg_ritr_ipv4_mc
6564 * IPv4 multicast routing enable.
6565 * Access: RW
6566 */
6567 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
6568
6569 /* reg_ritr_ipv6_mc
6570 * IPv6 multicast routing enable.
6571 * Access: RW
6572 */
6573 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
6574
6575 enum mlxsw_reg_ritr_if_type {
6576 /* VLAN interface. */
6577 MLXSW_REG_RITR_VLAN_IF,
6578 /* FID interface. */
6579 MLXSW_REG_RITR_FID_IF,
6580 /* Sub-port interface. */
6581 MLXSW_REG_RITR_SP_IF,
6582 /* Loopback Interface. */
6583 MLXSW_REG_RITR_LOOPBACK_IF,
6584 };
6585
6586 /* reg_ritr_type
6587 * Router interface type as per enum mlxsw_reg_ritr_if_type.
6588 * Access: RW
6589 */
6590 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
6591
6592 enum {
6593 MLXSW_REG_RITR_RIF_CREATE,
6594 MLXSW_REG_RITR_RIF_DEL,
6595 };
6596
6597 /* reg_ritr_op
6598 * Opcode:
6599 * 0 - Create or edit RIF.
6600 * 1 - Delete RIF.
6601 * Reserved for SwitchX-2. For Spectrum, editing of interface properties
6602 * is not supported. An interface must be deleted and re-created in order
6603 * to update properties.
6604 * Access: WO
6605 */
6606 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
6607
6608 /* reg_ritr_rif
6609 * Router interface index. A pointer to the Router Interface Table.
6610 * Access: Index
6611 */
6612 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
6613
6614 /* reg_ritr_ipv4_fe
6615 * IPv4 Forwarding Enable.
6616 * Enables routing of IPv4 traffic on the router interface. When disabled,
6617 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
6618 * Not supported in SwitchX-2.
6619 * Access: RW
6620 */
6621 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
6622
6623 /* reg_ritr_ipv6_fe
6624 * IPv6 Forwarding Enable.
6625 * Enables routing of IPv6 traffic on the router interface. When disabled,
6626 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
6627 * Not supported in SwitchX-2.
6628 * Access: RW
6629 */
6630 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
6631
6632 /* reg_ritr_ipv4_mc_fe
6633 * IPv4 Multicast Forwarding Enable.
6634 * When disabled, forwarding is blocked but local traffic (traps and IP to me)
6635 * will be enabled.
6636 * Access: RW
6637 */
6638 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
6639
6640 /* reg_ritr_ipv6_mc_fe
6641 * IPv6 Multicast Forwarding Enable.
6642 * When disabled, forwarding is blocked but local traffic (traps and IP to me)
6643 * will be enabled.
6644 * Access: RW
6645 */
6646 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
6647
6648 /* reg_ritr_lb_en
6649 * Loop-back filter enable for unicast packets.
6650 * If the flag is set then loop-back filter for unicast packets is
6651 * implemented on the RIF. Multicast packets are always subject to
6652 * loop-back filtering.
6653 * Access: RW
6654 */
6655 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
6656
6657 /* reg_ritr_virtual_router
6658 * Virtual router ID associated with the router interface.
6659 * Access: RW
6660 */
6661 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
6662
6663 /* reg_ritr_mtu
6664 * Router interface MTU.
6665 * Access: RW
6666 */
6667 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
6668
6669 /* reg_ritr_if_swid
6670 * Switch partition ID.
6671 * Access: RW
6672 */
6673 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
6674
6675 /* reg_ritr_if_mac_profile_id
6676 * MAC msb profile ID.
6677 * Access: RW
6678 */
6679 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4);
6680
6681 /* reg_ritr_if_mac
6682 * Router interface MAC address.
6683 * In Spectrum, all MAC addresses must have the same 38 MSBits.
6684 * Access: RW
6685 */
6686 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
6687
6688 /* reg_ritr_if_vrrp_id_ipv6
6689 * VRRP ID for IPv6
6690 * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
6691 * Access: RW
6692 */
6693 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
6694
6695 /* reg_ritr_if_vrrp_id_ipv4
6696 * VRRP ID for IPv4
6697 * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
6698 * Access: RW
6699 */
6700 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
6701
6702 /* VLAN Interface */
6703
6704 /* reg_ritr_vlan_if_vid
6705 * VLAN ID.
6706 * Access: RW
6707 */
6708 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
6709
6710 /* FID Interface */
6711
6712 /* reg_ritr_fid_if_fid
6713 * Filtering ID. Used to connect a bridge to the router. Only FIDs from
6714 * the vFID range are supported.
6715 * Access: RW
6716 */
6717 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
6718
mlxsw_reg_ritr_fid_set(char * payload,enum mlxsw_reg_ritr_if_type rif_type,u16 fid)6719 static inline void mlxsw_reg_ritr_fid_set(char *payload,
6720 enum mlxsw_reg_ritr_if_type rif_type,
6721 u16 fid)
6722 {
6723 if (rif_type == MLXSW_REG_RITR_FID_IF)
6724 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
6725 else
6726 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
6727 }
6728
6729 /* Sub-port Interface */
6730
6731 /* reg_ritr_sp_if_lag
6732 * LAG indication. When this bit is set the system_port field holds the
6733 * LAG identifier.
6734 * Access: RW
6735 */
6736 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
6737
6738 /* reg_ritr_sp_system_port
6739 * Port unique indentifier. When lag bit is set, this field holds the
6740 * lag_id in bits 0:9.
6741 * Access: RW
6742 */
6743 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
6744
6745 /* reg_ritr_sp_if_vid
6746 * VLAN ID.
6747 * Access: RW
6748 */
6749 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
6750
6751 /* Loopback Interface */
6752
6753 enum mlxsw_reg_ritr_loopback_protocol {
6754 /* IPinIP IPv4 underlay Unicast */
6755 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
6756 /* IPinIP IPv6 underlay Unicast */
6757 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
6758 /* IPinIP generic - used for Spectrum-2 underlay RIF */
6759 MLXSW_REG_RITR_LOOPBACK_GENERIC,
6760 };
6761
6762 /* reg_ritr_loopback_protocol
6763 * Access: RW
6764 */
6765 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
6766
6767 enum mlxsw_reg_ritr_loopback_ipip_type {
6768 /* Tunnel is IPinIP. */
6769 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
6770 /* Tunnel is GRE, no key. */
6771 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
6772 /* Tunnel is GRE, with a key. */
6773 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
6774 };
6775
6776 /* reg_ritr_loopback_ipip_type
6777 * Encapsulation type.
6778 * Access: RW
6779 */
6780 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
6781
6782 enum mlxsw_reg_ritr_loopback_ipip_options {
6783 /* The key is defined by gre_key. */
6784 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
6785 };
6786
6787 /* reg_ritr_loopback_ipip_options
6788 * Access: RW
6789 */
6790 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
6791
6792 /* reg_ritr_loopback_ipip_uvr
6793 * Underlay Virtual Router ID.
6794 * Range is 0..cap_max_virtual_routers-1.
6795 * Reserved for Spectrum-2.
6796 * Access: RW
6797 */
6798 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
6799
6800 /* reg_ritr_loopback_ipip_underlay_rif
6801 * Underlay ingress router interface.
6802 * Reserved for Spectrum.
6803 * Access: RW
6804 */
6805 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);
6806
6807 /* reg_ritr_loopback_ipip_usip*
6808 * Encapsulation Underlay source IP.
6809 * Access: RW
6810 */
6811 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
6812 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
6813
6814 /* reg_ritr_loopback_ipip_gre_key
6815 * GRE Key.
6816 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP.
6817 * Access: RW
6818 */
6819 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
6820
6821 /* Shared between ingress/egress */
6822 enum mlxsw_reg_ritr_counter_set_type {
6823 /* No Count. */
6824 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
6825 /* Basic. Used for router interfaces, counting the following:
6826 * - Error and Discard counters.
6827 * - Unicast, Multicast and Broadcast counters. Sharing the
6828 * same set of counters for the different type of traffic
6829 * (IPv4, IPv6 and mpls).
6830 */
6831 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
6832 };
6833
6834 /* reg_ritr_ingress_counter_index
6835 * Counter Index for flow counter.
6836 * Access: RW
6837 */
6838 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
6839
6840 /* reg_ritr_ingress_counter_set_type
6841 * Igress Counter Set Type for router interface counter.
6842 * Access: RW
6843 */
6844 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
6845
6846 /* reg_ritr_egress_counter_index
6847 * Counter Index for flow counter.
6848 * Access: RW
6849 */
6850 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
6851
6852 /* reg_ritr_egress_counter_set_type
6853 * Egress Counter Set Type for router interface counter.
6854 * Access: RW
6855 */
6856 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
6857
mlxsw_reg_ritr_counter_pack(char * payload,u32 index,bool enable,bool egress)6858 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
6859 bool enable, bool egress)
6860 {
6861 enum mlxsw_reg_ritr_counter_set_type set_type;
6862
6863 if (enable)
6864 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
6865 else
6866 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
6867
6868 if (egress) {
6869 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
6870 mlxsw_reg_ritr_egress_counter_index_set(payload, index);
6871 } else {
6872 mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type);
6873 mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
6874 }
6875 }
6876
mlxsw_reg_ritr_rif_pack(char * payload,u16 rif)6877 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
6878 {
6879 MLXSW_REG_ZERO(ritr, payload);
6880 mlxsw_reg_ritr_rif_set(payload, rif);
6881 }
6882
mlxsw_reg_ritr_sp_if_pack(char * payload,bool lag,u16 system_port,u16 vid)6883 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
6884 u16 system_port, u16 vid)
6885 {
6886 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
6887 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
6888 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
6889 }
6890
mlxsw_reg_ritr_pack(char * payload,bool enable,enum mlxsw_reg_ritr_if_type type,u16 rif,u16 vr_id,u16 mtu)6891 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
6892 enum mlxsw_reg_ritr_if_type type,
6893 u16 rif, u16 vr_id, u16 mtu)
6894 {
6895 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
6896
6897 MLXSW_REG_ZERO(ritr, payload);
6898 mlxsw_reg_ritr_enable_set(payload, enable);
6899 mlxsw_reg_ritr_ipv4_set(payload, 1);
6900 mlxsw_reg_ritr_ipv6_set(payload, 1);
6901 mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
6902 mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
6903 mlxsw_reg_ritr_type_set(payload, type);
6904 mlxsw_reg_ritr_op_set(payload, op);
6905 mlxsw_reg_ritr_rif_set(payload, rif);
6906 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
6907 mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
6908 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
6909 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
6910 mlxsw_reg_ritr_lb_en_set(payload, 1);
6911 mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
6912 mlxsw_reg_ritr_mtu_set(payload, mtu);
6913 }
6914
mlxsw_reg_ritr_mac_pack(char * payload,const char * mac)6915 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
6916 {
6917 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
6918 }
6919
6920 static inline void
mlxsw_reg_ritr_loopback_ipip_common_pack(char * payload,enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,enum mlxsw_reg_ritr_loopback_ipip_options options,u16 uvr_id,u16 underlay_rif,u32 gre_key)6921 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
6922 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6923 enum mlxsw_reg_ritr_loopback_ipip_options options,
6924 u16 uvr_id, u16 underlay_rif, u32 gre_key)
6925 {
6926 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
6927 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
6928 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
6929 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif);
6930 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
6931 }
6932
6933 static inline void
mlxsw_reg_ritr_loopback_ipip4_pack(char * payload,enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,enum mlxsw_reg_ritr_loopback_ipip_options options,u16 uvr_id,u16 underlay_rif,u32 usip,u32 gre_key)6934 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
6935 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6936 enum mlxsw_reg_ritr_loopback_ipip_options options,
6937 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key)
6938 {
6939 mlxsw_reg_ritr_loopback_protocol_set(payload,
6940 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
6941 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
6942 uvr_id, underlay_rif, gre_key);
6943 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
6944 }
6945
6946 static inline void
mlxsw_reg_ritr_loopback_ipip6_pack(char * payload,enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,enum mlxsw_reg_ritr_loopback_ipip_options options,u16 uvr_id,u16 underlay_rif,const struct in6_addr * usip,u32 gre_key)6947 mlxsw_reg_ritr_loopback_ipip6_pack(char *payload,
6948 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6949 enum mlxsw_reg_ritr_loopback_ipip_options options,
6950 u16 uvr_id, u16 underlay_rif,
6951 const struct in6_addr *usip, u32 gre_key)
6952 {
6953 enum mlxsw_reg_ritr_loopback_protocol protocol =
6954 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6;
6955
6956 mlxsw_reg_ritr_loopback_protocol_set(payload, protocol);
6957 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
6958 uvr_id, underlay_rif, gre_key);
6959 mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload,
6960 (const char *)usip);
6961 }
6962
6963 /* RTAR - Router TCAM Allocation Register
6964 * --------------------------------------
6965 * This register is used for allocation of regions in the TCAM table.
6966 */
6967 #define MLXSW_REG_RTAR_ID 0x8004
6968 #define MLXSW_REG_RTAR_LEN 0x20
6969
6970 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
6971
6972 enum mlxsw_reg_rtar_op {
6973 MLXSW_REG_RTAR_OP_ALLOCATE,
6974 MLXSW_REG_RTAR_OP_RESIZE,
6975 MLXSW_REG_RTAR_OP_DEALLOCATE,
6976 };
6977
6978 /* reg_rtar_op
6979 * Access: WO
6980 */
6981 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
6982
6983 enum mlxsw_reg_rtar_key_type {
6984 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
6985 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
6986 };
6987
6988 /* reg_rtar_key_type
6989 * TCAM key type for the region.
6990 * Access: WO
6991 */
6992 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
6993
6994 /* reg_rtar_region_size
6995 * TCAM region size. When allocating/resizing this is the requested
6996 * size, the response is the actual size.
6997 * Note: Actual size may be larger than requested.
6998 * Reserved for op = Deallocate
6999 * Access: WO
7000 */
7001 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
7002
mlxsw_reg_rtar_pack(char * payload,enum mlxsw_reg_rtar_op op,enum mlxsw_reg_rtar_key_type key_type,u16 region_size)7003 static inline void mlxsw_reg_rtar_pack(char *payload,
7004 enum mlxsw_reg_rtar_op op,
7005 enum mlxsw_reg_rtar_key_type key_type,
7006 u16 region_size)
7007 {
7008 MLXSW_REG_ZERO(rtar, payload);
7009 mlxsw_reg_rtar_op_set(payload, op);
7010 mlxsw_reg_rtar_key_type_set(payload, key_type);
7011 mlxsw_reg_rtar_region_size_set(payload, region_size);
7012 }
7013
7014 /* RATR - Router Adjacency Table Register
7015 * --------------------------------------
7016 * The RATR register is used to configure the Router Adjacency (next-hop)
7017 * Table.
7018 */
7019 #define MLXSW_REG_RATR_ID 0x8008
7020 #define MLXSW_REG_RATR_LEN 0x2C
7021
7022 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
7023
7024 enum mlxsw_reg_ratr_op {
7025 /* Read */
7026 MLXSW_REG_RATR_OP_QUERY_READ = 0,
7027 /* Read and clear activity */
7028 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
7029 /* Write Adjacency entry */
7030 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
7031 /* Write Adjacency entry only if the activity is cleared.
7032 * The write may not succeed if the activity is set. There is not
7033 * direct feedback if the write has succeeded or not, however
7034 * the get will reveal the actual entry (SW can compare the get
7035 * response to the set command).
7036 */
7037 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
7038 };
7039
7040 /* reg_ratr_op
7041 * Note that Write operation may also be used for updating
7042 * counter_set_type and counter_index. In this case all other
7043 * fields must not be updated.
7044 * Access: OP
7045 */
7046 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
7047
7048 /* reg_ratr_v
7049 * Valid bit. Indicates if the adjacency entry is valid.
7050 * Note: the device may need some time before reusing an invalidated
7051 * entry. During this time the entry can not be reused. It is
7052 * recommended to use another entry before reusing an invalidated
7053 * entry (e.g. software can put it at the end of the list for
7054 * reusing). Trying to access an invalidated entry not yet cleared
7055 * by the device results with failure indicating "Try Again" status.
7056 * When valid is '0' then egress_router_interface,trap_action,
7057 * adjacency_parameters and counters are reserved
7058 * Access: RW
7059 */
7060 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
7061
7062 /* reg_ratr_a
7063 * Activity. Set for new entries. Set if a packet lookup has hit on
7064 * the specific entry. To clear the a bit, use "clear activity".
7065 * Access: RO
7066 */
7067 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
7068
7069 enum mlxsw_reg_ratr_type {
7070 /* Ethernet */
7071 MLXSW_REG_RATR_TYPE_ETHERNET,
7072 /* IPoIB Unicast without GRH.
7073 * Reserved for Spectrum.
7074 */
7075 MLXSW_REG_RATR_TYPE_IPOIB_UC,
7076 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast
7077 * adjacency).
7078 * Reserved for Spectrum.
7079 */
7080 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
7081 /* IPoIB Multicast.
7082 * Reserved for Spectrum.
7083 */
7084 MLXSW_REG_RATR_TYPE_IPOIB_MC,
7085 /* MPLS.
7086 * Reserved for SwitchX/-2.
7087 */
7088 MLXSW_REG_RATR_TYPE_MPLS,
7089 /* IPinIP Encap.
7090 * Reserved for SwitchX/-2.
7091 */
7092 MLXSW_REG_RATR_TYPE_IPIP,
7093 };
7094
7095 /* reg_ratr_type
7096 * Adjacency entry type.
7097 * Access: RW
7098 */
7099 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
7100
7101 /* reg_ratr_adjacency_index_low
7102 * Bits 15:0 of index into the adjacency table.
7103 * For SwitchX and SwitchX-2, the adjacency table is linear and
7104 * used for adjacency entries only.
7105 * For Spectrum, the index is to the KVD linear.
7106 * Access: Index
7107 */
7108 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
7109
7110 /* reg_ratr_egress_router_interface
7111 * Range is 0 .. cap_max_router_interfaces - 1
7112 * Access: RW
7113 */
7114 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
7115
7116 enum mlxsw_reg_ratr_trap_action {
7117 MLXSW_REG_RATR_TRAP_ACTION_NOP,
7118 MLXSW_REG_RATR_TRAP_ACTION_TRAP,
7119 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
7120 MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
7121 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
7122 };
7123
7124 /* reg_ratr_trap_action
7125 * see mlxsw_reg_ratr_trap_action
7126 * Access: RW
7127 */
7128 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
7129
7130 /* reg_ratr_adjacency_index_high
7131 * Bits 23:16 of the adjacency_index.
7132 * Access: Index
7133 */
7134 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
7135
7136 enum mlxsw_reg_ratr_trap_id {
7137 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
7138 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
7139 };
7140
7141 /* reg_ratr_trap_id
7142 * Trap ID to be reported to CPU.
7143 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
7144 * For trap_action of NOP, MIRROR and DISCARD_ERROR
7145 * Access: RW
7146 */
7147 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
7148
7149 /* reg_ratr_eth_destination_mac
7150 * MAC address of the destination next-hop.
7151 * Access: RW
7152 */
7153 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
7154
7155 enum mlxsw_reg_ratr_ipip_type {
7156 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */
7157 MLXSW_REG_RATR_IPIP_TYPE_IPV4,
7158 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */
7159 MLXSW_REG_RATR_IPIP_TYPE_IPV6,
7160 };
7161
7162 /* reg_ratr_ipip_type
7163 * Underlay destination ip type.
7164 * Note: the type field must match the protocol of the router interface.
7165 * Access: RW
7166 */
7167 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
7168
7169 /* reg_ratr_ipip_ipv4_udip
7170 * Underlay ipv4 dip.
7171 * Reserved when ipip_type is IPv6.
7172 * Access: RW
7173 */
7174 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
7175
7176 /* reg_ratr_ipip_ipv6_ptr
7177 * Pointer to IPv6 underlay destination ip address.
7178 * For Spectrum: Pointer to KVD linear space.
7179 * Access: RW
7180 */
7181 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
7182
7183 enum mlxsw_reg_flow_counter_set_type {
7184 /* No count */
7185 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
7186 /* Count packets and bytes */
7187 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
7188 /* Count only packets */
7189 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
7190 };
7191
7192 /* reg_ratr_counter_set_type
7193 * Counter set type for flow counters
7194 * Access: RW
7195 */
7196 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
7197
7198 /* reg_ratr_counter_index
7199 * Counter index for flow counters
7200 * Access: RW
7201 */
7202 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
7203
7204 static inline void
mlxsw_reg_ratr_pack(char * payload,enum mlxsw_reg_ratr_op op,bool valid,enum mlxsw_reg_ratr_type type,u32 adjacency_index,u16 egress_rif)7205 mlxsw_reg_ratr_pack(char *payload,
7206 enum mlxsw_reg_ratr_op op, bool valid,
7207 enum mlxsw_reg_ratr_type type,
7208 u32 adjacency_index, u16 egress_rif)
7209 {
7210 MLXSW_REG_ZERO(ratr, payload);
7211 mlxsw_reg_ratr_op_set(payload, op);
7212 mlxsw_reg_ratr_v_set(payload, valid);
7213 mlxsw_reg_ratr_type_set(payload, type);
7214 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
7215 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
7216 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
7217 }
7218
mlxsw_reg_ratr_eth_entry_pack(char * payload,const char * dest_mac)7219 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
7220 const char *dest_mac)
7221 {
7222 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
7223 }
7224
mlxsw_reg_ratr_ipip4_entry_pack(char * payload,u32 ipv4_udip)7225 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
7226 {
7227 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
7228 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
7229 }
7230
mlxsw_reg_ratr_ipip6_entry_pack(char * payload,u32 ipv6_ptr)7231 static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr)
7232 {
7233 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6);
7234 mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr);
7235 }
7236
mlxsw_reg_ratr_counter_pack(char * payload,u64 counter_index,bool counter_enable)7237 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
7238 bool counter_enable)
7239 {
7240 enum mlxsw_reg_flow_counter_set_type set_type;
7241
7242 if (counter_enable)
7243 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
7244 else
7245 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
7246
7247 mlxsw_reg_ratr_counter_index_set(payload, counter_index);
7248 mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
7249 }
7250
7251 /* RDPM - Router DSCP to Priority Mapping
7252 * --------------------------------------
7253 * Controls the mapping from DSCP field to switch priority on routed packets
7254 */
7255 #define MLXSW_REG_RDPM_ID 0x8009
7256 #define MLXSW_REG_RDPM_BASE_LEN 0x00
7257 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
7258 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
7259 #define MLXSW_REG_RDPM_LEN 0x40
7260 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
7261 MLXSW_REG_RDPM_LEN - \
7262 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
7263
7264 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
7265
7266 /* reg_dscp_entry_e
7267 * Enable update of the specific entry
7268 * Access: Index
7269 */
7270 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
7271 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
7272
7273 /* reg_dscp_entry_prio
7274 * Switch Priority
7275 * Access: RW
7276 */
7277 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
7278 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
7279
mlxsw_reg_rdpm_pack(char * payload,unsigned short index,u8 prio)7280 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
7281 u8 prio)
7282 {
7283 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
7284 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
7285 }
7286
7287 /* RICNT - Router Interface Counter Register
7288 * -----------------------------------------
7289 * The RICNT register retrieves per port performance counters
7290 */
7291 #define MLXSW_REG_RICNT_ID 0x800B
7292 #define MLXSW_REG_RICNT_LEN 0x100
7293
7294 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
7295
7296 /* reg_ricnt_counter_index
7297 * Counter index
7298 * Access: RW
7299 */
7300 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
7301
7302 enum mlxsw_reg_ricnt_counter_set_type {
7303 /* No Count. */
7304 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
7305 /* Basic. Used for router interfaces, counting the following:
7306 * - Error and Discard counters.
7307 * - Unicast, Multicast and Broadcast counters. Sharing the
7308 * same set of counters for the different type of traffic
7309 * (IPv4, IPv6 and mpls).
7310 */
7311 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
7312 };
7313
7314 /* reg_ricnt_counter_set_type
7315 * Counter Set Type for router interface counter
7316 * Access: RW
7317 */
7318 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
7319
7320 enum mlxsw_reg_ricnt_opcode {
7321 /* Nop. Supported only for read access*/
7322 MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
7323 /* Clear. Setting the clr bit will reset the counter value for
7324 * all counters of the specified Router Interface.
7325 */
7326 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
7327 };
7328
7329 /* reg_ricnt_opcode
7330 * Opcode
7331 * Access: RW
7332 */
7333 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
7334
7335 /* reg_ricnt_good_unicast_packets
7336 * good unicast packets.
7337 * Access: RW
7338 */
7339 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
7340
7341 /* reg_ricnt_good_multicast_packets
7342 * good multicast packets.
7343 * Access: RW
7344 */
7345 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
7346
7347 /* reg_ricnt_good_broadcast_packets
7348 * good broadcast packets
7349 * Access: RW
7350 */
7351 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
7352
7353 /* reg_ricnt_good_unicast_bytes
7354 * A count of L3 data and padding octets not including L2 headers
7355 * for good unicast frames.
7356 * Access: RW
7357 */
7358 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
7359
7360 /* reg_ricnt_good_multicast_bytes
7361 * A count of L3 data and padding octets not including L2 headers
7362 * for good multicast frames.
7363 * Access: RW
7364 */
7365 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
7366
7367 /* reg_ritr_good_broadcast_bytes
7368 * A count of L3 data and padding octets not including L2 headers
7369 * for good broadcast frames.
7370 * Access: RW
7371 */
7372 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
7373
7374 /* reg_ricnt_error_packets
7375 * A count of errored frames that do not pass the router checks.
7376 * Access: RW
7377 */
7378 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
7379
7380 /* reg_ricnt_discrad_packets
7381 * A count of non-errored frames that do not pass the router checks.
7382 * Access: RW
7383 */
7384 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
7385
7386 /* reg_ricnt_error_bytes
7387 * A count of L3 data and padding octets not including L2 headers
7388 * for errored frames.
7389 * Access: RW
7390 */
7391 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
7392
7393 /* reg_ricnt_discard_bytes
7394 * A count of L3 data and padding octets not including L2 headers
7395 * for non-errored frames that do not pass the router checks.
7396 * Access: RW
7397 */
7398 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
7399
mlxsw_reg_ricnt_pack(char * payload,u32 index,enum mlxsw_reg_ricnt_opcode op)7400 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
7401 enum mlxsw_reg_ricnt_opcode op)
7402 {
7403 MLXSW_REG_ZERO(ricnt, payload);
7404 mlxsw_reg_ricnt_op_set(payload, op);
7405 mlxsw_reg_ricnt_counter_index_set(payload, index);
7406 mlxsw_reg_ricnt_counter_set_type_set(payload,
7407 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
7408 }
7409
7410 /* RRCR - Router Rules Copy Register Layout
7411 * ----------------------------------------
7412 * This register is used for moving and copying route entry rules.
7413 */
7414 #define MLXSW_REG_RRCR_ID 0x800F
7415 #define MLXSW_REG_RRCR_LEN 0x24
7416
7417 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
7418
7419 enum mlxsw_reg_rrcr_op {
7420 /* Move rules */
7421 MLXSW_REG_RRCR_OP_MOVE,
7422 /* Copy rules */
7423 MLXSW_REG_RRCR_OP_COPY,
7424 };
7425
7426 /* reg_rrcr_op
7427 * Access: WO
7428 */
7429 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
7430
7431 /* reg_rrcr_offset
7432 * Offset within the region from which to copy/move.
7433 * Access: Index
7434 */
7435 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
7436
7437 /* reg_rrcr_size
7438 * The number of rules to copy/move.
7439 * Access: WO
7440 */
7441 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
7442
7443 /* reg_rrcr_table_id
7444 * Identifier of the table on which to perform the operation. Encoding is the
7445 * same as in RTAR.key_type
7446 * Access: Index
7447 */
7448 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
7449
7450 /* reg_rrcr_dest_offset
7451 * Offset within the region to which to copy/move
7452 * Access: Index
7453 */
7454 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
7455
mlxsw_reg_rrcr_pack(char * payload,enum mlxsw_reg_rrcr_op op,u16 offset,u16 size,enum mlxsw_reg_rtar_key_type table_id,u16 dest_offset)7456 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
7457 u16 offset, u16 size,
7458 enum mlxsw_reg_rtar_key_type table_id,
7459 u16 dest_offset)
7460 {
7461 MLXSW_REG_ZERO(rrcr, payload);
7462 mlxsw_reg_rrcr_op_set(payload, op);
7463 mlxsw_reg_rrcr_offset_set(payload, offset);
7464 mlxsw_reg_rrcr_size_set(payload, size);
7465 mlxsw_reg_rrcr_table_id_set(payload, table_id);
7466 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
7467 }
7468
7469 /* RALTA - Router Algorithmic LPM Tree Allocation Register
7470 * -------------------------------------------------------
7471 * RALTA is used to allocate the LPM trees of the SHSPM method.
7472 */
7473 #define MLXSW_REG_RALTA_ID 0x8010
7474 #define MLXSW_REG_RALTA_LEN 0x04
7475
7476 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
7477
7478 /* reg_ralta_op
7479 * opcode (valid for Write, must be 0 on Read)
7480 * 0 - allocate a tree
7481 * 1 - deallocate a tree
7482 * Access: OP
7483 */
7484 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
7485
7486 enum mlxsw_reg_ralxx_protocol {
7487 MLXSW_REG_RALXX_PROTOCOL_IPV4,
7488 MLXSW_REG_RALXX_PROTOCOL_IPV6,
7489 };
7490
7491 /* reg_ralta_protocol
7492 * Protocol.
7493 * Deallocation opcode: Reserved.
7494 * Access: RW
7495 */
7496 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
7497
7498 /* reg_ralta_tree_id
7499 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
7500 * the tree identifier (managed by software).
7501 * Note that tree_id 0 is allocated for a default-route tree.
7502 * Access: Index
7503 */
7504 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
7505
mlxsw_reg_ralta_pack(char * payload,bool alloc,enum mlxsw_reg_ralxx_protocol protocol,u8 tree_id)7506 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
7507 enum mlxsw_reg_ralxx_protocol protocol,
7508 u8 tree_id)
7509 {
7510 MLXSW_REG_ZERO(ralta, payload);
7511 mlxsw_reg_ralta_op_set(payload, !alloc);
7512 mlxsw_reg_ralta_protocol_set(payload, protocol);
7513 mlxsw_reg_ralta_tree_id_set(payload, tree_id);
7514 }
7515
7516 /* RALST - Router Algorithmic LPM Structure Tree Register
7517 * ------------------------------------------------------
7518 * RALST is used to set and query the structure of an LPM tree.
7519 * The structure of the tree must be sorted as a sorted binary tree, while
7520 * each node is a bin that is tagged as the length of the prefixes the lookup
7521 * will refer to. Therefore, bin X refers to a set of entries with prefixes
7522 * of X bits to match with the destination address. The bin 0 indicates
7523 * the default action, when there is no match of any prefix.
7524 */
7525 #define MLXSW_REG_RALST_ID 0x8011
7526 #define MLXSW_REG_RALST_LEN 0x104
7527
7528 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
7529
7530 /* reg_ralst_root_bin
7531 * The bin number of the root bin.
7532 * 0<root_bin=<(length of IP address)
7533 * For a default-route tree configure 0xff
7534 * Access: RW
7535 */
7536 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
7537
7538 /* reg_ralst_tree_id
7539 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
7540 * Access: Index
7541 */
7542 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
7543
7544 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
7545 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
7546 #define MLXSW_REG_RALST_BIN_COUNT 128
7547
7548 /* reg_ralst_left_child_bin
7549 * Holding the children of the bin according to the stored tree's structure.
7550 * For trees composed of less than 4 blocks, the bins in excess are reserved.
7551 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
7552 * Access: RW
7553 */
7554 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
7555
7556 /* reg_ralst_right_child_bin
7557 * Holding the children of the bin according to the stored tree's structure.
7558 * For trees composed of less than 4 blocks, the bins in excess are reserved.
7559 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
7560 * Access: RW
7561 */
7562 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
7563 false);
7564
mlxsw_reg_ralst_pack(char * payload,u8 root_bin,u8 tree_id)7565 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
7566 {
7567 MLXSW_REG_ZERO(ralst, payload);
7568
7569 /* Initialize all bins to have no left or right child */
7570 memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
7571 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
7572
7573 mlxsw_reg_ralst_root_bin_set(payload, root_bin);
7574 mlxsw_reg_ralst_tree_id_set(payload, tree_id);
7575 }
7576
mlxsw_reg_ralst_bin_pack(char * payload,u8 bin_number,u8 left_child_bin,u8 right_child_bin)7577 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
7578 u8 left_child_bin,
7579 u8 right_child_bin)
7580 {
7581 int bin_index = bin_number - 1;
7582
7583 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
7584 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
7585 right_child_bin);
7586 }
7587
7588 /* RALTB - Router Algorithmic LPM Tree Binding Register
7589 * ----------------------------------------------------
7590 * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
7591 */
7592 #define MLXSW_REG_RALTB_ID 0x8012
7593 #define MLXSW_REG_RALTB_LEN 0x04
7594
7595 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
7596
7597 /* reg_raltb_virtual_router
7598 * Virtual Router ID
7599 * Range is 0..cap_max_virtual_routers-1
7600 * Access: Index
7601 */
7602 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
7603
7604 /* reg_raltb_protocol
7605 * Protocol.
7606 * Access: Index
7607 */
7608 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
7609
7610 /* reg_raltb_tree_id
7611 * Tree to be used for the {virtual_router, protocol}
7612 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
7613 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
7614 * Access: RW
7615 */
7616 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
7617
mlxsw_reg_raltb_pack(char * payload,u16 virtual_router,enum mlxsw_reg_ralxx_protocol protocol,u8 tree_id)7618 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
7619 enum mlxsw_reg_ralxx_protocol protocol,
7620 u8 tree_id)
7621 {
7622 MLXSW_REG_ZERO(raltb, payload);
7623 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
7624 mlxsw_reg_raltb_protocol_set(payload, protocol);
7625 mlxsw_reg_raltb_tree_id_set(payload, tree_id);
7626 }
7627
7628 /* RALUE - Router Algorithmic LPM Unicast Entry Register
7629 * -----------------------------------------------------
7630 * RALUE is used to configure and query LPM entries that serve
7631 * the Unicast protocols.
7632 */
7633 #define MLXSW_REG_RALUE_ID 0x8013
7634 #define MLXSW_REG_RALUE_LEN 0x38
7635
7636 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
7637
7638 /* reg_ralue_protocol
7639 * Protocol.
7640 * Access: Index
7641 */
7642 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
7643
7644 enum mlxsw_reg_ralue_op {
7645 /* Read operation. If entry doesn't exist, the operation fails. */
7646 MLXSW_REG_RALUE_OP_QUERY_READ = 0,
7647 /* Clear on read operation. Used to read entry and
7648 * clear Activity bit.
7649 */
7650 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
7651 /* Write operation. Used to write a new entry to the table. All RW
7652 * fields are written for new entry. Activity bit is set
7653 * for new entries.
7654 */
7655 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
7656 /* Update operation. Used to update an existing route entry and
7657 * only update the RW fields that are detailed in the field
7658 * op_u_mask. If entry doesn't exist, the operation fails.
7659 */
7660 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
7661 /* Clear activity. The Activity bit (the field a) is cleared
7662 * for the entry.
7663 */
7664 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
7665 /* Delete operation. Used to delete an existing entry. If entry
7666 * doesn't exist, the operation fails.
7667 */
7668 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
7669 };
7670
7671 /* reg_ralue_op
7672 * Operation.
7673 * Access: OP
7674 */
7675 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
7676
7677 /* reg_ralue_a
7678 * Activity. Set for new entries. Set if a packet lookup has hit on the
7679 * specific entry, only if the entry is a route. To clear the a bit, use
7680 * "clear activity" op.
7681 * Enabled by activity_dis in RGCR
7682 * Access: RO
7683 */
7684 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
7685
7686 /* reg_ralue_virtual_router
7687 * Virtual Router ID
7688 * Range is 0..cap_max_virtual_routers-1
7689 * Access: Index
7690 */
7691 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
7692
7693 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
7694 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
7695 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
7696
7697 /* reg_ralue_op_u_mask
7698 * opcode update mask.
7699 * On read operation, this field is reserved.
7700 * This field is valid for update opcode, otherwise - reserved.
7701 * This field is a bitmask of the fields that should be updated.
7702 * Access: WO
7703 */
7704 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
7705
7706 /* reg_ralue_prefix_len
7707 * Number of bits in the prefix of the LPM route.
7708 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
7709 * two entries in the physical HW table.
7710 * Access: Index
7711 */
7712 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
7713
7714 /* reg_ralue_dip*
7715 * The prefix of the route or of the marker that the object of the LPM
7716 * is compared with. The most significant bits of the dip are the prefix.
7717 * The least significant bits must be '0' if the prefix_len is smaller
7718 * than 128 for IPv6 or smaller than 32 for IPv4.
7719 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
7720 * Access: Index
7721 */
7722 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
7723 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
7724
7725 enum mlxsw_reg_ralue_entry_type {
7726 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
7727 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
7728 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
7729 };
7730
7731 /* reg_ralue_entry_type
7732 * Entry type.
7733 * Note - for Marker entries, the action_type and action fields are reserved.
7734 * Access: RW
7735 */
7736 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
7737
7738 /* reg_ralue_bmp_len
7739 * The best match prefix length in the case that there is no match for
7740 * longer prefixes.
7741 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
7742 * Note for any update operation with entry_type modification this
7743 * field must be set.
7744 * Access: RW
7745 */
7746 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
7747
7748 enum mlxsw_reg_ralue_action_type {
7749 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
7750 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
7751 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
7752 };
7753
7754 /* reg_ralue_action_type
7755 * Action Type
7756 * Indicates how the IP address is connected.
7757 * It can be connected to a local subnet through local_erif or can be
7758 * on a remote subnet connected through a next-hop router,
7759 * or transmitted to the CPU.
7760 * Reserved when entry_type = MARKER_ENTRY
7761 * Access: RW
7762 */
7763 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
7764
7765 enum mlxsw_reg_ralue_trap_action {
7766 MLXSW_REG_RALUE_TRAP_ACTION_NOP,
7767 MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
7768 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
7769 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
7770 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
7771 };
7772
7773 /* reg_ralue_trap_action
7774 * Trap action.
7775 * For IP2ME action, only NOP and MIRROR are possible.
7776 * Access: RW
7777 */
7778 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
7779
7780 /* reg_ralue_trap_id
7781 * Trap ID to be reported to CPU.
7782 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
7783 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
7784 * Access: RW
7785 */
7786 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
7787
7788 /* reg_ralue_adjacency_index
7789 * Points to the first entry of the group-based ECMP.
7790 * Only relevant in case of REMOTE action.
7791 * Access: RW
7792 */
7793 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
7794
7795 /* reg_ralue_ecmp_size
7796 * Amount of sequential entries starting
7797 * from the adjacency_index (the number of ECMPs).
7798 * The valid range is 1-64, 512, 1024, 2048 and 4096.
7799 * Reserved when trap_action is TRAP or DISCARD_ERROR.
7800 * Only relevant in case of REMOTE action.
7801 * Access: RW
7802 */
7803 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
7804
7805 /* reg_ralue_local_erif
7806 * Egress Router Interface.
7807 * Only relevant in case of LOCAL action.
7808 * Access: RW
7809 */
7810 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
7811
7812 /* reg_ralue_ip2me_v
7813 * Valid bit for the tunnel_ptr field.
7814 * If valid = 0 then trap to CPU as IP2ME trap ID.
7815 * If valid = 1 and the packet format allows NVE or IPinIP tunnel
7816 * decapsulation then tunnel decapsulation is done.
7817 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
7818 * decapsulation then trap as IP2ME trap ID.
7819 * Only relevant in case of IP2ME action.
7820 * Access: RW
7821 */
7822 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
7823
7824 /* reg_ralue_ip2me_tunnel_ptr
7825 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
7826 * For Spectrum, pointer to KVD Linear.
7827 * Only relevant in case of IP2ME action.
7828 * Access: RW
7829 */
7830 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
7831
mlxsw_reg_ralue_pack(char * payload,enum mlxsw_reg_ralxx_protocol protocol,enum mlxsw_reg_ralue_op op,u16 virtual_router,u8 prefix_len)7832 static inline void mlxsw_reg_ralue_pack(char *payload,
7833 enum mlxsw_reg_ralxx_protocol protocol,
7834 enum mlxsw_reg_ralue_op op,
7835 u16 virtual_router, u8 prefix_len)
7836 {
7837 MLXSW_REG_ZERO(ralue, payload);
7838 mlxsw_reg_ralue_protocol_set(payload, protocol);
7839 mlxsw_reg_ralue_op_set(payload, op);
7840 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
7841 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
7842 mlxsw_reg_ralue_entry_type_set(payload,
7843 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
7844 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
7845 }
7846
mlxsw_reg_ralue_pack4(char * payload,enum mlxsw_reg_ralxx_protocol protocol,enum mlxsw_reg_ralue_op op,u16 virtual_router,u8 prefix_len,u32 * dip)7847 static inline void mlxsw_reg_ralue_pack4(char *payload,
7848 enum mlxsw_reg_ralxx_protocol protocol,
7849 enum mlxsw_reg_ralue_op op,
7850 u16 virtual_router, u8 prefix_len,
7851 u32 *dip)
7852 {
7853 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
7854 if (dip)
7855 mlxsw_reg_ralue_dip4_set(payload, *dip);
7856 }
7857
mlxsw_reg_ralue_pack6(char * payload,enum mlxsw_reg_ralxx_protocol protocol,enum mlxsw_reg_ralue_op op,u16 virtual_router,u8 prefix_len,const void * dip)7858 static inline void mlxsw_reg_ralue_pack6(char *payload,
7859 enum mlxsw_reg_ralxx_protocol protocol,
7860 enum mlxsw_reg_ralue_op op,
7861 u16 virtual_router, u8 prefix_len,
7862 const void *dip)
7863 {
7864 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
7865 if (dip)
7866 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
7867 }
7868
7869 static inline void
mlxsw_reg_ralue_act_remote_pack(char * payload,enum mlxsw_reg_ralue_trap_action trap_action,u16 trap_id,u32 adjacency_index,u16 ecmp_size)7870 mlxsw_reg_ralue_act_remote_pack(char *payload,
7871 enum mlxsw_reg_ralue_trap_action trap_action,
7872 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
7873 {
7874 mlxsw_reg_ralue_action_type_set(payload,
7875 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
7876 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7877 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7878 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
7879 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
7880 }
7881
7882 static inline void
mlxsw_reg_ralue_act_local_pack(char * payload,enum mlxsw_reg_ralue_trap_action trap_action,u16 trap_id,u16 local_erif)7883 mlxsw_reg_ralue_act_local_pack(char *payload,
7884 enum mlxsw_reg_ralue_trap_action trap_action,
7885 u16 trap_id, u16 local_erif)
7886 {
7887 mlxsw_reg_ralue_action_type_set(payload,
7888 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
7889 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7890 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7891 mlxsw_reg_ralue_local_erif_set(payload, local_erif);
7892 }
7893
7894 static inline void
mlxsw_reg_ralue_act_ip2me_pack(char * payload)7895 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
7896 {
7897 mlxsw_reg_ralue_action_type_set(payload,
7898 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7899 }
7900
7901 static inline void
mlxsw_reg_ralue_act_ip2me_tun_pack(char * payload,u32 tunnel_ptr)7902 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
7903 {
7904 mlxsw_reg_ralue_action_type_set(payload,
7905 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7906 mlxsw_reg_ralue_ip2me_v_set(payload, 1);
7907 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
7908 }
7909
7910 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
7911 * ----------------------------------------------------------
7912 * The RAUHT register is used to configure and query the Unicast Host table in
7913 * devices that implement the Algorithmic LPM.
7914 */
7915 #define MLXSW_REG_RAUHT_ID 0x8014
7916 #define MLXSW_REG_RAUHT_LEN 0x74
7917
7918 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
7919
7920 enum mlxsw_reg_rauht_type {
7921 MLXSW_REG_RAUHT_TYPE_IPV4,
7922 MLXSW_REG_RAUHT_TYPE_IPV6,
7923 };
7924
7925 /* reg_rauht_type
7926 * Access: Index
7927 */
7928 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
7929
7930 enum mlxsw_reg_rauht_op {
7931 MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
7932 /* Read operation */
7933 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
7934 /* Clear on read operation. Used to read entry and clear
7935 * activity bit.
7936 */
7937 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
7938 /* Add. Used to write a new entry to the table. All R/W fields are
7939 * relevant for new entry. Activity bit is set for new entries.
7940 */
7941 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
7942 /* Update action. Used to update an existing route entry and
7943 * only update the following fields:
7944 * trap_action, trap_id, mac, counter_set_type, counter_index
7945 */
7946 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
7947 /* Clear activity. A bit is cleared for the entry. */
7948 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
7949 /* Delete entry */
7950 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
7951 /* Delete all host entries on a RIF. In this command, dip
7952 * field is reserved.
7953 */
7954 };
7955
7956 /* reg_rauht_op
7957 * Access: OP
7958 */
7959 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
7960
7961 /* reg_rauht_a
7962 * Activity. Set for new entries. Set if a packet lookup has hit on
7963 * the specific entry.
7964 * To clear the a bit, use "clear activity" op.
7965 * Enabled by activity_dis in RGCR
7966 * Access: RO
7967 */
7968 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
7969
7970 /* reg_rauht_rif
7971 * Router Interface
7972 * Access: Index
7973 */
7974 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
7975
7976 /* reg_rauht_dip*
7977 * Destination address.
7978 * Access: Index
7979 */
7980 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
7981 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
7982
7983 enum mlxsw_reg_rauht_trap_action {
7984 MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
7985 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
7986 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
7987 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
7988 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
7989 };
7990
7991 /* reg_rauht_trap_action
7992 * Access: RW
7993 */
7994 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
7995
7996 enum mlxsw_reg_rauht_trap_id {
7997 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
7998 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
7999 };
8000
8001 /* reg_rauht_trap_id
8002 * Trap ID to be reported to CPU.
8003 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
8004 * For trap_action of NOP, MIRROR and DISCARD_ERROR,
8005 * trap_id is reserved.
8006 * Access: RW
8007 */
8008 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
8009
8010 /* reg_rauht_counter_set_type
8011 * Counter set type for flow counters
8012 * Access: RW
8013 */
8014 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
8015
8016 /* reg_rauht_counter_index
8017 * Counter index for flow counters
8018 * Access: RW
8019 */
8020 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
8021
8022 /* reg_rauht_mac
8023 * MAC address.
8024 * Access: RW
8025 */
8026 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
8027
mlxsw_reg_rauht_pack(char * payload,enum mlxsw_reg_rauht_op op,u16 rif,const char * mac)8028 static inline void mlxsw_reg_rauht_pack(char *payload,
8029 enum mlxsw_reg_rauht_op op, u16 rif,
8030 const char *mac)
8031 {
8032 MLXSW_REG_ZERO(rauht, payload);
8033 mlxsw_reg_rauht_op_set(payload, op);
8034 mlxsw_reg_rauht_rif_set(payload, rif);
8035 mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
8036 }
8037
mlxsw_reg_rauht_pack4(char * payload,enum mlxsw_reg_rauht_op op,u16 rif,const char * mac,u32 dip)8038 static inline void mlxsw_reg_rauht_pack4(char *payload,
8039 enum mlxsw_reg_rauht_op op, u16 rif,
8040 const char *mac, u32 dip)
8041 {
8042 mlxsw_reg_rauht_pack(payload, op, rif, mac);
8043 mlxsw_reg_rauht_dip4_set(payload, dip);
8044 }
8045
mlxsw_reg_rauht_pack6(char * payload,enum mlxsw_reg_rauht_op op,u16 rif,const char * mac,const char * dip)8046 static inline void mlxsw_reg_rauht_pack6(char *payload,
8047 enum mlxsw_reg_rauht_op op, u16 rif,
8048 const char *mac, const char *dip)
8049 {
8050 mlxsw_reg_rauht_pack(payload, op, rif, mac);
8051 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
8052 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
8053 }
8054
mlxsw_reg_rauht_pack_counter(char * payload,u64 counter_index)8055 static inline void mlxsw_reg_rauht_pack_counter(char *payload,
8056 u64 counter_index)
8057 {
8058 mlxsw_reg_rauht_counter_index_set(payload, counter_index);
8059 mlxsw_reg_rauht_counter_set_type_set(payload,
8060 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
8061 }
8062
8063 /* RALEU - Router Algorithmic LPM ECMP Update Register
8064 * ---------------------------------------------------
8065 * The register enables updating the ECMP section in the action for multiple
8066 * LPM Unicast entries in a single operation. The update is executed to
8067 * all entries of a {virtual router, protocol} tuple using the same ECMP group.
8068 */
8069 #define MLXSW_REG_RALEU_ID 0x8015
8070 #define MLXSW_REG_RALEU_LEN 0x28
8071
8072 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
8073
8074 /* reg_raleu_protocol
8075 * Protocol.
8076 * Access: Index
8077 */
8078 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
8079
8080 /* reg_raleu_virtual_router
8081 * Virtual Router ID
8082 * Range is 0..cap_max_virtual_routers-1
8083 * Access: Index
8084 */
8085 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
8086
8087 /* reg_raleu_adjacency_index
8088 * Adjacency Index used for matching on the existing entries.
8089 * Access: Index
8090 */
8091 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
8092
8093 /* reg_raleu_ecmp_size
8094 * ECMP Size used for matching on the existing entries.
8095 * Access: Index
8096 */
8097 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
8098
8099 /* reg_raleu_new_adjacency_index
8100 * New Adjacency Index.
8101 * Access: WO
8102 */
8103 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
8104
8105 /* reg_raleu_new_ecmp_size
8106 * New ECMP Size.
8107 * Access: WO
8108 */
8109 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
8110
mlxsw_reg_raleu_pack(char * payload,enum mlxsw_reg_ralxx_protocol protocol,u16 virtual_router,u32 adjacency_index,u16 ecmp_size,u32 new_adjacency_index,u16 new_ecmp_size)8111 static inline void mlxsw_reg_raleu_pack(char *payload,
8112 enum mlxsw_reg_ralxx_protocol protocol,
8113 u16 virtual_router,
8114 u32 adjacency_index, u16 ecmp_size,
8115 u32 new_adjacency_index,
8116 u16 new_ecmp_size)
8117 {
8118 MLXSW_REG_ZERO(raleu, payload);
8119 mlxsw_reg_raleu_protocol_set(payload, protocol);
8120 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
8121 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
8122 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
8123 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
8124 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
8125 }
8126
8127 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
8128 * ----------------------------------------------------------------
8129 * The RAUHTD register allows dumping entries from the Router Unicast Host
8130 * Table. For a given session an entry is dumped no more than one time. The
8131 * first RAUHTD access after reset is a new session. A session ends when the
8132 * num_rec response is smaller than num_rec request or for IPv4 when the
8133 * num_entries is smaller than 4. The clear activity affect the current session
8134 * or the last session if a new session has not started.
8135 */
8136 #define MLXSW_REG_RAUHTD_ID 0x8018
8137 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
8138 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
8139 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
8140 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
8141 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
8142 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
8143
8144 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
8145
8146 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
8147 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
8148
8149 /* reg_rauhtd_filter_fields
8150 * if a bit is '0' then the relevant field is ignored and dump is done
8151 * regardless of the field value
8152 * Bit0 - filter by activity: entry_a
8153 * Bit3 - filter by entry rip: entry_rif
8154 * Access: Index
8155 */
8156 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
8157
8158 enum mlxsw_reg_rauhtd_op {
8159 MLXSW_REG_RAUHTD_OP_DUMP,
8160 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
8161 };
8162
8163 /* reg_rauhtd_op
8164 * Access: OP
8165 */
8166 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
8167
8168 /* reg_rauhtd_num_rec
8169 * At request: number of records requested
8170 * At response: number of records dumped
8171 * For IPv4, each record has 4 entries at request and up to 4 entries
8172 * at response
8173 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
8174 * Access: Index
8175 */
8176 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
8177
8178 /* reg_rauhtd_entry_a
8179 * Dump only if activity has value of entry_a
8180 * Reserved if filter_fields bit0 is '0'
8181 * Access: Index
8182 */
8183 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
8184
8185 enum mlxsw_reg_rauhtd_type {
8186 MLXSW_REG_RAUHTD_TYPE_IPV4,
8187 MLXSW_REG_RAUHTD_TYPE_IPV6,
8188 };
8189
8190 /* reg_rauhtd_type
8191 * Dump only if record type is:
8192 * 0 - IPv4
8193 * 1 - IPv6
8194 * Access: Index
8195 */
8196 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
8197
8198 /* reg_rauhtd_entry_rif
8199 * Dump only if RIF has value of entry_rif
8200 * Reserved if filter_fields bit3 is '0'
8201 * Access: Index
8202 */
8203 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
8204
mlxsw_reg_rauhtd_pack(char * payload,enum mlxsw_reg_rauhtd_type type)8205 static inline void mlxsw_reg_rauhtd_pack(char *payload,
8206 enum mlxsw_reg_rauhtd_type type)
8207 {
8208 MLXSW_REG_ZERO(rauhtd, payload);
8209 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
8210 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
8211 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
8212 mlxsw_reg_rauhtd_entry_a_set(payload, 1);
8213 mlxsw_reg_rauhtd_type_set(payload, type);
8214 }
8215
8216 /* reg_rauhtd_ipv4_rec_num_entries
8217 * Number of valid entries in this record:
8218 * 0 - 1 valid entry
8219 * 1 - 2 valid entries
8220 * 2 - 3 valid entries
8221 * 3 - 4 valid entries
8222 * Access: RO
8223 */
8224 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
8225 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
8226 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
8227
8228 /* reg_rauhtd_rec_type
8229 * Record type.
8230 * 0 - IPv4
8231 * 1 - IPv6
8232 * Access: RO
8233 */
8234 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
8235 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
8236
8237 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
8238
8239 /* reg_rauhtd_ipv4_ent_a
8240 * Activity. Set for new entries. Set if a packet lookup has hit on the
8241 * specific entry.
8242 * Access: RO
8243 */
8244 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
8245 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
8246
8247 /* reg_rauhtd_ipv4_ent_rif
8248 * Router interface.
8249 * Access: RO
8250 */
8251 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8252 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
8253
8254 /* reg_rauhtd_ipv4_ent_dip
8255 * Destination IPv4 address.
8256 * Access: RO
8257 */
8258 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8259 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
8260
8261 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
8262
8263 /* reg_rauhtd_ipv6_ent_a
8264 * Activity. Set for new entries. Set if a packet lookup has hit on the
8265 * specific entry.
8266 * Access: RO
8267 */
8268 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
8269 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
8270
8271 /* reg_rauhtd_ipv6_ent_rif
8272 * Router interface.
8273 * Access: RO
8274 */
8275 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8276 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
8277
8278 /* reg_rauhtd_ipv6_ent_dip
8279 * Destination IPv6 address.
8280 * Access: RO
8281 */
8282 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
8283 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
8284
mlxsw_reg_rauhtd_ent_ipv4_unpack(char * payload,int ent_index,u16 * p_rif,u32 * p_dip)8285 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
8286 int ent_index, u16 *p_rif,
8287 u32 *p_dip)
8288 {
8289 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
8290 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
8291 }
8292
mlxsw_reg_rauhtd_ent_ipv6_unpack(char * payload,int rec_index,u16 * p_rif,char * p_dip)8293 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
8294 int rec_index, u16 *p_rif,
8295 char *p_dip)
8296 {
8297 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
8298 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
8299 }
8300
8301 /* RTDP - Routing Tunnel Decap Properties Register
8302 * -----------------------------------------------
8303 * The RTDP register is used for configuring the tunnel decap properties of NVE
8304 * and IPinIP.
8305 */
8306 #define MLXSW_REG_RTDP_ID 0x8020
8307 #define MLXSW_REG_RTDP_LEN 0x44
8308
8309 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
8310
8311 enum mlxsw_reg_rtdp_type {
8312 MLXSW_REG_RTDP_TYPE_NVE,
8313 MLXSW_REG_RTDP_TYPE_IPIP,
8314 };
8315
8316 /* reg_rtdp_type
8317 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type.
8318 * Access: RW
8319 */
8320 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
8321
8322 /* reg_rtdp_tunnel_index
8323 * Index to the Decap entry.
8324 * For Spectrum, Index to KVD Linear.
8325 * Access: Index
8326 */
8327 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
8328
8329 /* reg_rtdp_egress_router_interface
8330 * Underlay egress router interface.
8331 * Valid range is from 0 to cap_max_router_interfaces - 1
8332 * Access: RW
8333 */
8334 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
8335
8336 /* IPinIP */
8337
8338 /* reg_rtdp_ipip_irif
8339 * Ingress Router Interface for the overlay router
8340 * Access: RW
8341 */
8342 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
8343
8344 enum mlxsw_reg_rtdp_ipip_sip_check {
8345 /* No sip checks. */
8346 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
8347 /* Filter packet if underlay is not IPv4 or if underlay SIP does not
8348 * equal ipv4_usip.
8349 */
8350 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
8351 /* Filter packet if underlay is not IPv6 or if underlay SIP does not
8352 * equal ipv6_usip.
8353 */
8354 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
8355 };
8356
8357 /* reg_rtdp_ipip_sip_check
8358 * SIP check to perform. If decapsulation failed due to these configurations
8359 * then trap_id is IPIP_DECAP_ERROR.
8360 * Access: RW
8361 */
8362 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
8363
8364 /* If set, allow decapsulation of IPinIP (without GRE). */
8365 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0)
8366 /* If set, allow decapsulation of IPinGREinIP without a key. */
8367 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1)
8368 /* If set, allow decapsulation of IPinGREinIP with a key. */
8369 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2)
8370
8371 /* reg_rtdp_ipip_type_check
8372 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to
8373 * these configurations then trap_id is IPIP_DECAP_ERROR.
8374 * Access: RW
8375 */
8376 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
8377
8378 /* reg_rtdp_ipip_gre_key_check
8379 * Whether GRE key should be checked. When check is enabled:
8380 * - A packet received as IPinIP (without GRE) will always pass.
8381 * - A packet received as IPinGREinIP without a key will not pass the check.
8382 * - A packet received as IPinGREinIP with a key will pass the check only if the
8383 * key in the packet is equal to expected_gre_key.
8384 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR.
8385 * Access: RW
8386 */
8387 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
8388
8389 /* reg_rtdp_ipip_ipv4_usip
8390 * Underlay IPv4 address for ipv4 source address check.
8391 * Reserved when sip_check is not '1'.
8392 * Access: RW
8393 */
8394 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
8395
8396 /* reg_rtdp_ipip_ipv6_usip_ptr
8397 * This field is valid when sip_check is "sipv6 check explicitly". This is a
8398 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index
8399 * is to the KVD linear.
8400 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6.
8401 * Access: RW
8402 */
8403 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
8404
8405 /* reg_rtdp_ipip_expected_gre_key
8406 * GRE key for checking.
8407 * Reserved when gre_key_check is '0'.
8408 * Access: RW
8409 */
8410 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
8411
mlxsw_reg_rtdp_pack(char * payload,enum mlxsw_reg_rtdp_type type,u32 tunnel_index)8412 static inline void mlxsw_reg_rtdp_pack(char *payload,
8413 enum mlxsw_reg_rtdp_type type,
8414 u32 tunnel_index)
8415 {
8416 MLXSW_REG_ZERO(rtdp, payload);
8417 mlxsw_reg_rtdp_type_set(payload, type);
8418 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
8419 }
8420
8421 static inline void
mlxsw_reg_rtdp_ipip_pack(char * payload,u16 irif,enum mlxsw_reg_rtdp_ipip_sip_check sip_check,unsigned int type_check,bool gre_key_check,u32 expected_gre_key)8422 mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif,
8423 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
8424 unsigned int type_check, bool gre_key_check,
8425 u32 expected_gre_key)
8426 {
8427 mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
8428 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
8429 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
8430 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
8431 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
8432 }
8433
8434 static inline void
mlxsw_reg_rtdp_ipip4_pack(char * payload,u16 irif,enum mlxsw_reg_rtdp_ipip_sip_check sip_check,unsigned int type_check,bool gre_key_check,u32 ipv4_usip,u32 expected_gre_key)8435 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
8436 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
8437 unsigned int type_check, bool gre_key_check,
8438 u32 ipv4_usip, u32 expected_gre_key)
8439 {
8440 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check,
8441 gre_key_check, expected_gre_key);
8442 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
8443 }
8444
8445 static inline void
mlxsw_reg_rtdp_ipip6_pack(char * payload,u16 irif,enum mlxsw_reg_rtdp_ipip_sip_check sip_check,unsigned int type_check,bool gre_key_check,u32 ipv6_usip_ptr,u32 expected_gre_key)8446 mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif,
8447 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
8448 unsigned int type_check, bool gre_key_check,
8449 u32 ipv6_usip_ptr, u32 expected_gre_key)
8450 {
8451 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check,
8452 gre_key_check, expected_gre_key);
8453 mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr);
8454 }
8455
8456 /* RIPS - Router IP version Six Register
8457 * -------------------------------------
8458 * The RIPS register is used to store IPv6 addresses for use by the NVE and
8459 * IPinIP
8460 */
8461 #define MLXSW_REG_RIPS_ID 0x8021
8462 #define MLXSW_REG_RIPS_LEN 0x14
8463
8464 MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN);
8465
8466 /* reg_rips_index
8467 * Index to IPv6 address.
8468 * For Spectrum, the index is to the KVD linear.
8469 * Access: Index
8470 */
8471 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24);
8472
8473 /* reg_rips_ipv6
8474 * IPv6 address
8475 * Access: RW
8476 */
8477 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16);
8478
mlxsw_reg_rips_pack(char * payload,u32 index,const struct in6_addr * ipv6)8479 static inline void mlxsw_reg_rips_pack(char *payload, u32 index,
8480 const struct in6_addr *ipv6)
8481 {
8482 MLXSW_REG_ZERO(rips, payload);
8483 mlxsw_reg_rips_index_set(payload, index);
8484 mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6);
8485 }
8486
8487 /* RATRAD - Router Adjacency Table Activity Dump Register
8488 * ------------------------------------------------------
8489 * The RATRAD register is used to dump and optionally clear activity bits of
8490 * router adjacency table entries.
8491 */
8492 #define MLXSW_REG_RATRAD_ID 0x8022
8493 #define MLXSW_REG_RATRAD_LEN 0x210
8494
8495 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN);
8496
8497 enum {
8498 /* Read activity */
8499 MLXSW_REG_RATRAD_OP_READ_ACTIVITY,
8500 /* Read and clear activity */
8501 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY,
8502 };
8503
8504 /* reg_ratrad_op
8505 * Access: Operation
8506 */
8507 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2);
8508
8509 /* reg_ratrad_ecmp_size
8510 * ecmp_size is the amount of sequential entries from adjacency_index. Valid
8511 * ranges:
8512 * Spectrum-1: 32-64, 512, 1024, 2048, 4096
8513 * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096
8514 * Access: Index
8515 */
8516 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13);
8517
8518 /* reg_ratrad_adjacency_index
8519 * Index into the adjacency table.
8520 * Access: Index
8521 */
8522 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24);
8523
8524 /* reg_ratrad_activity_vector
8525 * Activity bit per adjacency index.
8526 * Bits higher than ecmp_size are reserved.
8527 * Access: RO
8528 */
8529 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1);
8530
mlxsw_reg_ratrad_pack(char * payload,u32 adjacency_index,u16 ecmp_size)8531 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index,
8532 u16 ecmp_size)
8533 {
8534 MLXSW_REG_ZERO(ratrad, payload);
8535 mlxsw_reg_ratrad_op_set(payload,
8536 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY);
8537 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size);
8538 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index);
8539 }
8540
8541 /* RIGR-V2 - Router Interface Group Register Version 2
8542 * ---------------------------------------------------
8543 * The RIGR_V2 register is used to add, remove and query egress interface list
8544 * of a multicast forwarding entry.
8545 */
8546 #define MLXSW_REG_RIGR2_ID 0x8023
8547 #define MLXSW_REG_RIGR2_LEN 0xB0
8548
8549 #define MLXSW_REG_RIGR2_MAX_ERIFS 32
8550
8551 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
8552
8553 /* reg_rigr2_rigr_index
8554 * KVD Linear index.
8555 * Access: Index
8556 */
8557 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
8558
8559 /* reg_rigr2_vnext
8560 * Next RIGR Index is valid.
8561 * Access: RW
8562 */
8563 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
8564
8565 /* reg_rigr2_next_rigr_index
8566 * Next RIGR Index. The index is to the KVD linear.
8567 * Reserved when vnxet = '0'.
8568 * Access: RW
8569 */
8570 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
8571
8572 /* reg_rigr2_vrmid
8573 * RMID Index is valid.
8574 * Access: RW
8575 */
8576 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
8577
8578 /* reg_rigr2_rmid_index
8579 * RMID Index.
8580 * Range 0 .. max_mid - 1
8581 * Reserved when vrmid = '0'.
8582 * The index is to the Port Group Table (PGT)
8583 * Access: RW
8584 */
8585 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
8586
8587 /* reg_rigr2_erif_entry_v
8588 * Egress Router Interface is valid.
8589 * Note that low-entries must be set if high-entries are set. For
8590 * example: if erif_entry[2].v is set then erif_entry[1].v and
8591 * erif_entry[0].v must be set.
8592 * Index can be from 0 to cap_mc_erif_list_entries-1
8593 * Access: RW
8594 */
8595 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
8596
8597 /* reg_rigr2_erif_entry_erif
8598 * Egress Router Interface.
8599 * Valid range is from 0 to cap_max_router_interfaces - 1
8600 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1
8601 * Access: RW
8602 */
8603 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
8604
mlxsw_reg_rigr2_pack(char * payload,u32 rigr_index,bool vnext,u32 next_rigr_index)8605 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
8606 bool vnext, u32 next_rigr_index)
8607 {
8608 MLXSW_REG_ZERO(rigr2, payload);
8609 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
8610 mlxsw_reg_rigr2_vnext_set(payload, vnext);
8611 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
8612 mlxsw_reg_rigr2_vrmid_set(payload, 0);
8613 mlxsw_reg_rigr2_rmid_index_set(payload, 0);
8614 }
8615
mlxsw_reg_rigr2_erif_entry_pack(char * payload,int index,bool v,u16 erif)8616 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
8617 bool v, u16 erif)
8618 {
8619 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
8620 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
8621 }
8622
8623 /* RECR-V2 - Router ECMP Configuration Version 2 Register
8624 * ------------------------------------------------------
8625 */
8626 #define MLXSW_REG_RECR2_ID 0x8025
8627 #define MLXSW_REG_RECR2_LEN 0x38
8628
8629 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
8630
8631 /* reg_recr2_pp
8632 * Per-port configuration
8633 * Access: Index
8634 */
8635 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
8636
8637 /* reg_recr2_sh
8638 * Symmetric hash
8639 * Access: RW
8640 */
8641 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
8642
8643 /* reg_recr2_seed
8644 * Seed
8645 * Access: RW
8646 */
8647 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
8648
8649 enum {
8650 /* Enable IPv4 fields if packet is not TCP and not UDP */
8651 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3,
8652 /* Enable IPv4 fields if packet is TCP or UDP */
8653 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4,
8654 /* Enable IPv6 fields if packet is not TCP and not UDP */
8655 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5,
8656 /* Enable IPv6 fields if packet is TCP or UDP */
8657 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6,
8658 /* Enable TCP/UDP header fields if packet is IPv4 */
8659 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7,
8660 /* Enable TCP/UDP header fields if packet is IPv6 */
8661 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8,
8662
8663 __MLXSW_REG_RECR2_HEADER_CNT,
8664 };
8665
8666 /* reg_recr2_outer_header_enables
8667 * Bit mask where each bit enables a specific layer to be included in
8668 * the hash calculation.
8669 * Access: RW
8670 */
8671 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
8672
8673 enum {
8674 /* IPv4 Source IP */
8675 MLXSW_REG_RECR2_IPV4_SIP0 = 9,
8676 MLXSW_REG_RECR2_IPV4_SIP3 = 12,
8677 /* IPv4 Destination IP */
8678 MLXSW_REG_RECR2_IPV4_DIP0 = 13,
8679 MLXSW_REG_RECR2_IPV4_DIP3 = 16,
8680 /* IP Protocol */
8681 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17,
8682 /* IPv6 Source IP */
8683 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21,
8684 MLXSW_REG_RECR2_IPV6_SIP8 = 29,
8685 MLXSW_REG_RECR2_IPV6_SIP15 = 36,
8686 /* IPv6 Destination IP */
8687 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37,
8688 MLXSW_REG_RECR2_IPV6_DIP8 = 45,
8689 MLXSW_REG_RECR2_IPV6_DIP15 = 52,
8690 /* IPv6 Next Header */
8691 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53,
8692 /* IPv6 Flow Label */
8693 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57,
8694 /* TCP/UDP Source Port */
8695 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74,
8696 /* TCP/UDP Destination Port */
8697 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75,
8698
8699 __MLXSW_REG_RECR2_FIELD_CNT,
8700 };
8701
8702 /* reg_recr2_outer_header_fields_enable
8703 * Packet fields to enable for ECMP hash subject to outer_header_enable.
8704 * Access: RW
8705 */
8706 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
8707
8708 /* reg_recr2_inner_header_enables
8709 * Bit mask where each bit enables a specific inner layer to be included in the
8710 * hash calculation. Same values as reg_recr2_outer_header_enables.
8711 * Access: RW
8712 */
8713 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1);
8714
8715 enum {
8716 /* Inner IPv4 Source IP */
8717 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3,
8718 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6,
8719 /* Inner IPv4 Destination IP */
8720 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7,
8721 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10,
8722 /* Inner IP Protocol */
8723 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11,
8724 /* Inner IPv6 Source IP */
8725 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12,
8726 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20,
8727 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27,
8728 /* Inner IPv6 Destination IP */
8729 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28,
8730 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36,
8731 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43,
8732 /* Inner IPv6 Next Header */
8733 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44,
8734 /* Inner IPv6 Flow Label */
8735 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45,
8736 /* Inner TCP/UDP Source Port */
8737 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46,
8738 /* Inner TCP/UDP Destination Port */
8739 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47,
8740
8741 __MLXSW_REG_RECR2_INNER_FIELD_CNT,
8742 };
8743
8744 /* reg_recr2_inner_header_fields_enable
8745 * Inner packet fields to enable for ECMP hash subject to inner_header_enables.
8746 * Access: RW
8747 */
8748 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1);
8749
mlxsw_reg_recr2_pack(char * payload,u32 seed)8750 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
8751 {
8752 MLXSW_REG_ZERO(recr2, payload);
8753 mlxsw_reg_recr2_pp_set(payload, false);
8754 mlxsw_reg_recr2_sh_set(payload, true);
8755 mlxsw_reg_recr2_seed_set(payload, seed);
8756 }
8757
8758 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register
8759 * --------------------------------------------------------------
8760 * The RMFT_V2 register is used to configure and query the multicast table.
8761 */
8762 #define MLXSW_REG_RMFT2_ID 0x8027
8763 #define MLXSW_REG_RMFT2_LEN 0x174
8764
8765 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
8766
8767 /* reg_rmft2_v
8768 * Valid
8769 * Access: RW
8770 */
8771 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
8772
8773 enum mlxsw_reg_rmft2_type {
8774 MLXSW_REG_RMFT2_TYPE_IPV4,
8775 MLXSW_REG_RMFT2_TYPE_IPV6
8776 };
8777
8778 /* reg_rmft2_type
8779 * Access: Index
8780 */
8781 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
8782
8783 enum mlxsw_sp_reg_rmft2_op {
8784 /* For Write:
8785 * Write operation. Used to write a new entry to the table. All RW
8786 * fields are relevant for new entry. Activity bit is set for new
8787 * entries - Note write with v (Valid) 0 will delete the entry.
8788 * For Query:
8789 * Read operation
8790 */
8791 MLXSW_REG_RMFT2_OP_READ_WRITE,
8792 };
8793
8794 /* reg_rmft2_op
8795 * Operation.
8796 * Access: OP
8797 */
8798 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
8799
8800 /* reg_rmft2_a
8801 * Activity. Set for new entries. Set if a packet lookup has hit on the specific
8802 * entry.
8803 * Access: RO
8804 */
8805 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
8806
8807 /* reg_rmft2_offset
8808 * Offset within the multicast forwarding table to write to.
8809 * Access: Index
8810 */
8811 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
8812
8813 /* reg_rmft2_virtual_router
8814 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1
8815 * Access: RW
8816 */
8817 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
8818
8819 enum mlxsw_reg_rmft2_irif_mask {
8820 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
8821 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
8822 };
8823
8824 /* reg_rmft2_irif_mask
8825 * Ingress RIF mask.
8826 * Access: RW
8827 */
8828 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
8829
8830 /* reg_rmft2_irif
8831 * Ingress RIF index.
8832 * Access: RW
8833 */
8834 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
8835
8836 /* reg_rmft2_dip{4,6}
8837 * Destination IPv4/6 address
8838 * Access: RW
8839 */
8840 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
8841 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
8842
8843 /* reg_rmft2_dip{4,6}_mask
8844 * A bit that is set directs the TCAM to compare the corresponding bit in key. A
8845 * bit that is clear directs the TCAM to ignore the corresponding bit in key.
8846 * Access: RW
8847 */
8848 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
8849 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
8850
8851 /* reg_rmft2_sip{4,6}
8852 * Source IPv4/6 address
8853 * Access: RW
8854 */
8855 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
8856 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
8857
8858 /* reg_rmft2_sip{4,6}_mask
8859 * A bit that is set directs the TCAM to compare the corresponding bit in key. A
8860 * bit that is clear directs the TCAM to ignore the corresponding bit in key.
8861 * Access: RW
8862 */
8863 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
8864 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
8865
8866 /* reg_rmft2_flexible_action_set
8867 * ACL action set. The only supported action types in this field and in any
8868 * action-set pointed from here are as follows:
8869 * 00h: ACTION_NULL
8870 * 01h: ACTION_MAC_TTL, only TTL configuration is supported.
8871 * 03h: ACTION_TRAP
8872 * 06h: ACTION_QOS
8873 * 08h: ACTION_POLICING_MONITORING
8874 * 10h: ACTION_ROUTER_MC
8875 * Access: RW
8876 */
8877 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
8878 MLXSW_REG_FLEX_ACTION_SET_LEN);
8879
8880 static inline void
mlxsw_reg_rmft2_common_pack(char * payload,bool v,u16 offset,u16 virtual_router,enum mlxsw_reg_rmft2_irif_mask irif_mask,u16 irif,const char * flex_action_set)8881 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
8882 u16 virtual_router,
8883 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8884 const char *flex_action_set)
8885 {
8886 MLXSW_REG_ZERO(rmft2, payload);
8887 mlxsw_reg_rmft2_v_set(payload, v);
8888 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
8889 mlxsw_reg_rmft2_offset_set(payload, offset);
8890 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
8891 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
8892 mlxsw_reg_rmft2_irif_set(payload, irif);
8893 if (flex_action_set)
8894 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
8895 flex_action_set);
8896 }
8897
8898 static inline void
mlxsw_reg_rmft2_ipv4_pack(char * payload,bool v,u16 offset,u16 virtual_router,enum mlxsw_reg_rmft2_irif_mask irif_mask,u16 irif,u32 dip4,u32 dip4_mask,u32 sip4,u32 sip4_mask,const char * flexible_action_set)8899 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
8900 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8901 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
8902 const char *flexible_action_set)
8903 {
8904 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
8905 irif_mask, irif, flexible_action_set);
8906 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
8907 mlxsw_reg_rmft2_dip4_set(payload, dip4);
8908 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
8909 mlxsw_reg_rmft2_sip4_set(payload, sip4);
8910 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
8911 }
8912
8913 static inline void
mlxsw_reg_rmft2_ipv6_pack(char * payload,bool v,u16 offset,u16 virtual_router,enum mlxsw_reg_rmft2_irif_mask irif_mask,u16 irif,struct in6_addr dip6,struct in6_addr dip6_mask,struct in6_addr sip6,struct in6_addr sip6_mask,const char * flexible_action_set)8914 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
8915 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8916 struct in6_addr dip6, struct in6_addr dip6_mask,
8917 struct in6_addr sip6, struct in6_addr sip6_mask,
8918 const char *flexible_action_set)
8919 {
8920 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
8921 irif_mask, irif, flexible_action_set);
8922 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
8923 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
8924 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
8925 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
8926 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
8927 }
8928
8929 /* RXLTE - Router XLT Enable Register
8930 * ----------------------------------
8931 * The RXLTE enables XLT (eXtended Lookup Table) LPM lookups if a capable
8932 * XM is present on the system.
8933 */
8934
8935 #define MLXSW_REG_RXLTE_ID 0x8050
8936 #define MLXSW_REG_RXLTE_LEN 0x0C
8937
8938 MLXSW_REG_DEFINE(rxlte, MLXSW_REG_RXLTE_ID, MLXSW_REG_RXLTE_LEN);
8939
8940 /* reg_rxlte_virtual_router
8941 * Virtual router ID associated with the router interface.
8942 * Range is 0..cap_max_virtual_routers-1
8943 * Access: Index
8944 */
8945 MLXSW_ITEM32(reg, rxlte, virtual_router, 0x00, 0, 16);
8946
8947 enum mlxsw_reg_rxlte_protocol {
8948 MLXSW_REG_RXLTE_PROTOCOL_IPV4,
8949 MLXSW_REG_RXLTE_PROTOCOL_IPV6,
8950 };
8951
8952 /* reg_rxlte_protocol
8953 * Access: Index
8954 */
8955 MLXSW_ITEM32(reg, rxlte, protocol, 0x04, 0, 4);
8956
8957 /* reg_rxlte_lpm_xlt_en
8958 * Access: RW
8959 */
8960 MLXSW_ITEM32(reg, rxlte, lpm_xlt_en, 0x08, 0, 1);
8961
mlxsw_reg_rxlte_pack(char * payload,u16 virtual_router,enum mlxsw_reg_rxlte_protocol protocol,bool lpm_xlt_en)8962 static inline void mlxsw_reg_rxlte_pack(char *payload, u16 virtual_router,
8963 enum mlxsw_reg_rxlte_protocol protocol,
8964 bool lpm_xlt_en)
8965 {
8966 MLXSW_REG_ZERO(rxlte, payload);
8967 mlxsw_reg_rxlte_virtual_router_set(payload, virtual_router);
8968 mlxsw_reg_rxlte_protocol_set(payload, protocol);
8969 mlxsw_reg_rxlte_lpm_xlt_en_set(payload, lpm_xlt_en);
8970 }
8971
8972 /* RXLTM - Router XLT M select Register
8973 * ------------------------------------
8974 * The RXLTM configures and selects the M for the XM lookups.
8975 */
8976
8977 #define MLXSW_REG_RXLTM_ID 0x8051
8978 #define MLXSW_REG_RXLTM_LEN 0x14
8979
8980 MLXSW_REG_DEFINE(rxltm, MLXSW_REG_RXLTM_ID, MLXSW_REG_RXLTM_LEN);
8981
8982 /* reg_rxltm_m0_val_v6
8983 * Global M0 value For IPv6.
8984 * Range 0..128
8985 * Access: RW
8986 */
8987 MLXSW_ITEM32(reg, rxltm, m0_val_v6, 0x10, 16, 8);
8988
8989 /* reg_rxltm_m0_val_v4
8990 * Global M0 value For IPv4.
8991 * Range 0..32
8992 * Access: RW
8993 */
8994 MLXSW_ITEM32(reg, rxltm, m0_val_v4, 0x10, 0, 6);
8995
mlxsw_reg_rxltm_pack(char * payload,u8 m0_val_v4,u8 m0_val_v6)8996 static inline void mlxsw_reg_rxltm_pack(char *payload, u8 m0_val_v4, u8 m0_val_v6)
8997 {
8998 MLXSW_REG_ZERO(rxltm, payload);
8999 mlxsw_reg_rxltm_m0_val_v6_set(payload, m0_val_v6);
9000 mlxsw_reg_rxltm_m0_val_v4_set(payload, m0_val_v4);
9001 }
9002
9003 /* RLCMLD - Router LPM Cache ML Delete Register
9004 * --------------------------------------------
9005 * The RLCMLD register is used to bulk delete the XLT-LPM cache ML entries.
9006 * This can be used by SW when L is increased or decreased, thus need to
9007 * remove entries with old ML values.
9008 */
9009
9010 #define MLXSW_REG_RLCMLD_ID 0x8055
9011 #define MLXSW_REG_RLCMLD_LEN 0x30
9012
9013 MLXSW_REG_DEFINE(rlcmld, MLXSW_REG_RLCMLD_ID, MLXSW_REG_RLCMLD_LEN);
9014
9015 enum mlxsw_reg_rlcmld_select {
9016 MLXSW_REG_RLCMLD_SELECT_ML_ENTRIES,
9017 MLXSW_REG_RLCMLD_SELECT_M_ENTRIES,
9018 MLXSW_REG_RLCMLD_SELECT_M_AND_ML_ENTRIES,
9019 };
9020
9021 /* reg_rlcmld_select
9022 * Which entries to delete.
9023 * Access: Index
9024 */
9025 MLXSW_ITEM32(reg, rlcmld, select, 0x00, 16, 2);
9026
9027 enum mlxsw_reg_rlcmld_filter_fields {
9028 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_PROTOCOL = 0x04,
9029 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_VIRTUAL_ROUTER = 0x08,
9030 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_DIP = 0x10,
9031 };
9032
9033 /* reg_rlcmld_filter_fields
9034 * If a bit is '0' then the relevant field is ignored.
9035 * Access: Index
9036 */
9037 MLXSW_ITEM32(reg, rlcmld, filter_fields, 0x00, 0, 8);
9038
9039 enum mlxsw_reg_rlcmld_protocol {
9040 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV4,
9041 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV6,
9042 };
9043
9044 /* reg_rlcmld_protocol
9045 * Access: Index
9046 */
9047 MLXSW_ITEM32(reg, rlcmld, protocol, 0x08, 0, 4);
9048
9049 /* reg_rlcmld_virtual_router
9050 * Virtual router ID.
9051 * Range is 0..cap_max_virtual_routers-1
9052 * Access: Index
9053 */
9054 MLXSW_ITEM32(reg, rlcmld, virtual_router, 0x0C, 0, 16);
9055
9056 /* reg_rlcmld_dip
9057 * The prefix of the route or of the marker that the object of the LPM
9058 * is compared with. The most significant bits of the dip are the prefix.
9059 * Access: Index
9060 */
9061 MLXSW_ITEM32(reg, rlcmld, dip4, 0x1C, 0, 32);
9062 MLXSW_ITEM_BUF(reg, rlcmld, dip6, 0x10, 16);
9063
9064 /* reg_rlcmld_dip_mask
9065 * per bit:
9066 * 0: no match
9067 * 1: match
9068 * Access: Index
9069 */
9070 MLXSW_ITEM32(reg, rlcmld, dip_mask4, 0x2C, 0, 32);
9071 MLXSW_ITEM_BUF(reg, rlcmld, dip_mask6, 0x20, 16);
9072
__mlxsw_reg_rlcmld_pack(char * payload,enum mlxsw_reg_rlcmld_select select,enum mlxsw_reg_rlcmld_protocol protocol,u16 virtual_router)9073 static inline void __mlxsw_reg_rlcmld_pack(char *payload,
9074 enum mlxsw_reg_rlcmld_select select,
9075 enum mlxsw_reg_rlcmld_protocol protocol,
9076 u16 virtual_router)
9077 {
9078 u8 filter_fields = MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_PROTOCOL |
9079 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_VIRTUAL_ROUTER |
9080 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_DIP;
9081
9082 MLXSW_REG_ZERO(rlcmld, payload);
9083 mlxsw_reg_rlcmld_select_set(payload, select);
9084 mlxsw_reg_rlcmld_filter_fields_set(payload, filter_fields);
9085 mlxsw_reg_rlcmld_protocol_set(payload, protocol);
9086 mlxsw_reg_rlcmld_virtual_router_set(payload, virtual_router);
9087 }
9088
mlxsw_reg_rlcmld_pack4(char * payload,enum mlxsw_reg_rlcmld_select select,u16 virtual_router,u32 dip,u32 dip_mask)9089 static inline void mlxsw_reg_rlcmld_pack4(char *payload,
9090 enum mlxsw_reg_rlcmld_select select,
9091 u16 virtual_router,
9092 u32 dip, u32 dip_mask)
9093 {
9094 __mlxsw_reg_rlcmld_pack(payload, select,
9095 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV4,
9096 virtual_router);
9097 mlxsw_reg_rlcmld_dip4_set(payload, dip);
9098 mlxsw_reg_rlcmld_dip_mask4_set(payload, dip_mask);
9099 }
9100
mlxsw_reg_rlcmld_pack6(char * payload,enum mlxsw_reg_rlcmld_select select,u16 virtual_router,const void * dip,const void * dip_mask)9101 static inline void mlxsw_reg_rlcmld_pack6(char *payload,
9102 enum mlxsw_reg_rlcmld_select select,
9103 u16 virtual_router,
9104 const void *dip, const void *dip_mask)
9105 {
9106 __mlxsw_reg_rlcmld_pack(payload, select,
9107 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV6,
9108 virtual_router);
9109 mlxsw_reg_rlcmld_dip6_memcpy_to(payload, dip);
9110 mlxsw_reg_rlcmld_dip_mask6_memcpy_to(payload, dip_mask);
9111 }
9112
9113 /* RLPMCE - Router LPM Cache Enable Register
9114 * -----------------------------------------
9115 * Allows disabling the LPM cache. Can be changed on the fly.
9116 */
9117
9118 #define MLXSW_REG_RLPMCE_ID 0x8056
9119 #define MLXSW_REG_RLPMCE_LEN 0x4
9120
9121 MLXSW_REG_DEFINE(rlpmce, MLXSW_REG_RLPMCE_ID, MLXSW_REG_RLPMCE_LEN);
9122
9123 /* reg_rlpmce_flush
9124 * Flush:
9125 * 0: do not flush the cache (default)
9126 * 1: flush (clear) the cache
9127 * Access: WO
9128 */
9129 MLXSW_ITEM32(reg, rlpmce, flush, 0x00, 4, 1);
9130
9131 /* reg_rlpmce_disable
9132 * LPM cache:
9133 * 0: enabled (default)
9134 * 1: disabled
9135 * Access: RW
9136 */
9137 MLXSW_ITEM32(reg, rlpmce, disable, 0x00, 0, 1);
9138
mlxsw_reg_rlpmce_pack(char * payload,bool flush,bool disable)9139 static inline void mlxsw_reg_rlpmce_pack(char *payload, bool flush,
9140 bool disable)
9141 {
9142 MLXSW_REG_ZERO(rlpmce, payload);
9143 mlxsw_reg_rlpmce_flush_set(payload, flush);
9144 mlxsw_reg_rlpmce_disable_set(payload, disable);
9145 }
9146
9147 /* Note that XLTQ, XMDR, XRMT and XRALXX register positions violate the rule
9148 * of ordering register definitions by the ID. However, XRALXX pack helpers are
9149 * using RALXX pack helpers, RALXX registers have higher IDs.
9150 * Also XMDR is using RALUE enums. XLRQ and XRMT are just put alongside with the
9151 * related registers.
9152 */
9153
9154 /* XLTQ - XM Lookup Table Query Register
9155 * -------------------------------------
9156 */
9157 #define MLXSW_REG_XLTQ_ID 0x7802
9158 #define MLXSW_REG_XLTQ_LEN 0x2C
9159
9160 MLXSW_REG_DEFINE(xltq, MLXSW_REG_XLTQ_ID, MLXSW_REG_XLTQ_LEN);
9161
9162 enum mlxsw_reg_xltq_xm_device_id {
9163 MLXSW_REG_XLTQ_XM_DEVICE_ID_UNKNOWN,
9164 MLXSW_REG_XLTQ_XM_DEVICE_ID_XLT = 0xCF71,
9165 };
9166
9167 /* reg_xltq_xm_device_id
9168 * XM device ID.
9169 * Access: RO
9170 */
9171 MLXSW_ITEM32(reg, xltq, xm_device_id, 0x04, 0, 16);
9172
9173 /* reg_xltq_xlt_cap_ipv4_lpm
9174 * Access: RO
9175 */
9176 MLXSW_ITEM32(reg, xltq, xlt_cap_ipv4_lpm, 0x10, 0, 1);
9177
9178 /* reg_xltq_xlt_cap_ipv6_lpm
9179 * Access: RO
9180 */
9181 MLXSW_ITEM32(reg, xltq, xlt_cap_ipv6_lpm, 0x10, 1, 1);
9182
9183 /* reg_xltq_cap_xlt_entries
9184 * Number of XLT entries
9185 * Note: SW must not fill more than 80% in order to avoid overflow
9186 * Access: RO
9187 */
9188 MLXSW_ITEM32(reg, xltq, cap_xlt_entries, 0x20, 0, 32);
9189
9190 /* reg_xltq_cap_xlt_mtable
9191 * XLT M-Table max size
9192 * Access: RO
9193 */
9194 MLXSW_ITEM32(reg, xltq, cap_xlt_mtable, 0x24, 0, 32);
9195
mlxsw_reg_xltq_pack(char * payload)9196 static inline void mlxsw_reg_xltq_pack(char *payload)
9197 {
9198 MLXSW_REG_ZERO(xltq, payload);
9199 }
9200
mlxsw_reg_xltq_unpack(char * payload,u16 * xm_device_id,bool * xlt_cap_ipv4_lpm,bool * xlt_cap_ipv6_lpm,u32 * cap_xlt_entries,u32 * cap_xlt_mtable)9201 static inline void mlxsw_reg_xltq_unpack(char *payload, u16 *xm_device_id, bool *xlt_cap_ipv4_lpm,
9202 bool *xlt_cap_ipv6_lpm, u32 *cap_xlt_entries,
9203 u32 *cap_xlt_mtable)
9204 {
9205 *xm_device_id = mlxsw_reg_xltq_xm_device_id_get(payload);
9206 *xlt_cap_ipv4_lpm = mlxsw_reg_xltq_xlt_cap_ipv4_lpm_get(payload);
9207 *xlt_cap_ipv6_lpm = mlxsw_reg_xltq_xlt_cap_ipv6_lpm_get(payload);
9208 *cap_xlt_entries = mlxsw_reg_xltq_cap_xlt_entries_get(payload);
9209 *cap_xlt_mtable = mlxsw_reg_xltq_cap_xlt_mtable_get(payload);
9210 }
9211
9212 /* XMDR - XM Direct Register
9213 * -------------------------
9214 * The XMDR allows direct access to the XM device via the switch.
9215 * Working in synchronous mode. FW waits for response from the XLT
9216 * for each command. FW acks the XMDR accordingly.
9217 */
9218 #define MLXSW_REG_XMDR_ID 0x7803
9219 #define MLXSW_REG_XMDR_BASE_LEN 0x20
9220 #define MLXSW_REG_XMDR_TRANS_LEN 0x80
9221 #define MLXSW_REG_XMDR_LEN (MLXSW_REG_XMDR_BASE_LEN + \
9222 MLXSW_REG_XMDR_TRANS_LEN)
9223
9224 MLXSW_REG_DEFINE(xmdr, MLXSW_REG_XMDR_ID, MLXSW_REG_XMDR_LEN);
9225
9226 /* reg_xmdr_bulk_entry
9227 * Bulk_entry
9228 * 0: Last entry - immediate flush of XRT-cache
9229 * 1: Bulk entry - do not flush the XRT-cache
9230 * Access: OP
9231 */
9232 MLXSW_ITEM32(reg, xmdr, bulk_entry, 0x04, 8, 1);
9233
9234 /* reg_xmdr_num_rec
9235 * Number of records for Direct access to XM
9236 * Supported: 0..4 commands (except NOP which is a filler)
9237 * 0 commands is reserved when bulk_entry = 1.
9238 * 0 commands is allowed when bulk_entry = 0 for immediate XRT-cache flush.
9239 * Access: OP
9240 */
9241 MLXSW_ITEM32(reg, xmdr, num_rec, 0x04, 0, 4);
9242
9243 /* reg_xmdr_reply_vect
9244 * Reply Vector
9245 * Bit i for command index i+1
9246 * values per bit:
9247 * 0: failed
9248 * 1: succeeded
9249 * e.g. if commands 1, 2, 4 succeeded and command 3 failed then binary
9250 * value will be 0b1011
9251 * Access: RO
9252 */
9253 MLXSW_ITEM_BIT_ARRAY(reg, xmdr, reply_vect, 0x08, 4, 1);
9254
mlxsw_reg_xmdr_pack(char * payload,bool bulk_entry)9255 static inline void mlxsw_reg_xmdr_pack(char *payload, bool bulk_entry)
9256 {
9257 MLXSW_REG_ZERO(xmdr, payload);
9258 mlxsw_reg_xmdr_bulk_entry_set(payload, bulk_entry);
9259 }
9260
9261 enum mlxsw_reg_xmdr_c_cmd_id {
9262 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V4 = 0x30,
9263 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V6 = 0x31,
9264 };
9265
9266 #define MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN 32
9267 #define MLXSW_REG_XMDR_C_LT_ROUTE_V6_LEN 48
9268
9269 /* reg_xmdr_c_cmd_id
9270 */
9271 MLXSW_ITEM32(reg, xmdr_c, cmd_id, 0x00, 24, 8);
9272
9273 /* reg_xmdr_c_seq_number
9274 */
9275 MLXSW_ITEM32(reg, xmdr_c, seq_number, 0x00, 12, 12);
9276
9277 enum mlxsw_reg_xmdr_c_ltr_op {
9278 /* Activity is set */
9279 MLXSW_REG_XMDR_C_LTR_OP_WRITE = 0,
9280 /* There is no update mask. All fields are updated. */
9281 MLXSW_REG_XMDR_C_LTR_OP_UPDATE = 1,
9282 MLXSW_REG_XMDR_C_LTR_OP_DELETE = 2,
9283 };
9284
9285 /* reg_xmdr_c_ltr_op
9286 * Operation.
9287 */
9288 MLXSW_ITEM32(reg, xmdr_c, ltr_op, 0x04, 24, 8);
9289
9290 /* reg_xmdr_c_ltr_trap_action
9291 * Trap action.
9292 * Values are defined in enum mlxsw_reg_ralue_trap_action.
9293 */
9294 MLXSW_ITEM32(reg, xmdr_c, ltr_trap_action, 0x04, 20, 4);
9295
9296 enum mlxsw_reg_xmdr_c_ltr_trap_id_num {
9297 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS0,
9298 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS1,
9299 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS2,
9300 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS3,
9301 };
9302
9303 /* reg_xmdr_c_ltr_trap_id_num
9304 * Trap-ID number.
9305 */
9306 MLXSW_ITEM32(reg, xmdr_c, ltr_trap_id_num, 0x04, 16, 4);
9307
9308 /* reg_xmdr_c_ltr_virtual_router
9309 * Virtual Router ID.
9310 * Range is 0..cap_max_virtual_routers-1
9311 */
9312 MLXSW_ITEM32(reg, xmdr_c, ltr_virtual_router, 0x04, 0, 16);
9313
9314 /* reg_xmdr_c_ltr_prefix_len
9315 * Number of bits in the prefix of the LPM route.
9316 */
9317 MLXSW_ITEM32(reg, xmdr_c, ltr_prefix_len, 0x08, 24, 8);
9318
9319 /* reg_xmdr_c_ltr_bmp_len
9320 * The best match prefix length in the case that there is no match for
9321 * longer prefixes.
9322 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
9323 */
9324 MLXSW_ITEM32(reg, xmdr_c, ltr_bmp_len, 0x08, 16, 8);
9325
9326 /* reg_xmdr_c_ltr_entry_type
9327 * Entry type.
9328 * Values are defined in enum mlxsw_reg_ralue_entry_type.
9329 */
9330 MLXSW_ITEM32(reg, xmdr_c, ltr_entry_type, 0x08, 4, 4);
9331
9332 enum mlxsw_reg_xmdr_c_ltr_action_type {
9333 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_LOCAL,
9334 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_REMOTE,
9335 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME,
9336 };
9337
9338 /* reg_xmdr_c_ltr_action_type
9339 * Action Type.
9340 */
9341 MLXSW_ITEM32(reg, xmdr_c, ltr_action_type, 0x08, 0, 4);
9342
9343 /* reg_xmdr_c_ltr_erif
9344 * Egress Router Interface.
9345 * Only relevant in case of LOCAL action.
9346 */
9347 MLXSW_ITEM32(reg, xmdr_c, ltr_erif, 0x10, 0, 16);
9348
9349 /* reg_xmdr_c_ltr_adjacency_index
9350 * Points to the first entry of the group-based ECMP.
9351 * Only relevant in case of REMOTE action.
9352 */
9353 MLXSW_ITEM32(reg, xmdr_c, ltr_adjacency_index, 0x10, 0, 24);
9354
9355 #define MLXSW_REG_XMDR_C_LTR_POINTER_TO_TUNNEL_DISABLED_MAGIC 0xFFFFFF
9356
9357 /* reg_xmdr_c_ltr_pointer_to_tunnel
9358 * Only relevant in case of IP2ME action.
9359 */
9360 MLXSW_ITEM32(reg, xmdr_c, ltr_pointer_to_tunnel, 0x10, 0, 24);
9361
9362 /* reg_xmdr_c_ltr_ecmp_size
9363 * Amount of sequential entries starting
9364 * from the adjacency_index (the number of ECMPs).
9365 * The valid range is 1-64, 512, 1024, 2048 and 4096.
9366 * Only relevant in case of REMOTE action.
9367 */
9368 MLXSW_ITEM32(reg, xmdr_c, ltr_ecmp_size, 0x14, 0, 32);
9369
9370 /* reg_xmdr_c_ltr_dip*
9371 * The prefix of the route or of the marker that the object of the LPM
9372 * is compared with. The most significant bits of the dip are the prefix.
9373 * The least significant bits must be '0' if the prefix_len is smaller
9374 * than 128 for IPv6 or smaller than 32 for IPv4.
9375 */
9376 MLXSW_ITEM32(reg, xmdr_c, ltr_dip4, 0x1C, 0, 32);
9377 MLXSW_ITEM_BUF(reg, xmdr_c, ltr_dip6, 0x1C, 16);
9378
9379 static inline void
mlxsw_reg_xmdr_c_ltr_pack(char * xmdr_payload,unsigned int trans_offset,enum mlxsw_reg_xmdr_c_cmd_id cmd_id,u16 seq_number,enum mlxsw_reg_xmdr_c_ltr_op op,u16 virtual_router,u8 prefix_len)9380 mlxsw_reg_xmdr_c_ltr_pack(char *xmdr_payload, unsigned int trans_offset,
9381 enum mlxsw_reg_xmdr_c_cmd_id cmd_id, u16 seq_number,
9382 enum mlxsw_reg_xmdr_c_ltr_op op, u16 virtual_router,
9383 u8 prefix_len)
9384 {
9385 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9386 u8 num_rec = mlxsw_reg_xmdr_num_rec_get(xmdr_payload);
9387
9388 mlxsw_reg_xmdr_num_rec_set(xmdr_payload, num_rec + 1);
9389
9390 mlxsw_reg_xmdr_c_cmd_id_set(payload, cmd_id);
9391 mlxsw_reg_xmdr_c_seq_number_set(payload, seq_number);
9392 mlxsw_reg_xmdr_c_ltr_op_set(payload, op);
9393 mlxsw_reg_xmdr_c_ltr_virtual_router_set(payload, virtual_router);
9394 mlxsw_reg_xmdr_c_ltr_prefix_len_set(payload, prefix_len);
9395 mlxsw_reg_xmdr_c_ltr_entry_type_set(payload,
9396 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
9397 mlxsw_reg_xmdr_c_ltr_bmp_len_set(payload, prefix_len);
9398 }
9399
9400 static inline unsigned int
mlxsw_reg_xmdr_c_ltr_pack4(char * xmdr_payload,unsigned int trans_offset,u16 seq_number,enum mlxsw_reg_xmdr_c_ltr_op op,u16 virtual_router,u8 prefix_len,u32 * dip)9401 mlxsw_reg_xmdr_c_ltr_pack4(char *xmdr_payload, unsigned int trans_offset,
9402 u16 seq_number, enum mlxsw_reg_xmdr_c_ltr_op op,
9403 u16 virtual_router, u8 prefix_len, u32 *dip)
9404 {
9405 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9406
9407 mlxsw_reg_xmdr_c_ltr_pack(xmdr_payload, trans_offset,
9408 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V4,
9409 seq_number, op, virtual_router, prefix_len);
9410 if (dip)
9411 mlxsw_reg_xmdr_c_ltr_dip4_set(payload, *dip);
9412 return MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN;
9413 }
9414
9415 static inline unsigned int
mlxsw_reg_xmdr_c_ltr_pack6(char * xmdr_payload,unsigned int trans_offset,u16 seq_number,enum mlxsw_reg_xmdr_c_ltr_op op,u16 virtual_router,u8 prefix_len,const void * dip)9416 mlxsw_reg_xmdr_c_ltr_pack6(char *xmdr_payload, unsigned int trans_offset,
9417 u16 seq_number, enum mlxsw_reg_xmdr_c_ltr_op op,
9418 u16 virtual_router, u8 prefix_len, const void *dip)
9419 {
9420 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9421
9422 mlxsw_reg_xmdr_c_ltr_pack(xmdr_payload, trans_offset,
9423 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V6,
9424 seq_number, op, virtual_router, prefix_len);
9425 if (dip)
9426 mlxsw_reg_xmdr_c_ltr_dip6_memcpy_to(payload, dip);
9427 return MLXSW_REG_XMDR_C_LT_ROUTE_V6_LEN;
9428 }
9429
9430 static inline void
mlxsw_reg_xmdr_c_ltr_act_remote_pack(char * xmdr_payload,unsigned int trans_offset,enum mlxsw_reg_ralue_trap_action trap_action,enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num,u32 adjacency_index,u16 ecmp_size)9431 mlxsw_reg_xmdr_c_ltr_act_remote_pack(char *xmdr_payload, unsigned int trans_offset,
9432 enum mlxsw_reg_ralue_trap_action trap_action,
9433 enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num,
9434 u32 adjacency_index, u16 ecmp_size)
9435 {
9436 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9437
9438 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_REMOTE);
9439 mlxsw_reg_xmdr_c_ltr_trap_action_set(payload, trap_action);
9440 mlxsw_reg_xmdr_c_ltr_trap_id_num_set(payload, trap_id_num);
9441 mlxsw_reg_xmdr_c_ltr_adjacency_index_set(payload, adjacency_index);
9442 mlxsw_reg_xmdr_c_ltr_ecmp_size_set(payload, ecmp_size);
9443 }
9444
9445 static inline void
mlxsw_reg_xmdr_c_ltr_act_local_pack(char * xmdr_payload,unsigned int trans_offset,enum mlxsw_reg_ralue_trap_action trap_action,enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num,u16 erif)9446 mlxsw_reg_xmdr_c_ltr_act_local_pack(char *xmdr_payload, unsigned int trans_offset,
9447 enum mlxsw_reg_ralue_trap_action trap_action,
9448 enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num, u16 erif)
9449 {
9450 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9451
9452 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_LOCAL);
9453 mlxsw_reg_xmdr_c_ltr_trap_action_set(payload, trap_action);
9454 mlxsw_reg_xmdr_c_ltr_trap_id_num_set(payload, trap_id_num);
9455 mlxsw_reg_xmdr_c_ltr_erif_set(payload, erif);
9456 }
9457
mlxsw_reg_xmdr_c_ltr_act_ip2me_pack(char * xmdr_payload,unsigned int trans_offset)9458 static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_pack(char *xmdr_payload,
9459 unsigned int trans_offset)
9460 {
9461 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9462
9463 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME);
9464 mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload,
9465 MLXSW_REG_XMDR_C_LTR_POINTER_TO_TUNNEL_DISABLED_MAGIC);
9466 }
9467
mlxsw_reg_xmdr_c_ltr_act_ip2me_tun_pack(char * xmdr_payload,unsigned int trans_offset,u32 pointer_to_tunnel)9468 static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_tun_pack(char *xmdr_payload,
9469 unsigned int trans_offset,
9470 u32 pointer_to_tunnel)
9471 {
9472 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9473
9474 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME);
9475 mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload, pointer_to_tunnel);
9476 }
9477
9478 /* XRMT - XM Router M Table Register
9479 * ---------------------------------
9480 * The XRMT configures the M-Table for the XLT-LPM.
9481 */
9482 #define MLXSW_REG_XRMT_ID 0x7810
9483 #define MLXSW_REG_XRMT_LEN 0x14
9484
9485 MLXSW_REG_DEFINE(xrmt, MLXSW_REG_XRMT_ID, MLXSW_REG_XRMT_LEN);
9486
9487 /* reg_xrmt_index
9488 * Index in M-Table.
9489 * Range 0..cap_xlt_mtable-1
9490 * Access: Index
9491 */
9492 MLXSW_ITEM32(reg, xrmt, index, 0x04, 0, 20);
9493
9494 /* reg_xrmt_l0_val
9495 * Access: RW
9496 */
9497 MLXSW_ITEM32(reg, xrmt, l0_val, 0x10, 24, 8);
9498
mlxsw_reg_xrmt_pack(char * payload,u32 index,u8 l0_val)9499 static inline void mlxsw_reg_xrmt_pack(char *payload, u32 index, u8 l0_val)
9500 {
9501 MLXSW_REG_ZERO(xrmt, payload);
9502 mlxsw_reg_xrmt_index_set(payload, index);
9503 mlxsw_reg_xrmt_l0_val_set(payload, l0_val);
9504 }
9505
9506 /* XRALTA - XM Router Algorithmic LPM Tree Allocation Register
9507 * -----------------------------------------------------------
9508 * The XRALTA is used to allocate the XLT LPM trees.
9509 *
9510 * This register embeds original RALTA register.
9511 */
9512 #define MLXSW_REG_XRALTA_ID 0x7811
9513 #define MLXSW_REG_XRALTA_LEN 0x08
9514 #define MLXSW_REG_XRALTA_RALTA_OFFSET 0x04
9515
9516 MLXSW_REG_DEFINE(xralta, MLXSW_REG_XRALTA_ID, MLXSW_REG_XRALTA_LEN);
9517
mlxsw_reg_xralta_pack(char * payload,bool alloc,enum mlxsw_reg_ralxx_protocol protocol,u8 tree_id)9518 static inline void mlxsw_reg_xralta_pack(char *payload, bool alloc,
9519 enum mlxsw_reg_ralxx_protocol protocol,
9520 u8 tree_id)
9521 {
9522 char *ralta_payload = payload + MLXSW_REG_XRALTA_RALTA_OFFSET;
9523
9524 MLXSW_REG_ZERO(xralta, payload);
9525 mlxsw_reg_ralta_pack(ralta_payload, alloc, protocol, tree_id);
9526 }
9527
9528 /* XRALST - XM Router Algorithmic LPM Structure Tree Register
9529 * ----------------------------------------------------------
9530 * The XRALST is used to set and query the structure of an XLT LPM tree.
9531 *
9532 * This register embeds original RALST register.
9533 */
9534 #define MLXSW_REG_XRALST_ID 0x7812
9535 #define MLXSW_REG_XRALST_LEN 0x108
9536 #define MLXSW_REG_XRALST_RALST_OFFSET 0x04
9537
9538 MLXSW_REG_DEFINE(xralst, MLXSW_REG_XRALST_ID, MLXSW_REG_XRALST_LEN);
9539
mlxsw_reg_xralst_pack(char * payload,u8 root_bin,u8 tree_id)9540 static inline void mlxsw_reg_xralst_pack(char *payload, u8 root_bin, u8 tree_id)
9541 {
9542 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET;
9543
9544 MLXSW_REG_ZERO(xralst, payload);
9545 mlxsw_reg_ralst_pack(ralst_payload, root_bin, tree_id);
9546 }
9547
mlxsw_reg_xralst_bin_pack(char * payload,u8 bin_number,u8 left_child_bin,u8 right_child_bin)9548 static inline void mlxsw_reg_xralst_bin_pack(char *payload, u8 bin_number,
9549 u8 left_child_bin,
9550 u8 right_child_bin)
9551 {
9552 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET;
9553
9554 mlxsw_reg_ralst_bin_pack(ralst_payload, bin_number, left_child_bin,
9555 right_child_bin);
9556 }
9557
9558 /* XRALTB - XM Router Algorithmic LPM Tree Binding Register
9559 * --------------------------------------------------------
9560 * The XRALTB register is used to bind virtual router and protocol
9561 * to an allocated LPM tree.
9562 *
9563 * This register embeds original RALTB register.
9564 */
9565 #define MLXSW_REG_XRALTB_ID 0x7813
9566 #define MLXSW_REG_XRALTB_LEN 0x08
9567 #define MLXSW_REG_XRALTB_RALTB_OFFSET 0x04
9568
9569 MLXSW_REG_DEFINE(xraltb, MLXSW_REG_XRALTB_ID, MLXSW_REG_XRALTB_LEN);
9570
mlxsw_reg_xraltb_pack(char * payload,u16 virtual_router,enum mlxsw_reg_ralxx_protocol protocol,u8 tree_id)9571 static inline void mlxsw_reg_xraltb_pack(char *payload, u16 virtual_router,
9572 enum mlxsw_reg_ralxx_protocol protocol,
9573 u8 tree_id)
9574 {
9575 char *raltb_payload = payload + MLXSW_REG_XRALTB_RALTB_OFFSET;
9576
9577 MLXSW_REG_ZERO(xraltb, payload);
9578 mlxsw_reg_raltb_pack(raltb_payload, virtual_router, protocol, tree_id);
9579 }
9580
9581 /* MFCR - Management Fan Control Register
9582 * --------------------------------------
9583 * This register controls the settings of the Fan Speed PWM mechanism.
9584 */
9585 #define MLXSW_REG_MFCR_ID 0x9001
9586 #define MLXSW_REG_MFCR_LEN 0x08
9587
9588 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
9589
9590 enum mlxsw_reg_mfcr_pwm_frequency {
9591 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
9592 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
9593 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
9594 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
9595 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
9596 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
9597 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
9598 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
9599 };
9600
9601 /* reg_mfcr_pwm_frequency
9602 * Controls the frequency of the PWM signal.
9603 * Access: RW
9604 */
9605 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
9606
9607 #define MLXSW_MFCR_TACHOS_MAX 10
9608
9609 /* reg_mfcr_tacho_active
9610 * Indicates which of the tachometer is active (bit per tachometer).
9611 * Access: RO
9612 */
9613 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
9614
9615 #define MLXSW_MFCR_PWMS_MAX 5
9616
9617 /* reg_mfcr_pwm_active
9618 * Indicates which of the PWM control is active (bit per PWM).
9619 * Access: RO
9620 */
9621 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
9622
9623 static inline void
mlxsw_reg_mfcr_pack(char * payload,enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)9624 mlxsw_reg_mfcr_pack(char *payload,
9625 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
9626 {
9627 MLXSW_REG_ZERO(mfcr, payload);
9628 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
9629 }
9630
9631 static inline void
mlxsw_reg_mfcr_unpack(char * payload,enum mlxsw_reg_mfcr_pwm_frequency * p_pwm_frequency,u16 * p_tacho_active,u8 * p_pwm_active)9632 mlxsw_reg_mfcr_unpack(char *payload,
9633 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
9634 u16 *p_tacho_active, u8 *p_pwm_active)
9635 {
9636 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
9637 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
9638 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
9639 }
9640
9641 /* MFSC - Management Fan Speed Control Register
9642 * --------------------------------------------
9643 * This register controls the settings of the Fan Speed PWM mechanism.
9644 */
9645 #define MLXSW_REG_MFSC_ID 0x9002
9646 #define MLXSW_REG_MFSC_LEN 0x08
9647
9648 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
9649
9650 /* reg_mfsc_pwm
9651 * Fan pwm to control / monitor.
9652 * Access: Index
9653 */
9654 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
9655
9656 /* reg_mfsc_pwm_duty_cycle
9657 * Controls the duty cycle of the PWM. Value range from 0..255 to
9658 * represent duty cycle of 0%...100%.
9659 * Access: RW
9660 */
9661 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
9662
mlxsw_reg_mfsc_pack(char * payload,u8 pwm,u8 pwm_duty_cycle)9663 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
9664 u8 pwm_duty_cycle)
9665 {
9666 MLXSW_REG_ZERO(mfsc, payload);
9667 mlxsw_reg_mfsc_pwm_set(payload, pwm);
9668 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
9669 }
9670
9671 /* MFSM - Management Fan Speed Measurement
9672 * ---------------------------------------
9673 * This register controls the settings of the Tacho measurements and
9674 * enables reading the Tachometer measurements.
9675 */
9676 #define MLXSW_REG_MFSM_ID 0x9003
9677 #define MLXSW_REG_MFSM_LEN 0x08
9678
9679 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
9680
9681 /* reg_mfsm_tacho
9682 * Fan tachometer index.
9683 * Access: Index
9684 */
9685 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
9686
9687 /* reg_mfsm_rpm
9688 * Fan speed (round per minute).
9689 * Access: RO
9690 */
9691 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
9692
mlxsw_reg_mfsm_pack(char * payload,u8 tacho)9693 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
9694 {
9695 MLXSW_REG_ZERO(mfsm, payload);
9696 mlxsw_reg_mfsm_tacho_set(payload, tacho);
9697 }
9698
9699 /* MFSL - Management Fan Speed Limit Register
9700 * ------------------------------------------
9701 * The Fan Speed Limit register is used to configure the fan speed
9702 * event / interrupt notification mechanism. Fan speed threshold are
9703 * defined for both under-speed and over-speed.
9704 */
9705 #define MLXSW_REG_MFSL_ID 0x9004
9706 #define MLXSW_REG_MFSL_LEN 0x0C
9707
9708 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
9709
9710 /* reg_mfsl_tacho
9711 * Fan tachometer index.
9712 * Access: Index
9713 */
9714 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
9715
9716 /* reg_mfsl_tach_min
9717 * Tachometer minimum value (minimum RPM).
9718 * Access: RW
9719 */
9720 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
9721
9722 /* reg_mfsl_tach_max
9723 * Tachometer maximum value (maximum RPM).
9724 * Access: RW
9725 */
9726 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
9727
mlxsw_reg_mfsl_pack(char * payload,u8 tacho,u16 tach_min,u16 tach_max)9728 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
9729 u16 tach_min, u16 tach_max)
9730 {
9731 MLXSW_REG_ZERO(mfsl, payload);
9732 mlxsw_reg_mfsl_tacho_set(payload, tacho);
9733 mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
9734 mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
9735 }
9736
mlxsw_reg_mfsl_unpack(char * payload,u8 tacho,u16 * p_tach_min,u16 * p_tach_max)9737 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
9738 u16 *p_tach_min, u16 *p_tach_max)
9739 {
9740 if (p_tach_min)
9741 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
9742
9743 if (p_tach_max)
9744 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
9745 }
9746
9747 /* FORE - Fan Out of Range Event Register
9748 * --------------------------------------
9749 * This register reports the status of the controlled fans compared to the
9750 * range defined by the MFSL register.
9751 */
9752 #define MLXSW_REG_FORE_ID 0x9007
9753 #define MLXSW_REG_FORE_LEN 0x0C
9754
9755 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN);
9756
9757 /* fan_under_limit
9758 * Fan speed is below the low limit defined in MFSL register. Each bit relates
9759 * to a single tachometer and indicates the specific tachometer reading is
9760 * below the threshold.
9761 * Access: RO
9762 */
9763 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
9764
mlxsw_reg_fore_unpack(char * payload,u8 tacho,bool * fault)9765 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho,
9766 bool *fault)
9767 {
9768 u16 limit;
9769
9770 if (fault) {
9771 limit = mlxsw_reg_fore_fan_under_limit_get(payload);
9772 *fault = limit & BIT(tacho);
9773 }
9774 }
9775
9776 /* MTCAP - Management Temperature Capabilities
9777 * -------------------------------------------
9778 * This register exposes the capabilities of the device and
9779 * system temperature sensing.
9780 */
9781 #define MLXSW_REG_MTCAP_ID 0x9009
9782 #define MLXSW_REG_MTCAP_LEN 0x08
9783
9784 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
9785
9786 /* reg_mtcap_sensor_count
9787 * Number of sensors supported by the device.
9788 * This includes the QSFP module sensors (if exists in the QSFP module).
9789 * Access: RO
9790 */
9791 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
9792
9793 /* MTMP - Management Temperature
9794 * -----------------------------
9795 * This register controls the settings of the temperature measurements
9796 * and enables reading the temperature measurements. Note that temperature
9797 * is in 0.125 degrees Celsius.
9798 */
9799 #define MLXSW_REG_MTMP_ID 0x900A
9800 #define MLXSW_REG_MTMP_LEN 0x20
9801
9802 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
9803
9804 /* reg_mtmp_slot_index
9805 * Slot index (0: Main board).
9806 * Access: Index
9807 */
9808 MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4);
9809
9810 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64
9811 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256
9812 /* reg_mtmp_sensor_index
9813 * Sensors index to access.
9814 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
9815 * (module 0 is mapped to sensor_index 64).
9816 * Access: Index
9817 */
9818 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);
9819
9820 /* Convert to milli degrees Celsius */
9821 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \
9822 ((v_) >= 0) ? ((v_) * 125) : \
9823 ((s16)((GENMASK(15, 0) + (v_) + 1) \
9824 * 125)); })
9825
9826 /* reg_mtmp_max_operational_temperature
9827 * The highest temperature in the nominal operational range. Reading is in
9828 * 0.125 Celsius degrees units.
9829 * In case of module this is SFF critical temperature threshold.
9830 * Access: RO
9831 */
9832 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16);
9833
9834 /* reg_mtmp_temperature
9835 * Temperature reading from the sensor. Reading is in 0.125 Celsius
9836 * degrees units.
9837 * Access: RO
9838 */
9839 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
9840
9841 /* reg_mtmp_mte
9842 * Max Temperature Enable - enables measuring the max temperature on a sensor.
9843 * Access: RW
9844 */
9845 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
9846
9847 /* reg_mtmp_mtr
9848 * Max Temperature Reset - clears the value of the max temperature register.
9849 * Access: WO
9850 */
9851 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
9852
9853 /* reg_mtmp_max_temperature
9854 * The highest measured temperature from the sensor.
9855 * When the bit mte is cleared, the field max_temperature is reserved.
9856 * Access: RO
9857 */
9858 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
9859
9860 /* reg_mtmp_tee
9861 * Temperature Event Enable.
9862 * 0 - Do not generate event
9863 * 1 - Generate event
9864 * 2 - Generate single event
9865 * Access: RW
9866 */
9867
9868 enum mlxsw_reg_mtmp_tee {
9869 MLXSW_REG_MTMP_TEE_NO_EVENT,
9870 MLXSW_REG_MTMP_TEE_GENERATE_EVENT,
9871 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT,
9872 };
9873
9874 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
9875
9876 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */
9877
9878 /* reg_mtmp_temperature_threshold_hi
9879 * High threshold for Temperature Warning Event. In 0.125 Celsius.
9880 * Access: RW
9881 */
9882 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
9883
9884 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */
9885 /* reg_mtmp_temperature_threshold_lo
9886 * Low threshold for Temperature Warning Event. In 0.125 Celsius.
9887 * Access: RW
9888 */
9889 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
9890
9891 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
9892
9893 /* reg_mtmp_sensor_name
9894 * Sensor Name
9895 * Access: RO
9896 */
9897 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
9898
mlxsw_reg_mtmp_pack(char * payload,u8 slot_index,u16 sensor_index,bool max_temp_enable,bool max_temp_reset)9899 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 slot_index,
9900 u16 sensor_index, bool max_temp_enable,
9901 bool max_temp_reset)
9902 {
9903 MLXSW_REG_ZERO(mtmp, payload);
9904 mlxsw_reg_mtmp_slot_index_set(payload, slot_index);
9905 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
9906 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
9907 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
9908 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
9909 MLXSW_REG_MTMP_THRESH_HI);
9910 }
9911
mlxsw_reg_mtmp_unpack(char * payload,int * p_temp,int * p_max_temp,int * p_temp_hi,int * p_max_oper_temp,char * sensor_name)9912 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp,
9913 int *p_max_temp, int *p_temp_hi,
9914 int *p_max_oper_temp,
9915 char *sensor_name)
9916 {
9917 s16 temp;
9918
9919 if (p_temp) {
9920 temp = mlxsw_reg_mtmp_temperature_get(payload);
9921 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9922 }
9923 if (p_max_temp) {
9924 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
9925 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9926 }
9927 if (p_temp_hi) {
9928 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload);
9929 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9930 }
9931 if (p_max_oper_temp) {
9932 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload);
9933 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9934 }
9935 if (sensor_name)
9936 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
9937 }
9938
9939 /* MTWE - Management Temperature Warning Event
9940 * -------------------------------------------
9941 * This register is used for over temperature warning.
9942 */
9943 #define MLXSW_REG_MTWE_ID 0x900B
9944 #define MLXSW_REG_MTWE_LEN 0x10
9945
9946 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN);
9947
9948 /* reg_mtwe_sensor_warning
9949 * Bit vector indicating which of the sensor reading is above threshold.
9950 * Address 00h bit31 is sensor_warning[127].
9951 * Address 0Ch bit0 is sensor_warning[0].
9952 * Access: RO
9953 */
9954 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1);
9955
9956 /* MTBR - Management Temperature Bulk Register
9957 * -------------------------------------------
9958 * This register is used for bulk temperature reading.
9959 */
9960 #define MLXSW_REG_MTBR_ID 0x900F
9961 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */
9962 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */
9963 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */
9964 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \
9965 MLXSW_REG_MTBR_REC_LEN * \
9966 MLXSW_REG_MTBR_REC_MAX_COUNT)
9967
9968 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN);
9969
9970 /* reg_mtbr_slot_index
9971 * Slot index (0: Main board).
9972 * Access: Index
9973 */
9974 MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4);
9975
9976 /* reg_mtbr_base_sensor_index
9977 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors,
9978 * 64-127 are mapped to the SFP+/QSFP modules sequentially).
9979 * Access: Index
9980 */
9981 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);
9982
9983 /* reg_mtbr_num_rec
9984 * Request: Number of records to read
9985 * Response: Number of records read
9986 * See above description for more details.
9987 * Range 1..255
9988 * Access: RW
9989 */
9990 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
9991
9992 /* reg_mtbr_rec_max_temp
9993 * The highest measured temperature from the sensor.
9994 * When the bit mte is cleared, the field max_temperature is reserved.
9995 * Access: RO
9996 */
9997 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
9998 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);
9999
10000 /* reg_mtbr_rec_temp
10001 * Temperature reading from the sensor. Reading is in 0..125 Celsius
10002 * degrees units.
10003 * Access: RO
10004 */
10005 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
10006 MLXSW_REG_MTBR_REC_LEN, 0x00, false);
10007
mlxsw_reg_mtbr_pack(char * payload,u8 slot_index,u16 base_sensor_index,u8 num_rec)10008 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index,
10009 u16 base_sensor_index, u8 num_rec)
10010 {
10011 MLXSW_REG_ZERO(mtbr, payload);
10012 mlxsw_reg_mtbr_slot_index_set(payload, slot_index);
10013 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index);
10014 mlxsw_reg_mtbr_num_rec_set(payload, num_rec);
10015 }
10016
10017 /* Error codes from temperatute reading */
10018 enum mlxsw_reg_mtbr_temp_status {
10019 MLXSW_REG_MTBR_NO_CONN = 0x8000,
10020 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001,
10021 MLXSW_REG_MTBR_INDEX_NA = 0x8002,
10022 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003,
10023 };
10024
10025 /* Base index for reading modules temperature */
10026 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64
10027
mlxsw_reg_mtbr_temp_unpack(char * payload,int rec_ind,u16 * p_temp,u16 * p_max_temp)10028 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind,
10029 u16 *p_temp, u16 *p_max_temp)
10030 {
10031 if (p_temp)
10032 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind);
10033 if (p_max_temp)
10034 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind);
10035 }
10036
10037 /* MCIA - Management Cable Info Access
10038 * -----------------------------------
10039 * MCIA register is used to access the SFP+ and QSFP connector's EPROM.
10040 */
10041
10042 #define MLXSW_REG_MCIA_ID 0x9014
10043 #define MLXSW_REG_MCIA_LEN 0x40
10044
10045 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
10046
10047 /* reg_mcia_l
10048 * Lock bit. Setting this bit will lock the access to the specific
10049 * cable. Used for updating a full page in a cable EPROM. Any access
10050 * other then subsequence writes will fail while the port is locked.
10051 * Access: RW
10052 */
10053 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
10054
10055 /* reg_mcia_module
10056 * Module number.
10057 * Access: Index
10058 */
10059 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
10060
10061 /* reg_mcia_slot_index
10062 * Slot index (0: Main board)
10063 * Access: Index
10064 */
10065 MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4);
10066
10067 enum {
10068 MLXSW_REG_MCIA_STATUS_GOOD = 0,
10069 /* No response from module's EEPROM. */
10070 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1,
10071 /* Module type not supported by the device. */
10072 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2,
10073 /* No module present indication. */
10074 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3,
10075 /* Error occurred while trying to access module's EEPROM using I2C. */
10076 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9,
10077 /* Module is disabled. */
10078 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16,
10079 };
10080
10081 /* reg_mcia_status
10082 * Module status.
10083 * Access: RO
10084 */
10085 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
10086
10087 /* reg_mcia_i2c_device_address
10088 * I2C device address.
10089 * Access: RW
10090 */
10091 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
10092
10093 /* reg_mcia_page_number
10094 * Page number.
10095 * Access: RW
10096 */
10097 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
10098
10099 /* reg_mcia_device_address
10100 * Device address.
10101 * Access: RW
10102 */
10103 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
10104
10105 /* reg_mcia_bank_number
10106 * Bank number.
10107 * Access: Index
10108 */
10109 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8);
10110
10111 /* reg_mcia_size
10112 * Number of bytes to read/write (up to 48 bytes).
10113 * Access: RW
10114 */
10115 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
10116
10117 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256
10118 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128
10119 #define MLXSW_REG_MCIA_EEPROM_SIZE 48
10120 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50
10121 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51
10122 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0
10123 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2
10124 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3
10125 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2
10126 #define MLXSW_REG_MCIA_PAGE0_LO 0
10127 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80
10128 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7)
10129
10130 enum mlxsw_reg_mcia_eeprom_module_info_rev_id {
10131 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
10132 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
10133 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
10134 };
10135
10136 enum mlxsw_reg_mcia_eeprom_module_info_id {
10137 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03,
10138 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
10139 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
10140 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
10141 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18,
10142 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP = 0x19,
10143 };
10144
10145 enum mlxsw_reg_mcia_eeprom_module_info {
10146 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID,
10147 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID,
10148 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID,
10149 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE,
10150 };
10151
10152 /* reg_mcia_eeprom
10153 * Bytes to read/write.
10154 * Access: RW
10155 */
10156 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE);
10157
10158 /* This is used to access the optional upper pages (1-3) in the QSFP+
10159 * memory map. Page 1 is available on offset 256 through 383, page 2 -
10160 * on offset 384 through 511, page 3 - on offset 512 through 639.
10161 */
10162 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \
10163 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \
10164 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1)
10165
mlxsw_reg_mcia_pack(char * payload,u8 slot_index,u8 module,u8 lock,u8 page_number,u16 device_addr,u8 size,u8 i2c_device_addr)10166 static inline void mlxsw_reg_mcia_pack(char *payload, u8 slot_index, u8 module,
10167 u8 lock, u8 page_number,
10168 u16 device_addr, u8 size,
10169 u8 i2c_device_addr)
10170 {
10171 MLXSW_REG_ZERO(mcia, payload);
10172 mlxsw_reg_mcia_slot_set(payload, slot_index);
10173 mlxsw_reg_mcia_module_set(payload, module);
10174 mlxsw_reg_mcia_l_set(payload, lock);
10175 mlxsw_reg_mcia_page_number_set(payload, page_number);
10176 mlxsw_reg_mcia_device_address_set(payload, device_addr);
10177 mlxsw_reg_mcia_size_set(payload, size);
10178 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
10179 }
10180
10181 /* MPAT - Monitoring Port Analyzer Table
10182 * -------------------------------------
10183 * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
10184 * For an enabled analyzer, all fields except e (enable) cannot be modified.
10185 */
10186 #define MLXSW_REG_MPAT_ID 0x901A
10187 #define MLXSW_REG_MPAT_LEN 0x78
10188
10189 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
10190
10191 /* reg_mpat_pa_id
10192 * Port Analyzer ID.
10193 * Access: Index
10194 */
10195 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
10196
10197 /* reg_mpat_session_id
10198 * Mirror Session ID.
10199 * Used for MIRROR_SESSION<i> trap.
10200 * Access: RW
10201 */
10202 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4);
10203
10204 /* reg_mpat_system_port
10205 * A unique port identifier for the final destination of the packet.
10206 * Access: RW
10207 */
10208 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
10209
10210 /* reg_mpat_e
10211 * Enable. Indicating the Port Analyzer is enabled.
10212 * Access: RW
10213 */
10214 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
10215
10216 /* reg_mpat_qos
10217 * Quality Of Service Mode.
10218 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
10219 * PCP, DEI, DSCP or VL) are configured.
10220 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
10221 * same as in the original packet that has triggered the mirroring. For
10222 * SPAN also the pcp,dei are maintained.
10223 * Access: RW
10224 */
10225 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
10226
10227 /* reg_mpat_be
10228 * Best effort mode. Indicates mirroring traffic should not cause packet
10229 * drop or back pressure, but will discard the mirrored packets. Mirrored
10230 * packets will be forwarded on a best effort manner.
10231 * 0: Do not discard mirrored packets
10232 * 1: Discard mirrored packets if causing congestion
10233 * Access: RW
10234 */
10235 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
10236
10237 enum mlxsw_reg_mpat_span_type {
10238 /* Local SPAN Ethernet.
10239 * The original packet is not encapsulated.
10240 */
10241 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
10242
10243 /* Remote SPAN Ethernet VLAN.
10244 * The packet is forwarded to the monitoring port on the monitoring
10245 * VLAN.
10246 */
10247 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
10248
10249 /* Encapsulated Remote SPAN Ethernet L3 GRE.
10250 * The packet is encapsulated with GRE header.
10251 */
10252 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
10253 };
10254
10255 /* reg_mpat_span_type
10256 * SPAN type.
10257 * Access: RW
10258 */
10259 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
10260
10261 /* reg_mpat_pide
10262 * Policer enable.
10263 * Access: RW
10264 */
10265 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1);
10266
10267 /* reg_mpat_pid
10268 * Policer ID.
10269 * Access: RW
10270 */
10271 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14);
10272
10273 /* Remote SPAN - Ethernet VLAN
10274 * - - - - - - - - - - - - - -
10275 */
10276
10277 /* reg_mpat_eth_rspan_vid
10278 * Encapsulation header VLAN ID.
10279 * Access: RW
10280 */
10281 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
10282
10283 /* Encapsulated Remote SPAN - Ethernet L2
10284 * - - - - - - - - - - - - - - - - - - -
10285 */
10286
10287 enum mlxsw_reg_mpat_eth_rspan_version {
10288 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
10289 };
10290
10291 /* reg_mpat_eth_rspan_version
10292 * RSPAN mirror header version.
10293 * Access: RW
10294 */
10295 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
10296
10297 /* reg_mpat_eth_rspan_mac
10298 * Destination MAC address.
10299 * Access: RW
10300 */
10301 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
10302
10303 /* reg_mpat_eth_rspan_tp
10304 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged.
10305 * Access: RW
10306 */
10307 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
10308
10309 /* Encapsulated Remote SPAN - Ethernet L3
10310 * - - - - - - - - - - - - - - - - - - -
10311 */
10312
10313 enum mlxsw_reg_mpat_eth_rspan_protocol {
10314 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
10315 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
10316 };
10317
10318 /* reg_mpat_eth_rspan_protocol
10319 * SPAN encapsulation protocol.
10320 * Access: RW
10321 */
10322 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
10323
10324 /* reg_mpat_eth_rspan_ttl
10325 * Encapsulation header Time-to-Live/HopLimit.
10326 * Access: RW
10327 */
10328 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
10329
10330 /* reg_mpat_eth_rspan_smac
10331 * Source MAC address
10332 * Access: RW
10333 */
10334 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
10335
10336 /* reg_mpat_eth_rspan_dip*
10337 * Destination IP address. The IP version is configured by protocol.
10338 * Access: RW
10339 */
10340 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
10341 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
10342
10343 /* reg_mpat_eth_rspan_sip*
10344 * Source IP address. The IP version is configured by protocol.
10345 * Access: RW
10346 */
10347 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
10348 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
10349
mlxsw_reg_mpat_pack(char * payload,u8 pa_id,u16 system_port,bool e,enum mlxsw_reg_mpat_span_type span_type)10350 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
10351 u16 system_port, bool e,
10352 enum mlxsw_reg_mpat_span_type span_type)
10353 {
10354 MLXSW_REG_ZERO(mpat, payload);
10355 mlxsw_reg_mpat_pa_id_set(payload, pa_id);
10356 mlxsw_reg_mpat_system_port_set(payload, system_port);
10357 mlxsw_reg_mpat_e_set(payload, e);
10358 mlxsw_reg_mpat_qos_set(payload, 1);
10359 mlxsw_reg_mpat_be_set(payload, 1);
10360 mlxsw_reg_mpat_span_type_set(payload, span_type);
10361 }
10362
mlxsw_reg_mpat_eth_rspan_pack(char * payload,u16 vid)10363 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
10364 {
10365 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
10366 }
10367
10368 static inline void
mlxsw_reg_mpat_eth_rspan_l2_pack(char * payload,enum mlxsw_reg_mpat_eth_rspan_version version,const char * mac,bool tp)10369 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
10370 enum mlxsw_reg_mpat_eth_rspan_version version,
10371 const char *mac,
10372 bool tp)
10373 {
10374 mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
10375 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
10376 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
10377 }
10378
10379 static inline void
mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char * payload,u8 ttl,const char * smac,u32 sip,u32 dip)10380 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
10381 const char *smac,
10382 u32 sip, u32 dip)
10383 {
10384 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
10385 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
10386 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
10387 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
10388 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
10389 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
10390 }
10391
10392 static inline void
mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char * payload,u8 ttl,const char * smac,struct in6_addr sip,struct in6_addr dip)10393 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
10394 const char *smac,
10395 struct in6_addr sip, struct in6_addr dip)
10396 {
10397 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
10398 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
10399 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
10400 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
10401 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
10402 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
10403 }
10404
10405 /* MPAR - Monitoring Port Analyzer Register
10406 * ----------------------------------------
10407 * MPAR register is used to query and configure the port analyzer port mirroring
10408 * properties.
10409 */
10410 #define MLXSW_REG_MPAR_ID 0x901B
10411 #define MLXSW_REG_MPAR_LEN 0x0C
10412
10413 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
10414
10415 /* reg_mpar_local_port
10416 * The local port to mirror the packets from.
10417 * Access: Index
10418 */
10419 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4);
10420
10421 enum mlxsw_reg_mpar_i_e {
10422 MLXSW_REG_MPAR_TYPE_EGRESS,
10423 MLXSW_REG_MPAR_TYPE_INGRESS,
10424 };
10425
10426 /* reg_mpar_i_e
10427 * Ingress/Egress
10428 * Access: Index
10429 */
10430 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
10431
10432 /* reg_mpar_enable
10433 * Enable mirroring
10434 * By default, port mirroring is disabled for all ports.
10435 * Access: RW
10436 */
10437 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
10438
10439 /* reg_mpar_pa_id
10440 * Port Analyzer ID.
10441 * Access: RW
10442 */
10443 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
10444
10445 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL
10446
10447 /* reg_mpar_probability_rate
10448 * Sampling rate.
10449 * Valid values are: 1 to 3.5*10^9
10450 * Value of 1 means "sample all". Default is 1.
10451 * Reserved when Spectrum-1.
10452 * Access: RW
10453 */
10454 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32);
10455
mlxsw_reg_mpar_pack(char * payload,u16 local_port,enum mlxsw_reg_mpar_i_e i_e,bool enable,u8 pa_id,u32 probability_rate)10456 static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port,
10457 enum mlxsw_reg_mpar_i_e i_e,
10458 bool enable, u8 pa_id,
10459 u32 probability_rate)
10460 {
10461 MLXSW_REG_ZERO(mpar, payload);
10462 mlxsw_reg_mpar_local_port_set(payload, local_port);
10463 mlxsw_reg_mpar_enable_set(payload, enable);
10464 mlxsw_reg_mpar_i_e_set(payload, i_e);
10465 mlxsw_reg_mpar_pa_id_set(payload, pa_id);
10466 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate);
10467 }
10468
10469 /* MGIR - Management General Information Register
10470 * ----------------------------------------------
10471 * MGIR register allows software to query the hardware and firmware general
10472 * information.
10473 */
10474 #define MLXSW_REG_MGIR_ID 0x9020
10475 #define MLXSW_REG_MGIR_LEN 0x9C
10476
10477 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN);
10478
10479 /* reg_mgir_hw_info_device_hw_revision
10480 * Access: RO
10481 */
10482 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);
10483
10484 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16
10485
10486 /* reg_mgir_fw_info_psid
10487 * PSID (ASCII string).
10488 * Access: RO
10489 */
10490 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);
10491
10492 /* reg_mgir_fw_info_extended_major
10493 * Access: RO
10494 */
10495 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);
10496
10497 /* reg_mgir_fw_info_extended_minor
10498 * Access: RO
10499 */
10500 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);
10501
10502 /* reg_mgir_fw_info_extended_sub_minor
10503 * Access: RO
10504 */
10505 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);
10506
mlxsw_reg_mgir_pack(char * payload)10507 static inline void mlxsw_reg_mgir_pack(char *payload)
10508 {
10509 MLXSW_REG_ZERO(mgir, payload);
10510 }
10511
10512 static inline void
mlxsw_reg_mgir_unpack(char * payload,u32 * hw_rev,char * fw_info_psid,u32 * fw_major,u32 * fw_minor,u32 * fw_sub_minor)10513 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid,
10514 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor)
10515 {
10516 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload);
10517 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid);
10518 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload);
10519 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload);
10520 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload);
10521 }
10522
10523 /* MRSR - Management Reset and Shutdown Register
10524 * ---------------------------------------------
10525 * MRSR register is used to reset or shutdown the switch or
10526 * the entire system (when applicable).
10527 */
10528 #define MLXSW_REG_MRSR_ID 0x9023
10529 #define MLXSW_REG_MRSR_LEN 0x08
10530
10531 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
10532
10533 /* reg_mrsr_command
10534 * Reset/shutdown command
10535 * 0 - do nothing
10536 * 1 - software reset
10537 * Access: WO
10538 */
10539 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
10540
mlxsw_reg_mrsr_pack(char * payload)10541 static inline void mlxsw_reg_mrsr_pack(char *payload)
10542 {
10543 MLXSW_REG_ZERO(mrsr, payload);
10544 mlxsw_reg_mrsr_command_set(payload, 1);
10545 }
10546
10547 /* MLCR - Management LED Control Register
10548 * --------------------------------------
10549 * Controls the system LEDs.
10550 */
10551 #define MLXSW_REG_MLCR_ID 0x902B
10552 #define MLXSW_REG_MLCR_LEN 0x0C
10553
10554 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
10555
10556 /* reg_mlcr_local_port
10557 * Local port number.
10558 * Access: RW
10559 */
10560 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24);
10561
10562 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
10563
10564 /* reg_mlcr_beacon_duration
10565 * Duration of the beacon to be active, in seconds.
10566 * 0x0 - Will turn off the beacon.
10567 * 0xFFFF - Will turn on the beacon until explicitly turned off.
10568 * Access: RW
10569 */
10570 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
10571
10572 /* reg_mlcr_beacon_remain
10573 * Remaining duration of the beacon, in seconds.
10574 * 0xFFFF indicates an infinite amount of time.
10575 * Access: RO
10576 */
10577 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
10578
mlxsw_reg_mlcr_pack(char * payload,u16 local_port,bool active)10579 static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port,
10580 bool active)
10581 {
10582 MLXSW_REG_ZERO(mlcr, payload);
10583 mlxsw_reg_mlcr_local_port_set(payload, local_port);
10584 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
10585 MLXSW_REG_MLCR_DURATION_MAX : 0);
10586 }
10587
10588 /* MCION - Management Cable IO and Notifications Register
10589 * ------------------------------------------------------
10590 * The MCION register is used to query transceiver modules' IO pins and other
10591 * notifications.
10592 */
10593 #define MLXSW_REG_MCION_ID 0x9052
10594 #define MLXSW_REG_MCION_LEN 0x18
10595
10596 MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN);
10597
10598 /* reg_mcion_module
10599 * Module number.
10600 * Access: Index
10601 */
10602 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8);
10603
10604 /* reg_mcion_slot_index
10605 * Slot index.
10606 * Access: Index
10607 */
10608 MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4);
10609
10610 enum {
10611 MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0),
10612 MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8),
10613 };
10614
10615 /* reg_mcion_module_status_bits
10616 * Module IO status as defined by SFF.
10617 * Access: RO
10618 */
10619 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16);
10620
mlxsw_reg_mcion_pack(char * payload,u8 slot_index,u8 module)10621 static inline void mlxsw_reg_mcion_pack(char *payload, u8 slot_index, u8 module)
10622 {
10623 MLXSW_REG_ZERO(mcion, payload);
10624 mlxsw_reg_mcion_slot_index_set(payload, slot_index);
10625 mlxsw_reg_mcion_module_set(payload, module);
10626 }
10627
10628 /* MTPPS - Management Pulse Per Second Register
10629 * --------------------------------------------
10630 * This register provides the device PPS capabilities, configure the PPS in and
10631 * out modules and holds the PPS in time stamp.
10632 */
10633 #define MLXSW_REG_MTPPS_ID 0x9053
10634 #define MLXSW_REG_MTPPS_LEN 0x3C
10635
10636 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);
10637
10638 /* reg_mtpps_enable
10639 * Enables the PPS functionality the specific pin.
10640 * A boolean variable.
10641 * Access: RW
10642 */
10643 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
10644
10645 enum mlxsw_reg_mtpps_pin_mode {
10646 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,
10647 };
10648
10649 /* reg_mtpps_pin_mode
10650 * Pin mode to be used. The mode must comply with the supported modes of the
10651 * requested pin.
10652 * Access: RW
10653 */
10654 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
10655
10656 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7
10657
10658 /* reg_mtpps_pin
10659 * Pin to be configured or queried out of the supported pins.
10660 * Access: Index
10661 */
10662 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
10663
10664 /* reg_mtpps_time_stamp
10665 * When pin_mode = pps_in, the latched device time when it was triggered from
10666 * the external GPIO pin.
10667 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target
10668 * time to generate next output signal.
10669 * Time is in units of device clock.
10670 * Access: RW
10671 */
10672 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
10673
10674 static inline void
mlxsw_reg_mtpps_vpin_pack(char * payload,u64 time_stamp)10675 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)
10676 {
10677 MLXSW_REG_ZERO(mtpps, payload);
10678 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);
10679 mlxsw_reg_mtpps_pin_mode_set(payload,
10680 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);
10681 mlxsw_reg_mtpps_enable_set(payload, true);
10682 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);
10683 }
10684
10685 /* MTUTC - Management UTC Register
10686 * -------------------------------
10687 * Configures the HW UTC counter.
10688 */
10689 #define MLXSW_REG_MTUTC_ID 0x9055
10690 #define MLXSW_REG_MTUTC_LEN 0x1C
10691
10692 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);
10693
10694 enum mlxsw_reg_mtutc_operation {
10695 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,
10696 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,
10697 };
10698
10699 /* reg_mtutc_operation
10700 * Operation.
10701 * Access: OP
10702 */
10703 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);
10704
10705 /* reg_mtutc_freq_adjustment
10706 * Frequency adjustment: Every PPS the HW frequency will be
10707 * adjusted by this value. Units of HW clock, where HW counts
10708 * 10^9 HW clocks for 1 HW second.
10709 * Access: RW
10710 */
10711 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
10712
10713 /* reg_mtutc_utc_sec
10714 * UTC seconds.
10715 * Access: WO
10716 */
10717 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
10718
10719 static inline void
mlxsw_reg_mtutc_pack(char * payload,enum mlxsw_reg_mtutc_operation oper,u32 freq_adj,u32 utc_sec)10720 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,
10721 u32 freq_adj, u32 utc_sec)
10722 {
10723 MLXSW_REG_ZERO(mtutc, payload);
10724 mlxsw_reg_mtutc_operation_set(payload, oper);
10725 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);
10726 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);
10727 }
10728
10729 /* MCQI - Management Component Query Information
10730 * ---------------------------------------------
10731 * This register allows querying information about firmware components.
10732 */
10733 #define MLXSW_REG_MCQI_ID 0x9061
10734 #define MLXSW_REG_MCQI_BASE_LEN 0x18
10735 #define MLXSW_REG_MCQI_CAP_LEN 0x14
10736 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
10737
10738 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
10739
10740 /* reg_mcqi_component_index
10741 * Index of the accessed component.
10742 * Access: Index
10743 */
10744 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
10745
10746 enum mlxfw_reg_mcqi_info_type {
10747 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
10748 };
10749
10750 /* reg_mcqi_info_type
10751 * Component properties set.
10752 * Access: RW
10753 */
10754 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
10755
10756 /* reg_mcqi_offset
10757 * The requested/returned data offset from the section start, given in bytes.
10758 * Must be DWORD aligned.
10759 * Access: RW
10760 */
10761 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
10762
10763 /* reg_mcqi_data_size
10764 * The requested/returned data size, given in bytes. If data_size is not DWORD
10765 * aligned, the last bytes are zero padded.
10766 * Access: RW
10767 */
10768 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
10769
10770 /* reg_mcqi_cap_max_component_size
10771 * Maximum size for this component, given in bytes.
10772 * Access: RO
10773 */
10774 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
10775
10776 /* reg_mcqi_cap_log_mcda_word_size
10777 * Log 2 of the access word size in bytes. Read and write access must be aligned
10778 * to the word size. Write access must be done for an integer number of words.
10779 * Access: RO
10780 */
10781 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
10782
10783 /* reg_mcqi_cap_mcda_max_write_size
10784 * Maximal write size for MCDA register
10785 * Access: RO
10786 */
10787 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
10788
mlxsw_reg_mcqi_pack(char * payload,u16 component_index)10789 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
10790 {
10791 MLXSW_REG_ZERO(mcqi, payload);
10792 mlxsw_reg_mcqi_component_index_set(payload, component_index);
10793 mlxsw_reg_mcqi_info_type_set(payload,
10794 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
10795 mlxsw_reg_mcqi_offset_set(payload, 0);
10796 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
10797 }
10798
mlxsw_reg_mcqi_unpack(char * payload,u32 * p_cap_max_component_size,u8 * p_cap_log_mcda_word_size,u16 * p_cap_mcda_max_write_size)10799 static inline void mlxsw_reg_mcqi_unpack(char *payload,
10800 u32 *p_cap_max_component_size,
10801 u8 *p_cap_log_mcda_word_size,
10802 u16 *p_cap_mcda_max_write_size)
10803 {
10804 *p_cap_max_component_size =
10805 mlxsw_reg_mcqi_cap_max_component_size_get(payload);
10806 *p_cap_log_mcda_word_size =
10807 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
10808 *p_cap_mcda_max_write_size =
10809 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
10810 }
10811
10812 /* MCC - Management Component Control
10813 * ----------------------------------
10814 * Controls the firmware component and updates the FSM.
10815 */
10816 #define MLXSW_REG_MCC_ID 0x9062
10817 #define MLXSW_REG_MCC_LEN 0x1C
10818
10819 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
10820
10821 enum mlxsw_reg_mcc_instruction {
10822 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
10823 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
10824 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
10825 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
10826 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
10827 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
10828 };
10829
10830 /* reg_mcc_instruction
10831 * Command to be executed by the FSM.
10832 * Applicable for write operation only.
10833 * Access: RW
10834 */
10835 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
10836
10837 /* reg_mcc_component_index
10838 * Index of the accessed component. Applicable only for commands that
10839 * refer to components. Otherwise, this field is reserved.
10840 * Access: Index
10841 */
10842 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
10843
10844 /* reg_mcc_update_handle
10845 * Token representing the current flow executed by the FSM.
10846 * Access: WO
10847 */
10848 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
10849
10850 /* reg_mcc_error_code
10851 * Indicates the successful completion of the instruction, or the reason it
10852 * failed
10853 * Access: RO
10854 */
10855 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
10856
10857 /* reg_mcc_control_state
10858 * Current FSM state
10859 * Access: RO
10860 */
10861 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
10862
10863 /* reg_mcc_component_size
10864 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying
10865 * the size may shorten the update time. Value 0x0 means that size is
10866 * unspecified.
10867 * Access: WO
10868 */
10869 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
10870
mlxsw_reg_mcc_pack(char * payload,enum mlxsw_reg_mcc_instruction instr,u16 component_index,u32 update_handle,u32 component_size)10871 static inline void mlxsw_reg_mcc_pack(char *payload,
10872 enum mlxsw_reg_mcc_instruction instr,
10873 u16 component_index, u32 update_handle,
10874 u32 component_size)
10875 {
10876 MLXSW_REG_ZERO(mcc, payload);
10877 mlxsw_reg_mcc_instruction_set(payload, instr);
10878 mlxsw_reg_mcc_component_index_set(payload, component_index);
10879 mlxsw_reg_mcc_update_handle_set(payload, update_handle);
10880 mlxsw_reg_mcc_component_size_set(payload, component_size);
10881 }
10882
mlxsw_reg_mcc_unpack(char * payload,u32 * p_update_handle,u8 * p_error_code,u8 * p_control_state)10883 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
10884 u8 *p_error_code, u8 *p_control_state)
10885 {
10886 if (p_update_handle)
10887 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
10888 if (p_error_code)
10889 *p_error_code = mlxsw_reg_mcc_error_code_get(payload);
10890 if (p_control_state)
10891 *p_control_state = mlxsw_reg_mcc_control_state_get(payload);
10892 }
10893
10894 /* MCDA - Management Component Data Access
10895 * ---------------------------------------
10896 * This register allows reading and writing a firmware component.
10897 */
10898 #define MLXSW_REG_MCDA_ID 0x9063
10899 #define MLXSW_REG_MCDA_BASE_LEN 0x10
10900 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
10901 #define MLXSW_REG_MCDA_LEN \
10902 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
10903
10904 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
10905
10906 /* reg_mcda_update_handle
10907 * Token representing the current flow executed by the FSM.
10908 * Access: RW
10909 */
10910 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
10911
10912 /* reg_mcda_offset
10913 * Offset of accessed address relative to component start. Accesses must be in
10914 * accordance to log_mcda_word_size in MCQI reg.
10915 * Access: RW
10916 */
10917 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
10918
10919 /* reg_mcda_size
10920 * Size of the data accessed, given in bytes.
10921 * Access: RW
10922 */
10923 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
10924
10925 /* reg_mcda_data
10926 * Data block accessed.
10927 * Access: RW
10928 */
10929 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
10930
mlxsw_reg_mcda_pack(char * payload,u32 update_handle,u32 offset,u16 size,u8 * data)10931 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
10932 u32 offset, u16 size, u8 *data)
10933 {
10934 int i;
10935
10936 MLXSW_REG_ZERO(mcda, payload);
10937 mlxsw_reg_mcda_update_handle_set(payload, update_handle);
10938 mlxsw_reg_mcda_offset_set(payload, offset);
10939 mlxsw_reg_mcda_size_set(payload, size);
10940
10941 for (i = 0; i < size / 4; i++)
10942 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
10943 }
10944
10945 /* MPSC - Monitoring Packet Sampling Configuration Register
10946 * --------------------------------------------------------
10947 * MPSC Register is used to configure the Packet Sampling mechanism.
10948 */
10949 #define MLXSW_REG_MPSC_ID 0x9080
10950 #define MLXSW_REG_MPSC_LEN 0x1C
10951
10952 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
10953
10954 /* reg_mpsc_local_port
10955 * Local port number
10956 * Not supported for CPU port
10957 * Access: Index
10958 */
10959 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12);
10960
10961 /* reg_mpsc_e
10962 * Enable sampling on port local_port
10963 * Access: RW
10964 */
10965 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
10966
10967 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
10968
10969 /* reg_mpsc_rate
10970 * Sampling rate = 1 out of rate packets (with randomization around
10971 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX
10972 * Access: RW
10973 */
10974 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
10975
mlxsw_reg_mpsc_pack(char * payload,u16 local_port,bool e,u32 rate)10976 static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e,
10977 u32 rate)
10978 {
10979 MLXSW_REG_ZERO(mpsc, payload);
10980 mlxsw_reg_mpsc_local_port_set(payload, local_port);
10981 mlxsw_reg_mpsc_e_set(payload, e);
10982 mlxsw_reg_mpsc_rate_set(payload, rate);
10983 }
10984
10985 /* MGPC - Monitoring General Purpose Counter Set Register
10986 * The MGPC register retrieves and sets the General Purpose Counter Set.
10987 */
10988 #define MLXSW_REG_MGPC_ID 0x9081
10989 #define MLXSW_REG_MGPC_LEN 0x18
10990
10991 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
10992
10993 /* reg_mgpc_counter_set_type
10994 * Counter set type.
10995 * Access: OP
10996 */
10997 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
10998
10999 /* reg_mgpc_counter_index
11000 * Counter index.
11001 * Access: Index
11002 */
11003 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
11004
11005 enum mlxsw_reg_mgpc_opcode {
11006 /* Nop */
11007 MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
11008 /* Clear counters */
11009 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
11010 };
11011
11012 /* reg_mgpc_opcode
11013 * Opcode.
11014 * Access: OP
11015 */
11016 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
11017
11018 /* reg_mgpc_byte_counter
11019 * Byte counter value.
11020 * Access: RW
11021 */
11022 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
11023
11024 /* reg_mgpc_packet_counter
11025 * Packet counter value.
11026 * Access: RW
11027 */
11028 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
11029
mlxsw_reg_mgpc_pack(char * payload,u32 counter_index,enum mlxsw_reg_mgpc_opcode opcode,enum mlxsw_reg_flow_counter_set_type set_type)11030 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
11031 enum mlxsw_reg_mgpc_opcode opcode,
11032 enum mlxsw_reg_flow_counter_set_type set_type)
11033 {
11034 MLXSW_REG_ZERO(mgpc, payload);
11035 mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
11036 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
11037 mlxsw_reg_mgpc_opcode_set(payload, opcode);
11038 }
11039
11040 /* MPRS - Monitoring Parsing State Register
11041 * ----------------------------------------
11042 * The MPRS register is used for setting up the parsing for hash,
11043 * policy-engine and routing.
11044 */
11045 #define MLXSW_REG_MPRS_ID 0x9083
11046 #define MLXSW_REG_MPRS_LEN 0x14
11047
11048 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
11049
11050 /* reg_mprs_parsing_depth
11051 * Minimum parsing depth.
11052 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL
11053 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2.
11054 * Access: RW
11055 */
11056 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
11057
11058 /* reg_mprs_parsing_en
11059 * Parsing enable.
11060 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and
11061 * NVGRE. Default is enabled. Reserved when SwitchX-2.
11062 * Access: RW
11063 */
11064 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
11065
11066 /* reg_mprs_vxlan_udp_dport
11067 * VxLAN UDP destination port.
11068 * Used for identifying VxLAN packets and for dport field in
11069 * encapsulation. Default is 4789.
11070 * Access: RW
11071 */
11072 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
11073
mlxsw_reg_mprs_pack(char * payload,u16 parsing_depth,u16 vxlan_udp_dport)11074 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
11075 u16 vxlan_udp_dport)
11076 {
11077 MLXSW_REG_ZERO(mprs, payload);
11078 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
11079 mlxsw_reg_mprs_parsing_en_set(payload, true);
11080 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
11081 }
11082
11083 /* MOGCR - Monitoring Global Configuration Register
11084 * ------------------------------------------------
11085 */
11086 #define MLXSW_REG_MOGCR_ID 0x9086
11087 #define MLXSW_REG_MOGCR_LEN 0x20
11088
11089 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);
11090
11091 /* reg_mogcr_ptp_iftc
11092 * PTP Ingress FIFO Trap Clear
11093 * The PTP_ING_FIFO trap provides MTPPTR with clr according
11094 * to this value. Default 0.
11095 * Reserved when IB switches and when SwitchX/-2, Spectrum-2
11096 * Access: RW
11097 */
11098 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
11099
11100 /* reg_mogcr_ptp_eftc
11101 * PTP Egress FIFO Trap Clear
11102 * The PTP_EGR_FIFO trap provides MTPPTR with clr according
11103 * to this value. Default 0.
11104 * Reserved when IB switches and when SwitchX/-2, Spectrum-2
11105 * Access: RW
11106 */
11107 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
11108
11109 /* reg_mogcr_mirroring_pid_base
11110 * Base policer id for mirroring policers.
11111 * Must have an even value (e.g. 1000, not 1001).
11112 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum.
11113 * Access: RW
11114 */
11115 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14);
11116
11117 /* MPAGR - Monitoring Port Analyzer Global Register
11118 * ------------------------------------------------
11119 * This register is used for global port analyzer configurations.
11120 * Note: This register is not supported by current FW versions for Spectrum-1.
11121 */
11122 #define MLXSW_REG_MPAGR_ID 0x9089
11123 #define MLXSW_REG_MPAGR_LEN 0x0C
11124
11125 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN);
11126
11127 enum mlxsw_reg_mpagr_trigger {
11128 MLXSW_REG_MPAGR_TRIGGER_EGRESS,
11129 MLXSW_REG_MPAGR_TRIGGER_INGRESS,
11130 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED,
11131 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER,
11132 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG,
11133 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG,
11134 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN,
11135 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY,
11136 };
11137
11138 /* reg_mpagr_trigger
11139 * Mirror trigger.
11140 * Access: Index
11141 */
11142 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4);
11143
11144 /* reg_mpagr_pa_id
11145 * Port analyzer ID.
11146 * Access: RW
11147 */
11148 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4);
11149
11150 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL
11151
11152 /* reg_mpagr_probability_rate
11153 * Sampling rate.
11154 * Valid values are: 1 to 3.5*10^9
11155 * Value of 1 means "sample all". Default is 1.
11156 * Access: RW
11157 */
11158 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32);
11159
mlxsw_reg_mpagr_pack(char * payload,enum mlxsw_reg_mpagr_trigger trigger,u8 pa_id,u32 probability_rate)11160 static inline void mlxsw_reg_mpagr_pack(char *payload,
11161 enum mlxsw_reg_mpagr_trigger trigger,
11162 u8 pa_id, u32 probability_rate)
11163 {
11164 MLXSW_REG_ZERO(mpagr, payload);
11165 mlxsw_reg_mpagr_trigger_set(payload, trigger);
11166 mlxsw_reg_mpagr_pa_id_set(payload, pa_id);
11167 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate);
11168 }
11169
11170 /* MOMTE - Monitoring Mirror Trigger Enable Register
11171 * -------------------------------------------------
11172 * This register is used to configure the mirror enable for different mirror
11173 * reasons.
11174 */
11175 #define MLXSW_REG_MOMTE_ID 0x908D
11176 #define MLXSW_REG_MOMTE_LEN 0x10
11177
11178 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN);
11179
11180 /* reg_momte_local_port
11181 * Local port number.
11182 * Access: Index
11183 */
11184 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12);
11185
11186 enum mlxsw_reg_momte_type {
11187 MLXSW_REG_MOMTE_TYPE_WRED = 0x20,
11188 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31,
11189 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32,
11190 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33,
11191 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40,
11192 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50,
11193 MLXSW_REG_MOMTE_TYPE_ECN = 0x60,
11194 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70,
11195 };
11196
11197 /* reg_momte_type
11198 * Type of mirroring.
11199 * Access: Index
11200 */
11201 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8);
11202
11203 /* reg_momte_tclass_en
11204 * TClass/PG mirror enable. Each bit represents corresponding tclass.
11205 * 0: disable (default)
11206 * 1: enable
11207 * Access: RW
11208 */
11209 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1);
11210
mlxsw_reg_momte_pack(char * payload,u16 local_port,enum mlxsw_reg_momte_type type)11211 static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port,
11212 enum mlxsw_reg_momte_type type)
11213 {
11214 MLXSW_REG_ZERO(momte, payload);
11215 mlxsw_reg_momte_local_port_set(payload, local_port);
11216 mlxsw_reg_momte_type_set(payload, type);
11217 }
11218
11219 /* MTPPPC - Time Precision Packet Port Configuration
11220 * -------------------------------------------------
11221 * This register serves for configuration of which PTP messages should be
11222 * timestamped. This is a global configuration, despite the register name.
11223 *
11224 * Reserved when Spectrum-2.
11225 */
11226 #define MLXSW_REG_MTPPPC_ID 0x9090
11227 #define MLXSW_REG_MTPPPC_LEN 0x28
11228
11229 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN);
11230
11231 /* reg_mtpppc_ing_timestamp_message_type
11232 * Bitwise vector of PTP message types to timestamp at ingress.
11233 * MessageType field as defined by IEEE 1588
11234 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
11235 * Default all 0
11236 * Access: RW
11237 */
11238 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
11239
11240 /* reg_mtpppc_egr_timestamp_message_type
11241 * Bitwise vector of PTP message types to timestamp at egress.
11242 * MessageType field as defined by IEEE 1588
11243 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
11244 * Default all 0
11245 * Access: RW
11246 */
11247 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
11248
mlxsw_reg_mtpppc_pack(char * payload,u16 ing,u16 egr)11249 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr)
11250 {
11251 MLXSW_REG_ZERO(mtpppc, payload);
11252 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing);
11253 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr);
11254 }
11255
11256 /* MTPPTR - Time Precision Packet Timestamping Reading
11257 * ---------------------------------------------------
11258 * The MTPPTR is used for reading the per port PTP timestamp FIFO.
11259 * There is a trap for packets which are latched to the timestamp FIFO, thus the
11260 * SW knows which FIFO to read. Note that packets enter the FIFO before been
11261 * trapped. The sequence number is used to synchronize the timestamp FIFO
11262 * entries and the trapped packets.
11263 * Reserved when Spectrum-2.
11264 */
11265
11266 #define MLXSW_REG_MTPPTR_ID 0x9091
11267 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */
11268 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */
11269 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4
11270 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \
11271 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)
11272
11273 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN);
11274
11275 /* reg_mtpptr_local_port
11276 * Not supported for CPU port.
11277 * Access: Index
11278 */
11279 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12);
11280
11281 enum mlxsw_reg_mtpptr_dir {
11282 MLXSW_REG_MTPPTR_DIR_INGRESS,
11283 MLXSW_REG_MTPPTR_DIR_EGRESS,
11284 };
11285
11286 /* reg_mtpptr_dir
11287 * Direction.
11288 * Access: Index
11289 */
11290 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);
11291
11292 /* reg_mtpptr_clr
11293 * Clear the records.
11294 * Access: OP
11295 */
11296 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
11297
11298 /* reg_mtpptr_num_rec
11299 * Number of valid records in the response
11300 * Range 0.. cap_ptp_timestamp_fifo
11301 * Access: RO
11302 */
11303 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
11304
11305 /* reg_mtpptr_rec_message_type
11306 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value
11307 * (e.g. Bit0: Sync, Bit1: Delay_Req)
11308 * Access: RO
11309 */
11310 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
11311 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,
11312 MLXSW_REG_MTPPTR_REC_LEN, 0, false);
11313
11314 /* reg_mtpptr_rec_domain_number
11315 * DomainNumber field as defined by IEEE 1588
11316 * Access: RO
11317 */
11318 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
11319 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,
11320 MLXSW_REG_MTPPTR_REC_LEN, 0, false);
11321
11322 /* reg_mtpptr_rec_sequence_id
11323 * SequenceId field as defined by IEEE 1588
11324 * Access: RO
11325 */
11326 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
11327 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,
11328 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);
11329
11330 /* reg_mtpptr_rec_timestamp_high
11331 * Timestamp of when the PTP packet has passed through the port Units of PLL
11332 * clock time.
11333 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec.
11334 * Access: RO
11335 */
11336 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
11337 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
11338 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);
11339
11340 /* reg_mtpptr_rec_timestamp_low
11341 * See rec_timestamp_high.
11342 * Access: RO
11343 */
11344 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,
11345 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
11346 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false);
11347
mlxsw_reg_mtpptr_unpack(const char * payload,unsigned int rec,u8 * p_message_type,u8 * p_domain_number,u16 * p_sequence_id,u64 * p_timestamp)11348 static inline void mlxsw_reg_mtpptr_unpack(const char *payload,
11349 unsigned int rec,
11350 u8 *p_message_type,
11351 u8 *p_domain_number,
11352 u16 *p_sequence_id,
11353 u64 *p_timestamp)
11354 {
11355 u32 timestamp_high, timestamp_low;
11356
11357 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec);
11358 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec);
11359 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec);
11360 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec);
11361 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec);
11362 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low;
11363 }
11364
11365 /* MTPTPT - Monitoring Precision Time Protocol Trap Register
11366 * ---------------------------------------------------------
11367 * This register is used for configuring under which trap to deliver PTP
11368 * packets depending on type of the packet.
11369 */
11370 #define MLXSW_REG_MTPTPT_ID 0x9092
11371 #define MLXSW_REG_MTPTPT_LEN 0x08
11372
11373 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN);
11374
11375 enum mlxsw_reg_mtptpt_trap_id {
11376 MLXSW_REG_MTPTPT_TRAP_ID_PTP0,
11377 MLXSW_REG_MTPTPT_TRAP_ID_PTP1,
11378 };
11379
11380 /* reg_mtptpt_trap_id
11381 * Trap id.
11382 * Access: Index
11383 */
11384 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);
11385
11386 /* reg_mtptpt_message_type
11387 * Bitwise vector of PTP message types to trap. This is a necessary but
11388 * non-sufficient condition since need to enable also per port. See MTPPPC.
11389 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g.
11390 * Bit0: Sync, Bit1: Delay_Req)
11391 */
11392 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
11393
mlxsw_reg_mtptptp_pack(char * payload,enum mlxsw_reg_mtptpt_trap_id trap_id,u16 message_type)11394 static inline void mlxsw_reg_mtptptp_pack(char *payload,
11395 enum mlxsw_reg_mtptpt_trap_id trap_id,
11396 u16 message_type)
11397 {
11398 MLXSW_REG_ZERO(mtptpt, payload);
11399 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id);
11400 mlxsw_reg_mtptpt_message_type_set(payload, message_type);
11401 }
11402
11403 /* MFGD - Monitoring FW General Debug Register
11404 * -------------------------------------------
11405 */
11406 #define MLXSW_REG_MFGD_ID 0x90F0
11407 #define MLXSW_REG_MFGD_LEN 0x0C
11408
11409 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN);
11410
11411 /* reg_mfgd_fw_fatal_event_mode
11412 * 0 - don't check FW fatal (default)
11413 * 1 - check FW fatal - enable MFDE trap
11414 * Access: RW
11415 */
11416 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2);
11417
11418 /* reg_mfgd_trigger_test
11419 * Access: WO
11420 */
11421 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1);
11422
11423 /* MGPIR - Management General Peripheral Information Register
11424 * ----------------------------------------------------------
11425 * MGPIR register allows software to query the hardware and
11426 * firmware general information of peripheral entities.
11427 */
11428 #define MLXSW_REG_MGPIR_ID 0x9100
11429 #define MLXSW_REG_MGPIR_LEN 0xA0
11430
11431 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN);
11432
11433 enum mlxsw_reg_mgpir_device_type {
11434 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE,
11435 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE,
11436 };
11437
11438 /* mgpir_slot_index
11439 * Slot index (0: Main board).
11440 * Access: Index
11441 */
11442 MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4);
11443
11444 /* mgpir_device_type
11445 * Access: RO
11446 */
11447 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4);
11448
11449 /* mgpir_devices_per_flash
11450 * Number of devices of device_type per flash (can be shared by few devices).
11451 * Access: RO
11452 */
11453 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);
11454
11455 /* mgpir_num_of_devices
11456 * Number of devices of device_type.
11457 * Access: RO
11458 */
11459 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);
11460
11461 /* max_modules_per_slot
11462 * Maximum number of modules that can be connected per slot.
11463 * Access: RO
11464 */
11465 MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8);
11466
11467 /* mgpir_num_of_slots
11468 * Number of slots in the system.
11469 * Access: RO
11470 */
11471 MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8);
11472
11473 /* mgpir_num_of_modules
11474 * Number of modules.
11475 * Access: RO
11476 */
11477 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8);
11478
mlxsw_reg_mgpir_pack(char * payload,u8 slot_index)11479 static inline void mlxsw_reg_mgpir_pack(char *payload, u8 slot_index)
11480 {
11481 MLXSW_REG_ZERO(mgpir, payload);
11482 mlxsw_reg_mgpir_slot_index_set(payload, slot_index);
11483 }
11484
11485 static inline void
mlxsw_reg_mgpir_unpack(char * payload,u8 * num_of_devices,enum mlxsw_reg_mgpir_device_type * device_type,u8 * devices_per_flash,u8 * num_of_modules,u8 * num_of_slots)11486 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,
11487 enum mlxsw_reg_mgpir_device_type *device_type,
11488 u8 *devices_per_flash, u8 *num_of_modules,
11489 u8 *num_of_slots)
11490 {
11491 if (num_of_devices)
11492 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload);
11493 if (device_type)
11494 *device_type = mlxsw_reg_mgpir_device_type_get(payload);
11495 if (devices_per_flash)
11496 *devices_per_flash =
11497 mlxsw_reg_mgpir_devices_per_flash_get(payload);
11498 if (num_of_modules)
11499 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload);
11500 if (num_of_slots)
11501 *num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload);
11502 }
11503
11504 /* MBCT - Management Binary Code Transfer Register
11505 * -----------------------------------------------
11506 * This register allows to transfer binary codes from the host to
11507 * the management FW by transferring it by chunks of maximum 1KB.
11508 */
11509 #define MLXSW_REG_MBCT_ID 0x9120
11510 #define MLXSW_REG_MBCT_LEN 0x420
11511
11512 MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN);
11513
11514 /* reg_mbct_slot_index
11515 * Slot index. 0 is reserved.
11516 * Access: Index
11517 */
11518 MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4);
11519
11520 /* reg_mbct_data_size
11521 * Actual data field size in bytes for the current data transfer.
11522 * Access: WO
11523 */
11524 MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11);
11525
11526 enum mlxsw_reg_mbct_op {
11527 MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1,
11528 MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */
11529 MLXSW_REG_MBCT_OP_ACTIVATE,
11530 MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6,
11531 MLXSW_REG_MBCT_OP_QUERY_STATUS,
11532 };
11533
11534 /* reg_mbct_op
11535 * Access: WO
11536 */
11537 MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4);
11538
11539 /* reg_mbct_last
11540 * Indicates that the current data field is the last chunk of the INI.
11541 * Access: WO
11542 */
11543 MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1);
11544
11545 /* reg_mbct_oee
11546 * Opcode Event Enable. When set a BCTOE event will be sent once the opcode
11547 * was executed and the fsm_state has changed.
11548 * Access: WO
11549 */
11550 MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1);
11551
11552 enum mlxsw_reg_mbct_status {
11553 /* Partial data transfer completed successfully and ready for next
11554 * data transfer.
11555 */
11556 MLXSW_REG_MBCT_STATUS_PART_DATA = 2,
11557 MLXSW_REG_MBCT_STATUS_LAST_DATA,
11558 MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE,
11559 /* Error - trying to erase INI while it being used. */
11560 MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE,
11561 /* Last data transfer completed, applying magic pattern. */
11562 MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7,
11563 MLXSW_REG_MBCT_STATUS_INI_ERROR,
11564 MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED,
11565 MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11,
11566 };
11567
11568 /* reg_mbct_status
11569 * Status.
11570 * Access: RO
11571 */
11572 MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5);
11573
11574 enum mlxsw_reg_mbct_fsm_state {
11575 MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5,
11576 MLXSW_REG_MBCT_FSM_STATE_ERROR,
11577 };
11578
11579 /* reg_mbct_fsm_state
11580 * FSM state.
11581 * Access: RO
11582 */
11583 MLXSW_ITEM32(reg, mbct, fsm_state, 0x0C, 16, 4);
11584
11585 #define MLXSW_REG_MBCT_DATA_LEN 1024
11586
11587 /* reg_mbct_data
11588 * Up to 1KB of data.
11589 * Access: WO
11590 */
11591 MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN);
11592
mlxsw_reg_mbct_pack(char * payload,u8 slot_index,enum mlxsw_reg_mbct_op op,bool oee)11593 static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index,
11594 enum mlxsw_reg_mbct_op op, bool oee)
11595 {
11596 MLXSW_REG_ZERO(mbct, payload);
11597 mlxsw_reg_mbct_slot_index_set(payload, slot_index);
11598 mlxsw_reg_mbct_op_set(payload, op);
11599 mlxsw_reg_mbct_oee_set(payload, oee);
11600 }
11601
mlxsw_reg_mbct_dt_pack(char * payload,u16 data_size,bool last,const char * data)11602 static inline void mlxsw_reg_mbct_dt_pack(char *payload,
11603 u16 data_size, bool last,
11604 const char *data)
11605 {
11606 if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN))
11607 return;
11608 mlxsw_reg_mbct_data_size_set(payload, data_size);
11609 mlxsw_reg_mbct_last_set(payload, last);
11610 mlxsw_reg_mbct_data_memcpy_to(payload, data);
11611 }
11612
11613 static inline void
mlxsw_reg_mbct_unpack(const char * payload,u8 * p_slot_index,enum mlxsw_reg_mbct_status * p_status,enum mlxsw_reg_mbct_fsm_state * p_fsm_state)11614 mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index,
11615 enum mlxsw_reg_mbct_status *p_status,
11616 enum mlxsw_reg_mbct_fsm_state *p_fsm_state)
11617 {
11618 if (p_slot_index)
11619 *p_slot_index = mlxsw_reg_mbct_slot_index_get(payload);
11620 *p_status = mlxsw_reg_mbct_status_get(payload);
11621 if (p_fsm_state)
11622 *p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload);
11623 }
11624
11625 /* MDDQ - Management DownStream Device Query Register
11626 * --------------------------------------------------
11627 * This register allows to query the DownStream device properties. The desired
11628 * information is chosen upon the query_type field and is delivered by 32B
11629 * of data blocks.
11630 */
11631 #define MLXSW_REG_MDDQ_ID 0x9161
11632 #define MLXSW_REG_MDDQ_LEN 0x30
11633
11634 MLXSW_REG_DEFINE(mddq, MLXSW_REG_MDDQ_ID, MLXSW_REG_MDDQ_LEN);
11635
11636 /* reg_mddq_sie
11637 * Slot info event enable.
11638 * When set to '1', each change in the slot_info.provisioned / sr_valid /
11639 * active / ready will generate a DSDSC event.
11640 * Access: RW
11641 */
11642 MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1);
11643
11644 enum mlxsw_reg_mddq_query_type {
11645 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1,
11646 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME = 3,
11647 };
11648
11649 /* reg_mddq_query_type
11650 * Access: Index
11651 */
11652 MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8);
11653
11654 /* reg_mddq_slot_index
11655 * Slot index. 0 is reserved.
11656 * Access: Index
11657 */
11658 MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4);
11659
11660 /* reg_mddq_slot_info_provisioned
11661 * If set, the INI file is applied and the card is provisioned.
11662 * Access: RO
11663 */
11664 MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1);
11665
11666 /* reg_mddq_slot_info_sr_valid
11667 * If set, Shift Register is valid (after being provisioned) and data
11668 * can be sent from the switch ASIC to the line-card CPLD over Shift-Register.
11669 * Access: RO
11670 */
11671 MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1);
11672
11673 enum mlxsw_reg_mddq_slot_info_ready {
11674 MLXSW_REG_MDDQ_SLOT_INFO_READY_NOT_READY,
11675 MLXSW_REG_MDDQ_SLOT_INFO_READY_READY,
11676 MLXSW_REG_MDDQ_SLOT_INFO_READY_ERROR,
11677 };
11678
11679 /* reg_mddq_slot_info_lc_ready
11680 * If set, the LC is powered on, matching the INI version and a new FW
11681 * version can be burnt (if necessary).
11682 * Access: RO
11683 */
11684 MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2);
11685
11686 /* reg_mddq_slot_info_active
11687 * If set, the FW has completed the MDDC.device_enable command.
11688 * Access: RO
11689 */
11690 MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1);
11691
11692 /* reg_mddq_slot_info_hw_revision
11693 * Major user-configured version number of the current INI file.
11694 * Valid only when active or ready are '1'.
11695 * Access: RO
11696 */
11697 MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16);
11698
11699 /* reg_mddq_slot_info_ini_file_version
11700 * User-configured version number of the current INI file.
11701 * Valid only when active or lc_ready are '1'.
11702 * Access: RO
11703 */
11704 MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16);
11705
11706 /* reg_mddq_slot_info_card_type
11707 * Access: RO
11708 */
11709 MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8);
11710
11711 static inline void
__mlxsw_reg_mddq_pack(char * payload,u8 slot_index,enum mlxsw_reg_mddq_query_type query_type)11712 __mlxsw_reg_mddq_pack(char *payload, u8 slot_index,
11713 enum mlxsw_reg_mddq_query_type query_type)
11714 {
11715 MLXSW_REG_ZERO(mddq, payload);
11716 mlxsw_reg_mddq_slot_index_set(payload, slot_index);
11717 mlxsw_reg_mddq_query_type_set(payload, query_type);
11718 }
11719
11720 static inline void
mlxsw_reg_mddq_slot_info_pack(char * payload,u8 slot_index,bool sie)11721 mlxsw_reg_mddq_slot_info_pack(char *payload, u8 slot_index, bool sie)
11722 {
11723 __mlxsw_reg_mddq_pack(payload, slot_index,
11724 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO);
11725 mlxsw_reg_mddq_sie_set(payload, sie);
11726 }
11727
11728 static inline void
mlxsw_reg_mddq_slot_info_unpack(const char * payload,u8 * p_slot_index,bool * p_provisioned,bool * p_sr_valid,enum mlxsw_reg_mddq_slot_info_ready * p_lc_ready,bool * p_active,u16 * p_hw_revision,u16 * p_ini_file_version,u8 * p_card_type)11729 mlxsw_reg_mddq_slot_info_unpack(const char *payload, u8 *p_slot_index,
11730 bool *p_provisioned, bool *p_sr_valid,
11731 enum mlxsw_reg_mddq_slot_info_ready *p_lc_ready,
11732 bool *p_active, u16 *p_hw_revision,
11733 u16 *p_ini_file_version,
11734 u8 *p_card_type)
11735 {
11736 *p_slot_index = mlxsw_reg_mddq_slot_index_get(payload);
11737 *p_provisioned = mlxsw_reg_mddq_slot_info_provisioned_get(payload);
11738 *p_sr_valid = mlxsw_reg_mddq_slot_info_sr_valid_get(payload);
11739 *p_lc_ready = mlxsw_reg_mddq_slot_info_lc_ready_get(payload);
11740 *p_active = mlxsw_reg_mddq_slot_info_active_get(payload);
11741 *p_hw_revision = mlxsw_reg_mddq_slot_info_hw_revision_get(payload);
11742 *p_ini_file_version = mlxsw_reg_mddq_slot_info_ini_file_version_get(payload);
11743 *p_card_type = mlxsw_reg_mddq_slot_info_card_type_get(payload);
11744 }
11745
11746 #define MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN 20
11747
11748 /* reg_mddq_slot_ascii_name
11749 * Slot's ASCII name.
11750 * Access: RO
11751 */
11752 MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10,
11753 MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN);
11754
11755 static inline void
mlxsw_reg_mddq_slot_name_pack(char * payload,u8 slot_index)11756 mlxsw_reg_mddq_slot_name_pack(char *payload, u8 slot_index)
11757 {
11758 __mlxsw_reg_mddq_pack(payload, slot_index,
11759 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME);
11760 }
11761
11762 static inline void
mlxsw_reg_mddq_slot_name_unpack(const char * payload,char * slot_ascii_name)11763 mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name)
11764 {
11765 mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name);
11766 }
11767
11768 /* MDDC - Management DownStream Device Control Register
11769 * ----------------------------------------------------
11770 * This register allows to control downstream devices and line cards.
11771 */
11772 #define MLXSW_REG_MDDC_ID 0x9163
11773 #define MLXSW_REG_MDDC_LEN 0x30
11774
11775 MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN);
11776
11777 /* reg_mddc_slot_index
11778 * Slot index. 0 is reserved.
11779 * Access: Index
11780 */
11781 MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4);
11782
11783 /* reg_mddc_rst
11784 * Reset request.
11785 * Access: OP
11786 */
11787 MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1);
11788
11789 /* reg_mddc_device_enable
11790 * When set, FW is the manager and allowed to program the downstream device.
11791 * Access: RW
11792 */
11793 MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1);
11794
mlxsw_reg_mddc_pack(char * payload,u8 slot_index,bool rst,bool device_enable)11795 static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst,
11796 bool device_enable)
11797 {
11798 MLXSW_REG_ZERO(mddc, payload);
11799 mlxsw_reg_mddc_slot_index_set(payload, slot_index);
11800 mlxsw_reg_mddc_rst_set(payload, rst);
11801 mlxsw_reg_mddc_device_enable_set(payload, device_enable);
11802 }
11803
11804 /* MFDE - Monitoring FW Debug Register
11805 * -----------------------------------
11806 */
11807 #define MLXSW_REG_MFDE_ID 0x9200
11808 #define MLXSW_REG_MFDE_LEN 0x30
11809
11810 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN);
11811
11812 /* reg_mfde_irisc_id
11813 * Which irisc triggered the event
11814 * Access: RO
11815 */
11816 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8);
11817
11818 enum mlxsw_reg_mfde_severity {
11819 /* Unrecoverable switch behavior */
11820 MLXSW_REG_MFDE_SEVERITY_FATL = 2,
11821 /* Unexpected state with possible systemic failure */
11822 MLXSW_REG_MFDE_SEVERITY_NRML = 3,
11823 /* Unexpected state without systemic failure */
11824 MLXSW_REG_MFDE_SEVERITY_INTR = 5,
11825 };
11826
11827 /* reg_mfde_severity
11828 * The severity of the event.
11829 * Access: RO
11830 */
11831 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8);
11832
11833 enum mlxsw_reg_mfde_event_id {
11834 /* CRspace timeout */
11835 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1,
11836 /* KVD insertion machine stopped */
11837 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP,
11838 /* Triggered by MFGD.trigger_test */
11839 MLXSW_REG_MFDE_EVENT_ID_TEST,
11840 /* Triggered when firmware hits an assert */
11841 MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT,
11842 /* Fatal error interrupt from hardware */
11843 MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE,
11844 };
11845
11846 /* reg_mfde_event_id
11847 * Access: RO
11848 */
11849 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16);
11850
11851 enum mlxsw_reg_mfde_method {
11852 MLXSW_REG_MFDE_METHOD_QUERY,
11853 MLXSW_REG_MFDE_METHOD_WRITE,
11854 };
11855
11856 /* reg_mfde_method
11857 * Access: RO
11858 */
11859 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1);
11860
11861 /* reg_mfde_long_process
11862 * Indicates if the command is in long_process mode.
11863 * Access: RO
11864 */
11865 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1);
11866
11867 enum mlxsw_reg_mfde_command_type {
11868 MLXSW_REG_MFDE_COMMAND_TYPE_MAD,
11869 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD,
11870 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF,
11871 };
11872
11873 /* reg_mfde_command_type
11874 * Access: RO
11875 */
11876 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2);
11877
11878 /* reg_mfde_reg_attr_id
11879 * EMAD - register id, MAD - attibute id
11880 * Access: RO
11881 */
11882 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16);
11883
11884 /* reg_mfde_crspace_to_log_address
11885 * crspace address accessed, which resulted in timeout.
11886 * Access: RO
11887 */
11888 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32);
11889
11890 /* reg_mfde_crspace_to_oe
11891 * 0 - New event
11892 * 1 - Old event, occurred before MFGD activation.
11893 * Access: RO
11894 */
11895 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1);
11896
11897 /* reg_mfde_crspace_to_log_id
11898 * Which irisc triggered the timeout.
11899 * Access: RO
11900 */
11901 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4);
11902
11903 /* reg_mfde_crspace_to_log_ip
11904 * IP (instruction pointer) that triggered the timeout.
11905 * Access: RO
11906 */
11907 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64);
11908
11909 /* reg_mfde_kvd_im_stop_oe
11910 * 0 - New event
11911 * 1 - Old event, occurred before MFGD activation.
11912 * Access: RO
11913 */
11914 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1);
11915
11916 /* reg_mfde_kvd_im_stop_pipes_mask
11917 * Bit per kvh pipe.
11918 * Access: RO
11919 */
11920 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16);
11921
11922 /* reg_mfde_fw_assert_var0-4
11923 * Variables passed to assert.
11924 * Access: RO
11925 */
11926 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32);
11927 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32);
11928 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32);
11929 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32);
11930 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32);
11931
11932 /* reg_mfde_fw_assert_existptr
11933 * The instruction pointer when assert was triggered.
11934 * Access: RO
11935 */
11936 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32);
11937
11938 /* reg_mfde_fw_assert_callra
11939 * The return address after triggering assert.
11940 * Access: RO
11941 */
11942 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32);
11943
11944 /* reg_mfde_fw_assert_oe
11945 * 0 - New event
11946 * 1 - Old event, occurred before MFGD activation.
11947 * Access: RO
11948 */
11949 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1);
11950
11951 /* reg_mfde_fw_assert_tile_v
11952 * 0: The assert was from main
11953 * 1: The assert was from a tile
11954 * Access: RO
11955 */
11956 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1);
11957
11958 /* reg_mfde_fw_assert_tile_index
11959 * When tile_v=1, the tile_index that caused the assert.
11960 * Access: RO
11961 */
11962 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6);
11963
11964 /* reg_mfde_fw_assert_ext_synd
11965 * A generated one-to-one identifier which is specific per-assert.
11966 * Access: RO
11967 */
11968 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16);
11969
11970 /* reg_mfde_fatal_cause_id
11971 * HW interrupt cause id.
11972 * Access: RO
11973 */
11974 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18);
11975
11976 /* reg_mfde_fatal_cause_tile_v
11977 * 0: The assert was from main
11978 * 1: The assert was from a tile
11979 * Access: RO
11980 */
11981 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1);
11982
11983 /* reg_mfde_fatal_cause_tile_index
11984 * When tile_v=1, the tile_index that caused the assert.
11985 * Access: RO
11986 */
11987 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6);
11988
11989 /* TNGCR - Tunneling NVE General Configuration Register
11990 * ----------------------------------------------------
11991 * The TNGCR register is used for setting up the NVE Tunneling configuration.
11992 */
11993 #define MLXSW_REG_TNGCR_ID 0xA001
11994 #define MLXSW_REG_TNGCR_LEN 0x44
11995
11996 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
11997
11998 enum mlxsw_reg_tngcr_type {
11999 MLXSW_REG_TNGCR_TYPE_VXLAN,
12000 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
12001 MLXSW_REG_TNGCR_TYPE_GENEVE,
12002 MLXSW_REG_TNGCR_TYPE_NVGRE,
12003 };
12004
12005 /* reg_tngcr_type
12006 * Tunnel type for encapsulation and decapsulation. The types are mutually
12007 * exclusive.
12008 * Note: For Spectrum the NVE parsing must be enabled in MPRS.
12009 * Access: RW
12010 */
12011 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
12012
12013 /* reg_tngcr_nve_valid
12014 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation.
12015 * Access: RW
12016 */
12017 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
12018
12019 /* reg_tngcr_nve_ttl_uc
12020 * The TTL for NVE tunnel encapsulation underlay unicast packets.
12021 * Access: RW
12022 */
12023 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
12024
12025 /* reg_tngcr_nve_ttl_mc
12026 * The TTL for NVE tunnel encapsulation underlay multicast packets.
12027 * Access: RW
12028 */
12029 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
12030
12031 enum {
12032 /* Do not copy flow label. Calculate flow label using nve_flh. */
12033 MLXSW_REG_TNGCR_FL_NO_COPY,
12034 /* Copy flow label from inner packet if packet is IPv6 and
12035 * encapsulation is by IPv6. Otherwise, calculate flow label using
12036 * nve_flh.
12037 */
12038 MLXSW_REG_TNGCR_FL_COPY,
12039 };
12040
12041 /* reg_tngcr_nve_flc
12042 * For NVE tunnel encapsulation: Flow label copy from inner packet.
12043 * Access: RW
12044 */
12045 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
12046
12047 enum {
12048 /* Flow label is static. In Spectrum this means '0'. Spectrum-2
12049 * uses {nve_fl_prefix, nve_fl_suffix}.
12050 */
12051 MLXSW_REG_TNGCR_FL_NO_HASH,
12052 /* 8 LSBs of the flow label are calculated from ECMP hash of the
12053 * inner packet. 12 MSBs are configured by nve_fl_prefix.
12054 */
12055 MLXSW_REG_TNGCR_FL_HASH,
12056 };
12057
12058 /* reg_tngcr_nve_flh
12059 * NVE flow label hash.
12060 * Access: RW
12061 */
12062 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
12063
12064 /* reg_tngcr_nve_fl_prefix
12065 * NVE flow label prefix. Constant 12 MSBs of the flow label.
12066 * Access: RW
12067 */
12068 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
12069
12070 /* reg_tngcr_nve_fl_suffix
12071 * NVE flow label suffix. Constant 8 LSBs of the flow label.
12072 * Reserved when nve_flh=1 and for Spectrum.
12073 * Access: RW
12074 */
12075 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
12076
12077 enum {
12078 /* Source UDP port is fixed (default '0') */
12079 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
12080 /* Source UDP port is calculated based on hash */
12081 MLXSW_REG_TNGCR_UDP_SPORT_HASH,
12082 };
12083
12084 /* reg_tngcr_nve_udp_sport_type
12085 * NVE UDP source port type.
12086 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2).
12087 * When the source UDP port is calculated based on hash, then the 8 LSBs
12088 * are calculated from hash the 8 MSBs are configured by
12089 * nve_udp_sport_prefix.
12090 * Access: RW
12091 */
12092 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
12093
12094 /* reg_tngcr_nve_udp_sport_prefix
12095 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port.
12096 * Reserved when NVE type is NVGRE.
12097 * Access: RW
12098 */
12099 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
12100
12101 /* reg_tngcr_nve_group_size_mc
12102 * The amount of sequential linked lists of MC entries. The first linked
12103 * list is configured by SFD.underlay_mc_ptr.
12104 * Valid values: 1, 2, 4, 8, 16, 32, 64
12105 * The linked list are configured by TNUMT.
12106 * The hash is set by LAG hash.
12107 * Access: RW
12108 */
12109 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
12110
12111 /* reg_tngcr_nve_group_size_flood
12112 * The amount of sequential linked lists of flooding entries. The first
12113 * linked list is configured by SFMR.nve_tunnel_flood_ptr
12114 * Valid values: 1, 2, 4, 8, 16, 32, 64
12115 * The linked list are configured by TNUMT.
12116 * The hash is set by LAG hash.
12117 * Access: RW
12118 */
12119 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
12120
12121 /* reg_tngcr_learn_enable
12122 * During decapsulation, whether to learn from NVE port.
12123 * Reserved when Spectrum-2. See TNPC.
12124 * Access: RW
12125 */
12126 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
12127
12128 /* reg_tngcr_underlay_virtual_router
12129 * Underlay virtual router.
12130 * Reserved when Spectrum-2.
12131 * Access: RW
12132 */
12133 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
12134
12135 /* reg_tngcr_underlay_rif
12136 * Underlay ingress router interface. RIF type should be loopback generic.
12137 * Reserved when Spectrum.
12138 * Access: RW
12139 */
12140 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
12141
12142 /* reg_tngcr_usipv4
12143 * Underlay source IPv4 address of the NVE.
12144 * Access: RW
12145 */
12146 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
12147
12148 /* reg_tngcr_usipv6
12149 * Underlay source IPv6 address of the NVE. For Spectrum, must not be
12150 * modified under traffic of NVE tunneling encapsulation.
12151 * Access: RW
12152 */
12153 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
12154
mlxsw_reg_tngcr_pack(char * payload,enum mlxsw_reg_tngcr_type type,bool valid,u8 ttl)12155 static inline void mlxsw_reg_tngcr_pack(char *payload,
12156 enum mlxsw_reg_tngcr_type type,
12157 bool valid, u8 ttl)
12158 {
12159 MLXSW_REG_ZERO(tngcr, payload);
12160 mlxsw_reg_tngcr_type_set(payload, type);
12161 mlxsw_reg_tngcr_nve_valid_set(payload, valid);
12162 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
12163 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
12164 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
12165 mlxsw_reg_tngcr_nve_flh_set(payload, 0);
12166 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
12167 MLXSW_REG_TNGCR_UDP_SPORT_HASH);
12168 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
12169 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
12170 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
12171 }
12172
12173 /* TNUMT - Tunneling NVE Underlay Multicast Table Register
12174 * -------------------------------------------------------
12175 * The TNUMT register is for building the underlay MC table. It is used
12176 * for MC, flooding and BC traffic into the NVE tunnel.
12177 */
12178 #define MLXSW_REG_TNUMT_ID 0xA003
12179 #define MLXSW_REG_TNUMT_LEN 0x20
12180
12181 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
12182
12183 enum mlxsw_reg_tnumt_record_type {
12184 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
12185 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
12186 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
12187 };
12188
12189 /* reg_tnumt_record_type
12190 * Record type.
12191 * Access: RW
12192 */
12193 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
12194
12195 /* reg_tnumt_tunnel_port
12196 * Tunnel port.
12197 * Access: RW
12198 */
12199 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
12200
12201 /* reg_tnumt_underlay_mc_ptr
12202 * Index to the underlay multicast table.
12203 * For Spectrum the index is to the KVD linear.
12204 * Access: Index
12205 */
12206 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
12207
12208 /* reg_tnumt_vnext
12209 * The next_underlay_mc_ptr is valid.
12210 * Access: RW
12211 */
12212 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
12213
12214 /* reg_tnumt_next_underlay_mc_ptr
12215 * The next index to the underlay multicast table.
12216 * Access: RW
12217 */
12218 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
12219
12220 /* reg_tnumt_record_size
12221 * Number of IP addresses in the record.
12222 * Range is 1..cap_max_nve_mc_entries_ipv{4,6}
12223 * Access: RW
12224 */
12225 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
12226
12227 /* reg_tnumt_udip
12228 * The underlay IPv4 addresses. udip[i] is reserved if i >= size
12229 * Access: RW
12230 */
12231 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
12232
12233 /* reg_tnumt_udip_ptr
12234 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if
12235 * i >= size. The IPv6 addresses are configured by RIPS.
12236 * Access: RW
12237 */
12238 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
12239
mlxsw_reg_tnumt_pack(char * payload,enum mlxsw_reg_tnumt_record_type type,enum mlxsw_reg_tunnel_port tport,u32 underlay_mc_ptr,bool vnext,u32 next_underlay_mc_ptr,u8 record_size)12240 static inline void mlxsw_reg_tnumt_pack(char *payload,
12241 enum mlxsw_reg_tnumt_record_type type,
12242 enum mlxsw_reg_tunnel_port tport,
12243 u32 underlay_mc_ptr, bool vnext,
12244 u32 next_underlay_mc_ptr,
12245 u8 record_size)
12246 {
12247 MLXSW_REG_ZERO(tnumt, payload);
12248 mlxsw_reg_tnumt_record_type_set(payload, type);
12249 mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
12250 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
12251 mlxsw_reg_tnumt_vnext_set(payload, vnext);
12252 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
12253 mlxsw_reg_tnumt_record_size_set(payload, record_size);
12254 }
12255
12256 /* TNQCR - Tunneling NVE QoS Configuration Register
12257 * ------------------------------------------------
12258 * The TNQCR register configures how QoS is set in encapsulation into the
12259 * underlay network.
12260 */
12261 #define MLXSW_REG_TNQCR_ID 0xA010
12262 #define MLXSW_REG_TNQCR_LEN 0x0C
12263
12264 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
12265
12266 /* reg_tnqcr_enc_set_dscp
12267 * For encapsulation: How to set DSCP field:
12268 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay
12269 * (outer) IP header. If there is no IP header, use TNQDR.dscp
12270 * 1 - Set the DSCP field as TNQDR.dscp
12271 * Access: RW
12272 */
12273 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
12274
mlxsw_reg_tnqcr_pack(char * payload)12275 static inline void mlxsw_reg_tnqcr_pack(char *payload)
12276 {
12277 MLXSW_REG_ZERO(tnqcr, payload);
12278 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
12279 }
12280
12281 /* TNQDR - Tunneling NVE QoS Default Register
12282 * ------------------------------------------
12283 * The TNQDR register configures the default QoS settings for NVE
12284 * encapsulation.
12285 */
12286 #define MLXSW_REG_TNQDR_ID 0xA011
12287 #define MLXSW_REG_TNQDR_LEN 0x08
12288
12289 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
12290
12291 /* reg_tnqdr_local_port
12292 * Local port number (receive port). CPU port is supported.
12293 * Access: Index
12294 */
12295 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12);
12296
12297 /* reg_tnqdr_dscp
12298 * For encapsulation, the default DSCP.
12299 * Access: RW
12300 */
12301 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
12302
mlxsw_reg_tnqdr_pack(char * payload,u16 local_port)12303 static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port)
12304 {
12305 MLXSW_REG_ZERO(tnqdr, payload);
12306 mlxsw_reg_tnqdr_local_port_set(payload, local_port);
12307 mlxsw_reg_tnqdr_dscp_set(payload, 0);
12308 }
12309
12310 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
12311 * --------------------------------------------------------
12312 * The TNEEM register maps ECN of the IP header at the ingress to the
12313 * encapsulation to the ECN of the underlay network.
12314 */
12315 #define MLXSW_REG_TNEEM_ID 0xA012
12316 #define MLXSW_REG_TNEEM_LEN 0x0C
12317
12318 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
12319
12320 /* reg_tneem_overlay_ecn
12321 * ECN of the IP header in the overlay network.
12322 * Access: Index
12323 */
12324 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
12325
12326 /* reg_tneem_underlay_ecn
12327 * ECN of the IP header in the underlay network.
12328 * Access: RW
12329 */
12330 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
12331
mlxsw_reg_tneem_pack(char * payload,u8 overlay_ecn,u8 underlay_ecn)12332 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
12333 u8 underlay_ecn)
12334 {
12335 MLXSW_REG_ZERO(tneem, payload);
12336 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
12337 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
12338 }
12339
12340 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register
12341 * --------------------------------------------------------
12342 * The TNDEM register configures the actions that are done in the
12343 * decapsulation.
12344 */
12345 #define MLXSW_REG_TNDEM_ID 0xA013
12346 #define MLXSW_REG_TNDEM_LEN 0x0C
12347
12348 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
12349
12350 /* reg_tndem_underlay_ecn
12351 * ECN field of the IP header in the underlay network.
12352 * Access: Index
12353 */
12354 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
12355
12356 /* reg_tndem_overlay_ecn
12357 * ECN field of the IP header in the overlay network.
12358 * Access: Index
12359 */
12360 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
12361
12362 /* reg_tndem_eip_ecn
12363 * Egress IP ECN. ECN field of the IP header of the packet which goes out
12364 * from the decapsulation.
12365 * Access: RW
12366 */
12367 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
12368
12369 /* reg_tndem_trap_en
12370 * Trap enable:
12371 * 0 - No trap due to decap ECN
12372 * 1 - Trap enable with trap_id
12373 * Access: RW
12374 */
12375 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
12376
12377 /* reg_tndem_trap_id
12378 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
12379 * Reserved when trap_en is '0'.
12380 * Access: RW
12381 */
12382 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
12383
mlxsw_reg_tndem_pack(char * payload,u8 underlay_ecn,u8 overlay_ecn,u8 ecn,bool trap_en,u16 trap_id)12384 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
12385 u8 overlay_ecn, u8 ecn, bool trap_en,
12386 u16 trap_id)
12387 {
12388 MLXSW_REG_ZERO(tndem, payload);
12389 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
12390 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
12391 mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
12392 mlxsw_reg_tndem_trap_en_set(payload, trap_en);
12393 mlxsw_reg_tndem_trap_id_set(payload, trap_id);
12394 }
12395
12396 /* TNPC - Tunnel Port Configuration Register
12397 * -----------------------------------------
12398 * The TNPC register is used for tunnel port configuration.
12399 * Reserved when Spectrum.
12400 */
12401 #define MLXSW_REG_TNPC_ID 0xA020
12402 #define MLXSW_REG_TNPC_LEN 0x18
12403
12404 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
12405
12406 /* reg_tnpc_tunnel_port
12407 * Tunnel port.
12408 * Access: Index
12409 */
12410 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
12411
12412 /* reg_tnpc_learn_enable_v6
12413 * During IPv6 underlay decapsulation, whether to learn from tunnel port.
12414 * Access: RW
12415 */
12416 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
12417
12418 /* reg_tnpc_learn_enable_v4
12419 * During IPv4 underlay decapsulation, whether to learn from tunnel port.
12420 * Access: RW
12421 */
12422 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
12423
mlxsw_reg_tnpc_pack(char * payload,enum mlxsw_reg_tunnel_port tport,bool learn_enable)12424 static inline void mlxsw_reg_tnpc_pack(char *payload,
12425 enum mlxsw_reg_tunnel_port tport,
12426 bool learn_enable)
12427 {
12428 MLXSW_REG_ZERO(tnpc, payload);
12429 mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
12430 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
12431 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
12432 }
12433
12434 /* TIGCR - Tunneling IPinIP General Configuration Register
12435 * -------------------------------------------------------
12436 * The TIGCR register is used for setting up the IPinIP Tunnel configuration.
12437 */
12438 #define MLXSW_REG_TIGCR_ID 0xA801
12439 #define MLXSW_REG_TIGCR_LEN 0x10
12440
12441 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
12442
12443 /* reg_tigcr_ipip_ttlc
12444 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet
12445 * header.
12446 * Access: RW
12447 */
12448 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
12449
12450 /* reg_tigcr_ipip_ttl_uc
12451 * The TTL for IPinIP Tunnel encapsulation of unicast packets if
12452 * reg_tigcr_ipip_ttlc is unset.
12453 * Access: RW
12454 */
12455 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
12456
mlxsw_reg_tigcr_pack(char * payload,bool ttlc,u8 ttl_uc)12457 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
12458 {
12459 MLXSW_REG_ZERO(tigcr, payload);
12460 mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
12461 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
12462 }
12463
12464 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register
12465 * -----------------------------------------------------------
12466 * The TIEEM register maps ECN of the IP header at the ingress to the
12467 * encapsulation to the ECN of the underlay network.
12468 */
12469 #define MLXSW_REG_TIEEM_ID 0xA812
12470 #define MLXSW_REG_TIEEM_LEN 0x0C
12471
12472 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN);
12473
12474 /* reg_tieem_overlay_ecn
12475 * ECN of the IP header in the overlay network.
12476 * Access: Index
12477 */
12478 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2);
12479
12480 /* reg_tineem_underlay_ecn
12481 * ECN of the IP header in the underlay network.
12482 * Access: RW
12483 */
12484 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2);
12485
mlxsw_reg_tieem_pack(char * payload,u8 overlay_ecn,u8 underlay_ecn)12486 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn,
12487 u8 underlay_ecn)
12488 {
12489 MLXSW_REG_ZERO(tieem, payload);
12490 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn);
12491 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn);
12492 }
12493
12494 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register
12495 * -----------------------------------------------------------
12496 * The TIDEM register configures the actions that are done in the
12497 * decapsulation.
12498 */
12499 #define MLXSW_REG_TIDEM_ID 0xA813
12500 #define MLXSW_REG_TIDEM_LEN 0x0C
12501
12502 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN);
12503
12504 /* reg_tidem_underlay_ecn
12505 * ECN field of the IP header in the underlay network.
12506 * Access: Index
12507 */
12508 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2);
12509
12510 /* reg_tidem_overlay_ecn
12511 * ECN field of the IP header in the overlay network.
12512 * Access: Index
12513 */
12514 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2);
12515
12516 /* reg_tidem_eip_ecn
12517 * Egress IP ECN. ECN field of the IP header of the packet which goes out
12518 * from the decapsulation.
12519 * Access: RW
12520 */
12521 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2);
12522
12523 /* reg_tidem_trap_en
12524 * Trap enable:
12525 * 0 - No trap due to decap ECN
12526 * 1 - Trap enable with trap_id
12527 * Access: RW
12528 */
12529 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4);
12530
12531 /* reg_tidem_trap_id
12532 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
12533 * Reserved when trap_en is '0'.
12534 * Access: RW
12535 */
12536 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9);
12537
mlxsw_reg_tidem_pack(char * payload,u8 underlay_ecn,u8 overlay_ecn,u8 eip_ecn,bool trap_en,u16 trap_id)12538 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn,
12539 u8 overlay_ecn, u8 eip_ecn,
12540 bool trap_en, u16 trap_id)
12541 {
12542 MLXSW_REG_ZERO(tidem, payload);
12543 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn);
12544 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn);
12545 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn);
12546 mlxsw_reg_tidem_trap_en_set(payload, trap_en);
12547 mlxsw_reg_tidem_trap_id_set(payload, trap_id);
12548 }
12549
12550 /* SBPR - Shared Buffer Pools Register
12551 * -----------------------------------
12552 * The SBPR configures and retrieves the shared buffer pools and configuration.
12553 */
12554 #define MLXSW_REG_SBPR_ID 0xB001
12555 #define MLXSW_REG_SBPR_LEN 0x14
12556
12557 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
12558
12559 /* reg_sbpr_desc
12560 * When set, configures descriptor buffer.
12561 * Access: Index
12562 */
12563 MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1);
12564
12565 /* shared direstion enum for SBPR, SBCM, SBPM */
12566 enum mlxsw_reg_sbxx_dir {
12567 MLXSW_REG_SBXX_DIR_INGRESS,
12568 MLXSW_REG_SBXX_DIR_EGRESS,
12569 };
12570
12571 /* reg_sbpr_dir
12572 * Direction.
12573 * Access: Index
12574 */
12575 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
12576
12577 /* reg_sbpr_pool
12578 * Pool index.
12579 * Access: Index
12580 */
12581 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
12582
12583 /* reg_sbpr_infi_size
12584 * Size is infinite.
12585 * Access: RW
12586 */
12587 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
12588
12589 /* reg_sbpr_size
12590 * Pool size in buffer cells.
12591 * Reserved when infi_size = 1.
12592 * Access: RW
12593 */
12594 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
12595
12596 enum mlxsw_reg_sbpr_mode {
12597 MLXSW_REG_SBPR_MODE_STATIC,
12598 MLXSW_REG_SBPR_MODE_DYNAMIC,
12599 };
12600
12601 /* reg_sbpr_mode
12602 * Pool quota calculation mode.
12603 * Access: RW
12604 */
12605 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
12606
mlxsw_reg_sbpr_pack(char * payload,u8 pool,enum mlxsw_reg_sbxx_dir dir,enum mlxsw_reg_sbpr_mode mode,u32 size,bool infi_size)12607 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
12608 enum mlxsw_reg_sbxx_dir dir,
12609 enum mlxsw_reg_sbpr_mode mode, u32 size,
12610 bool infi_size)
12611 {
12612 MLXSW_REG_ZERO(sbpr, payload);
12613 mlxsw_reg_sbpr_pool_set(payload, pool);
12614 mlxsw_reg_sbpr_dir_set(payload, dir);
12615 mlxsw_reg_sbpr_mode_set(payload, mode);
12616 mlxsw_reg_sbpr_size_set(payload, size);
12617 mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
12618 }
12619
12620 /* SBCM - Shared Buffer Class Management Register
12621 * ----------------------------------------------
12622 * The SBCM register configures and retrieves the shared buffer allocation
12623 * and configuration according to Port-PG, including the binding to pool
12624 * and definition of the associated quota.
12625 */
12626 #define MLXSW_REG_SBCM_ID 0xB002
12627 #define MLXSW_REG_SBCM_LEN 0x28
12628
12629 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
12630
12631 /* reg_sbcm_local_port
12632 * Local port number.
12633 * For Ingress: excludes CPU port and Router port
12634 * For Egress: excludes IP Router
12635 * Access: Index
12636 */
12637 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4);
12638
12639 /* reg_sbcm_pg_buff
12640 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
12641 * For PG buffer: range is 0..cap_max_pg_buffers - 1
12642 * For traffic class: range is 0..cap_max_tclass - 1
12643 * Note that when traffic class is in MC aware mode then the traffic
12644 * classes which are MC aware cannot be configured.
12645 * Access: Index
12646 */
12647 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
12648
12649 /* reg_sbcm_dir
12650 * Direction.
12651 * Access: Index
12652 */
12653 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
12654
12655 /* reg_sbcm_min_buff
12656 * Minimum buffer size for the limiter, in cells.
12657 * Access: RW
12658 */
12659 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
12660
12661 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
12662 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
12663 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
12664
12665 /* reg_sbcm_infi_max
12666 * Max buffer is infinite.
12667 * Access: RW
12668 */
12669 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
12670
12671 /* reg_sbcm_max_buff
12672 * When the pool associated to the port-pg/tclass is configured to
12673 * static, Maximum buffer size for the limiter configured in cells.
12674 * When the pool associated to the port-pg/tclass is configured to
12675 * dynamic, the max_buff holds the "alpha" parameter, supporting
12676 * the following values:
12677 * 0: 0
12678 * i: (1/128)*2^(i-1), for i=1..14
12679 * 0xFF: Infinity
12680 * Reserved when infi_max = 1.
12681 * Access: RW
12682 */
12683 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
12684
12685 /* reg_sbcm_pool
12686 * Association of the port-priority to a pool.
12687 * Access: RW
12688 */
12689 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
12690
mlxsw_reg_sbcm_pack(char * payload,u16 local_port,u8 pg_buff,enum mlxsw_reg_sbxx_dir dir,u32 min_buff,u32 max_buff,bool infi_max,u8 pool)12691 static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff,
12692 enum mlxsw_reg_sbxx_dir dir,
12693 u32 min_buff, u32 max_buff,
12694 bool infi_max, u8 pool)
12695 {
12696 MLXSW_REG_ZERO(sbcm, payload);
12697 mlxsw_reg_sbcm_local_port_set(payload, local_port);
12698 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
12699 mlxsw_reg_sbcm_dir_set(payload, dir);
12700 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
12701 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
12702 mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
12703 mlxsw_reg_sbcm_pool_set(payload, pool);
12704 }
12705
12706 /* SBPM - Shared Buffer Port Management Register
12707 * ---------------------------------------------
12708 * The SBPM register configures and retrieves the shared buffer allocation
12709 * and configuration according to Port-Pool, including the definition
12710 * of the associated quota.
12711 */
12712 #define MLXSW_REG_SBPM_ID 0xB003
12713 #define MLXSW_REG_SBPM_LEN 0x28
12714
12715 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
12716
12717 /* reg_sbpm_local_port
12718 * Local port number.
12719 * For Ingress: excludes CPU port and Router port
12720 * For Egress: excludes IP Router
12721 * Access: Index
12722 */
12723 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12);
12724
12725 /* reg_sbpm_pool
12726 * The pool associated to quota counting on the local_port.
12727 * Access: Index
12728 */
12729 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
12730
12731 /* reg_sbpm_dir
12732 * Direction.
12733 * Access: Index
12734 */
12735 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
12736
12737 /* reg_sbpm_buff_occupancy
12738 * Current buffer occupancy in cells.
12739 * Access: RO
12740 */
12741 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
12742
12743 /* reg_sbpm_clr
12744 * Clear Max Buffer Occupancy
12745 * When this bit is set, max_buff_occupancy field is cleared (and a
12746 * new max value is tracked from the time the clear was performed).
12747 * Access: OP
12748 */
12749 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
12750
12751 /* reg_sbpm_max_buff_occupancy
12752 * Maximum value of buffer occupancy in cells monitored. Cleared by
12753 * writing to the clr field.
12754 * Access: RO
12755 */
12756 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
12757
12758 /* reg_sbpm_min_buff
12759 * Minimum buffer size for the limiter, in cells.
12760 * Access: RW
12761 */
12762 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
12763
12764 /* reg_sbpm_max_buff
12765 * When the pool associated to the port-pg/tclass is configured to
12766 * static, Maximum buffer size for the limiter configured in cells.
12767 * When the pool associated to the port-pg/tclass is configured to
12768 * dynamic, the max_buff holds the "alpha" parameter, supporting
12769 * the following values:
12770 * 0: 0
12771 * i: (1/128)*2^(i-1), for i=1..14
12772 * 0xFF: Infinity
12773 * Access: RW
12774 */
12775 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
12776
mlxsw_reg_sbpm_pack(char * payload,u16 local_port,u8 pool,enum mlxsw_reg_sbxx_dir dir,bool clr,u32 min_buff,u32 max_buff)12777 static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool,
12778 enum mlxsw_reg_sbxx_dir dir, bool clr,
12779 u32 min_buff, u32 max_buff)
12780 {
12781 MLXSW_REG_ZERO(sbpm, payload);
12782 mlxsw_reg_sbpm_local_port_set(payload, local_port);
12783 mlxsw_reg_sbpm_pool_set(payload, pool);
12784 mlxsw_reg_sbpm_dir_set(payload, dir);
12785 mlxsw_reg_sbpm_clr_set(payload, clr);
12786 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
12787 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
12788 }
12789
mlxsw_reg_sbpm_unpack(char * payload,u32 * p_buff_occupancy,u32 * p_max_buff_occupancy)12790 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
12791 u32 *p_max_buff_occupancy)
12792 {
12793 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
12794 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
12795 }
12796
12797 /* SBMM - Shared Buffer Multicast Management Register
12798 * --------------------------------------------------
12799 * The SBMM register configures and retrieves the shared buffer allocation
12800 * and configuration for MC packets according to Switch-Priority, including
12801 * the binding to pool and definition of the associated quota.
12802 */
12803 #define MLXSW_REG_SBMM_ID 0xB004
12804 #define MLXSW_REG_SBMM_LEN 0x28
12805
12806 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
12807
12808 /* reg_sbmm_prio
12809 * Switch Priority.
12810 * Access: Index
12811 */
12812 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
12813
12814 /* reg_sbmm_min_buff
12815 * Minimum buffer size for the limiter, in cells.
12816 * Access: RW
12817 */
12818 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
12819
12820 /* reg_sbmm_max_buff
12821 * When the pool associated to the port-pg/tclass is configured to
12822 * static, Maximum buffer size for the limiter configured in cells.
12823 * When the pool associated to the port-pg/tclass is configured to
12824 * dynamic, the max_buff holds the "alpha" parameter, supporting
12825 * the following values:
12826 * 0: 0
12827 * i: (1/128)*2^(i-1), for i=1..14
12828 * 0xFF: Infinity
12829 * Access: RW
12830 */
12831 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
12832
12833 /* reg_sbmm_pool
12834 * Association of the port-priority to a pool.
12835 * Access: RW
12836 */
12837 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
12838
mlxsw_reg_sbmm_pack(char * payload,u8 prio,u32 min_buff,u32 max_buff,u8 pool)12839 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
12840 u32 max_buff, u8 pool)
12841 {
12842 MLXSW_REG_ZERO(sbmm, payload);
12843 mlxsw_reg_sbmm_prio_set(payload, prio);
12844 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
12845 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
12846 mlxsw_reg_sbmm_pool_set(payload, pool);
12847 }
12848
12849 /* SBSR - Shared Buffer Status Register
12850 * ------------------------------------
12851 * The SBSR register retrieves the shared buffer occupancy according to
12852 * Port-Pool. Note that this register enables reading a large amount of data.
12853 * It is the user's responsibility to limit the amount of data to ensure the
12854 * response can match the maximum transfer unit. In case the response exceeds
12855 * the maximum transport unit, it will be truncated with no special notice.
12856 */
12857 #define MLXSW_REG_SBSR_ID 0xB005
12858 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
12859 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
12860 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
12861 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
12862 MLXSW_REG_SBSR_REC_LEN * \
12863 MLXSW_REG_SBSR_REC_MAX_COUNT)
12864
12865 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
12866
12867 /* reg_sbsr_clr
12868 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
12869 * field is cleared (and a new max value is tracked from the time the clear
12870 * was performed).
12871 * Access: OP
12872 */
12873 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
12874
12875 #define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256
12876
12877 /* reg_sbsr_port_page
12878 * Determines the range of the ports specified in the 'ingress_port_mask'
12879 * and 'egress_port_mask' bit masks.
12880 * {ingress,egress}_port_mask[x] is (256 * port_page) + x
12881 * Access: Index
12882 */
12883 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4);
12884
12885 /* reg_sbsr_ingress_port_mask
12886 * Bit vector for all ingress network ports.
12887 * Indicates which of the ports (for which the relevant bit is set)
12888 * are affected by the set operation. Configuration of any other port
12889 * does not change.
12890 * Access: Index
12891 */
12892 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
12893
12894 /* reg_sbsr_pg_buff_mask
12895 * Bit vector for all switch priority groups.
12896 * Indicates which of the priorities (for which the relevant bit is set)
12897 * are affected by the set operation. Configuration of any other priority
12898 * does not change.
12899 * Range is 0..cap_max_pg_buffers - 1
12900 * Access: Index
12901 */
12902 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
12903
12904 /* reg_sbsr_egress_port_mask
12905 * Bit vector for all egress network ports.
12906 * Indicates which of the ports (for which the relevant bit is set)
12907 * are affected by the set operation. Configuration of any other port
12908 * does not change.
12909 * Access: Index
12910 */
12911 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
12912
12913 /* reg_sbsr_tclass_mask
12914 * Bit vector for all traffic classes.
12915 * Indicates which of the traffic classes (for which the relevant bit is
12916 * set) are affected by the set operation. Configuration of any other
12917 * traffic class does not change.
12918 * Range is 0..cap_max_tclass - 1
12919 * Access: Index
12920 */
12921 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
12922
mlxsw_reg_sbsr_pack(char * payload,bool clr)12923 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
12924 {
12925 MLXSW_REG_ZERO(sbsr, payload);
12926 mlxsw_reg_sbsr_clr_set(payload, clr);
12927 }
12928
12929 /* reg_sbsr_rec_buff_occupancy
12930 * Current buffer occupancy in cells.
12931 * Access: RO
12932 */
12933 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
12934 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
12935
12936 /* reg_sbsr_rec_max_buff_occupancy
12937 * Maximum value of buffer occupancy in cells monitored. Cleared by
12938 * writing to the clr field.
12939 * Access: RO
12940 */
12941 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
12942 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
12943
mlxsw_reg_sbsr_rec_unpack(char * payload,int rec_index,u32 * p_buff_occupancy,u32 * p_max_buff_occupancy)12944 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
12945 u32 *p_buff_occupancy,
12946 u32 *p_max_buff_occupancy)
12947 {
12948 *p_buff_occupancy =
12949 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
12950 *p_max_buff_occupancy =
12951 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
12952 }
12953
12954 /* SBIB - Shared Buffer Internal Buffer Register
12955 * ---------------------------------------------
12956 * The SBIB register configures per port buffers for internal use. The internal
12957 * buffers consume memory on the port buffers (note that the port buffers are
12958 * used also by PBMC).
12959 *
12960 * For Spectrum this is used for egress mirroring.
12961 */
12962 #define MLXSW_REG_SBIB_ID 0xB006
12963 #define MLXSW_REG_SBIB_LEN 0x10
12964
12965 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
12966
12967 /* reg_sbib_local_port
12968 * Local port number
12969 * Not supported for CPU port and router port
12970 * Access: Index
12971 */
12972 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12);
12973
12974 /* reg_sbib_buff_size
12975 * Units represented in cells
12976 * Allowed range is 0 to (cap_max_headroom_size - 1)
12977 * Default is 0
12978 * Access: RW
12979 */
12980 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
12981
mlxsw_reg_sbib_pack(char * payload,u16 local_port,u32 buff_size)12982 static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port,
12983 u32 buff_size)
12984 {
12985 MLXSW_REG_ZERO(sbib, payload);
12986 mlxsw_reg_sbib_local_port_set(payload, local_port);
12987 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
12988 }
12989
12990 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
12991 MLXSW_REG(sgcr),
12992 MLXSW_REG(spad),
12993 MLXSW_REG(sspr),
12994 MLXSW_REG(sfdat),
12995 MLXSW_REG(sfd),
12996 MLXSW_REG(sfn),
12997 MLXSW_REG(spms),
12998 MLXSW_REG(spvid),
12999 MLXSW_REG(spvm),
13000 MLXSW_REG(spaft),
13001 MLXSW_REG(sfgc),
13002 MLXSW_REG(sfdf),
13003 MLXSW_REG(sldr),
13004 MLXSW_REG(slcr),
13005 MLXSW_REG(slcor),
13006 MLXSW_REG(spmlr),
13007 MLXSW_REG(svfa),
13008 MLXSW_REG(spvtr),
13009 MLXSW_REG(svpe),
13010 MLXSW_REG(sfmr),
13011 MLXSW_REG(spvmlr),
13012 MLXSW_REG(spvc),
13013 MLXSW_REG(spevet),
13014 MLXSW_REG(sftr2),
13015 MLXSW_REG(smid2),
13016 MLXSW_REG(cwtp),
13017 MLXSW_REG(cwtpm),
13018 MLXSW_REG(pgcr),
13019 MLXSW_REG(ppbt),
13020 MLXSW_REG(pacl),
13021 MLXSW_REG(pagt),
13022 MLXSW_REG(ptar),
13023 MLXSW_REG(ppbs),
13024 MLXSW_REG(prcr),
13025 MLXSW_REG(pefa),
13026 MLXSW_REG(pemrbt),
13027 MLXSW_REG(ptce2),
13028 MLXSW_REG(perpt),
13029 MLXSW_REG(peabfe),
13030 MLXSW_REG(perar),
13031 MLXSW_REG(ptce3),
13032 MLXSW_REG(percr),
13033 MLXSW_REG(pererp),
13034 MLXSW_REG(iedr),
13035 MLXSW_REG(qpts),
13036 MLXSW_REG(qpcr),
13037 MLXSW_REG(qtct),
13038 MLXSW_REG(qeec),
13039 MLXSW_REG(qrwe),
13040 MLXSW_REG(qpdsm),
13041 MLXSW_REG(qpdp),
13042 MLXSW_REG(qpdpm),
13043 MLXSW_REG(qtctm),
13044 MLXSW_REG(qpsc),
13045 MLXSW_REG(pmlp),
13046 MLXSW_REG(pmtu),
13047 MLXSW_REG(ptys),
13048 MLXSW_REG(ppad),
13049 MLXSW_REG(paos),
13050 MLXSW_REG(pfcc),
13051 MLXSW_REG(ppcnt),
13052 MLXSW_REG(plib),
13053 MLXSW_REG(pptb),
13054 MLXSW_REG(pbmc),
13055 MLXSW_REG(pspa),
13056 MLXSW_REG(pmaos),
13057 MLXSW_REG(pplr),
13058 MLXSW_REG(pmtdb),
13059 MLXSW_REG(pmecr),
13060 MLXSW_REG(pmpe),
13061 MLXSW_REG(pddr),
13062 MLXSW_REG(pmmp),
13063 MLXSW_REG(pllp),
13064 MLXSW_REG(pmtm),
13065 MLXSW_REG(htgt),
13066 MLXSW_REG(hpkt),
13067 MLXSW_REG(rgcr),
13068 MLXSW_REG(ritr),
13069 MLXSW_REG(rtar),
13070 MLXSW_REG(ratr),
13071 MLXSW_REG(rtdp),
13072 MLXSW_REG(rips),
13073 MLXSW_REG(ratrad),
13074 MLXSW_REG(rdpm),
13075 MLXSW_REG(ricnt),
13076 MLXSW_REG(rrcr),
13077 MLXSW_REG(ralta),
13078 MLXSW_REG(ralst),
13079 MLXSW_REG(raltb),
13080 MLXSW_REG(ralue),
13081 MLXSW_REG(rauht),
13082 MLXSW_REG(raleu),
13083 MLXSW_REG(rauhtd),
13084 MLXSW_REG(rigr2),
13085 MLXSW_REG(recr2),
13086 MLXSW_REG(rmft2),
13087 MLXSW_REG(rxlte),
13088 MLXSW_REG(rxltm),
13089 MLXSW_REG(rlcmld),
13090 MLXSW_REG(rlpmce),
13091 MLXSW_REG(xltq),
13092 MLXSW_REG(xmdr),
13093 MLXSW_REG(xrmt),
13094 MLXSW_REG(xralta),
13095 MLXSW_REG(xralst),
13096 MLXSW_REG(xraltb),
13097 MLXSW_REG(mfcr),
13098 MLXSW_REG(mfsc),
13099 MLXSW_REG(mfsm),
13100 MLXSW_REG(mfsl),
13101 MLXSW_REG(fore),
13102 MLXSW_REG(mtcap),
13103 MLXSW_REG(mtmp),
13104 MLXSW_REG(mtwe),
13105 MLXSW_REG(mtbr),
13106 MLXSW_REG(mcia),
13107 MLXSW_REG(mpat),
13108 MLXSW_REG(mpar),
13109 MLXSW_REG(mgir),
13110 MLXSW_REG(mrsr),
13111 MLXSW_REG(mlcr),
13112 MLXSW_REG(mcion),
13113 MLXSW_REG(mtpps),
13114 MLXSW_REG(mtutc),
13115 MLXSW_REG(mpsc),
13116 MLXSW_REG(mcqi),
13117 MLXSW_REG(mcc),
13118 MLXSW_REG(mcda),
13119 MLXSW_REG(mgpc),
13120 MLXSW_REG(mprs),
13121 MLXSW_REG(mogcr),
13122 MLXSW_REG(mpagr),
13123 MLXSW_REG(momte),
13124 MLXSW_REG(mtpppc),
13125 MLXSW_REG(mtpptr),
13126 MLXSW_REG(mtptpt),
13127 MLXSW_REG(mfgd),
13128 MLXSW_REG(mgpir),
13129 MLXSW_REG(mbct),
13130 MLXSW_REG(mddq),
13131 MLXSW_REG(mddc),
13132 MLXSW_REG(mfde),
13133 MLXSW_REG(tngcr),
13134 MLXSW_REG(tnumt),
13135 MLXSW_REG(tnqcr),
13136 MLXSW_REG(tnqdr),
13137 MLXSW_REG(tneem),
13138 MLXSW_REG(tndem),
13139 MLXSW_REG(tnpc),
13140 MLXSW_REG(tigcr),
13141 MLXSW_REG(tieem),
13142 MLXSW_REG(tidem),
13143 MLXSW_REG(sbpr),
13144 MLXSW_REG(sbcm),
13145 MLXSW_REG(sbpm),
13146 MLXSW_REG(sbmm),
13147 MLXSW_REG(sbsr),
13148 MLXSW_REG(sbib),
13149 };
13150
mlxsw_reg_id_str(u16 reg_id)13151 static inline const char *mlxsw_reg_id_str(u16 reg_id)
13152 {
13153 const struct mlxsw_reg_info *reg_info;
13154 int i;
13155
13156 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
13157 reg_info = mlxsw_reg_infos[i];
13158 if (reg_info->id == reg_id)
13159 return reg_info->name;
13160 }
13161 return "*UNKNOWN*";
13162 }
13163
13164 /* PUDE - Port Up / Down Event
13165 * ---------------------------
13166 * Reports the operational state change of a port.
13167 */
13168 #define MLXSW_REG_PUDE_LEN 0x10
13169
13170 /* reg_pude_swid
13171 * Switch partition ID with which to associate the port.
13172 * Access: Index
13173 */
13174 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
13175
13176 /* reg_pude_local_port
13177 * Local port number.
13178 * Access: Index
13179 */
13180 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12);
13181
13182 /* reg_pude_admin_status
13183 * Port administrative state (the desired state).
13184 * 1 - Up.
13185 * 2 - Down.
13186 * 3 - Up once. This means that in case of link failure, the port won't go
13187 * into polling mode, but will wait to be re-enabled by software.
13188 * 4 - Disabled by system. Can only be set by hardware.
13189 * Access: RO
13190 */
13191 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
13192
13193 /* reg_pude_oper_status
13194 * Port operatioanl state.
13195 * 1 - Up.
13196 * 2 - Down.
13197 * 3 - Down by port failure. This means that the device will not let the
13198 * port up again until explicitly specified by software.
13199 * Access: RO
13200 */
13201 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
13202
13203 #endif
13204