1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/tcp.h>
34 #include <linux/if_vlan.h>
35 #include <net/geneve.h>
36 #include <net/dsfield.h>
37 #include "en.h"
38 #include "en/txrx.h"
39 #include "ipoib/ipoib.h"
40 #include "en_accel/en_accel.h"
41 #include "en_accel/ipsec_rxtx.h"
42 #include "en_accel/macsec.h"
43 #include "en/ptp.h"
44 #include <net/ipv6.h>
45
mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq * sq,u8 num_dma)46 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma)
47 {
48 int i;
49
50 for (i = 0; i < num_dma; i++) {
51 struct mlx5e_sq_dma *last_pushed_dma =
52 mlx5e_dma_get(sq, --sq->dma_fifo_pc);
53
54 mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
55 }
56 }
57
mlx5e_skb_l2_header_offset(struct sk_buff * skb)58 static inline int mlx5e_skb_l2_header_offset(struct sk_buff *skb)
59 {
60 #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
61
62 return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
63 }
64
mlx5e_skb_l3_header_offset(struct sk_buff * skb)65 static inline int mlx5e_skb_l3_header_offset(struct sk_buff *skb)
66 {
67 if (skb_transport_header_was_set(skb))
68 return skb_transport_offset(skb);
69 else
70 return mlx5e_skb_l2_header_offset(skb);
71 }
72
mlx5e_calc_min_inline(enum mlx5_inline_modes mode,struct sk_buff * skb)73 static inline u16 mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
74 struct sk_buff *skb)
75 {
76 u16 hlen;
77
78 switch (mode) {
79 case MLX5_INLINE_MODE_NONE:
80 return 0;
81 case MLX5_INLINE_MODE_TCP_UDP:
82 hlen = eth_get_headlen(skb->dev, skb->data, skb_headlen(skb));
83 if (hlen == ETH_HLEN && !skb_vlan_tag_present(skb))
84 hlen += VLAN_HLEN;
85 break;
86 case MLX5_INLINE_MODE_IP:
87 hlen = mlx5e_skb_l3_header_offset(skb);
88 break;
89 case MLX5_INLINE_MODE_L2:
90 default:
91 hlen = mlx5e_skb_l2_header_offset(skb);
92 }
93 return min_t(u16, hlen, skb_headlen(skb));
94 }
95
96 #define MLX5_UNSAFE_MEMCPY_DISCLAIMER \
97 "This copy has been bounds-checked earlier in " \
98 "mlx5i_sq_calc_wqe_attr() and intentionally " \
99 "crosses a flex array boundary. Since it is " \
100 "performance sensitive, splitting the copy is " \
101 "undesirable."
102
mlx5e_insert_vlan(void * start,struct sk_buff * skb,u16 ihs)103 static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs)
104 {
105 struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
106 int cpy1_sz = 2 * ETH_ALEN;
107 int cpy2_sz = ihs - cpy1_sz;
108
109 memcpy(&vhdr->addrs, skb->data, cpy1_sz);
110 vhdr->h_vlan_proto = skb->vlan_proto;
111 vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
112 unsafe_memcpy(&vhdr->h_vlan_encapsulated_proto,
113 skb->data + cpy1_sz,
114 cpy2_sz,
115 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
116 }
117
118 static inline void
mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5e_accel_tx_state * accel,struct mlx5_wqe_eth_seg * eseg)119 mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb,
120 struct mlx5e_accel_tx_state *accel,
121 struct mlx5_wqe_eth_seg *eseg)
122 {
123 if (unlikely(mlx5e_ipsec_txwqe_build_eseg_csum(sq, skb, eseg)))
124 return;
125
126 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
127 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
128 if (skb->encapsulation) {
129 eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM |
130 MLX5_ETH_WQE_L4_INNER_CSUM;
131 sq->stats->csum_partial_inner++;
132 } else {
133 eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
134 sq->stats->csum_partial++;
135 }
136 #ifdef CONFIG_MLX5_EN_TLS
137 } else if (unlikely(accel && accel->tls.tls_tisn)) {
138 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
139 sq->stats->csum_partial++;
140 #endif
141 } else
142 sq->stats->csum_none++;
143 }
144
145 /* Returns the number of header bytes that we plan
146 * to inline later in the transmit descriptor
147 */
148 static inline u16
mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq * sq,struct sk_buff * skb,int * hopbyhop)149 mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq *sq, struct sk_buff *skb, int *hopbyhop)
150 {
151 struct mlx5e_sq_stats *stats = sq->stats;
152 u16 ihs;
153
154 *hopbyhop = 0;
155 if (skb->encapsulation) {
156 ihs = skb_inner_tcp_all_headers(skb);
157 stats->tso_inner_packets++;
158 stats->tso_inner_bytes += skb->len - ihs;
159 } else {
160 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
161 ihs = skb_transport_offset(skb) + sizeof(struct udphdr);
162 } else {
163 ihs = skb_tcp_all_headers(skb);
164 if (ipv6_has_hopopt_jumbo(skb)) {
165 *hopbyhop = sizeof(struct hop_jumbo_hdr);
166 ihs -= sizeof(struct hop_jumbo_hdr);
167 }
168 }
169 stats->tso_packets++;
170 stats->tso_bytes += skb->len - ihs - *hopbyhop;
171 }
172
173 return ihs;
174 }
175
176 static inline int
mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq * sq,struct sk_buff * skb,unsigned char * skb_data,u16 headlen,struct mlx5_wqe_data_seg * dseg)177 mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb,
178 unsigned char *skb_data, u16 headlen,
179 struct mlx5_wqe_data_seg *dseg)
180 {
181 dma_addr_t dma_addr = 0;
182 u8 num_dma = 0;
183 int i;
184
185 if (headlen) {
186 dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
187 DMA_TO_DEVICE);
188 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
189 goto dma_unmap_wqe_err;
190
191 dseg->addr = cpu_to_be64(dma_addr);
192 dseg->lkey = sq->mkey_be;
193 dseg->byte_count = cpu_to_be32(headlen);
194
195 mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
196 num_dma++;
197 dseg++;
198 }
199
200 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
201 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
202 int fsz = skb_frag_size(frag);
203
204 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
205 DMA_TO_DEVICE);
206 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
207 goto dma_unmap_wqe_err;
208
209 dseg->addr = cpu_to_be64(dma_addr);
210 dseg->lkey = sq->mkey_be;
211 dseg->byte_count = cpu_to_be32(fsz);
212
213 mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
214 num_dma++;
215 dseg++;
216 }
217
218 return num_dma;
219
220 dma_unmap_wqe_err:
221 mlx5e_dma_unmap_wqe_err(sq, num_dma);
222 return -ENOMEM;
223 }
224
225 struct mlx5e_tx_attr {
226 u32 num_bytes;
227 u16 headlen;
228 u16 ihs;
229 __be16 mss;
230 u16 insz;
231 u8 opcode;
232 u8 hopbyhop;
233 };
234
235 struct mlx5e_tx_wqe_attr {
236 u16 ds_cnt;
237 u16 ds_cnt_inl;
238 u16 ds_cnt_ids;
239 u8 num_wqebbs;
240 };
241
242 static u8
mlx5e_tx_wqe_inline_mode(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5e_accel_tx_state * accel)243 mlx5e_tx_wqe_inline_mode(struct mlx5e_txqsq *sq, struct sk_buff *skb,
244 struct mlx5e_accel_tx_state *accel)
245 {
246 u8 mode;
247
248 #ifdef CONFIG_MLX5_EN_TLS
249 if (accel && accel->tls.tls_tisn)
250 return MLX5_INLINE_MODE_TCP_UDP;
251 #endif
252
253 mode = sq->min_inline_mode;
254
255 if (skb_vlan_tag_present(skb) &&
256 test_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state))
257 mode = max_t(u8, MLX5_INLINE_MODE_L2, mode);
258
259 return mode;
260 }
261
mlx5e_sq_xmit_prepare(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5e_accel_tx_state * accel,struct mlx5e_tx_attr * attr)262 static void mlx5e_sq_xmit_prepare(struct mlx5e_txqsq *sq, struct sk_buff *skb,
263 struct mlx5e_accel_tx_state *accel,
264 struct mlx5e_tx_attr *attr)
265 {
266 struct mlx5e_sq_stats *stats = sq->stats;
267
268 if (skb_is_gso(skb)) {
269 int hopbyhop;
270 u16 ihs = mlx5e_tx_get_gso_ihs(sq, skb, &hopbyhop);
271
272 *attr = (struct mlx5e_tx_attr) {
273 .opcode = MLX5_OPCODE_LSO,
274 .mss = cpu_to_be16(skb_shinfo(skb)->gso_size),
275 .ihs = ihs,
276 .num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs,
277 .headlen = skb_headlen(skb) - ihs - hopbyhop,
278 .hopbyhop = hopbyhop,
279 };
280
281 stats->packets += skb_shinfo(skb)->gso_segs;
282 } else {
283 u8 mode = mlx5e_tx_wqe_inline_mode(sq, skb, accel);
284 u16 ihs = mlx5e_calc_min_inline(mode, skb);
285
286 *attr = (struct mlx5e_tx_attr) {
287 .opcode = MLX5_OPCODE_SEND,
288 .mss = cpu_to_be16(0),
289 .ihs = ihs,
290 .num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN),
291 .headlen = skb_headlen(skb) - ihs,
292 };
293
294 stats->packets++;
295 }
296
297 attr->insz = mlx5e_accel_tx_ids_len(sq, accel);
298 stats->bytes += attr->num_bytes;
299 }
300
mlx5e_sq_calc_wqe_attr(struct sk_buff * skb,const struct mlx5e_tx_attr * attr,struct mlx5e_tx_wqe_attr * wqe_attr)301 static void mlx5e_sq_calc_wqe_attr(struct sk_buff *skb, const struct mlx5e_tx_attr *attr,
302 struct mlx5e_tx_wqe_attr *wqe_attr)
303 {
304 u16 ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT;
305 u16 ds_cnt_inl = 0;
306 u16 ds_cnt_ids = 0;
307
308 /* Sync the calculation with MLX5E_MAX_TX_WQEBBS. */
309
310 if (attr->insz)
311 ds_cnt_ids = DIV_ROUND_UP(sizeof(struct mlx5_wqe_inline_seg) + attr->insz,
312 MLX5_SEND_WQE_DS);
313
314 ds_cnt += !!attr->headlen + skb_shinfo(skb)->nr_frags + ds_cnt_ids;
315 if (attr->ihs) {
316 u16 inl = attr->ihs - INL_HDR_START_SZ;
317
318 if (skb_vlan_tag_present(skb))
319 inl += VLAN_HLEN;
320
321 ds_cnt_inl = DIV_ROUND_UP(inl, MLX5_SEND_WQE_DS);
322 if (WARN_ON_ONCE(ds_cnt_inl > MLX5E_MAX_TX_INLINE_DS))
323 netdev_warn(skb->dev, "ds_cnt_inl = %u > max %u\n", ds_cnt_inl,
324 (u16)MLX5E_MAX_TX_INLINE_DS);
325 ds_cnt += ds_cnt_inl;
326 }
327
328 *wqe_attr = (struct mlx5e_tx_wqe_attr) {
329 .ds_cnt = ds_cnt,
330 .ds_cnt_inl = ds_cnt_inl,
331 .ds_cnt_ids = ds_cnt_ids,
332 .num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS),
333 };
334 }
335
mlx5e_tx_skb_update_hwts_flags(struct sk_buff * skb)336 static void mlx5e_tx_skb_update_hwts_flags(struct sk_buff *skb)
337 {
338 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
339 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
340 }
341
mlx5e_tx_check_stop(struct mlx5e_txqsq * sq)342 static void mlx5e_tx_check_stop(struct mlx5e_txqsq *sq)
343 {
344 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, sq->stop_room))) {
345 netif_tx_stop_queue(sq->txq);
346 sq->stats->stopped++;
347 }
348 }
349
mlx5e_tx_flush(struct mlx5e_txqsq * sq)350 static void mlx5e_tx_flush(struct mlx5e_txqsq *sq)
351 {
352 struct mlx5e_tx_wqe_info *wi;
353 struct mlx5e_tx_wqe *wqe;
354 u16 pi;
355
356 /* Must not be called when a MPWQE session is active but empty. */
357 mlx5e_tx_mpwqe_ensure_complete(sq);
358
359 pi = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->pc);
360 wi = &sq->db.wqe_info[pi];
361
362 *wi = (struct mlx5e_tx_wqe_info) {
363 .num_wqebbs = 1,
364 };
365
366 wqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
367 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl);
368 }
369
370 static inline void
mlx5e_txwqe_complete(struct mlx5e_txqsq * sq,struct sk_buff * skb,const struct mlx5e_tx_attr * attr,const struct mlx5e_tx_wqe_attr * wqe_attr,u8 num_dma,struct mlx5e_tx_wqe_info * wi,struct mlx5_wqe_ctrl_seg * cseg,struct mlx5_wqe_eth_seg * eseg,bool xmit_more)371 mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb,
372 const struct mlx5e_tx_attr *attr,
373 const struct mlx5e_tx_wqe_attr *wqe_attr, u8 num_dma,
374 struct mlx5e_tx_wqe_info *wi, struct mlx5_wqe_ctrl_seg *cseg,
375 struct mlx5_wqe_eth_seg *eseg, bool xmit_more)
376 {
377 struct mlx5_wq_cyc *wq = &sq->wq;
378 bool send_doorbell;
379
380 *wi = (struct mlx5e_tx_wqe_info) {
381 .skb = skb,
382 .num_bytes = attr->num_bytes,
383 .num_dma = num_dma,
384 .num_wqebbs = wqe_attr->num_wqebbs,
385 .num_fifo_pkts = 0,
386 };
387
388 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | attr->opcode);
389 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | wqe_attr->ds_cnt);
390
391 mlx5e_tx_skb_update_hwts_flags(skb);
392
393 sq->pc += wi->num_wqebbs;
394
395 mlx5e_tx_check_stop(sq);
396
397 if (unlikely(sq->ptpsq &&
398 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) {
399 u8 metadata_index = be32_to_cpu(eseg->flow_table_metadata);
400
401 mlx5e_skb_cb_hwtstamp_init(skb);
402 mlx5e_ptp_metadata_map_put(&sq->ptpsq->metadata_map, skb,
403 metadata_index);
404 mlx5e_ptpsq_track_metadata(sq->ptpsq, metadata_index);
405 if (!netif_tx_queue_stopped(sq->txq) &&
406 mlx5e_ptpsq_metadata_freelist_empty(sq->ptpsq)) {
407 netif_tx_stop_queue(sq->txq);
408 sq->stats->stopped++;
409 }
410 skb_get(skb);
411 }
412
413 send_doorbell = __netdev_tx_sent_queue(sq->txq, attr->num_bytes, xmit_more);
414 if (send_doorbell)
415 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, cseg);
416 }
417
418 static void
mlx5e_sq_xmit_wqe(struct mlx5e_txqsq * sq,struct sk_buff * skb,const struct mlx5e_tx_attr * attr,const struct mlx5e_tx_wqe_attr * wqe_attr,struct mlx5e_tx_wqe * wqe,u16 pi,bool xmit_more)419 mlx5e_sq_xmit_wqe(struct mlx5e_txqsq *sq, struct sk_buff *skb,
420 const struct mlx5e_tx_attr *attr, const struct mlx5e_tx_wqe_attr *wqe_attr,
421 struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more)
422 {
423 struct mlx5_wqe_ctrl_seg *cseg;
424 struct mlx5_wqe_eth_seg *eseg;
425 struct mlx5_wqe_data_seg *dseg;
426 struct mlx5e_tx_wqe_info *wi;
427 u16 ihs = attr->ihs;
428 struct ipv6hdr *h6;
429 struct mlx5e_sq_stats *stats = sq->stats;
430 int num_dma;
431
432 stats->xmit_more += xmit_more;
433
434 /* fill wqe */
435 wi = &sq->db.wqe_info[pi];
436 cseg = &wqe->ctrl;
437 eseg = &wqe->eth;
438 dseg = wqe->data;
439
440 eseg->mss = attr->mss;
441
442 if (ihs) {
443 u8 *start = eseg->inline_hdr.start;
444
445 if (unlikely(attr->hopbyhop)) {
446 /* remove the HBH header.
447 * Layout: [Ethernet header][IPv6 header][HBH][TCP header]
448 */
449 if (skb_vlan_tag_present(skb)) {
450 mlx5e_insert_vlan(start, skb, ETH_HLEN + sizeof(*h6));
451 ihs += VLAN_HLEN;
452 h6 = (struct ipv6hdr *)(start + sizeof(struct vlan_ethhdr));
453 } else {
454 unsafe_memcpy(start, skb->data,
455 ETH_HLEN + sizeof(*h6),
456 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
457 h6 = (struct ipv6hdr *)(start + ETH_HLEN);
458 }
459 h6->nexthdr = IPPROTO_TCP;
460 /* Copy the TCP header after the IPv6 one */
461 memcpy(h6 + 1,
462 skb->data + ETH_HLEN + sizeof(*h6) +
463 sizeof(struct hop_jumbo_hdr),
464 tcp_hdrlen(skb));
465 /* Leave ipv6 payload_len set to 0, as LSO v2 specs request. */
466 } else if (skb_vlan_tag_present(skb)) {
467 mlx5e_insert_vlan(start, skb, ihs);
468 ihs += VLAN_HLEN;
469 stats->added_vlan_packets++;
470 } else {
471 unsafe_memcpy(eseg->inline_hdr.start, skb->data,
472 attr->ihs,
473 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
474 }
475 eseg->inline_hdr.sz |= cpu_to_be16(ihs);
476 dseg += wqe_attr->ds_cnt_inl;
477 } else if (skb_vlan_tag_present(skb)) {
478 eseg->insert.type = cpu_to_be16(MLX5_ETH_WQE_INSERT_VLAN);
479 if (skb->vlan_proto == cpu_to_be16(ETH_P_8021AD))
480 eseg->insert.type |= cpu_to_be16(MLX5_ETH_WQE_SVLAN);
481 eseg->insert.vlan_tci = cpu_to_be16(skb_vlan_tag_get(skb));
482 stats->added_vlan_packets++;
483 }
484
485 dseg += wqe_attr->ds_cnt_ids;
486 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + attr->ihs + attr->hopbyhop,
487 attr->headlen, dseg);
488 if (unlikely(num_dma < 0))
489 goto err_drop;
490
491 mlx5e_txwqe_complete(sq, skb, attr, wqe_attr, num_dma, wi, cseg, eseg, xmit_more);
492
493 return;
494
495 err_drop:
496 stats->dropped++;
497 if (unlikely(sq->ptpsq && (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
498 mlx5e_ptp_metadata_fifo_push(&sq->ptpsq->metadata_freelist,
499 be32_to_cpu(eseg->flow_table_metadata));
500 dev_kfree_skb_any(skb);
501 mlx5e_tx_flush(sq);
502 }
503
mlx5e_tx_skb_supports_mpwqe(struct sk_buff * skb,struct mlx5e_tx_attr * attr)504 static bool mlx5e_tx_skb_supports_mpwqe(struct sk_buff *skb, struct mlx5e_tx_attr *attr)
505 {
506 return !skb_is_nonlinear(skb) && !skb_vlan_tag_present(skb) && !attr->ihs &&
507 !attr->insz && !mlx5e_macsec_skb_is_offload(skb);
508 }
509
mlx5e_tx_mpwqe_same_eseg(struct mlx5e_txqsq * sq,struct mlx5_wqe_eth_seg * eseg)510 static bool mlx5e_tx_mpwqe_same_eseg(struct mlx5e_txqsq *sq, struct mlx5_wqe_eth_seg *eseg)
511 {
512 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
513
514 /* Assumes the session is already running and has at least one packet. */
515 return !memcmp(&session->wqe->eth, eseg, MLX5E_ACCEL_ESEG_LEN);
516 }
517
mlx5e_tx_mpwqe_session_start(struct mlx5e_txqsq * sq,struct mlx5_wqe_eth_seg * eseg)518 static void mlx5e_tx_mpwqe_session_start(struct mlx5e_txqsq *sq,
519 struct mlx5_wqe_eth_seg *eseg)
520 {
521 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
522 struct mlx5e_tx_wqe *wqe;
523 u16 pi;
524
525 pi = mlx5e_txqsq_get_next_pi(sq, sq->max_sq_mpw_wqebbs);
526 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
527 net_prefetchw(wqe->data);
528
529 *session = (struct mlx5e_tx_mpwqe) {
530 .wqe = wqe,
531 .bytes_count = 0,
532 .ds_count = MLX5E_TX_WQE_EMPTY_DS_COUNT,
533 .pkt_count = 0,
534 .inline_on = 0,
535 };
536
537 memcpy(&session->wqe->eth, eseg, MLX5E_ACCEL_ESEG_LEN);
538
539 sq->stats->mpwqe_blks++;
540 }
541
mlx5e_tx_mpwqe_session_is_active(struct mlx5e_txqsq * sq)542 static bool mlx5e_tx_mpwqe_session_is_active(struct mlx5e_txqsq *sq)
543 {
544 return sq->mpwqe.wqe;
545 }
546
mlx5e_tx_mpwqe_add_dseg(struct mlx5e_txqsq * sq,struct mlx5e_xmit_data * txd)547 static void mlx5e_tx_mpwqe_add_dseg(struct mlx5e_txqsq *sq, struct mlx5e_xmit_data *txd)
548 {
549 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
550 struct mlx5_wqe_data_seg *dseg;
551
552 dseg = (struct mlx5_wqe_data_seg *)session->wqe + session->ds_count;
553
554 session->pkt_count++;
555 session->bytes_count += txd->len;
556
557 dseg->addr = cpu_to_be64(txd->dma_addr);
558 dseg->byte_count = cpu_to_be32(txd->len);
559 dseg->lkey = sq->mkey_be;
560 session->ds_count++;
561
562 sq->stats->mpwqe_pkts++;
563 }
564
mlx5e_tx_mpwqe_session_complete(struct mlx5e_txqsq * sq)565 static struct mlx5_wqe_ctrl_seg *mlx5e_tx_mpwqe_session_complete(struct mlx5e_txqsq *sq)
566 {
567 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
568 u8 ds_count = session->ds_count;
569 struct mlx5_wqe_ctrl_seg *cseg;
570 struct mlx5e_tx_wqe_info *wi;
571 u16 pi;
572
573 cseg = &session->wqe->ctrl;
574 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_ENHANCED_MPSW);
575 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_count);
576
577 pi = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->pc);
578 wi = &sq->db.wqe_info[pi];
579 *wi = (struct mlx5e_tx_wqe_info) {
580 .skb = NULL,
581 .num_bytes = session->bytes_count,
582 .num_wqebbs = DIV_ROUND_UP(ds_count, MLX5_SEND_WQEBB_NUM_DS),
583 .num_dma = session->pkt_count,
584 .num_fifo_pkts = session->pkt_count,
585 };
586
587 sq->pc += wi->num_wqebbs;
588
589 session->wqe = NULL;
590
591 mlx5e_tx_check_stop(sq);
592
593 return cseg;
594 }
595
596 static void
mlx5e_sq_xmit_mpwqe(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5_wqe_eth_seg * eseg,bool xmit_more)597 mlx5e_sq_xmit_mpwqe(struct mlx5e_txqsq *sq, struct sk_buff *skb,
598 struct mlx5_wqe_eth_seg *eseg, bool xmit_more)
599 {
600 struct mlx5_wqe_ctrl_seg *cseg;
601 struct mlx5e_xmit_data txd;
602
603 txd.data = skb->data;
604 txd.len = skb->len;
605
606 txd.dma_addr = dma_map_single(sq->pdev, txd.data, txd.len, DMA_TO_DEVICE);
607 if (unlikely(dma_mapping_error(sq->pdev, txd.dma_addr)))
608 goto err_unmap;
609
610 if (!mlx5e_tx_mpwqe_session_is_active(sq)) {
611 mlx5e_tx_mpwqe_session_start(sq, eseg);
612 } else if (!mlx5e_tx_mpwqe_same_eseg(sq, eseg)) {
613 mlx5e_tx_mpwqe_session_complete(sq);
614 mlx5e_tx_mpwqe_session_start(sq, eseg);
615 }
616
617 sq->stats->xmit_more += xmit_more;
618
619 mlx5e_dma_push(sq, txd.dma_addr, txd.len, MLX5E_DMA_MAP_SINGLE);
620 mlx5e_skb_fifo_push(&sq->db.skb_fifo, skb);
621 mlx5e_tx_mpwqe_add_dseg(sq, &txd);
622 mlx5e_tx_skb_update_hwts_flags(skb);
623
624 if (unlikely(mlx5e_tx_mpwqe_is_full(&sq->mpwqe, sq->max_sq_mpw_wqebbs))) {
625 /* Might stop the queue and affect the retval of __netdev_tx_sent_queue. */
626 cseg = mlx5e_tx_mpwqe_session_complete(sq);
627
628 if (__netdev_tx_sent_queue(sq->txq, txd.len, xmit_more))
629 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg);
630 } else if (__netdev_tx_sent_queue(sq->txq, txd.len, xmit_more)) {
631 /* Might stop the queue, but we were asked to ring the doorbell anyway. */
632 cseg = mlx5e_tx_mpwqe_session_complete(sq);
633
634 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg);
635 }
636
637 return;
638
639 err_unmap:
640 mlx5e_dma_unmap_wqe_err(sq, 1);
641 sq->stats->dropped++;
642 dev_kfree_skb_any(skb);
643 mlx5e_tx_flush(sq);
644 }
645
mlx5e_tx_mpwqe_ensure_complete(struct mlx5e_txqsq * sq)646 void mlx5e_tx_mpwqe_ensure_complete(struct mlx5e_txqsq *sq)
647 {
648 /* Unlikely in non-MPWQE workloads; not important in MPWQE workloads. */
649 if (unlikely(mlx5e_tx_mpwqe_session_is_active(sq)))
650 mlx5e_tx_mpwqe_session_complete(sq);
651 }
652
mlx5e_cqe_ts_id_eseg(struct mlx5e_ptpsq * ptpsq,struct sk_buff * skb,struct mlx5_wqe_eth_seg * eseg)653 static void mlx5e_cqe_ts_id_eseg(struct mlx5e_ptpsq *ptpsq, struct sk_buff *skb,
654 struct mlx5_wqe_eth_seg *eseg)
655 {
656 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
657 eseg->flow_table_metadata =
658 cpu_to_be32(mlx5e_ptp_metadata_fifo_pop(&ptpsq->metadata_freelist));
659 }
660
mlx5e_txwqe_build_eseg(struct mlx5e_priv * priv,struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5e_accel_tx_state * accel,struct mlx5_wqe_eth_seg * eseg,u16 ihs)661 static void mlx5e_txwqe_build_eseg(struct mlx5e_priv *priv, struct mlx5e_txqsq *sq,
662 struct sk_buff *skb, struct mlx5e_accel_tx_state *accel,
663 struct mlx5_wqe_eth_seg *eseg, u16 ihs)
664 {
665 mlx5e_accel_tx_eseg(priv, skb, eseg, ihs);
666 mlx5e_txwqe_build_eseg_csum(sq, skb, accel, eseg);
667 if (unlikely(sq->ptpsq))
668 mlx5e_cqe_ts_id_eseg(sq->ptpsq, skb, eseg);
669 }
670
mlx5e_xmit(struct sk_buff * skb,struct net_device * dev)671 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
672 {
673 struct mlx5e_priv *priv = netdev_priv(dev);
674 struct mlx5e_accel_tx_state accel = {};
675 struct mlx5e_tx_wqe_attr wqe_attr;
676 struct mlx5e_tx_attr attr;
677 struct mlx5e_tx_wqe *wqe;
678 struct mlx5e_txqsq *sq;
679 u16 pi;
680
681 /* All changes to txq2sq are performed in sync with mlx5e_xmit, when the
682 * queue being changed is disabled, and smp_wmb guarantees that the
683 * changes are visible before mlx5e_xmit tries to read from txq2sq. It
684 * guarantees that the value of txq2sq[qid] doesn't change while
685 * mlx5e_xmit is running on queue number qid. smb_wmb is paired with
686 * HARD_TX_LOCK around ndo_start_xmit, which serves as an ACQUIRE.
687 */
688 sq = priv->txq2sq[skb_get_queue_mapping(skb)];
689 if (unlikely(!sq)) {
690 /* Two cases when sq can be NULL:
691 * 1. The HTB node is registered, and mlx5e_select_queue
692 * selected its queue ID, but the SQ itself is not yet created.
693 * 2. HTB SQ creation failed. Similar to the previous case, but
694 * the SQ won't be created.
695 */
696 dev_kfree_skb_any(skb);
697 return NETDEV_TX_OK;
698 }
699
700 /* May send SKBs and WQEs. */
701 if (unlikely(!mlx5e_accel_tx_begin(dev, sq, skb, &accel)))
702 return NETDEV_TX_OK;
703
704 mlx5e_sq_xmit_prepare(sq, skb, &accel, &attr);
705
706 if (test_bit(MLX5E_SQ_STATE_MPWQE, &sq->state)) {
707 if (mlx5e_tx_skb_supports_mpwqe(skb, &attr)) {
708 struct mlx5_wqe_eth_seg eseg = {};
709
710 mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &eseg, attr.ihs);
711 mlx5e_sq_xmit_mpwqe(sq, skb, &eseg, netdev_xmit_more());
712 return NETDEV_TX_OK;
713 }
714
715 mlx5e_tx_mpwqe_ensure_complete(sq);
716 }
717
718 mlx5e_sq_calc_wqe_attr(skb, &attr, &wqe_attr);
719 pi = mlx5e_txqsq_get_next_pi(sq, wqe_attr.num_wqebbs);
720 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
721
722 /* May update the WQE, but may not post other WQEs. */
723 mlx5e_accel_tx_finish(sq, wqe, &accel,
724 (struct mlx5_wqe_inline_seg *)(wqe->data + wqe_attr.ds_cnt_inl));
725 mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &wqe->eth, attr.ihs);
726 mlx5e_sq_xmit_wqe(sq, skb, &attr, &wqe_attr, wqe, pi, netdev_xmit_more());
727
728 return NETDEV_TX_OK;
729 }
730
mlx5e_tx_wi_dma_unmap(struct mlx5e_txqsq * sq,struct mlx5e_tx_wqe_info * wi,u32 * dma_fifo_cc)731 static void mlx5e_tx_wi_dma_unmap(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi,
732 u32 *dma_fifo_cc)
733 {
734 int i;
735
736 for (i = 0; i < wi->num_dma; i++) {
737 struct mlx5e_sq_dma *dma = mlx5e_dma_get(sq, (*dma_fifo_cc)++);
738
739 mlx5e_tx_dma_unmap(sq->pdev, dma);
740 }
741 }
742
mlx5e_consume_skb(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5_cqe64 * cqe,int napi_budget)743 static void mlx5e_consume_skb(struct mlx5e_txqsq *sq, struct sk_buff *skb,
744 struct mlx5_cqe64 *cqe, int napi_budget)
745 {
746 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
747 struct skb_shared_hwtstamps hwts = {};
748 u64 ts = get_cqe_ts(cqe);
749
750 hwts.hwtstamp = mlx5e_cqe_ts_to_ns(sq->ptp_cyc2time, sq->clock, ts);
751 if (sq->ptpsq)
752 mlx5e_skb_cb_hwtstamp_handler(skb, MLX5E_SKB_CB_CQE_HWTSTAMP,
753 hwts.hwtstamp, sq->ptpsq->cq_stats);
754 else
755 skb_tstamp_tx(skb, &hwts);
756 }
757
758 napi_consume_skb(skb, napi_budget);
759 }
760
mlx5e_tx_wi_consume_fifo_skbs(struct mlx5e_txqsq * sq,struct mlx5e_tx_wqe_info * wi,struct mlx5_cqe64 * cqe,int napi_budget)761 static void mlx5e_tx_wi_consume_fifo_skbs(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi,
762 struct mlx5_cqe64 *cqe, int napi_budget)
763 {
764 int i;
765
766 for (i = 0; i < wi->num_fifo_pkts; i++) {
767 struct sk_buff *skb = mlx5e_skb_fifo_pop(&sq->db.skb_fifo);
768
769 mlx5e_consume_skb(sq, skb, cqe, napi_budget);
770 }
771 }
772
mlx5e_txqsq_wake(struct mlx5e_txqsq * sq)773 void mlx5e_txqsq_wake(struct mlx5e_txqsq *sq)
774 {
775 if (netif_tx_queue_stopped(sq->txq) &&
776 mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, sq->stop_room) &&
777 !mlx5e_ptpsq_metadata_freelist_empty(sq->ptpsq) &&
778 !test_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state)) {
779 netif_tx_wake_queue(sq->txq);
780 sq->stats->wake++;
781 }
782 }
783
mlx5e_poll_tx_cq(struct mlx5e_cq * cq,int napi_budget)784 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
785 {
786 struct mlx5e_sq_stats *stats;
787 struct mlx5e_txqsq *sq;
788 struct mlx5_cqe64 *cqe;
789 u32 dma_fifo_cc;
790 u32 nbytes;
791 u16 npkts;
792 u16 sqcc;
793 int i;
794
795 sq = container_of(cq, struct mlx5e_txqsq, cq);
796
797 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
798 return false;
799
800 cqe = mlx5_cqwq_get_cqe(&cq->wq);
801 if (!cqe)
802 return false;
803
804 stats = sq->stats;
805
806 npkts = 0;
807 nbytes = 0;
808
809 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
810 * otherwise a cq overrun may occur
811 */
812 sqcc = sq->cc;
813
814 /* avoid dirtying sq cache line every cqe */
815 dma_fifo_cc = sq->dma_fifo_cc;
816
817 i = 0;
818 do {
819 struct mlx5e_tx_wqe_info *wi;
820 u16 wqe_counter;
821 bool last_wqe;
822 u16 ci;
823
824 mlx5_cqwq_pop(&cq->wq);
825
826 wqe_counter = be16_to_cpu(cqe->wqe_counter);
827
828 do {
829 last_wqe = (sqcc == wqe_counter);
830
831 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
832 wi = &sq->db.wqe_info[ci];
833
834 sqcc += wi->num_wqebbs;
835
836 if (likely(wi->skb)) {
837 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
838 mlx5e_consume_skb(sq, wi->skb, cqe, napi_budget);
839
840 npkts++;
841 nbytes += wi->num_bytes;
842 continue;
843 }
844
845 if (unlikely(mlx5e_ktls_tx_try_handle_resync_dump_comp(sq, wi,
846 &dma_fifo_cc)))
847 continue;
848
849 if (wi->num_fifo_pkts) {
850 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
851 mlx5e_tx_wi_consume_fifo_skbs(sq, wi, cqe, napi_budget);
852
853 npkts += wi->num_fifo_pkts;
854 nbytes += wi->num_bytes;
855 }
856 } while (!last_wqe);
857
858 if (unlikely(get_cqe_opcode(cqe) == MLX5_CQE_REQ_ERR)) {
859 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING,
860 &sq->state)) {
861 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
862 (struct mlx5_err_cqe *)cqe);
863 mlx5_wq_cyc_wqe_dump(&sq->wq, ci, wi->num_wqebbs);
864 queue_work(cq->priv->wq, &sq->recover_work);
865 }
866 stats->cqe_err++;
867 }
868
869 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
870
871 stats->cqes += i;
872
873 mlx5_cqwq_update_db_record(&cq->wq);
874
875 /* ensure cq space is freed before enabling more cqes */
876 wmb();
877
878 sq->dma_fifo_cc = dma_fifo_cc;
879 sq->cc = sqcc;
880
881 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
882
883 mlx5e_txqsq_wake(sq);
884
885 return (i == MLX5E_TX_CQ_POLL_BUDGET);
886 }
887
mlx5e_tx_wi_kfree_fifo_skbs(struct mlx5e_txqsq * sq,struct mlx5e_tx_wqe_info * wi)888 static void mlx5e_tx_wi_kfree_fifo_skbs(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi)
889 {
890 int i;
891
892 for (i = 0; i < wi->num_fifo_pkts; i++)
893 dev_kfree_skb_any(mlx5e_skb_fifo_pop(&sq->db.skb_fifo));
894 }
895
mlx5e_free_txqsq_descs(struct mlx5e_txqsq * sq)896 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq)
897 {
898 struct mlx5e_tx_wqe_info *wi;
899 u32 dma_fifo_cc, nbytes = 0;
900 u16 ci, sqcc, npkts = 0;
901
902 sqcc = sq->cc;
903 dma_fifo_cc = sq->dma_fifo_cc;
904
905 while (sqcc != sq->pc) {
906 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
907 wi = &sq->db.wqe_info[ci];
908
909 sqcc += wi->num_wqebbs;
910
911 if (likely(wi->skb)) {
912 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
913 dev_kfree_skb_any(wi->skb);
914
915 npkts++;
916 nbytes += wi->num_bytes;
917 continue;
918 }
919
920 if (unlikely(mlx5e_ktls_tx_try_handle_resync_dump_comp(sq, wi, &dma_fifo_cc)))
921 continue;
922
923 if (wi->num_fifo_pkts) {
924 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
925 mlx5e_tx_wi_kfree_fifo_skbs(sq, wi);
926
927 npkts += wi->num_fifo_pkts;
928 nbytes += wi->num_bytes;
929 }
930 }
931
932 sq->dma_fifo_cc = dma_fifo_cc;
933 sq->cc = sqcc;
934
935 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
936 }
937
938 #ifdef CONFIG_MLX5_CORE_IPOIB
939 static inline void
mlx5i_txwqe_build_datagram(struct mlx5_av * av,u32 dqpn,u32 dqkey,struct mlx5_wqe_datagram_seg * dseg)940 mlx5i_txwqe_build_datagram(struct mlx5_av *av, u32 dqpn, u32 dqkey,
941 struct mlx5_wqe_datagram_seg *dseg)
942 {
943 memcpy(&dseg->av, av, sizeof(struct mlx5_av));
944 dseg->av.dqp_dct = cpu_to_be32(dqpn | MLX5_EXTENDED_UD_AV);
945 dseg->av.key.qkey.qkey = cpu_to_be32(dqkey);
946 }
947
mlx5i_sq_calc_wqe_attr(struct sk_buff * skb,const struct mlx5e_tx_attr * attr,struct mlx5e_tx_wqe_attr * wqe_attr)948 static void mlx5i_sq_calc_wqe_attr(struct sk_buff *skb,
949 const struct mlx5e_tx_attr *attr,
950 struct mlx5e_tx_wqe_attr *wqe_attr)
951 {
952 u16 ds_cnt = sizeof(struct mlx5i_tx_wqe) / MLX5_SEND_WQE_DS;
953 u16 ds_cnt_inl = 0;
954
955 ds_cnt += !!attr->headlen + skb_shinfo(skb)->nr_frags;
956
957 if (attr->ihs) {
958 u16 inl = attr->ihs - INL_HDR_START_SZ;
959
960 ds_cnt_inl = DIV_ROUND_UP(inl, MLX5_SEND_WQE_DS);
961 ds_cnt += ds_cnt_inl;
962 }
963
964 *wqe_attr = (struct mlx5e_tx_wqe_attr) {
965 .ds_cnt = ds_cnt,
966 .ds_cnt_inl = ds_cnt_inl,
967 .num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS),
968 };
969 }
970
mlx5i_sq_xmit(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5_av * av,u32 dqpn,u32 dqkey,bool xmit_more)971 void mlx5i_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
972 struct mlx5_av *av, u32 dqpn, u32 dqkey, bool xmit_more)
973 {
974 struct mlx5e_tx_wqe_attr wqe_attr;
975 struct mlx5e_tx_attr attr;
976 struct mlx5i_tx_wqe *wqe;
977
978 struct mlx5_wqe_datagram_seg *datagram;
979 struct mlx5_wqe_ctrl_seg *cseg;
980 struct mlx5_wqe_eth_seg *eseg;
981 struct mlx5_wqe_data_seg *dseg;
982 struct mlx5e_tx_wqe_info *wi;
983
984 struct mlx5e_sq_stats *stats = sq->stats;
985 int num_dma;
986 u16 pi;
987
988 mlx5e_sq_xmit_prepare(sq, skb, NULL, &attr);
989 mlx5i_sq_calc_wqe_attr(skb, &attr, &wqe_attr);
990
991 pi = mlx5e_txqsq_get_next_pi(sq, wqe_attr.num_wqebbs);
992 wqe = MLX5I_SQ_FETCH_WQE(sq, pi);
993
994 stats->xmit_more += xmit_more;
995
996 /* fill wqe */
997 wi = &sq->db.wqe_info[pi];
998 cseg = &wqe->ctrl;
999 datagram = &wqe->datagram;
1000 eseg = &wqe->eth;
1001 dseg = wqe->data;
1002
1003 mlx5i_txwqe_build_datagram(av, dqpn, dqkey, datagram);
1004
1005 mlx5e_txwqe_build_eseg_csum(sq, skb, NULL, eseg);
1006
1007 eseg->mss = attr.mss;
1008
1009 if (attr.ihs) {
1010 if (unlikely(attr.hopbyhop)) {
1011 struct ipv6hdr *h6;
1012
1013 /* remove the HBH header.
1014 * Layout: [Ethernet header][IPv6 header][HBH][TCP header]
1015 */
1016 unsafe_memcpy(eseg->inline_hdr.start, skb->data,
1017 ETH_HLEN + sizeof(*h6),
1018 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
1019 h6 = (struct ipv6hdr *)((char *)eseg->inline_hdr.start + ETH_HLEN);
1020 h6->nexthdr = IPPROTO_TCP;
1021 /* Copy the TCP header after the IPv6 one */
1022 unsafe_memcpy(h6 + 1,
1023 skb->data + ETH_HLEN + sizeof(*h6) +
1024 sizeof(struct hop_jumbo_hdr),
1025 tcp_hdrlen(skb),
1026 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
1027 /* Leave ipv6 payload_len set to 0, as LSO v2 specs request. */
1028 } else {
1029 unsafe_memcpy(eseg->inline_hdr.start, skb->data,
1030 attr.ihs,
1031 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
1032 }
1033 eseg->inline_hdr.sz = cpu_to_be16(attr.ihs);
1034 dseg += wqe_attr.ds_cnt_inl;
1035 }
1036
1037 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + attr.ihs + attr.hopbyhop,
1038 attr.headlen, dseg);
1039 if (unlikely(num_dma < 0))
1040 goto err_drop;
1041
1042 mlx5e_txwqe_complete(sq, skb, &attr, &wqe_attr, num_dma, wi, cseg, eseg, xmit_more);
1043
1044 return;
1045
1046 err_drop:
1047 stats->dropped++;
1048 dev_kfree_skb_any(skb);
1049 mlx5e_tx_flush(sq);
1050 }
1051 #endif
1052