1 /*
2  * Copyright (c) 2017, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #include <rdma/ib_verbs.h>
34 #include <linux/mlx5/fs.h>
35 #include "en.h"
36 #include "en/params.h"
37 #include "ipoib.h"
38 #include "en/fs_ethtool.h"
39 
40 #define IB_DEFAULT_Q_KEY   0xb1b
41 #define MLX5I_PARAMS_DEFAULT_LOG_RQ_SIZE 9
42 
43 static int mlx5i_open(struct net_device *netdev);
44 static int mlx5i_close(struct net_device *netdev);
45 static int mlx5i_change_mtu(struct net_device *netdev, int new_mtu);
46 
47 static const struct net_device_ops mlx5i_netdev_ops = {
48 	.ndo_open                = mlx5i_open,
49 	.ndo_stop                = mlx5i_close,
50 	.ndo_get_stats64         = mlx5i_get_stats,
51 	.ndo_init                = mlx5i_dev_init,
52 	.ndo_uninit              = mlx5i_dev_cleanup,
53 	.ndo_change_mtu          = mlx5i_change_mtu,
54 	.ndo_eth_ioctl            = mlx5i_ioctl,
55 };
56 
57 /* IPoIB mlx5 netdev profile */
mlx5i_build_nic_params(struct mlx5_core_dev * mdev,struct mlx5e_params * params)58 static void mlx5i_build_nic_params(struct mlx5_core_dev *mdev,
59 				   struct mlx5e_params *params)
60 {
61 	/* Override RQ params as IPoIB supports only LINKED LIST RQ for now */
62 	MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, false);
63 	mlx5e_set_rq_type(mdev, params);
64 	mlx5e_init_rq_type_params(mdev, params);
65 
66 	/* RQ size in ipoib by default is 512 */
67 	params->log_rq_mtu_frames = is_kdump_kernel() ?
68 		MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
69 		MLX5I_PARAMS_DEFAULT_LOG_RQ_SIZE;
70 
71 	params->packet_merge.type = MLX5E_PACKET_MERGE_NONE;
72 	params->hard_mtu = MLX5_IB_GRH_BYTES + MLX5_IPOIB_HARD_LEN;
73 	params->tunneled_offload_en = false;
74 
75 	/* CQE compression is not supported for IPoIB */
76 	params->rx_cqe_compress_def = false;
77 	MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
78 }
79 
80 /* Called directly after IPoIB netdevice was created to initialize SW structs */
mlx5i_init(struct mlx5_core_dev * mdev,struct net_device * netdev)81 int mlx5i_init(struct mlx5_core_dev *mdev, struct net_device *netdev)
82 {
83 	struct mlx5e_priv *priv  = mlx5i_epriv(netdev);
84 
85 	netif_carrier_off(netdev);
86 	mlx5e_set_netdev_mtu_boundaries(priv);
87 	netdev->mtu = netdev->max_mtu;
88 
89 	mlx5e_build_nic_params(priv, NULL, netdev->mtu);
90 	mlx5i_build_nic_params(mdev, &priv->channels.params);
91 
92 	mlx5e_timestamp_init(priv);
93 
94 	/* netdev init */
95 	netdev->hw_features    |= NETIF_F_SG;
96 	netdev->hw_features    |= NETIF_F_IP_CSUM;
97 	netdev->hw_features    |= NETIF_F_IPV6_CSUM;
98 	netdev->hw_features    |= NETIF_F_GRO;
99 	netdev->hw_features    |= NETIF_F_TSO;
100 	netdev->hw_features    |= NETIF_F_TSO6;
101 	netdev->hw_features    |= NETIF_F_RXCSUM;
102 	netdev->hw_features    |= NETIF_F_RXHASH;
103 
104 	netdev->netdev_ops = &mlx5i_netdev_ops;
105 	netdev->ethtool_ops = &mlx5i_ethtool_ops;
106 
107 	return 0;
108 }
109 
110 /* Called directly before IPoIB netdevice is destroyed to cleanup SW structs */
mlx5i_cleanup(struct mlx5e_priv * priv)111 void mlx5i_cleanup(struct mlx5e_priv *priv)
112 {
113 	mlx5e_priv_cleanup(priv);
114 }
115 
mlx5i_grp_sw_update_stats(struct mlx5e_priv * priv)116 static void mlx5i_grp_sw_update_stats(struct mlx5e_priv *priv)
117 {
118 	struct rtnl_link_stats64 s = {};
119 	int i, j;
120 
121 	for (i = 0; i < priv->stats_nch; i++) {
122 		struct mlx5e_channel_stats *channel_stats;
123 		struct mlx5e_rq_stats *rq_stats;
124 
125 		channel_stats = priv->channel_stats[i];
126 		rq_stats = &channel_stats->rq;
127 
128 		s.rx_packets += rq_stats->packets;
129 		s.rx_bytes   += rq_stats->bytes;
130 
131 		for (j = 0; j < priv->max_opened_tc; j++) {
132 			struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
133 
134 			s.tx_packets           += sq_stats->packets;
135 			s.tx_bytes             += sq_stats->bytes;
136 			s.tx_dropped           += sq_stats->dropped;
137 		}
138 	}
139 
140 	memset(&priv->stats.sw, 0, sizeof(s));
141 
142 	priv->stats.sw.rx_packets = s.rx_packets;
143 	priv->stats.sw.rx_bytes = s.rx_bytes;
144 	priv->stats.sw.tx_packets = s.tx_packets;
145 	priv->stats.sw.tx_bytes = s.tx_bytes;
146 	priv->stats.sw.tx_queue_dropped = s.tx_dropped;
147 }
148 
mlx5i_get_stats(struct net_device * dev,struct rtnl_link_stats64 * stats)149 void mlx5i_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
150 {
151 	struct mlx5e_priv     *priv   = mlx5i_epriv(dev);
152 	struct mlx5e_sw_stats *sstats = &priv->stats.sw;
153 
154 	mlx5i_grp_sw_update_stats(priv);
155 
156 	stats->rx_packets = sstats->rx_packets;
157 	stats->rx_bytes   = sstats->rx_bytes;
158 	stats->tx_packets = sstats->tx_packets;
159 	stats->tx_bytes   = sstats->tx_bytes;
160 	stats->tx_dropped = sstats->tx_queue_dropped;
161 }
162 
mlx5i_parent_get(struct net_device * netdev)163 struct net_device *mlx5i_parent_get(struct net_device *netdev)
164 {
165 	struct mlx5e_priv *priv = mlx5i_epriv(netdev);
166 	struct mlx5i_priv *ipriv, *parent_ipriv;
167 	struct net_device *parent_dev;
168 	int parent_ifindex;
169 
170 	ipriv = priv->ppriv;
171 
172 	parent_ifindex = netdev->netdev_ops->ndo_get_iflink(netdev);
173 	parent_dev = dev_get_by_index(dev_net(netdev), parent_ifindex);
174 	if (!parent_dev)
175 		return NULL;
176 
177 	parent_ipriv = netdev_priv(parent_dev);
178 
179 	ASSERT_RTNL();
180 	parent_ipriv->num_sub_interfaces++;
181 
182 	ipriv->parent_dev = parent_dev;
183 
184 	return parent_dev;
185 }
186 
mlx5i_parent_put(struct net_device * netdev)187 void mlx5i_parent_put(struct net_device *netdev)
188 {
189 	struct mlx5e_priv *priv = mlx5i_epriv(netdev);
190 	struct mlx5i_priv *ipriv, *parent_ipriv;
191 
192 	ipriv = priv->ppriv;
193 	parent_ipriv = netdev_priv(ipriv->parent_dev);
194 
195 	ASSERT_RTNL();
196 	parent_ipriv->num_sub_interfaces--;
197 
198 	dev_put(ipriv->parent_dev);
199 }
200 
mlx5i_init_underlay_qp(struct mlx5e_priv * priv)201 int mlx5i_init_underlay_qp(struct mlx5e_priv *priv)
202 {
203 	struct mlx5_core_dev *mdev = priv->mdev;
204 	struct mlx5i_priv *ipriv = priv->ppriv;
205 	int ret;
206 
207 	{
208 		u32 in[MLX5_ST_SZ_DW(rst2init_qp_in)] = {};
209 		u32 *qpc;
210 
211 		qpc = MLX5_ADDR_OF(rst2init_qp_in, in, qpc);
212 
213 		MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
214 		MLX5_SET(qpc, qpc, primary_address_path.pkey_index,
215 			 ipriv->pkey_index);
216 		MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
217 		MLX5_SET(qpc, qpc, q_key, IB_DEFAULT_Q_KEY);
218 
219 		MLX5_SET(rst2init_qp_in, in, opcode, MLX5_CMD_OP_RST2INIT_QP);
220 		MLX5_SET(rst2init_qp_in, in, qpn, ipriv->qpn);
221 		ret = mlx5_cmd_exec_in(mdev, rst2init_qp, in);
222 		if (ret)
223 			goto err_qp_modify_to_err;
224 	}
225 	{
226 		u32 in[MLX5_ST_SZ_DW(init2rtr_qp_in)] = {};
227 
228 		MLX5_SET(init2rtr_qp_in, in, opcode, MLX5_CMD_OP_INIT2RTR_QP);
229 		MLX5_SET(init2rtr_qp_in, in, qpn, ipriv->qpn);
230 		ret = mlx5_cmd_exec_in(mdev, init2rtr_qp, in);
231 		if (ret)
232 			goto err_qp_modify_to_err;
233 	}
234 	{
235 		u32 in[MLX5_ST_SZ_DW(rtr2rts_qp_in)] = {};
236 
237 		MLX5_SET(rtr2rts_qp_in, in, opcode, MLX5_CMD_OP_RTR2RTS_QP);
238 		MLX5_SET(rtr2rts_qp_in, in, qpn, ipriv->qpn);
239 		ret = mlx5_cmd_exec_in(mdev, rtr2rts_qp, in);
240 		if (ret)
241 			goto err_qp_modify_to_err;
242 	}
243 	return 0;
244 
245 err_qp_modify_to_err:
246 	{
247 		u32 in[MLX5_ST_SZ_DW(qp_2err_in)] = {};
248 
249 		MLX5_SET(qp_2err_in, in, opcode, MLX5_CMD_OP_2ERR_QP);
250 		MLX5_SET(qp_2err_in, in, qpn, ipriv->qpn);
251 		mlx5_cmd_exec_in(mdev, qp_2err, in);
252 	}
253 	return ret;
254 }
255 
mlx5i_uninit_underlay_qp(struct mlx5e_priv * priv)256 void mlx5i_uninit_underlay_qp(struct mlx5e_priv *priv)
257 {
258 	struct mlx5i_priv *ipriv = priv->ppriv;
259 	struct mlx5_core_dev *mdev = priv->mdev;
260 	u32 in[MLX5_ST_SZ_DW(qp_2rst_in)] = {};
261 
262 	MLX5_SET(qp_2rst_in, in, opcode, MLX5_CMD_OP_2RST_QP);
263 	MLX5_SET(qp_2rst_in, in, qpn, ipriv->qpn);
264 	mlx5_cmd_exec_in(mdev, qp_2rst, in);
265 }
266 
267 #define MLX5_QP_ENHANCED_ULP_STATELESS_MODE 2
268 
mlx5i_create_underlay_qp(struct mlx5e_priv * priv)269 int mlx5i_create_underlay_qp(struct mlx5e_priv *priv)
270 {
271 	const unsigned char *dev_addr = priv->netdev->dev_addr;
272 	u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
273 	u32 in[MLX5_ST_SZ_DW(create_qp_in)] = {};
274 	struct mlx5i_priv *ipriv = priv->ppriv;
275 	void *addr_path;
276 	int qpn = 0;
277 	int ret = 0;
278 	void *qpc;
279 
280 	if (MLX5_CAP_GEN(priv->mdev, mkey_by_name)) {
281 		qpn = (dev_addr[1] << 16) + (dev_addr[2] << 8) + dev_addr[3];
282 		MLX5_SET(create_qp_in, in, input_qpn, qpn);
283 	}
284 
285 	qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
286 	MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(priv->mdev));
287 	MLX5_SET(qpc, qpc, st, MLX5_QP_ST_UD);
288 	MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
289 	MLX5_SET(qpc, qpc, ulp_stateless_offload_mode,
290 		 MLX5_QP_ENHANCED_ULP_STATELESS_MODE);
291 
292 	addr_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
293 	MLX5_SET(ads, addr_path, vhca_port_num, 1);
294 	MLX5_SET(ads, addr_path, grh, 1);
295 
296 	MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
297 	ret = mlx5_cmd_exec_inout(priv->mdev, create_qp, in, out);
298 	if (ret)
299 		return ret;
300 
301 	ipriv->qpn = MLX5_GET(create_qp_out, out, qpn);
302 
303 	return 0;
304 }
305 
mlx5i_destroy_underlay_qp(struct mlx5_core_dev * mdev,u32 qpn)306 void mlx5i_destroy_underlay_qp(struct mlx5_core_dev *mdev, u32 qpn)
307 {
308 	u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {};
309 
310 	MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP);
311 	MLX5_SET(destroy_qp_in, in, qpn, qpn);
312 	mlx5_cmd_exec_in(mdev, destroy_qp, in);
313 }
314 
mlx5i_update_nic_rx(struct mlx5e_priv * priv)315 int mlx5i_update_nic_rx(struct mlx5e_priv *priv)
316 {
317 	return mlx5e_refresh_tirs(priv, true, true);
318 }
319 
mlx5i_create_tis(struct mlx5_core_dev * mdev,u32 underlay_qpn,u32 * tisn)320 int mlx5i_create_tis(struct mlx5_core_dev *mdev, u32 underlay_qpn, u32 *tisn)
321 {
322 	u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
323 	void *tisc;
324 
325 	tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
326 
327 	MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
328 
329 	return mlx5e_create_tis(mdev, in, tisn);
330 }
331 
mlx5i_init_tx(struct mlx5e_priv * priv)332 static int mlx5i_init_tx(struct mlx5e_priv *priv)
333 {
334 	struct mlx5i_priv *ipriv = priv->ppriv;
335 	int err;
336 
337 	err = mlx5i_create_underlay_qp(priv);
338 	if (err) {
339 		mlx5_core_warn(priv->mdev, "create underlay QP failed, %d\n", err);
340 		return err;
341 	}
342 
343 	err = mlx5i_create_tis(priv->mdev, ipriv->qpn, &priv->tisn[0][0]);
344 	if (err) {
345 		mlx5_core_warn(priv->mdev, "create tis failed, %d\n", err);
346 		goto err_destroy_underlay_qp;
347 	}
348 
349 	return 0;
350 
351 err_destroy_underlay_qp:
352 	mlx5i_destroy_underlay_qp(priv->mdev, ipriv->qpn);
353 	return err;
354 }
355 
mlx5i_cleanup_tx(struct mlx5e_priv * priv)356 static void mlx5i_cleanup_tx(struct mlx5e_priv *priv)
357 {
358 	struct mlx5i_priv *ipriv = priv->ppriv;
359 
360 	mlx5e_destroy_tis(priv->mdev, priv->tisn[0][0]);
361 	mlx5i_destroy_underlay_qp(priv->mdev, ipriv->qpn);
362 }
363 
mlx5i_create_flow_steering(struct mlx5e_priv * priv)364 static int mlx5i_create_flow_steering(struct mlx5e_priv *priv)
365 {
366 	struct mlx5_flow_namespace *ns =
367 		mlx5_get_flow_namespace(priv->mdev, MLX5_FLOW_NAMESPACE_KERNEL);
368 	int err;
369 
370 
371 	if (!ns)
372 		return -EINVAL;
373 
374 	mlx5e_fs_set_ns(priv->fs, ns, false);
375 	err = mlx5e_arfs_create_tables(priv->fs, priv->rx_res,
376 				       !!(priv->netdev->hw_features & NETIF_F_NTUPLE));
377 	if (err) {
378 		netdev_err(priv->netdev, "Failed to create arfs tables, err=%d\n",
379 			   err);
380 		priv->netdev->hw_features &= ~NETIF_F_NTUPLE;
381 	}
382 
383 	err = mlx5e_create_ttc_table(priv->fs, priv->rx_res);
384 	if (err) {
385 		netdev_err(priv->netdev, "Failed to create ttc table, err=%d\n",
386 			   err);
387 		goto err_destroy_arfs_tables;
388 	}
389 
390 	mlx5e_ethtool_init_steering(priv->fs);
391 
392 	return 0;
393 
394 err_destroy_arfs_tables:
395 	mlx5e_arfs_destroy_tables(priv->fs,
396 				  !!(priv->netdev->hw_features & NETIF_F_NTUPLE));
397 
398 	return err;
399 }
400 
mlx5i_destroy_flow_steering(struct mlx5e_priv * priv)401 static void mlx5i_destroy_flow_steering(struct mlx5e_priv *priv)
402 {
403 	mlx5e_destroy_ttc_table(priv->fs);
404 	mlx5e_arfs_destroy_tables(priv->fs,
405 				  !!(priv->netdev->hw_features & NETIF_F_NTUPLE));
406 	mlx5e_ethtool_cleanup_steering(priv->fs);
407 }
408 
mlx5i_init_rx(struct mlx5e_priv * priv)409 static int mlx5i_init_rx(struct mlx5e_priv *priv)
410 {
411 	struct mlx5_core_dev *mdev = priv->mdev;
412 	int err;
413 
414 	priv->fs = mlx5e_fs_init(priv->profile, mdev,
415 				 !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
416 	if (!priv->fs) {
417 		netdev_err(priv->netdev, "FS allocation failed\n");
418 		return -ENOMEM;
419 	}
420 
421 	priv->rx_res = mlx5e_rx_res_alloc();
422 	if (!priv->rx_res) {
423 		err = -ENOMEM;
424 		goto err_free_fs;
425 	}
426 
427 	mlx5e_create_q_counters(priv);
428 
429 	err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
430 	if (err) {
431 		mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
432 		goto err_destroy_q_counters;
433 	}
434 
435 	err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, 0,
436 				priv->max_nch, priv->drop_rq.rqn,
437 				&priv->channels.params.packet_merge,
438 				priv->channels.params.num_channels);
439 	if (err)
440 		goto err_close_drop_rq;
441 
442 	err = mlx5i_create_flow_steering(priv);
443 	if (err)
444 		goto err_destroy_rx_res;
445 
446 	return 0;
447 
448 err_destroy_rx_res:
449 	mlx5e_rx_res_destroy(priv->rx_res);
450 err_close_drop_rq:
451 	mlx5e_close_drop_rq(&priv->drop_rq);
452 err_destroy_q_counters:
453 	mlx5e_destroy_q_counters(priv);
454 	mlx5e_rx_res_free(priv->rx_res);
455 	priv->rx_res = NULL;
456 err_free_fs:
457 	mlx5e_fs_cleanup(priv->fs);
458 	return err;
459 }
460 
mlx5i_cleanup_rx(struct mlx5e_priv * priv)461 static void mlx5i_cleanup_rx(struct mlx5e_priv *priv)
462 {
463 	mlx5i_destroy_flow_steering(priv);
464 	mlx5e_rx_res_destroy(priv->rx_res);
465 	mlx5e_close_drop_rq(&priv->drop_rq);
466 	mlx5e_destroy_q_counters(priv);
467 	mlx5e_rx_res_free(priv->rx_res);
468 	priv->rx_res = NULL;
469 	mlx5e_fs_cleanup(priv->fs);
470 }
471 
472 /* The stats groups order is opposite to the update_stats() order calls */
473 static mlx5e_stats_grp_t mlx5i_stats_grps[] = {
474 	&MLX5E_STATS_GRP(sw),
475 	&MLX5E_STATS_GRP(qcnt),
476 	&MLX5E_STATS_GRP(vnic_env),
477 	&MLX5E_STATS_GRP(vport),
478 	&MLX5E_STATS_GRP(802_3),
479 	&MLX5E_STATS_GRP(2863),
480 	&MLX5E_STATS_GRP(2819),
481 	&MLX5E_STATS_GRP(phy),
482 	&MLX5E_STATS_GRP(pcie),
483 	&MLX5E_STATS_GRP(per_prio),
484 	&MLX5E_STATS_GRP(pme),
485 	&MLX5E_STATS_GRP(channels),
486 	&MLX5E_STATS_GRP(per_port_buff_congest),
487 };
488 
mlx5i_stats_grps_num(struct mlx5e_priv * priv)489 static unsigned int mlx5i_stats_grps_num(struct mlx5e_priv *priv)
490 {
491 	return ARRAY_SIZE(mlx5i_stats_grps);
492 }
493 
494 static const struct mlx5e_profile mlx5i_nic_profile = {
495 	.init		   = mlx5i_init,
496 	.cleanup	   = mlx5i_cleanup,
497 	.init_tx	   = mlx5i_init_tx,
498 	.cleanup_tx	   = mlx5i_cleanup_tx,
499 	.init_rx	   = mlx5i_init_rx,
500 	.cleanup_rx	   = mlx5i_cleanup_rx,
501 	.enable		   = NULL, /* mlx5i_enable */
502 	.disable	   = NULL, /* mlx5i_disable */
503 	.update_rx	   = mlx5i_update_nic_rx,
504 	.update_stats	   = NULL, /* mlx5i_update_stats */
505 	.update_carrier    = NULL, /* no HW update in IB link */
506 	.rx_handlers       = &mlx5i_rx_handlers,
507 	.max_tc		   = MLX5I_MAX_NUM_TC,
508 	.stats_grps        = mlx5i_stats_grps,
509 	.stats_grps_num    = mlx5i_stats_grps_num,
510 };
511 
512 /* mlx5i netdev NDos */
513 
mlx5i_change_mtu(struct net_device * netdev,int new_mtu)514 static int mlx5i_change_mtu(struct net_device *netdev, int new_mtu)
515 {
516 	struct mlx5e_priv *priv = mlx5i_epriv(netdev);
517 	struct mlx5e_params new_params;
518 	int err = 0;
519 
520 	mutex_lock(&priv->state_lock);
521 
522 	new_params = priv->channels.params;
523 	new_params.sw_mtu = new_mtu;
524 
525 	err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
526 	if (err)
527 		goto out;
528 
529 	netdev->mtu = new_params.sw_mtu;
530 
531 out:
532 	mutex_unlock(&priv->state_lock);
533 	return err;
534 }
535 
mlx5i_dev_init(struct net_device * dev)536 int mlx5i_dev_init(struct net_device *dev)
537 {
538 	struct mlx5e_priv    *priv   = mlx5i_epriv(dev);
539 	struct mlx5i_priv    *ipriv  = priv->ppriv;
540 	u8 addr_mod[3];
541 
542 	/* Set dev address using underlay QP */
543 	addr_mod[0] = (ipriv->qpn >> 16) & 0xff;
544 	addr_mod[1] = (ipriv->qpn >>  8) & 0xff;
545 	addr_mod[2] = (ipriv->qpn) & 0xff;
546 	dev_addr_mod(dev, 1, addr_mod, sizeof(addr_mod));
547 
548 	/* Add QPN to net-device mapping to HT */
549 	mlx5i_pkey_add_qpn(dev, ipriv->qpn);
550 
551 	return 0;
552 }
553 
mlx5i_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)554 int mlx5i_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
555 {
556 	struct mlx5e_priv *priv = mlx5i_epriv(dev);
557 
558 	switch (cmd) {
559 	case SIOCSHWTSTAMP:
560 		return mlx5e_hwstamp_set(priv, ifr);
561 	case SIOCGHWTSTAMP:
562 		return mlx5e_hwstamp_get(priv, ifr);
563 	default:
564 		return -EOPNOTSUPP;
565 	}
566 }
567 
mlx5i_dev_cleanup(struct net_device * dev)568 void mlx5i_dev_cleanup(struct net_device *dev)
569 {
570 	struct mlx5e_priv    *priv   = mlx5i_epriv(dev);
571 	struct mlx5i_priv    *ipriv = priv->ppriv;
572 
573 	mlx5i_uninit_underlay_qp(priv);
574 
575 	/* Delete QPN to net-device mapping from HT */
576 	mlx5i_pkey_del_qpn(dev, ipriv->qpn);
577 }
578 
mlx5i_open(struct net_device * netdev)579 static int mlx5i_open(struct net_device *netdev)
580 {
581 	struct mlx5e_priv *epriv = mlx5i_epriv(netdev);
582 	struct mlx5i_priv *ipriv = epriv->ppriv;
583 	struct mlx5_core_dev *mdev = epriv->mdev;
584 	int err;
585 
586 	mutex_lock(&epriv->state_lock);
587 
588 	set_bit(MLX5E_STATE_OPENED, &epriv->state);
589 
590 	err = mlx5i_init_underlay_qp(epriv);
591 	if (err) {
592 		mlx5_core_warn(mdev, "prepare underlay qp state failed, %d\n", err);
593 		goto err_clear_state_opened_flag;
594 	}
595 
596 	err = mlx5_fs_add_rx_underlay_qpn(mdev, ipriv->qpn);
597 	if (err) {
598 		mlx5_core_warn(mdev, "attach underlay qp to ft failed, %d\n", err);
599 		goto err_reset_qp;
600 	}
601 
602 	err = mlx5e_open_channels(epriv, &epriv->channels);
603 	if (err)
604 		goto err_remove_fs_underlay_qp;
605 
606 	epriv->profile->update_rx(epriv);
607 	mlx5e_activate_priv_channels(epriv);
608 
609 	mutex_unlock(&epriv->state_lock);
610 	return 0;
611 
612 err_remove_fs_underlay_qp:
613 	mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qpn);
614 err_reset_qp:
615 	mlx5i_uninit_underlay_qp(epriv);
616 err_clear_state_opened_flag:
617 	clear_bit(MLX5E_STATE_OPENED, &epriv->state);
618 	mutex_unlock(&epriv->state_lock);
619 	return err;
620 }
621 
mlx5i_close(struct net_device * netdev)622 static int mlx5i_close(struct net_device *netdev)
623 {
624 	struct mlx5e_priv *epriv = mlx5i_epriv(netdev);
625 	struct mlx5i_priv *ipriv = epriv->ppriv;
626 	struct mlx5_core_dev *mdev = epriv->mdev;
627 
628 	/* May already be CLOSED in case a previous configuration operation
629 	 * (e.g RX/TX queue size change) that involves close&open failed.
630 	 */
631 	mutex_lock(&epriv->state_lock);
632 
633 	if (!test_bit(MLX5E_STATE_OPENED, &epriv->state))
634 		goto unlock;
635 
636 	clear_bit(MLX5E_STATE_OPENED, &epriv->state);
637 
638 	netif_carrier_off(epriv->netdev);
639 	mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qpn);
640 	mlx5e_deactivate_priv_channels(epriv);
641 	mlx5e_close_channels(&epriv->channels);
642 	mlx5i_uninit_underlay_qp(epriv);
643 unlock:
644 	mutex_unlock(&epriv->state_lock);
645 	return 0;
646 }
647 
648 /* IPoIB RDMA netdev callbacks */
mlx5i_attach_mcast(struct net_device * netdev,struct ib_device * hca,union ib_gid * gid,u16 lid,int set_qkey,u32 qkey)649 static int mlx5i_attach_mcast(struct net_device *netdev, struct ib_device *hca,
650 			      union ib_gid *gid, u16 lid, int set_qkey,
651 			      u32 qkey)
652 {
653 	struct mlx5e_priv    *epriv = mlx5i_epriv(netdev);
654 	struct mlx5_core_dev *mdev  = epriv->mdev;
655 	struct mlx5i_priv    *ipriv = epriv->ppriv;
656 	int err;
657 
658 	mlx5_core_dbg(mdev, "attaching QPN 0x%x, MGID %pI6\n", ipriv->qpn,
659 		      gid->raw);
660 	err = mlx5_core_attach_mcg(mdev, gid, ipriv->qpn);
661 	if (err)
662 		mlx5_core_warn(mdev, "failed attaching QPN 0x%x, MGID %pI6\n",
663 			       ipriv->qpn, gid->raw);
664 
665 	if (set_qkey) {
666 		mlx5_core_dbg(mdev, "%s setting qkey 0x%x\n",
667 			      netdev->name, qkey);
668 		ipriv->qkey = qkey;
669 	}
670 
671 	return err;
672 }
673 
mlx5i_detach_mcast(struct net_device * netdev,struct ib_device * hca,union ib_gid * gid,u16 lid)674 static int mlx5i_detach_mcast(struct net_device *netdev, struct ib_device *hca,
675 			      union ib_gid *gid, u16 lid)
676 {
677 	struct mlx5e_priv    *epriv = mlx5i_epriv(netdev);
678 	struct mlx5_core_dev *mdev  = epriv->mdev;
679 	struct mlx5i_priv    *ipriv = epriv->ppriv;
680 	int err;
681 
682 	mlx5_core_dbg(mdev, "detaching QPN 0x%x, MGID %pI6\n", ipriv->qpn,
683 		      gid->raw);
684 
685 	err = mlx5_core_detach_mcg(mdev, gid, ipriv->qpn);
686 	if (err)
687 		mlx5_core_dbg(mdev, "failed detaching QPN 0x%x, MGID %pI6\n",
688 			      ipriv->qpn, gid->raw);
689 
690 	return err;
691 }
692 
mlx5i_xmit(struct net_device * dev,struct sk_buff * skb,struct ib_ah * address,u32 dqpn)693 static int mlx5i_xmit(struct net_device *dev, struct sk_buff *skb,
694 		      struct ib_ah *address, u32 dqpn)
695 {
696 	struct mlx5e_priv *epriv = mlx5i_epriv(dev);
697 	struct mlx5e_txqsq *sq   = epriv->txq2sq[skb_get_queue_mapping(skb)];
698 	struct mlx5_ib_ah *mah   = to_mah(address);
699 	struct mlx5i_priv *ipriv = epriv->ppriv;
700 
701 	mlx5i_sq_xmit(sq, skb, &mah->av, dqpn, ipriv->qkey, netdev_xmit_more());
702 
703 	return NETDEV_TX_OK;
704 }
705 
mlx5i_set_pkey_index(struct net_device * netdev,int id)706 static void mlx5i_set_pkey_index(struct net_device *netdev, int id)
707 {
708 	struct mlx5i_priv *ipriv = netdev_priv(netdev);
709 
710 	ipriv->pkey_index = (u16)id;
711 }
712 
mlx5i_check_required_hca_cap(struct mlx5_core_dev * mdev)713 static int mlx5i_check_required_hca_cap(struct mlx5_core_dev *mdev)
714 {
715 	if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_IB)
716 		return -EOPNOTSUPP;
717 
718 	if (!MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) {
719 		mlx5_core_warn(mdev, "IPoIB enhanced offloads are not supported\n");
720 		return -EOPNOTSUPP;
721 	}
722 
723 	return 0;
724 }
725 
mlx5_rdma_netdev_free(struct net_device * netdev)726 static void mlx5_rdma_netdev_free(struct net_device *netdev)
727 {
728 	struct mlx5e_priv *priv = mlx5i_epriv(netdev);
729 	struct mlx5_core_dev *mdev = priv->mdev;
730 	struct mlx5i_priv *ipriv = priv->ppriv;
731 	const struct mlx5e_profile *profile = priv->profile;
732 
733 	mlx5e_detach_netdev(priv);
734 	profile->cleanup(priv);
735 
736 	if (!ipriv->sub_interface) {
737 		mlx5i_pkey_qpn_ht_cleanup(netdev);
738 		mlx5e_destroy_mdev_resources(mdev);
739 	}
740 }
741 
mlx5_is_sub_interface(struct mlx5_core_dev * mdev)742 static bool mlx5_is_sub_interface(struct mlx5_core_dev *mdev)
743 {
744 	return mdev->mlx5e_res.hw_objs.pdn != 0;
745 }
746 
mlx5_get_profile(struct mlx5_core_dev * mdev)747 static const struct mlx5e_profile *mlx5_get_profile(struct mlx5_core_dev *mdev)
748 {
749 	if (mlx5_is_sub_interface(mdev))
750 		return mlx5i_pkey_get_profile();
751 	return &mlx5i_nic_profile;
752 }
753 
mlx5_rdma_setup_rn(struct ib_device * ibdev,u32 port_num,struct net_device * netdev,void * param)754 static int mlx5_rdma_setup_rn(struct ib_device *ibdev, u32 port_num,
755 			      struct net_device *netdev, void *param)
756 {
757 	struct mlx5_core_dev *mdev = (struct mlx5_core_dev *)param;
758 	const struct mlx5e_profile *prof = mlx5_get_profile(mdev);
759 	struct mlx5i_priv *ipriv;
760 	struct mlx5e_priv *epriv;
761 	struct rdma_netdev *rn;
762 	int err;
763 
764 	ipriv = netdev_priv(netdev);
765 	epriv = mlx5i_epriv(netdev);
766 
767 	ipriv->sub_interface = mlx5_is_sub_interface(mdev);
768 	if (!ipriv->sub_interface) {
769 		err = mlx5i_pkey_qpn_ht_init(netdev);
770 		if (err) {
771 			mlx5_core_warn(mdev, "allocate qpn_to_netdev ht failed\n");
772 			return err;
773 		}
774 
775 		/* This should only be called once per mdev */
776 		err = mlx5e_create_mdev_resources(mdev);
777 		if (err)
778 			goto destroy_ht;
779 	}
780 
781 	err = mlx5e_priv_init(epriv, prof, netdev, mdev);
782 	if (err)
783 		goto destroy_mdev_resources;
784 
785 	epriv->profile = prof;
786 	epriv->ppriv = ipriv;
787 
788 	prof->init(mdev, netdev);
789 
790 	err = mlx5e_attach_netdev(epriv);
791 	if (err)
792 		goto detach;
793 	netif_carrier_off(netdev);
794 
795 	/* set rdma_netdev func pointers */
796 	rn = &ipriv->rn;
797 	rn->hca  = ibdev;
798 	rn->send = mlx5i_xmit;
799 	rn->attach_mcast = mlx5i_attach_mcast;
800 	rn->detach_mcast = mlx5i_detach_mcast;
801 	rn->set_id = mlx5i_set_pkey_index;
802 
803 	netdev->priv_destructor = mlx5_rdma_netdev_free;
804 	netdev->needs_free_netdev = 1;
805 
806 	return 0;
807 
808 detach:
809 	prof->cleanup(epriv);
810 	if (ipriv->sub_interface)
811 		return err;
812 destroy_mdev_resources:
813 	mlx5e_destroy_mdev_resources(mdev);
814 destroy_ht:
815 	mlx5i_pkey_qpn_ht_cleanup(netdev);
816 	return err;
817 }
818 
mlx5_rdma_rn_get_params(struct mlx5_core_dev * mdev,struct ib_device * device,struct rdma_netdev_alloc_params * params)819 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
820 			    struct ib_device *device,
821 			    struct rdma_netdev_alloc_params *params)
822 {
823 	int nch;
824 	int rc;
825 
826 	rc = mlx5i_check_required_hca_cap(mdev);
827 	if (rc)
828 		return rc;
829 
830 	nch = mlx5e_get_max_num_channels(mdev);
831 
832 	*params = (struct rdma_netdev_alloc_params){
833 		.sizeof_priv = sizeof(struct mlx5i_priv) +
834 			       sizeof(struct mlx5e_priv),
835 		.txqs = nch * MLX5E_MAX_NUM_TC,
836 		.rxqs = nch,
837 		.param = mdev,
838 		.initialize_rdma_netdev = mlx5_rdma_setup_rn,
839 	};
840 
841 	return 0;
842 }
843 EXPORT_SYMBOL(mlx5_rdma_rn_get_params);
844