1 /*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include "en.h"
34
35 /* mlx5e global resources should be placed in this file.
36 * Global resources are common to all the netdevices created on the same nic.
37 */
38
mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev * mdev,void * mkc)39 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc)
40 {
41 bool ro_pci_enable = pcie_relaxed_ordering_enabled(mdev->pdev);
42 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write);
43 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read);
44
45 MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read);
46 MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write);
47 }
48
mlx5e_create_mkey(struct mlx5_core_dev * mdev,u32 pdn,u32 * mkey)49 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey)
50 {
51 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
52 void *mkc;
53 u32 *in;
54 int err;
55
56 in = kvzalloc(inlen, GFP_KERNEL);
57 if (!in)
58 return -ENOMEM;
59
60 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
61 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
62 MLX5_SET(mkc, mkc, lw, 1);
63 MLX5_SET(mkc, mkc, lr, 1);
64 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
65 MLX5_SET(mkc, mkc, pd, pdn);
66 MLX5_SET(mkc, mkc, length64, 1);
67 MLX5_SET(mkc, mkc, qpn, 0xffffff);
68
69 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
70
71 kvfree(in);
72 return err;
73 }
74
mlx5e_create_mdev_resources(struct mlx5_core_dev * mdev)75 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev)
76 {
77 struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;
78 int err;
79
80 err = mlx5_core_alloc_pd(mdev, &res->pdn);
81 if (err) {
82 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
83 return err;
84 }
85
86 err = mlx5_core_alloc_transport_domain(mdev, &res->td.tdn);
87 if (err) {
88 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
89 goto err_dealloc_pd;
90 }
91
92 err = mlx5e_create_mkey(mdev, res->pdn, &res->mkey);
93 if (err) {
94 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
95 goto err_dealloc_transport_domain;
96 }
97
98 err = mlx5_alloc_bfreg(mdev, &res->bfreg, false, false);
99 if (err) {
100 mlx5_core_err(mdev, "alloc bfreg failed, %d\n", err);
101 goto err_destroy_mkey;
102 }
103
104 INIT_LIST_HEAD(&res->td.tirs_list);
105 mutex_init(&res->td.list_lock);
106
107 return 0;
108
109 err_destroy_mkey:
110 mlx5_core_destroy_mkey(mdev, res->mkey);
111 err_dealloc_transport_domain:
112 mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);
113 err_dealloc_pd:
114 mlx5_core_dealloc_pd(mdev, res->pdn);
115 return err;
116 }
117
mlx5e_destroy_mdev_resources(struct mlx5_core_dev * mdev)118 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev)
119 {
120 struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;
121
122 mlx5_free_bfreg(mdev, &res->bfreg);
123 mlx5_core_destroy_mkey(mdev, res->mkey);
124 mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);
125 mlx5_core_dealloc_pd(mdev, res->pdn);
126 memset(res, 0, sizeof(*res));
127 }
128
mlx5e_refresh_tirs(struct mlx5e_priv * priv,bool enable_uc_lb,bool enable_mc_lb)129 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
130 bool enable_mc_lb)
131 {
132 struct mlx5_core_dev *mdev = priv->mdev;
133 struct mlx5e_tir *tir;
134 u8 lb_flags = 0;
135 int err = 0;
136 u32 tirn = 0;
137 int inlen;
138 void *in;
139
140 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
141 in = kvzalloc(inlen, GFP_KERNEL);
142 if (!in) {
143 err = -ENOMEM;
144 goto out;
145 }
146
147 if (enable_uc_lb)
148 lb_flags = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
149
150 if (enable_mc_lb)
151 lb_flags |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
152
153 if (lb_flags)
154 MLX5_SET(modify_tir_in, in, ctx.self_lb_block, lb_flags);
155
156 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
157
158 mutex_lock(&mdev->mlx5e_res.hw_objs.td.list_lock);
159 list_for_each_entry(tir, &mdev->mlx5e_res.hw_objs.td.tirs_list, list) {
160 tirn = tir->tirn;
161 err = mlx5_core_modify_tir(mdev, tirn, in);
162 if (err)
163 goto out;
164 }
165
166 out:
167 kvfree(in);
168 if (err)
169 netdev_err(priv->netdev, "refresh tir(0x%x) failed, %d\n", tirn, err);
170 mutex_unlock(&mdev->mlx5e_res.hw_objs.td.list_lock);
171
172 return err;
173 }
174