1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2019 Mellanox Technologies. */
3
4 #include "dr_types.h"
5
mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev * mdev,bool other_vport,u16 vport_number,u64 * icm_address_rx,u64 * icm_address_tx)6 int mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev *mdev,
7 bool other_vport,
8 u16 vport_number,
9 u64 *icm_address_rx,
10 u64 *icm_address_tx)
11 {
12 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
13 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
14 int err;
15
16 MLX5_SET(query_esw_vport_context_in, in, opcode,
17 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
18 MLX5_SET(query_esw_vport_context_in, in, other_vport, other_vport);
19 MLX5_SET(query_esw_vport_context_in, in, vport_number, vport_number);
20
21 err = mlx5_cmd_exec_inout(mdev, query_esw_vport_context, in, out);
22 if (err)
23 return err;
24
25 *icm_address_rx =
26 MLX5_GET64(query_esw_vport_context_out, out,
27 esw_vport_context.sw_steering_vport_icm_address_rx);
28 *icm_address_tx =
29 MLX5_GET64(query_esw_vport_context_out, out,
30 esw_vport_context.sw_steering_vport_icm_address_tx);
31 return 0;
32 }
33
mlx5dr_cmd_query_gvmi(struct mlx5_core_dev * mdev,bool other_vport,u16 vport_number,u16 * gvmi)34 int mlx5dr_cmd_query_gvmi(struct mlx5_core_dev *mdev, bool other_vport,
35 u16 vport_number, u16 *gvmi)
36 {
37 u32 in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {};
38 int out_size;
39 void *out;
40 int err;
41
42 out_size = MLX5_ST_SZ_BYTES(query_hca_cap_out);
43 out = kzalloc(out_size, GFP_KERNEL);
44 if (!out)
45 return -ENOMEM;
46
47 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
48 MLX5_SET(query_hca_cap_in, in, other_function, other_vport);
49 MLX5_SET(query_hca_cap_in, in, function_id, vport_number);
50 MLX5_SET(query_hca_cap_in, in, op_mod,
51 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE << 1 |
52 HCA_CAP_OPMOD_GET_CUR);
53
54 err = mlx5_cmd_exec_inout(mdev, query_hca_cap, in, out);
55 if (err) {
56 kfree(out);
57 return err;
58 }
59
60 *gvmi = MLX5_GET(query_hca_cap_out, out, capability.cmd_hca_cap.vhca_id);
61
62 kfree(out);
63 return 0;
64 }
65
mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev * mdev,struct mlx5dr_esw_caps * caps)66 int mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev *mdev,
67 struct mlx5dr_esw_caps *caps)
68 {
69 caps->drop_icm_address_rx =
70 MLX5_CAP64_ESW_FLOWTABLE(mdev,
71 sw_steering_fdb_action_drop_icm_address_rx);
72 caps->drop_icm_address_tx =
73 MLX5_CAP64_ESW_FLOWTABLE(mdev,
74 sw_steering_fdb_action_drop_icm_address_tx);
75 caps->uplink_icm_address_rx =
76 MLX5_CAP64_ESW_FLOWTABLE(mdev,
77 sw_steering_uplink_icm_address_rx);
78 caps->uplink_icm_address_tx =
79 MLX5_CAP64_ESW_FLOWTABLE(mdev,
80 sw_steering_uplink_icm_address_tx);
81 caps->sw_owner_v2 = MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, sw_owner_v2);
82 if (!caps->sw_owner_v2)
83 caps->sw_owner = MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, sw_owner);
84
85 return 0;
86 }
87
dr_cmd_query_nic_vport_roce_en(struct mlx5_core_dev * mdev,u16 vport,bool * roce_en)88 static int dr_cmd_query_nic_vport_roce_en(struct mlx5_core_dev *mdev,
89 u16 vport, bool *roce_en)
90 {
91 u32 out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {};
92 u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {};
93 int err;
94
95 MLX5_SET(query_nic_vport_context_in, in, opcode,
96 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
97 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
98 MLX5_SET(query_nic_vport_context_in, in, other_vport, !!vport);
99
100 err = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
101 if (err)
102 return err;
103
104 *roce_en = MLX5_GET(query_nic_vport_context_out, out,
105 nic_vport_context.roce_en);
106 return 0;
107 }
108
mlx5dr_cmd_query_device(struct mlx5_core_dev * mdev,struct mlx5dr_cmd_caps * caps)109 int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev,
110 struct mlx5dr_cmd_caps *caps)
111 {
112 bool roce_en;
113 int err;
114
115 caps->prio_tag_required = MLX5_CAP_GEN(mdev, prio_tag_required);
116 caps->eswitch_manager = MLX5_CAP_GEN(mdev, eswitch_manager);
117 caps->gvmi = MLX5_CAP_GEN(mdev, vhca_id);
118 caps->flex_protocols = MLX5_CAP_GEN(mdev, flex_parser_protocols);
119 caps->sw_format_ver = MLX5_CAP_GEN(mdev, steering_format_version);
120
121 if (MLX5_CAP_GEN(mdev, roce)) {
122 err = dr_cmd_query_nic_vport_roce_en(mdev, 0, &roce_en);
123 if (err)
124 return err;
125
126 caps->roce_caps.roce_en = roce_en;
127 caps->roce_caps.fl_rc_qp_when_roce_disabled =
128 MLX5_CAP_ROCE(mdev, fl_rc_qp_when_roce_disabled);
129 caps->roce_caps.fl_rc_qp_when_roce_enabled =
130 MLX5_CAP_ROCE(mdev, fl_rc_qp_when_roce_enabled);
131 }
132
133 caps->isolate_vl_tc = MLX5_CAP_GEN(mdev, isolate_vl_tc_new);
134
135 /* geneve_tlv_option_0_exist is the indication of
136 * STE support for lookup type flex_parser_ok
137 */
138 caps->flex_parser_ok_bits_supp =
139 MLX5_CAP_FLOWTABLE(mdev,
140 flow_table_properties_nic_receive.ft_field_support.geneve_tlv_option_0_exist);
141
142 if (caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V4_ENABLED) {
143 caps->flex_parser_id_icmp_dw0 = MLX5_CAP_GEN(mdev, flex_parser_id_icmp_dw0);
144 caps->flex_parser_id_icmp_dw1 = MLX5_CAP_GEN(mdev, flex_parser_id_icmp_dw1);
145 }
146
147 if (caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V6_ENABLED) {
148 caps->flex_parser_id_icmpv6_dw0 =
149 MLX5_CAP_GEN(mdev, flex_parser_id_icmpv6_dw0);
150 caps->flex_parser_id_icmpv6_dw1 =
151 MLX5_CAP_GEN(mdev, flex_parser_id_icmpv6_dw1);
152 }
153
154 if (caps->flex_protocols & MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED)
155 caps->flex_parser_id_geneve_tlv_option_0 =
156 MLX5_CAP_GEN(mdev, flex_parser_id_geneve_tlv_option_0);
157
158 if (caps->flex_protocols & MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED)
159 caps->flex_parser_id_mpls_over_gre =
160 MLX5_CAP_GEN(mdev, flex_parser_id_outer_first_mpls_over_gre);
161
162 if (caps->flex_protocols & MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED)
163 caps->flex_parser_id_mpls_over_udp =
164 MLX5_CAP_GEN(mdev, flex_parser_id_outer_first_mpls_over_udp_label);
165
166 if (caps->flex_protocols & MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED)
167 caps->flex_parser_id_gtpu_dw_0 =
168 MLX5_CAP_GEN(mdev, flex_parser_id_gtpu_dw_0);
169
170 if (caps->flex_protocols & MLX5_FLEX_PARSER_GTPU_TEID_ENABLED)
171 caps->flex_parser_id_gtpu_teid =
172 MLX5_CAP_GEN(mdev, flex_parser_id_gtpu_teid);
173
174 if (caps->flex_protocols & MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED)
175 caps->flex_parser_id_gtpu_dw_2 =
176 MLX5_CAP_GEN(mdev, flex_parser_id_gtpu_dw_2);
177
178 if (caps->flex_protocols & MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED)
179 caps->flex_parser_id_gtpu_first_ext_dw_0 =
180 MLX5_CAP_GEN(mdev, flex_parser_id_gtpu_first_ext_dw_0);
181
182 caps->nic_rx_drop_address =
183 MLX5_CAP64_FLOWTABLE(mdev, sw_steering_nic_rx_action_drop_icm_address);
184 caps->nic_tx_drop_address =
185 MLX5_CAP64_FLOWTABLE(mdev, sw_steering_nic_tx_action_drop_icm_address);
186 caps->nic_tx_allow_address =
187 MLX5_CAP64_FLOWTABLE(mdev, sw_steering_nic_tx_action_allow_icm_address);
188
189 caps->rx_sw_owner_v2 = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, sw_owner_v2);
190 caps->tx_sw_owner_v2 = MLX5_CAP_FLOWTABLE_NIC_TX(mdev, sw_owner_v2);
191
192 if (!caps->rx_sw_owner_v2)
193 caps->rx_sw_owner = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, sw_owner);
194 if (!caps->tx_sw_owner_v2)
195 caps->tx_sw_owner = MLX5_CAP_FLOWTABLE_NIC_TX(mdev, sw_owner);
196
197 caps->max_ft_level = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_ft_level);
198
199 caps->log_icm_size = MLX5_CAP_DEV_MEM(mdev, log_steering_sw_icm_size);
200 caps->hdr_modify_icm_addr =
201 MLX5_CAP64_DEV_MEM(mdev, header_modify_sw_icm_start_address);
202
203 caps->roce_min_src_udp = MLX5_CAP_ROCE(mdev, r_roce_min_src_udp_port);
204
205 caps->is_ecpf = mlx5_core_is_ecpf_esw_manager(mdev);
206
207 return 0;
208 }
209
mlx5dr_cmd_query_flow_table(struct mlx5_core_dev * dev,enum fs_flow_table_type type,u32 table_id,struct mlx5dr_cmd_query_flow_table_details * output)210 int mlx5dr_cmd_query_flow_table(struct mlx5_core_dev *dev,
211 enum fs_flow_table_type type,
212 u32 table_id,
213 struct mlx5dr_cmd_query_flow_table_details *output)
214 {
215 u32 out[MLX5_ST_SZ_DW(query_flow_table_out)] = {};
216 u32 in[MLX5_ST_SZ_DW(query_flow_table_in)] = {};
217 int err;
218
219 MLX5_SET(query_flow_table_in, in, opcode,
220 MLX5_CMD_OP_QUERY_FLOW_TABLE);
221
222 MLX5_SET(query_flow_table_in, in, table_type, type);
223 MLX5_SET(query_flow_table_in, in, table_id, table_id);
224
225 err = mlx5_cmd_exec_inout(dev, query_flow_table, in, out);
226 if (err)
227 return err;
228
229 output->status = MLX5_GET(query_flow_table_out, out, status);
230 output->level = MLX5_GET(query_flow_table_out, out, flow_table_context.level);
231
232 output->sw_owner_icm_root_1 = MLX5_GET64(query_flow_table_out, out,
233 flow_table_context.sw_owner_icm_root_1);
234 output->sw_owner_icm_root_0 = MLX5_GET64(query_flow_table_out, out,
235 flow_table_context.sw_owner_icm_root_0);
236
237 return 0;
238 }
239
mlx5dr_cmd_query_flow_sampler(struct mlx5_core_dev * dev,u32 sampler_id,u64 * rx_icm_addr,u64 * tx_icm_addr)240 int mlx5dr_cmd_query_flow_sampler(struct mlx5_core_dev *dev,
241 u32 sampler_id,
242 u64 *rx_icm_addr,
243 u64 *tx_icm_addr)
244 {
245 u32 out[MLX5_ST_SZ_DW(query_sampler_obj_out)] = {};
246 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {};
247 void *attr;
248 int ret;
249
250 MLX5_SET(general_obj_in_cmd_hdr, in, opcode,
251 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
252 MLX5_SET(general_obj_in_cmd_hdr, in, obj_type,
253 MLX5_GENERAL_OBJECT_TYPES_SAMPLER);
254 MLX5_SET(general_obj_in_cmd_hdr, in, obj_id, sampler_id);
255
256 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
257 if (ret)
258 return ret;
259
260 attr = MLX5_ADDR_OF(query_sampler_obj_out, out, sampler_object);
261
262 *rx_icm_addr = MLX5_GET64(sampler_obj, attr,
263 sw_steering_icm_address_rx);
264 *tx_icm_addr = MLX5_GET64(sampler_obj, attr,
265 sw_steering_icm_address_tx);
266
267 return 0;
268 }
269
mlx5dr_cmd_sync_steering(struct mlx5_core_dev * mdev)270 int mlx5dr_cmd_sync_steering(struct mlx5_core_dev *mdev)
271 {
272 u32 in[MLX5_ST_SZ_DW(sync_steering_in)] = {};
273
274 MLX5_SET(sync_steering_in, in, opcode, MLX5_CMD_OP_SYNC_STEERING);
275
276 return mlx5_cmd_exec_in(mdev, sync_steering, in);
277 }
278
mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev * mdev,u32 table_type,u32 table_id,u32 group_id,u32 modify_header_id,u16 vport)279 int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev,
280 u32 table_type,
281 u32 table_id,
282 u32 group_id,
283 u32 modify_header_id,
284 u16 vport)
285 {
286 u32 out[MLX5_ST_SZ_DW(set_fte_out)] = {};
287 void *in_flow_context;
288 unsigned int inlen;
289 void *in_dests;
290 u32 *in;
291 int err;
292
293 inlen = MLX5_ST_SZ_BYTES(set_fte_in) +
294 1 * MLX5_ST_SZ_BYTES(dest_format_struct); /* One destination only */
295
296 in = kvzalloc(inlen, GFP_KERNEL);
297 if (!in)
298 return -ENOMEM;
299
300 MLX5_SET(set_fte_in, in, opcode, MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY);
301 MLX5_SET(set_fte_in, in, table_type, table_type);
302 MLX5_SET(set_fte_in, in, table_id, table_id);
303
304 in_flow_context = MLX5_ADDR_OF(set_fte_in, in, flow_context);
305 MLX5_SET(flow_context, in_flow_context, group_id, group_id);
306 MLX5_SET(flow_context, in_flow_context, modify_header_id, modify_header_id);
307 MLX5_SET(flow_context, in_flow_context, destination_list_size, 1);
308 MLX5_SET(flow_context, in_flow_context, action,
309 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
310 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR);
311
312 in_dests = MLX5_ADDR_OF(flow_context, in_flow_context, destination);
313 MLX5_SET(dest_format_struct, in_dests, destination_type,
314 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT);
315 MLX5_SET(dest_format_struct, in_dests, destination_id, vport);
316
317 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
318 kvfree(in);
319
320 return err;
321 }
322
mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev * mdev,u32 table_type,u32 table_id)323 int mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev *mdev,
324 u32 table_type,
325 u32 table_id)
326 {
327 u32 in[MLX5_ST_SZ_DW(delete_fte_in)] = {};
328
329 MLX5_SET(delete_fte_in, in, opcode, MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY);
330 MLX5_SET(delete_fte_in, in, table_type, table_type);
331 MLX5_SET(delete_fte_in, in, table_id, table_id);
332
333 return mlx5_cmd_exec_in(mdev, delete_fte, in);
334 }
335
mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev * mdev,u32 table_type,u8 num_of_actions,u64 * actions,u32 * modify_header_id)336 int mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev *mdev,
337 u32 table_type,
338 u8 num_of_actions,
339 u64 *actions,
340 u32 *modify_header_id)
341 {
342 u32 out[MLX5_ST_SZ_DW(alloc_modify_header_context_out)] = {};
343 void *p_actions;
344 u32 inlen;
345 u32 *in;
346 int err;
347
348 inlen = MLX5_ST_SZ_BYTES(alloc_modify_header_context_in) +
349 num_of_actions * sizeof(u64);
350 in = kvzalloc(inlen, GFP_KERNEL);
351 if (!in)
352 return -ENOMEM;
353
354 MLX5_SET(alloc_modify_header_context_in, in, opcode,
355 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT);
356 MLX5_SET(alloc_modify_header_context_in, in, table_type, table_type);
357 MLX5_SET(alloc_modify_header_context_in, in, num_of_actions, num_of_actions);
358 p_actions = MLX5_ADDR_OF(alloc_modify_header_context_in, in, actions);
359 memcpy(p_actions, actions, num_of_actions * sizeof(u64));
360
361 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
362 if (err)
363 goto out;
364
365 *modify_header_id = MLX5_GET(alloc_modify_header_context_out, out,
366 modify_header_id);
367 out:
368 kvfree(in);
369 return err;
370 }
371
mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev * mdev,u32 modify_header_id)372 int mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev *mdev,
373 u32 modify_header_id)
374 {
375 u32 in[MLX5_ST_SZ_DW(dealloc_modify_header_context_in)] = {};
376
377 MLX5_SET(dealloc_modify_header_context_in, in, opcode,
378 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT);
379 MLX5_SET(dealloc_modify_header_context_in, in, modify_header_id,
380 modify_header_id);
381
382 return mlx5_cmd_exec_in(mdev, dealloc_modify_header_context, in);
383 }
384
mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev * mdev,u32 table_type,u32 table_id,u32 * group_id)385 int mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev *mdev,
386 u32 table_type,
387 u32 table_id,
388 u32 *group_id)
389 {
390 u32 out[MLX5_ST_SZ_DW(create_flow_group_out)] = {};
391 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
392 u32 *in;
393 int err;
394
395 in = kvzalloc(inlen, GFP_KERNEL);
396 if (!in)
397 return -ENOMEM;
398
399 MLX5_SET(create_flow_group_in, in, opcode, MLX5_CMD_OP_CREATE_FLOW_GROUP);
400 MLX5_SET(create_flow_group_in, in, table_type, table_type);
401 MLX5_SET(create_flow_group_in, in, table_id, table_id);
402
403 err = mlx5_cmd_exec_inout(mdev, create_flow_group, in, out);
404 if (err)
405 goto out;
406
407 *group_id = MLX5_GET(create_flow_group_out, out, group_id);
408
409 out:
410 kvfree(in);
411 return err;
412 }
413
mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev * mdev,u32 table_type,u32 table_id,u32 group_id)414 int mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev *mdev,
415 u32 table_type,
416 u32 table_id,
417 u32 group_id)
418 {
419 u32 in[MLX5_ST_SZ_DW(destroy_flow_group_in)] = {};
420
421 MLX5_SET(destroy_flow_group_in, in, opcode,
422 MLX5_CMD_OP_DESTROY_FLOW_GROUP);
423 MLX5_SET(destroy_flow_group_in, in, table_type, table_type);
424 MLX5_SET(destroy_flow_group_in, in, table_id, table_id);
425 MLX5_SET(destroy_flow_group_in, in, group_id, group_id);
426
427 return mlx5_cmd_exec_in(mdev, destroy_flow_group, in);
428 }
429
mlx5dr_cmd_create_flow_table(struct mlx5_core_dev * mdev,struct mlx5dr_cmd_create_flow_table_attr * attr,u64 * fdb_rx_icm_addr,u32 * table_id)430 int mlx5dr_cmd_create_flow_table(struct mlx5_core_dev *mdev,
431 struct mlx5dr_cmd_create_flow_table_attr *attr,
432 u64 *fdb_rx_icm_addr,
433 u32 *table_id)
434 {
435 u32 out[MLX5_ST_SZ_DW(create_flow_table_out)] = {};
436 u32 in[MLX5_ST_SZ_DW(create_flow_table_in)] = {};
437 void *ft_mdev;
438 int err;
439
440 MLX5_SET(create_flow_table_in, in, opcode, MLX5_CMD_OP_CREATE_FLOW_TABLE);
441 MLX5_SET(create_flow_table_in, in, table_type, attr->table_type);
442
443 ft_mdev = MLX5_ADDR_OF(create_flow_table_in, in, flow_table_context);
444 MLX5_SET(flow_table_context, ft_mdev, termination_table, attr->term_tbl);
445 MLX5_SET(flow_table_context, ft_mdev, sw_owner, attr->sw_owner);
446 MLX5_SET(flow_table_context, ft_mdev, level, attr->level);
447
448 if (attr->sw_owner) {
449 /* icm_addr_0 used for FDB RX / NIC TX / NIC_RX
450 * icm_addr_1 used for FDB TX
451 */
452 if (attr->table_type == MLX5_FLOW_TABLE_TYPE_NIC_RX) {
453 MLX5_SET64(flow_table_context, ft_mdev,
454 sw_owner_icm_root_0, attr->icm_addr_rx);
455 } else if (attr->table_type == MLX5_FLOW_TABLE_TYPE_NIC_TX) {
456 MLX5_SET64(flow_table_context, ft_mdev,
457 sw_owner_icm_root_0, attr->icm_addr_tx);
458 } else if (attr->table_type == MLX5_FLOW_TABLE_TYPE_FDB) {
459 MLX5_SET64(flow_table_context, ft_mdev,
460 sw_owner_icm_root_0, attr->icm_addr_rx);
461 MLX5_SET64(flow_table_context, ft_mdev,
462 sw_owner_icm_root_1, attr->icm_addr_tx);
463 }
464 }
465
466 MLX5_SET(create_flow_table_in, in, flow_table_context.decap_en,
467 attr->decap_en);
468 MLX5_SET(create_flow_table_in, in, flow_table_context.reformat_en,
469 attr->reformat_en);
470
471 err = mlx5_cmd_exec_inout(mdev, create_flow_table, in, out);
472 if (err)
473 return err;
474
475 *table_id = MLX5_GET(create_flow_table_out, out, table_id);
476 if (!attr->sw_owner && attr->table_type == MLX5_FLOW_TABLE_TYPE_FDB &&
477 fdb_rx_icm_addr)
478 *fdb_rx_icm_addr =
479 (u64)MLX5_GET(create_flow_table_out, out, icm_address_31_0) |
480 (u64)MLX5_GET(create_flow_table_out, out, icm_address_39_32) << 32 |
481 (u64)MLX5_GET(create_flow_table_out, out, icm_address_63_40) << 40;
482
483 return 0;
484 }
485
mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev * mdev,u32 table_id,u32 table_type)486 int mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev *mdev,
487 u32 table_id,
488 u32 table_type)
489 {
490 u32 in[MLX5_ST_SZ_DW(destroy_flow_table_in)] = {};
491
492 MLX5_SET(destroy_flow_table_in, in, opcode,
493 MLX5_CMD_OP_DESTROY_FLOW_TABLE);
494 MLX5_SET(destroy_flow_table_in, in, table_type, table_type);
495 MLX5_SET(destroy_flow_table_in, in, table_id, table_id);
496
497 return mlx5_cmd_exec_in(mdev, destroy_flow_table, in);
498 }
499
mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev * mdev,enum mlx5_reformat_ctx_type rt,u8 reformat_param_0,u8 reformat_param_1,size_t reformat_size,void * reformat_data,u32 * reformat_id)500 int mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev *mdev,
501 enum mlx5_reformat_ctx_type rt,
502 u8 reformat_param_0,
503 u8 reformat_param_1,
504 size_t reformat_size,
505 void *reformat_data,
506 u32 *reformat_id)
507 {
508 u32 out[MLX5_ST_SZ_DW(alloc_packet_reformat_context_out)] = {};
509 size_t inlen, cmd_data_sz, cmd_total_sz;
510 void *prctx;
511 void *pdata;
512 void *in;
513 int err;
514
515 cmd_total_sz = MLX5_ST_SZ_BYTES(alloc_packet_reformat_context_in);
516 cmd_data_sz = MLX5_FLD_SZ_BYTES(alloc_packet_reformat_context_in,
517 packet_reformat_context.reformat_data);
518 inlen = ALIGN(cmd_total_sz + reformat_size - cmd_data_sz, 4);
519 in = kvzalloc(inlen, GFP_KERNEL);
520 if (!in)
521 return -ENOMEM;
522
523 MLX5_SET(alloc_packet_reformat_context_in, in, opcode,
524 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT);
525
526 prctx = MLX5_ADDR_OF(alloc_packet_reformat_context_in, in, packet_reformat_context);
527 pdata = MLX5_ADDR_OF(packet_reformat_context_in, prctx, reformat_data);
528
529 MLX5_SET(packet_reformat_context_in, prctx, reformat_type, rt);
530 MLX5_SET(packet_reformat_context_in, prctx, reformat_param_0, reformat_param_0);
531 MLX5_SET(packet_reformat_context_in, prctx, reformat_param_1, reformat_param_1);
532 MLX5_SET(packet_reformat_context_in, prctx, reformat_data_size, reformat_size);
533 if (reformat_data && reformat_size)
534 memcpy(pdata, reformat_data, reformat_size);
535
536 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
537 if (err)
538 return err;
539
540 *reformat_id = MLX5_GET(alloc_packet_reformat_context_out, out, packet_reformat_id);
541 kvfree(in);
542
543 return err;
544 }
545
mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev * mdev,u32 reformat_id)546 void mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev *mdev,
547 u32 reformat_id)
548 {
549 u32 in[MLX5_ST_SZ_DW(dealloc_packet_reformat_context_in)] = {};
550
551 MLX5_SET(dealloc_packet_reformat_context_in, in, opcode,
552 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT);
553 MLX5_SET(dealloc_packet_reformat_context_in, in, packet_reformat_id,
554 reformat_id);
555
556 mlx5_cmd_exec_in(mdev, dealloc_packet_reformat_context, in);
557 }
558
mlx5dr_cmd_query_gid(struct mlx5_core_dev * mdev,u8 vhca_port_num,u16 index,struct mlx5dr_cmd_gid_attr * attr)559 int mlx5dr_cmd_query_gid(struct mlx5_core_dev *mdev, u8 vhca_port_num,
560 u16 index, struct mlx5dr_cmd_gid_attr *attr)
561 {
562 u32 out[MLX5_ST_SZ_DW(query_roce_address_out)] = {};
563 u32 in[MLX5_ST_SZ_DW(query_roce_address_in)] = {};
564 int err;
565
566 MLX5_SET(query_roce_address_in, in, opcode,
567 MLX5_CMD_OP_QUERY_ROCE_ADDRESS);
568
569 MLX5_SET(query_roce_address_in, in, roce_address_index, index);
570 MLX5_SET(query_roce_address_in, in, vhca_port_num, vhca_port_num);
571
572 err = mlx5_cmd_exec_inout(mdev, query_roce_address, in, out);
573 if (err)
574 return err;
575
576 memcpy(&attr->gid,
577 MLX5_ADDR_OF(query_roce_address_out,
578 out, roce_address.source_l3_address),
579 sizeof(attr->gid));
580 memcpy(attr->mac,
581 MLX5_ADDR_OF(query_roce_address_out, out,
582 roce_address.source_mac_47_32),
583 sizeof(attr->mac));
584
585 if (MLX5_GET(query_roce_address_out, out,
586 roce_address.roce_version) == MLX5_ROCE_VERSION_2)
587 attr->roce_ver = MLX5_ROCE_VERSION_2;
588 else
589 attr->roce_ver = MLX5_ROCE_VERSION_1;
590
591 return 0;
592 }
593
mlx5dr_cmd_set_extended_dest(struct mlx5_core_dev * dev,struct mlx5dr_cmd_fte_info * fte,bool * extended_dest)594 static int mlx5dr_cmd_set_extended_dest(struct mlx5_core_dev *dev,
595 struct mlx5dr_cmd_fte_info *fte,
596 bool *extended_dest)
597 {
598 int fw_log_max_fdb_encap_uplink = MLX5_CAP_ESW(dev, log_max_fdb_encap_uplink);
599 int num_fwd_destinations = 0;
600 int num_encap = 0;
601 int i;
602
603 *extended_dest = false;
604 if (!(fte->action.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST))
605 return 0;
606 for (i = 0; i < fte->dests_size; i++) {
607 if (fte->dest_arr[i].type == MLX5_FLOW_DESTINATION_TYPE_COUNTER ||
608 fte->dest_arr[i].type == MLX5_FLOW_DESTINATION_TYPE_NONE)
609 continue;
610 if ((fte->dest_arr[i].type == MLX5_FLOW_DESTINATION_TYPE_VPORT ||
611 fte->dest_arr[i].type == MLX5_FLOW_DESTINATION_TYPE_UPLINK) &&
612 fte->dest_arr[i].vport.flags & MLX5_FLOW_DEST_VPORT_REFORMAT_ID)
613 num_encap++;
614 num_fwd_destinations++;
615 }
616
617 if (num_fwd_destinations > 1 && num_encap > 0)
618 *extended_dest = true;
619
620 if (*extended_dest && !fw_log_max_fdb_encap_uplink) {
621 mlx5_core_warn(dev, "FW does not support extended destination");
622 return -EOPNOTSUPP;
623 }
624 if (num_encap > (1 << fw_log_max_fdb_encap_uplink)) {
625 mlx5_core_warn(dev, "FW does not support more than %d encaps",
626 1 << fw_log_max_fdb_encap_uplink);
627 return -EOPNOTSUPP;
628 }
629
630 return 0;
631 }
632
mlx5dr_cmd_set_fte(struct mlx5_core_dev * dev,int opmod,int modify_mask,struct mlx5dr_cmd_ft_info * ft,u32 group_id,struct mlx5dr_cmd_fte_info * fte)633 int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev,
634 int opmod, int modify_mask,
635 struct mlx5dr_cmd_ft_info *ft,
636 u32 group_id,
637 struct mlx5dr_cmd_fte_info *fte)
638 {
639 u32 out[MLX5_ST_SZ_DW(set_fte_out)] = {};
640 void *in_flow_context, *vlan;
641 bool extended_dest = false;
642 void *in_match_value;
643 unsigned int inlen;
644 int dst_cnt_size;
645 void *in_dests;
646 u32 *in;
647 int err;
648 int i;
649
650 if (mlx5dr_cmd_set_extended_dest(dev, fte, &extended_dest))
651 return -EOPNOTSUPP;
652
653 if (!extended_dest)
654 dst_cnt_size = MLX5_ST_SZ_BYTES(dest_format_struct);
655 else
656 dst_cnt_size = MLX5_ST_SZ_BYTES(extended_dest_format);
657
658 inlen = MLX5_ST_SZ_BYTES(set_fte_in) + fte->dests_size * dst_cnt_size;
659 in = kvzalloc(inlen, GFP_KERNEL);
660 if (!in)
661 return -ENOMEM;
662
663 MLX5_SET(set_fte_in, in, opcode, MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY);
664 MLX5_SET(set_fte_in, in, op_mod, opmod);
665 MLX5_SET(set_fte_in, in, modify_enable_mask, modify_mask);
666 MLX5_SET(set_fte_in, in, table_type, ft->type);
667 MLX5_SET(set_fte_in, in, table_id, ft->id);
668 MLX5_SET(set_fte_in, in, flow_index, fte->index);
669 MLX5_SET(set_fte_in, in, ignore_flow_level, fte->ignore_flow_level);
670 if (ft->vport) {
671 MLX5_SET(set_fte_in, in, vport_number, ft->vport);
672 MLX5_SET(set_fte_in, in, other_vport, 1);
673 }
674
675 in_flow_context = MLX5_ADDR_OF(set_fte_in, in, flow_context);
676 MLX5_SET(flow_context, in_flow_context, group_id, group_id);
677
678 MLX5_SET(flow_context, in_flow_context, flow_tag,
679 fte->flow_context.flow_tag);
680 MLX5_SET(flow_context, in_flow_context, flow_source,
681 fte->flow_context.flow_source);
682
683 MLX5_SET(flow_context, in_flow_context, extended_destination,
684 extended_dest);
685 if (extended_dest) {
686 u32 action;
687
688 action = fte->action.action &
689 ~MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
690 MLX5_SET(flow_context, in_flow_context, action, action);
691 } else {
692 MLX5_SET(flow_context, in_flow_context, action,
693 fte->action.action);
694 if (fte->action.pkt_reformat)
695 MLX5_SET(flow_context, in_flow_context, packet_reformat_id,
696 fte->action.pkt_reformat->id);
697 }
698 if (fte->action.modify_hdr)
699 MLX5_SET(flow_context, in_flow_context, modify_header_id,
700 fte->action.modify_hdr->id);
701
702 vlan = MLX5_ADDR_OF(flow_context, in_flow_context, push_vlan);
703
704 MLX5_SET(vlan, vlan, ethtype, fte->action.vlan[0].ethtype);
705 MLX5_SET(vlan, vlan, vid, fte->action.vlan[0].vid);
706 MLX5_SET(vlan, vlan, prio, fte->action.vlan[0].prio);
707
708 vlan = MLX5_ADDR_OF(flow_context, in_flow_context, push_vlan_2);
709
710 MLX5_SET(vlan, vlan, ethtype, fte->action.vlan[1].ethtype);
711 MLX5_SET(vlan, vlan, vid, fte->action.vlan[1].vid);
712 MLX5_SET(vlan, vlan, prio, fte->action.vlan[1].prio);
713
714 in_match_value = MLX5_ADDR_OF(flow_context, in_flow_context,
715 match_value);
716 memcpy(in_match_value, fte->val, sizeof(u32) * MLX5_ST_SZ_DW_MATCH_PARAM);
717
718 in_dests = MLX5_ADDR_OF(flow_context, in_flow_context, destination);
719 if (fte->action.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
720 int list_size = 0;
721
722 for (i = 0; i < fte->dests_size; i++) {
723 enum mlx5_flow_destination_type type = fte->dest_arr[i].type;
724 enum mlx5_ifc_flow_destination_type ifc_type;
725 unsigned int id;
726
727 if (type == MLX5_FLOW_DESTINATION_TYPE_COUNTER)
728 continue;
729
730 switch (type) {
731 case MLX5_FLOW_DESTINATION_TYPE_NONE:
732 continue;
733 case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM:
734 id = fte->dest_arr[i].ft_num;
735 ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE;
736 break;
737 case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE:
738 id = fte->dest_arr[i].ft_id;
739 ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE;
740
741 break;
742 case MLX5_FLOW_DESTINATION_TYPE_UPLINK:
743 case MLX5_FLOW_DESTINATION_TYPE_VPORT:
744 if (type == MLX5_FLOW_DESTINATION_TYPE_VPORT) {
745 id = fte->dest_arr[i].vport.num;
746 MLX5_SET(dest_format_struct, in_dests,
747 destination_eswitch_owner_vhca_id_valid,
748 !!(fte->dest_arr[i].vport.flags &
749 MLX5_FLOW_DEST_VPORT_VHCA_ID));
750 ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT;
751 } else {
752 id = 0;
753 ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK;
754 MLX5_SET(dest_format_struct, in_dests,
755 destination_eswitch_owner_vhca_id_valid, 1);
756 }
757 MLX5_SET(dest_format_struct, in_dests,
758 destination_eswitch_owner_vhca_id,
759 fte->dest_arr[i].vport.vhca_id);
760 if (extended_dest && (fte->dest_arr[i].vport.flags &
761 MLX5_FLOW_DEST_VPORT_REFORMAT_ID)) {
762 MLX5_SET(dest_format_struct, in_dests,
763 packet_reformat,
764 !!(fte->dest_arr[i].vport.flags &
765 MLX5_FLOW_DEST_VPORT_REFORMAT_ID));
766 MLX5_SET(extended_dest_format, in_dests,
767 packet_reformat_id,
768 fte->dest_arr[i].vport.reformat_id);
769 }
770 break;
771 case MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER:
772 id = fte->dest_arr[i].sampler_id;
773 ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
774 break;
775 default:
776 id = fte->dest_arr[i].tir_num;
777 ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_TIR;
778 }
779
780 MLX5_SET(dest_format_struct, in_dests, destination_type,
781 ifc_type);
782 MLX5_SET(dest_format_struct, in_dests, destination_id, id);
783 in_dests += dst_cnt_size;
784 list_size++;
785 }
786
787 MLX5_SET(flow_context, in_flow_context, destination_list_size,
788 list_size);
789 }
790
791 if (fte->action.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
792 int max_list_size = BIT(MLX5_CAP_FLOWTABLE_TYPE(dev,
793 log_max_flow_counter,
794 ft->type));
795 int list_size = 0;
796
797 for (i = 0; i < fte->dests_size; i++) {
798 if (fte->dest_arr[i].type !=
799 MLX5_FLOW_DESTINATION_TYPE_COUNTER)
800 continue;
801
802 MLX5_SET(flow_counter_list, in_dests, flow_counter_id,
803 fte->dest_arr[i].counter_id);
804 in_dests += dst_cnt_size;
805 list_size++;
806 }
807 if (list_size > max_list_size) {
808 err = -EINVAL;
809 goto err_out;
810 }
811
812 MLX5_SET(flow_context, in_flow_context, flow_counter_list_size,
813 list_size);
814 }
815
816 err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
817 err_out:
818 kvfree(in);
819 return err;
820 }
821