1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2019 Mellanox Technologies. */
3
4 #include "dr_types.h"
5 #include "dr_ste.h"
6
7 enum dr_action_domain {
8 DR_ACTION_DOMAIN_NIC_INGRESS,
9 DR_ACTION_DOMAIN_NIC_EGRESS,
10 DR_ACTION_DOMAIN_FDB_INGRESS,
11 DR_ACTION_DOMAIN_FDB_EGRESS,
12 DR_ACTION_DOMAIN_MAX,
13 };
14
15 enum dr_action_valid_state {
16 DR_ACTION_STATE_ERR,
17 DR_ACTION_STATE_NO_ACTION,
18 DR_ACTION_STATE_ENCAP,
19 DR_ACTION_STATE_DECAP,
20 DR_ACTION_STATE_MODIFY_HDR,
21 DR_ACTION_STATE_POP_VLAN,
22 DR_ACTION_STATE_PUSH_VLAN,
23 DR_ACTION_STATE_NON_TERM,
24 DR_ACTION_STATE_TERM,
25 DR_ACTION_STATE_ASO,
26 DR_ACTION_STATE_MAX,
27 };
28
29 static const char * const action_type_to_str[] = {
30 [DR_ACTION_TYP_TNL_L2_TO_L2] = "DR_ACTION_TYP_TNL_L2_TO_L2",
31 [DR_ACTION_TYP_L2_TO_TNL_L2] = "DR_ACTION_TYP_L2_TO_TNL_L2",
32 [DR_ACTION_TYP_TNL_L3_TO_L2] = "DR_ACTION_TYP_TNL_L3_TO_L2",
33 [DR_ACTION_TYP_L2_TO_TNL_L3] = "DR_ACTION_TYP_L2_TO_TNL_L3",
34 [DR_ACTION_TYP_DROP] = "DR_ACTION_TYP_DROP",
35 [DR_ACTION_TYP_QP] = "DR_ACTION_TYP_QP",
36 [DR_ACTION_TYP_FT] = "DR_ACTION_TYP_FT",
37 [DR_ACTION_TYP_CTR] = "DR_ACTION_TYP_CTR",
38 [DR_ACTION_TYP_TAG] = "DR_ACTION_TYP_TAG",
39 [DR_ACTION_TYP_MODIFY_HDR] = "DR_ACTION_TYP_MODIFY_HDR",
40 [DR_ACTION_TYP_VPORT] = "DR_ACTION_TYP_VPORT",
41 [DR_ACTION_TYP_POP_VLAN] = "DR_ACTION_TYP_POP_VLAN",
42 [DR_ACTION_TYP_PUSH_VLAN] = "DR_ACTION_TYP_PUSH_VLAN",
43 [DR_ACTION_TYP_SAMPLER] = "DR_ACTION_TYP_SAMPLER",
44 [DR_ACTION_TYP_INSERT_HDR] = "DR_ACTION_TYP_INSERT_HDR",
45 [DR_ACTION_TYP_REMOVE_HDR] = "DR_ACTION_TYP_REMOVE_HDR",
46 [DR_ACTION_TYP_ASO_FLOW_METER] = "DR_ACTION_TYP_ASO_FLOW_METER",
47 [DR_ACTION_TYP_RANGE] = "DR_ACTION_TYP_RANGE",
48 [DR_ACTION_TYP_MAX] = "DR_ACTION_UNKNOWN",
49 };
50
dr_action_id_to_str(enum mlx5dr_action_type action_id)51 static const char *dr_action_id_to_str(enum mlx5dr_action_type action_id)
52 {
53 if (action_id > DR_ACTION_TYP_MAX)
54 action_id = DR_ACTION_TYP_MAX;
55 return action_type_to_str[action_id];
56 }
57
58 static const enum dr_action_valid_state
59 next_action_state[DR_ACTION_DOMAIN_MAX][DR_ACTION_STATE_MAX][DR_ACTION_TYP_MAX] = {
60 [DR_ACTION_DOMAIN_NIC_INGRESS] = {
61 [DR_ACTION_STATE_NO_ACTION] = {
62 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
63 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
64 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
65 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
66 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
67 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM,
68 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
69 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP,
70 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP,
71 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
72 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
73 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
74 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
75 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
76 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
77 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
78 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
79 },
80 [DR_ACTION_STATE_DECAP] = {
81 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
82 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
83 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
84 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
85 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
86 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_DECAP,
87 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP,
88 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
89 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
90 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
91 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
92 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
93 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
94 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
95 },
96 [DR_ACTION_STATE_ENCAP] = {
97 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
98 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
99 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
100 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
101 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
102 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_ENCAP,
103 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP,
104 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
105 },
106 [DR_ACTION_STATE_MODIFY_HDR] = {
107 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
108 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
109 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
110 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
111 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
112 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_MODIFY_HDR,
113 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
114 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
115 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
116 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
117 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
118 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
119 },
120 [DR_ACTION_STATE_POP_VLAN] = {
121 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
122 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
123 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
124 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
125 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
126 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_POP_VLAN,
127 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN,
128 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
129 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
130 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
131 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
132 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
133 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
134 },
135 [DR_ACTION_STATE_PUSH_VLAN] = {
136 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
137 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
138 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
139 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
140 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_PUSH_VLAN,
141 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN,
142 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
143 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
144 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
145 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
146 },
147 [DR_ACTION_STATE_NON_TERM] = {
148 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
149 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
150 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
151 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
152 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
153 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM,
154 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
155 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP,
156 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP,
157 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
158 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
159 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
160 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
161 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
162 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
163 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
164 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
165 },
166 [DR_ACTION_STATE_ASO] = {
167 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
168 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
169 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
170 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
171 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO,
172 },
173 [DR_ACTION_STATE_TERM] = {
174 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
175 },
176 },
177 [DR_ACTION_DOMAIN_NIC_EGRESS] = {
178 [DR_ACTION_STATE_NO_ACTION] = {
179 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
180 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
181 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
182 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
183 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
184 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
185 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
186 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
187 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
188 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
189 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
190 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
191 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
192 },
193 [DR_ACTION_STATE_DECAP] = {
194 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
195 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
196 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
197 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
198 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP,
199 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
200 },
201 [DR_ACTION_STATE_ENCAP] = {
202 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
203 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
204 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
205 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
206 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP,
207 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
208 },
209 [DR_ACTION_STATE_MODIFY_HDR] = {
210 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
211 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
212 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
213 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
214 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
215 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
216 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
217 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
218 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
219 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
220 },
221 [DR_ACTION_STATE_POP_VLAN] = {
222 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
223 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
224 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
225 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN,
226 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
227 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
228 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
229 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
230 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
231 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
232 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
233 },
234 [DR_ACTION_STATE_PUSH_VLAN] = {
235 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
236 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
237 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
238 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
239 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN,
240 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
241 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
242 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
243 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
244 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
245 },
246 [DR_ACTION_STATE_NON_TERM] = {
247 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
248 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
249 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
250 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
251 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
252 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
253 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
254 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
255 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
256 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
257 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
258 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
259 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
260 },
261 [DR_ACTION_STATE_ASO] = {
262 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
263 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
264 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
265 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
266 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO,
267 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
268 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
269 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
270 },
271 [DR_ACTION_STATE_TERM] = {
272 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
273 },
274 },
275 [DR_ACTION_DOMAIN_FDB_INGRESS] = {
276 [DR_ACTION_STATE_NO_ACTION] = {
277 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
278 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
279 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
280 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
281 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
282 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP,
283 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP,
284 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
285 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
286 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
287 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
288 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
289 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
290 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
291 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
292 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
293 },
294 [DR_ACTION_STATE_DECAP] = {
295 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
296 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
297 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
298 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP,
299 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
300 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
301 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
302 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
303 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
304 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
305 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
306 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
307 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
308 },
309 [DR_ACTION_STATE_ENCAP] = {
310 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
311 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
312 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
313 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
314 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
315 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
316 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP,
317 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
318 },
319 [DR_ACTION_STATE_MODIFY_HDR] = {
320 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
321 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
322 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
323 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
324 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
325 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
326 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
327 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
328 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
329 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
330 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
331 },
332 [DR_ACTION_STATE_POP_VLAN] = {
333 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
334 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
335 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
336 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
337 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
338 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN,
339 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
340 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
341 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
342 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
343 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
344 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
345 },
346 [DR_ACTION_STATE_PUSH_VLAN] = {
347 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
348 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
349 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
350 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
351 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
352 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN,
353 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
354 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
355 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
356 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
357 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
358 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
359 },
360 [DR_ACTION_STATE_NON_TERM] = {
361 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
362 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
363 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
364 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
365 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
366 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP,
367 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP,
368 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
369 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
370 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
371 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
372 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
373 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
374 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
375 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
376 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
377 },
378 [DR_ACTION_STATE_ASO] = {
379 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
380 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
381 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
382 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
383 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO,
384 },
385 [DR_ACTION_STATE_TERM] = {
386 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
387 },
388 },
389 [DR_ACTION_DOMAIN_FDB_EGRESS] = {
390 [DR_ACTION_STATE_NO_ACTION] = {
391 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
392 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
393 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
394 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
395 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
396 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
397 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
398 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
399 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
400 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
401 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
402 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
403 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
404 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
405 },
406 [DR_ACTION_STATE_DECAP] = {
407 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
408 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
409 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
410 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP,
411 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
412 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
413 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
414 },
415 [DR_ACTION_STATE_ENCAP] = {
416 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
417 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
418 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
419 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP,
420 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
421 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
422 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
423 },
424 [DR_ACTION_STATE_MODIFY_HDR] = {
425 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
426 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
427 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
428 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
429 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
430 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
431 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
432 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
433 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
434 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
435 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
436 },
437 [DR_ACTION_STATE_POP_VLAN] = {
438 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
439 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
440 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
441 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN,
442 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
443 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
444 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
445 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
446 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
447 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
448 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
449 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
450 },
451 [DR_ACTION_STATE_PUSH_VLAN] = {
452 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
453 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
454 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
455 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
456 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
457 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN,
458 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
459 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
460 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
461 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
462 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
463 },
464 [DR_ACTION_STATE_NON_TERM] = {
465 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
466 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
467 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
468 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
469 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
470 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
471 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
472 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
473 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
474 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
475 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
476 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
477 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
478 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
479 },
480 [DR_ACTION_STATE_ASO] = {
481 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
482 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
483 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
484 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
485 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
486 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
487 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
488 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
489 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO,
490 },
491 [DR_ACTION_STATE_TERM] = {
492 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
493 },
494 },
495 };
496
497 static int
dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type,enum mlx5dr_action_type * action_type)498 dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type,
499 enum mlx5dr_action_type *action_type)
500 {
501 switch (reformat_type) {
502 case DR_ACTION_REFORMAT_TYP_TNL_L2_TO_L2:
503 *action_type = DR_ACTION_TYP_TNL_L2_TO_L2;
504 break;
505 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L2:
506 *action_type = DR_ACTION_TYP_L2_TO_TNL_L2;
507 break;
508 case DR_ACTION_REFORMAT_TYP_TNL_L3_TO_L2:
509 *action_type = DR_ACTION_TYP_TNL_L3_TO_L2;
510 break;
511 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L3:
512 *action_type = DR_ACTION_TYP_L2_TO_TNL_L3;
513 break;
514 case DR_ACTION_REFORMAT_TYP_INSERT_HDR:
515 *action_type = DR_ACTION_TYP_INSERT_HDR;
516 break;
517 case DR_ACTION_REFORMAT_TYP_REMOVE_HDR:
518 *action_type = DR_ACTION_TYP_REMOVE_HDR;
519 break;
520 default:
521 return -EINVAL;
522 }
523
524 return 0;
525 }
526
527 /* Apply the actions on the rule STE array starting from the last_ste.
528 * Actions might require more than one STE, new_num_stes will return
529 * the new size of the STEs array, rule with actions.
530 */
dr_actions_apply(struct mlx5dr_domain * dmn,enum mlx5dr_domain_nic_type nic_type,u8 * action_type_set,u8 * last_ste,struct mlx5dr_ste_actions_attr * attr,u32 * new_num_stes)531 static void dr_actions_apply(struct mlx5dr_domain *dmn,
532 enum mlx5dr_domain_nic_type nic_type,
533 u8 *action_type_set,
534 u8 *last_ste,
535 struct mlx5dr_ste_actions_attr *attr,
536 u32 *new_num_stes)
537 {
538 struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx;
539 u32 added_stes = 0;
540
541 if (nic_type == DR_DOMAIN_NIC_TYPE_RX)
542 mlx5dr_ste_set_actions_rx(ste_ctx, dmn, action_type_set,
543 last_ste, attr, &added_stes);
544 else
545 mlx5dr_ste_set_actions_tx(ste_ctx, dmn, action_type_set,
546 last_ste, attr, &added_stes);
547
548 *new_num_stes += added_stes;
549 }
550
551 static enum dr_action_domain
dr_action_get_action_domain(enum mlx5dr_domain_type domain,enum mlx5dr_domain_nic_type nic_type)552 dr_action_get_action_domain(enum mlx5dr_domain_type domain,
553 enum mlx5dr_domain_nic_type nic_type)
554 {
555 switch (domain) {
556 case MLX5DR_DOMAIN_TYPE_NIC_RX:
557 return DR_ACTION_DOMAIN_NIC_INGRESS;
558 case MLX5DR_DOMAIN_TYPE_NIC_TX:
559 return DR_ACTION_DOMAIN_NIC_EGRESS;
560 case MLX5DR_DOMAIN_TYPE_FDB:
561 if (nic_type == DR_DOMAIN_NIC_TYPE_RX)
562 return DR_ACTION_DOMAIN_FDB_INGRESS;
563 return DR_ACTION_DOMAIN_FDB_EGRESS;
564 default:
565 WARN_ON(true);
566 return DR_ACTION_DOMAIN_MAX;
567 }
568 }
569
570 static
dr_action_validate_and_get_next_state(enum dr_action_domain action_domain,u32 action_type,u32 * state)571 int dr_action_validate_and_get_next_state(enum dr_action_domain action_domain,
572 u32 action_type,
573 u32 *state)
574 {
575 u32 cur_state = *state;
576
577 /* Check action state machine is valid */
578 *state = next_action_state[action_domain][cur_state][action_type];
579
580 if (*state == DR_ACTION_STATE_ERR)
581 return -EOPNOTSUPP;
582
583 return 0;
584 }
585
dr_action_handle_cs_recalc(struct mlx5dr_domain * dmn,struct mlx5dr_action * dest_action,u64 * final_icm_addr)586 static int dr_action_handle_cs_recalc(struct mlx5dr_domain *dmn,
587 struct mlx5dr_action *dest_action,
588 u64 *final_icm_addr)
589 {
590 int ret;
591
592 switch (dest_action->action_type) {
593 case DR_ACTION_TYP_FT:
594 /* Allow destination flow table only if table is a terminating
595 * table, since there is an *assumption* that in such case FW
596 * will recalculate the CS.
597 */
598 if (dest_action->dest_tbl->is_fw_tbl) {
599 *final_icm_addr = dest_action->dest_tbl->fw_tbl.rx_icm_addr;
600 } else {
601 mlx5dr_dbg(dmn,
602 "Destination FT should be terminating when modify TTL is used\n");
603 return -EINVAL;
604 }
605 break;
606
607 case DR_ACTION_TYP_VPORT:
608 /* If destination is vport we will get the FW flow table
609 * that recalculates the CS and forwards to the vport.
610 */
611 ret = mlx5dr_domain_get_recalc_cs_ft_addr(dest_action->vport->dmn,
612 dest_action->vport->caps->num,
613 final_icm_addr);
614 if (ret) {
615 mlx5dr_err(dmn, "Failed to get FW cs recalc flow table\n");
616 return ret;
617 }
618 break;
619
620 default:
621 break;
622 }
623
624 return 0;
625 }
626
dr_action_modify_ttl_adjust(struct mlx5dr_domain * dmn,struct mlx5dr_ste_actions_attr * attr,bool rx_rule,bool * recalc_cs_required)627 static void dr_action_modify_ttl_adjust(struct mlx5dr_domain *dmn,
628 struct mlx5dr_ste_actions_attr *attr,
629 bool rx_rule,
630 bool *recalc_cs_required)
631 {
632 *recalc_cs_required = false;
633
634 /* if device supports csum recalculation - no adjustment needed */
635 if (mlx5dr_ste_supp_ttl_cs_recalc(&dmn->info.caps))
636 return;
637
638 /* no adjustment needed on TX rules */
639 if (!rx_rule)
640 return;
641
642 if (!MLX5_CAP_ESW_FLOWTABLE(dmn->mdev, fdb_ipv4_ttl_modify)) {
643 /* Ignore the modify TTL action.
644 * It is always kept as last HW action.
645 */
646 attr->modify_actions--;
647 return;
648 }
649
650 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB)
651 /* Due to a HW bug on some devices, modifying TTL on RX flows
652 * will cause an incorrect checksum calculation. In such cases
653 * we will use a FW table to recalculate the checksum.
654 */
655 *recalc_cs_required = true;
656 }
657
dr_action_print_sequence(struct mlx5dr_domain * dmn,struct mlx5dr_action * actions[],int last_idx)658 static void dr_action_print_sequence(struct mlx5dr_domain *dmn,
659 struct mlx5dr_action *actions[],
660 int last_idx)
661 {
662 int i;
663
664 for (i = 0; i <= last_idx; i++)
665 mlx5dr_err(dmn, "< %s (%d) > ",
666 dr_action_id_to_str(actions[i]->action_type),
667 actions[i]->action_type);
668 }
669
dr_action_get_dest_fw_tbl_addr(struct mlx5dr_matcher * matcher,struct mlx5dr_action_dest_tbl * dest_tbl,bool is_rx_rule,u64 * final_icm_addr)670 static int dr_action_get_dest_fw_tbl_addr(struct mlx5dr_matcher *matcher,
671 struct mlx5dr_action_dest_tbl *dest_tbl,
672 bool is_rx_rule,
673 u64 *final_icm_addr)
674 {
675 struct mlx5dr_cmd_query_flow_table_details output;
676 struct mlx5dr_domain *dmn = matcher->tbl->dmn;
677 int ret;
678
679 if (!dest_tbl->fw_tbl.rx_icm_addr) {
680 ret = mlx5dr_cmd_query_flow_table(dmn->mdev,
681 dest_tbl->fw_tbl.type,
682 dest_tbl->fw_tbl.id,
683 &output);
684 if (ret) {
685 mlx5dr_err(dmn,
686 "Failed mlx5_cmd_query_flow_table ret: %d\n",
687 ret);
688 return ret;
689 }
690
691 dest_tbl->fw_tbl.tx_icm_addr = output.sw_owner_icm_root_1;
692 dest_tbl->fw_tbl.rx_icm_addr = output.sw_owner_icm_root_0;
693 }
694
695 *final_icm_addr = is_rx_rule ? dest_tbl->fw_tbl.rx_icm_addr :
696 dest_tbl->fw_tbl.tx_icm_addr;
697 return 0;
698 }
699
dr_action_get_dest_sw_tbl_addr(struct mlx5dr_matcher * matcher,struct mlx5dr_action_dest_tbl * dest_tbl,bool is_rx_rule,u64 * final_icm_addr)700 static int dr_action_get_dest_sw_tbl_addr(struct mlx5dr_matcher *matcher,
701 struct mlx5dr_action_dest_tbl *dest_tbl,
702 bool is_rx_rule,
703 u64 *final_icm_addr)
704 {
705 struct mlx5dr_domain *dmn = matcher->tbl->dmn;
706 struct mlx5dr_icm_chunk *chunk;
707
708 if (dest_tbl->tbl->dmn != dmn) {
709 mlx5dr_err(dmn,
710 "Destination table belongs to a different domain\n");
711 return -EINVAL;
712 }
713
714 if (dest_tbl->tbl->level <= matcher->tbl->level) {
715 mlx5_core_dbg_once(dmn->mdev,
716 "Connecting table to a lower/same level destination table\n");
717 mlx5dr_dbg(dmn,
718 "Connecting table at level %d to a destination table at level %d\n",
719 matcher->tbl->level,
720 dest_tbl->tbl->level);
721 }
722
723 chunk = is_rx_rule ? dest_tbl->tbl->rx.s_anchor->chunk :
724 dest_tbl->tbl->tx.s_anchor->chunk;
725
726 *final_icm_addr = mlx5dr_icm_pool_get_chunk_icm_addr(chunk);
727 return 0;
728 }
729
dr_action_get_dest_tbl_addr(struct mlx5dr_matcher * matcher,struct mlx5dr_action_dest_tbl * dest_tbl,bool is_rx_rule,u64 * final_icm_addr)730 static int dr_action_get_dest_tbl_addr(struct mlx5dr_matcher *matcher,
731 struct mlx5dr_action_dest_tbl *dest_tbl,
732 bool is_rx_rule,
733 u64 *final_icm_addr)
734 {
735 if (dest_tbl->is_fw_tbl)
736 return dr_action_get_dest_fw_tbl_addr(matcher,
737 dest_tbl,
738 is_rx_rule,
739 final_icm_addr);
740
741 return dr_action_get_dest_sw_tbl_addr(matcher,
742 dest_tbl,
743 is_rx_rule,
744 final_icm_addr);
745 }
746
747 #define WITH_VLAN_NUM_HW_ACTIONS 6
748
mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher * matcher,struct mlx5dr_matcher_rx_tx * nic_matcher,struct mlx5dr_action * actions[],u32 num_actions,u8 * ste_arr,u32 * new_hw_ste_arr_sz)749 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher,
750 struct mlx5dr_matcher_rx_tx *nic_matcher,
751 struct mlx5dr_action *actions[],
752 u32 num_actions,
753 u8 *ste_arr,
754 u32 *new_hw_ste_arr_sz)
755 {
756 struct mlx5dr_domain_rx_tx *nic_dmn = nic_matcher->nic_tbl->nic_dmn;
757 bool rx_rule = nic_dmn->type == DR_DOMAIN_NIC_TYPE_RX;
758 struct mlx5dr_domain *dmn = matcher->tbl->dmn;
759 u8 action_type_set[DR_ACTION_TYP_MAX] = {};
760 struct mlx5dr_ste_actions_attr attr = {};
761 struct mlx5dr_action *dest_action = NULL;
762 u32 state = DR_ACTION_STATE_NO_ACTION;
763 enum dr_action_domain action_domain;
764 bool recalc_cs_required = false;
765 u8 *last_ste;
766 int i, ret;
767
768 attr.gvmi = dmn->info.caps.gvmi;
769 attr.hit_gvmi = dmn->info.caps.gvmi;
770 attr.final_icm_addr = nic_dmn->default_icm_addr;
771 action_domain = dr_action_get_action_domain(dmn->type, nic_dmn->type);
772
773 for (i = 0; i < num_actions; i++) {
774 struct mlx5dr_action *action;
775 int max_actions_type = 1;
776 u32 action_type;
777
778 action = actions[i];
779 action_type = action->action_type;
780
781 switch (action_type) {
782 case DR_ACTION_TYP_DROP:
783 attr.final_icm_addr = nic_dmn->drop_icm_addr;
784 attr.hit_gvmi = nic_dmn->drop_icm_addr >> 48;
785 break;
786 case DR_ACTION_TYP_FT:
787 dest_action = action;
788 ret = dr_action_get_dest_tbl_addr(matcher, action->dest_tbl,
789 rx_rule, &attr.final_icm_addr);
790 if (ret)
791 return ret;
792 break;
793 case DR_ACTION_TYP_RANGE:
794 ret = dr_action_get_dest_tbl_addr(matcher,
795 action->range->hit_tbl_action->dest_tbl,
796 rx_rule, &attr.final_icm_addr);
797 if (ret)
798 return ret;
799
800 ret = dr_action_get_dest_tbl_addr(matcher,
801 action->range->miss_tbl_action->dest_tbl,
802 rx_rule, &attr.range.miss_icm_addr);
803 if (ret)
804 return ret;
805
806 attr.range.definer_id = action->range->definer_id;
807 attr.range.min = action->range->min;
808 attr.range.max = action->range->max;
809 break;
810 case DR_ACTION_TYP_QP:
811 mlx5dr_info(dmn, "Domain doesn't support QP\n");
812 return -EOPNOTSUPP;
813 case DR_ACTION_TYP_CTR:
814 attr.ctr_id = action->ctr->ctr_id +
815 action->ctr->offset;
816 break;
817 case DR_ACTION_TYP_TAG:
818 attr.flow_tag = action->flow_tag->flow_tag;
819 break;
820 case DR_ACTION_TYP_TNL_L2_TO_L2:
821 break;
822 case DR_ACTION_TYP_TNL_L3_TO_L2:
823 if (action->rewrite->ptrn && action->rewrite->arg) {
824 attr.decap_index = mlx5dr_arg_get_obj_id(action->rewrite->arg);
825 attr.decap_actions = action->rewrite->ptrn->num_of_actions;
826 attr.decap_pat_idx = action->rewrite->ptrn->index;
827 } else {
828 attr.decap_index = action->rewrite->index;
829 attr.decap_actions = action->rewrite->num_of_actions;
830 attr.decap_with_vlan =
831 attr.decap_actions == WITH_VLAN_NUM_HW_ACTIONS;
832 attr.decap_pat_idx = MLX5DR_INVALID_PATTERN_INDEX;
833 }
834 break;
835 case DR_ACTION_TYP_MODIFY_HDR:
836 if (action->rewrite->single_action_opt) {
837 attr.modify_actions = action->rewrite->num_of_actions;
838 attr.single_modify_action = action->rewrite->data;
839 } else {
840 if (action->rewrite->ptrn && action->rewrite->arg) {
841 attr.modify_index =
842 mlx5dr_arg_get_obj_id(action->rewrite->arg);
843 attr.modify_actions = action->rewrite->ptrn->num_of_actions;
844 attr.modify_pat_idx = action->rewrite->ptrn->index;
845 } else {
846 attr.modify_index = action->rewrite->index;
847 attr.modify_actions = action->rewrite->num_of_actions;
848 attr.modify_pat_idx = MLX5DR_INVALID_PATTERN_INDEX;
849 }
850 }
851 if (action->rewrite->modify_ttl)
852 dr_action_modify_ttl_adjust(dmn, &attr, rx_rule,
853 &recalc_cs_required);
854 break;
855 case DR_ACTION_TYP_L2_TO_TNL_L2:
856 case DR_ACTION_TYP_L2_TO_TNL_L3:
857 if (rx_rule &&
858 !(dmn->ste_ctx->actions_caps & DR_STE_CTX_ACTION_CAP_RX_ENCAP)) {
859 mlx5dr_info(dmn, "Device doesn't support Encap on RX\n");
860 return -EOPNOTSUPP;
861 }
862 attr.reformat.size = action->reformat->size;
863 attr.reformat.id = action->reformat->id;
864 break;
865 case DR_ACTION_TYP_SAMPLER:
866 attr.final_icm_addr = rx_rule ? action->sampler->rx_icm_addr :
867 action->sampler->tx_icm_addr;
868 break;
869 case DR_ACTION_TYP_VPORT:
870 if (unlikely(rx_rule && action->vport->caps->num == MLX5_VPORT_UPLINK)) {
871 /* can't go to uplink on RX rule - dropping instead */
872 attr.final_icm_addr = nic_dmn->drop_icm_addr;
873 attr.hit_gvmi = nic_dmn->drop_icm_addr >> 48;
874 } else {
875 attr.hit_gvmi = action->vport->caps->vhca_gvmi;
876 dest_action = action;
877 attr.final_icm_addr = rx_rule ?
878 action->vport->caps->icm_address_rx :
879 action->vport->caps->icm_address_tx;
880 }
881 break;
882 case DR_ACTION_TYP_POP_VLAN:
883 if (!rx_rule && !(dmn->ste_ctx->actions_caps &
884 DR_STE_CTX_ACTION_CAP_TX_POP)) {
885 mlx5dr_dbg(dmn, "Device doesn't support POP VLAN action on TX\n");
886 return -EOPNOTSUPP;
887 }
888
889 max_actions_type = MLX5DR_MAX_VLANS;
890 attr.vlans.count++;
891 break;
892 case DR_ACTION_TYP_PUSH_VLAN:
893 if (rx_rule && !(dmn->ste_ctx->actions_caps &
894 DR_STE_CTX_ACTION_CAP_RX_PUSH)) {
895 mlx5dr_dbg(dmn, "Device doesn't support PUSH VLAN action on RX\n");
896 return -EOPNOTSUPP;
897 }
898
899 max_actions_type = MLX5DR_MAX_VLANS;
900 if (attr.vlans.count == MLX5DR_MAX_VLANS) {
901 mlx5dr_dbg(dmn, "Max VLAN push/pop count exceeded\n");
902 return -EINVAL;
903 }
904
905 attr.vlans.headers[attr.vlans.count++] = action->push_vlan->vlan_hdr;
906 break;
907 case DR_ACTION_TYP_INSERT_HDR:
908 case DR_ACTION_TYP_REMOVE_HDR:
909 attr.reformat.size = action->reformat->size;
910 attr.reformat.id = action->reformat->id;
911 attr.reformat.param_0 = action->reformat->param_0;
912 attr.reformat.param_1 = action->reformat->param_1;
913 break;
914 case DR_ACTION_TYP_ASO_FLOW_METER:
915 attr.aso_flow_meter.obj_id = action->aso->obj_id;
916 attr.aso_flow_meter.offset = action->aso->offset;
917 attr.aso_flow_meter.dest_reg_id = action->aso->dest_reg_id;
918 attr.aso_flow_meter.init_color = action->aso->init_color;
919 break;
920 default:
921 mlx5dr_err(dmn, "Unsupported action type %d\n", action_type);
922 return -EINVAL;
923 }
924
925 /* Check action duplication */
926 if (++action_type_set[action_type] > max_actions_type) {
927 mlx5dr_err(dmn, "Action type %d supports only max %d time(s)\n",
928 action_type, max_actions_type);
929 return -EINVAL;
930 }
931
932 /* Check action state machine is valid */
933 if (dr_action_validate_and_get_next_state(action_domain,
934 action_type,
935 &state)) {
936 mlx5dr_err(dmn, "Invalid action (gvmi: %d, is_rx: %d) sequence provided:",
937 attr.gvmi, rx_rule);
938 dr_action_print_sequence(dmn, actions, i);
939 return -EOPNOTSUPP;
940 }
941 }
942
943 *new_hw_ste_arr_sz = nic_matcher->num_of_builders;
944 last_ste = ste_arr + DR_STE_SIZE * (nic_matcher->num_of_builders - 1);
945
946 if (recalc_cs_required && dest_action) {
947 ret = dr_action_handle_cs_recalc(dmn, dest_action, &attr.final_icm_addr);
948 if (ret) {
949 mlx5dr_err(dmn,
950 "Failed to handle checksum recalculation err %d\n",
951 ret);
952 return ret;
953 }
954 }
955
956 dr_actions_apply(dmn,
957 nic_dmn->type,
958 action_type_set,
959 last_ste,
960 &attr,
961 new_hw_ste_arr_sz);
962
963 return 0;
964 }
965
966 static unsigned int action_size[DR_ACTION_TYP_MAX] = {
967 [DR_ACTION_TYP_TNL_L2_TO_L2] = sizeof(struct mlx5dr_action_reformat),
968 [DR_ACTION_TYP_L2_TO_TNL_L2] = sizeof(struct mlx5dr_action_reformat),
969 [DR_ACTION_TYP_TNL_L3_TO_L2] = sizeof(struct mlx5dr_action_rewrite),
970 [DR_ACTION_TYP_L2_TO_TNL_L3] = sizeof(struct mlx5dr_action_reformat),
971 [DR_ACTION_TYP_FT] = sizeof(struct mlx5dr_action_dest_tbl),
972 [DR_ACTION_TYP_CTR] = sizeof(struct mlx5dr_action_ctr),
973 [DR_ACTION_TYP_TAG] = sizeof(struct mlx5dr_action_flow_tag),
974 [DR_ACTION_TYP_MODIFY_HDR] = sizeof(struct mlx5dr_action_rewrite),
975 [DR_ACTION_TYP_VPORT] = sizeof(struct mlx5dr_action_vport),
976 [DR_ACTION_TYP_PUSH_VLAN] = sizeof(struct mlx5dr_action_push_vlan),
977 [DR_ACTION_TYP_INSERT_HDR] = sizeof(struct mlx5dr_action_reformat),
978 [DR_ACTION_TYP_REMOVE_HDR] = sizeof(struct mlx5dr_action_reformat),
979 [DR_ACTION_TYP_SAMPLER] = sizeof(struct mlx5dr_action_sampler),
980 [DR_ACTION_TYP_ASO_FLOW_METER] = sizeof(struct mlx5dr_action_aso_flow_meter),
981 [DR_ACTION_TYP_RANGE] = sizeof(struct mlx5dr_action_range),
982 };
983
984 static struct mlx5dr_action *
dr_action_create_generic(enum mlx5dr_action_type action_type)985 dr_action_create_generic(enum mlx5dr_action_type action_type)
986 {
987 struct mlx5dr_action *action;
988 int extra_size;
989
990 if (action_type < DR_ACTION_TYP_MAX)
991 extra_size = action_size[action_type];
992 else
993 return NULL;
994
995 action = kzalloc(sizeof(*action) + extra_size, GFP_KERNEL);
996 if (!action)
997 return NULL;
998
999 action->action_type = action_type;
1000 refcount_set(&action->refcount, 1);
1001 action->data = action + 1;
1002
1003 return action;
1004 }
1005
mlx5dr_action_create_drop(void)1006 struct mlx5dr_action *mlx5dr_action_create_drop(void)
1007 {
1008 return dr_action_create_generic(DR_ACTION_TYP_DROP);
1009 }
1010
1011 struct mlx5dr_action *
mlx5dr_action_create_dest_table_num(struct mlx5dr_domain * dmn,u32 table_num)1012 mlx5dr_action_create_dest_table_num(struct mlx5dr_domain *dmn, u32 table_num)
1013 {
1014 struct mlx5dr_action *action;
1015
1016 action = dr_action_create_generic(DR_ACTION_TYP_FT);
1017 if (!action)
1018 return NULL;
1019
1020 action->dest_tbl->is_fw_tbl = true;
1021 action->dest_tbl->fw_tbl.dmn = dmn;
1022 action->dest_tbl->fw_tbl.id = table_num;
1023 action->dest_tbl->fw_tbl.type = FS_FT_FDB;
1024 refcount_inc(&dmn->refcount);
1025
1026 return action;
1027 }
1028
1029 struct mlx5dr_action *
mlx5dr_action_create_dest_table(struct mlx5dr_table * tbl)1030 mlx5dr_action_create_dest_table(struct mlx5dr_table *tbl)
1031 {
1032 struct mlx5dr_action *action;
1033
1034 refcount_inc(&tbl->refcount);
1035
1036 action = dr_action_create_generic(DR_ACTION_TYP_FT);
1037 if (!action)
1038 goto dec_ref;
1039
1040 action->dest_tbl->tbl = tbl;
1041
1042 return action;
1043
1044 dec_ref:
1045 refcount_dec(&tbl->refcount);
1046 return NULL;
1047 }
1048
dr_action_range_definer_fill(u16 * format_id,u8 * dw_selectors,u8 * byte_selectors,u8 * match_mask)1049 static void dr_action_range_definer_fill(u16 *format_id,
1050 u8 *dw_selectors,
1051 u8 *byte_selectors,
1052 u8 *match_mask)
1053 {
1054 int i;
1055
1056 *format_id = MLX5_IFC_DEFINER_FORMAT_ID_SELECT;
1057
1058 dw_selectors[0] = MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN / 4;
1059
1060 for (i = 1; i < MLX5_IFC_DEFINER_DW_SELECTORS_NUM; i++)
1061 dw_selectors[i] = MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED;
1062
1063 for (i = 0; i < MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM; i++)
1064 byte_selectors[i] = MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED;
1065
1066 MLX5_SET(match_definer_match_mask, match_mask,
1067 match_dw_0, 0xffffUL << 16);
1068 }
1069
dr_action_create_range_definer(struct mlx5dr_action * action)1070 static int dr_action_create_range_definer(struct mlx5dr_action *action)
1071 {
1072 u8 match_mask[MLX5_FLD_SZ_BYTES(match_definer, match_mask)] = {};
1073 u8 byte_selectors[MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM] = {};
1074 u8 dw_selectors[MLX5_IFC_DEFINER_DW_SELECTORS_NUM] = {};
1075 struct mlx5dr_domain *dmn = action->range->dmn;
1076 u32 definer_id;
1077 u16 format_id;
1078 int ret;
1079
1080 dr_action_range_definer_fill(&format_id,
1081 dw_selectors,
1082 byte_selectors,
1083 match_mask);
1084
1085 ret = mlx5dr_definer_get(dmn, format_id,
1086 dw_selectors, byte_selectors,
1087 match_mask, &definer_id);
1088 if (ret)
1089 return ret;
1090
1091 action->range->definer_id = definer_id;
1092 return 0;
1093 }
1094
dr_action_destroy_range_definer(struct mlx5dr_action * action)1095 static void dr_action_destroy_range_definer(struct mlx5dr_action *action)
1096 {
1097 mlx5dr_definer_put(action->range->dmn, action->range->definer_id);
1098 }
1099
1100 struct mlx5dr_action *
mlx5dr_action_create_dest_match_range(struct mlx5dr_domain * dmn,u32 field,struct mlx5_flow_table * hit_ft,struct mlx5_flow_table * miss_ft,u32 min,u32 max)1101 mlx5dr_action_create_dest_match_range(struct mlx5dr_domain *dmn,
1102 u32 field,
1103 struct mlx5_flow_table *hit_ft,
1104 struct mlx5_flow_table *miss_ft,
1105 u32 min,
1106 u32 max)
1107 {
1108 struct mlx5dr_action *action;
1109 int ret;
1110
1111 if (!mlx5dr_supp_match_ranges(dmn->mdev)) {
1112 mlx5dr_dbg(dmn, "SELECT definer support is needed for match range\n");
1113 return NULL;
1114 }
1115
1116 if (field != MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN ||
1117 min > 0xffff || max > 0xffff) {
1118 mlx5dr_err(dmn, "Invalid match range parameters\n");
1119 return NULL;
1120 }
1121
1122 action = dr_action_create_generic(DR_ACTION_TYP_RANGE);
1123 if (!action)
1124 return NULL;
1125
1126 action->range->hit_tbl_action =
1127 mlx5dr_is_fw_table(hit_ft) ?
1128 mlx5dr_action_create_dest_flow_fw_table(dmn, hit_ft) :
1129 mlx5dr_action_create_dest_table(hit_ft->fs_dr_table.dr_table);
1130
1131 if (!action->range->hit_tbl_action)
1132 goto free_action;
1133
1134 action->range->miss_tbl_action =
1135 mlx5dr_is_fw_table(miss_ft) ?
1136 mlx5dr_action_create_dest_flow_fw_table(dmn, miss_ft) :
1137 mlx5dr_action_create_dest_table(miss_ft->fs_dr_table.dr_table);
1138
1139 if (!action->range->miss_tbl_action)
1140 goto free_hit_tbl_action;
1141
1142 action->range->min = min;
1143 action->range->max = max;
1144 action->range->dmn = dmn;
1145
1146 ret = dr_action_create_range_definer(action);
1147 if (ret)
1148 goto free_miss_tbl_action;
1149
1150 /* No need to increase refcount on domain for this action,
1151 * the hit/miss table actions will do it internally.
1152 */
1153
1154 return action;
1155
1156 free_miss_tbl_action:
1157 mlx5dr_action_destroy(action->range->miss_tbl_action);
1158 free_hit_tbl_action:
1159 mlx5dr_action_destroy(action->range->hit_tbl_action);
1160 free_action:
1161 kfree(action);
1162
1163 return NULL;
1164 }
1165
1166 struct mlx5dr_action *
mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain * dmn,struct mlx5dr_action_dest * dests,u32 num_of_dests,bool ignore_flow_level,u32 flow_source)1167 mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain *dmn,
1168 struct mlx5dr_action_dest *dests,
1169 u32 num_of_dests,
1170 bool ignore_flow_level,
1171 u32 flow_source)
1172 {
1173 struct mlx5dr_cmd_flow_destination_hw_info *hw_dests;
1174 struct mlx5dr_action **ref_actions;
1175 struct mlx5dr_action *action;
1176 bool reformat_req = false;
1177 u32 num_of_ref = 0;
1178 u32 ref_act_cnt;
1179 int ret;
1180 int i;
1181
1182 if (dmn->type != MLX5DR_DOMAIN_TYPE_FDB) {
1183 mlx5dr_err(dmn, "Multiple destination support is for FDB only\n");
1184 return NULL;
1185 }
1186
1187 hw_dests = kcalloc(num_of_dests, sizeof(*hw_dests), GFP_KERNEL);
1188 if (!hw_dests)
1189 return NULL;
1190
1191 if (unlikely(check_mul_overflow(num_of_dests, 2u, &ref_act_cnt)))
1192 goto free_hw_dests;
1193
1194 ref_actions = kcalloc(ref_act_cnt, sizeof(*ref_actions), GFP_KERNEL);
1195 if (!ref_actions)
1196 goto free_hw_dests;
1197
1198 for (i = 0; i < num_of_dests; i++) {
1199 struct mlx5dr_action *reformat_action = dests[i].reformat;
1200 struct mlx5dr_action *dest_action = dests[i].dest;
1201
1202 ref_actions[num_of_ref++] = dest_action;
1203
1204 switch (dest_action->action_type) {
1205 case DR_ACTION_TYP_VPORT:
1206 hw_dests[i].vport.flags = MLX5_FLOW_DEST_VPORT_VHCA_ID;
1207 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1208 hw_dests[i].vport.num = dest_action->vport->caps->num;
1209 hw_dests[i].vport.vhca_id = dest_action->vport->caps->vhca_gvmi;
1210 if (reformat_action) {
1211 reformat_req = true;
1212 hw_dests[i].vport.reformat_id =
1213 reformat_action->reformat->id;
1214 ref_actions[num_of_ref++] = reformat_action;
1215 hw_dests[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
1216 }
1217 break;
1218
1219 case DR_ACTION_TYP_FT:
1220 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1221 if (dest_action->dest_tbl->is_fw_tbl)
1222 hw_dests[i].ft_id = dest_action->dest_tbl->fw_tbl.id;
1223 else
1224 hw_dests[i].ft_id = dest_action->dest_tbl->tbl->table_id;
1225 break;
1226
1227 default:
1228 mlx5dr_dbg(dmn, "Invalid multiple destinations action\n");
1229 goto free_ref_actions;
1230 }
1231 }
1232
1233 action = dr_action_create_generic(DR_ACTION_TYP_FT);
1234 if (!action)
1235 goto free_ref_actions;
1236
1237 ret = mlx5dr_fw_create_md_tbl(dmn,
1238 hw_dests,
1239 num_of_dests,
1240 reformat_req,
1241 &action->dest_tbl->fw_tbl.id,
1242 &action->dest_tbl->fw_tbl.group_id,
1243 ignore_flow_level,
1244 flow_source);
1245 if (ret)
1246 goto free_action;
1247
1248 refcount_inc(&dmn->refcount);
1249
1250 for (i = 0; i < num_of_ref; i++)
1251 refcount_inc(&ref_actions[i]->refcount);
1252
1253 action->dest_tbl->is_fw_tbl = true;
1254 action->dest_tbl->fw_tbl.dmn = dmn;
1255 action->dest_tbl->fw_tbl.type = FS_FT_FDB;
1256 action->dest_tbl->fw_tbl.ref_actions = ref_actions;
1257 action->dest_tbl->fw_tbl.num_of_ref_actions = num_of_ref;
1258
1259 kfree(hw_dests);
1260
1261 return action;
1262
1263 free_action:
1264 kfree(action);
1265 free_ref_actions:
1266 kfree(ref_actions);
1267 free_hw_dests:
1268 kfree(hw_dests);
1269 return NULL;
1270 }
1271
1272 struct mlx5dr_action *
mlx5dr_action_create_dest_flow_fw_table(struct mlx5dr_domain * dmn,struct mlx5_flow_table * ft)1273 mlx5dr_action_create_dest_flow_fw_table(struct mlx5dr_domain *dmn,
1274 struct mlx5_flow_table *ft)
1275 {
1276 struct mlx5dr_action *action;
1277
1278 action = dr_action_create_generic(DR_ACTION_TYP_FT);
1279 if (!action)
1280 return NULL;
1281
1282 action->dest_tbl->is_fw_tbl = 1;
1283 action->dest_tbl->fw_tbl.type = ft->type;
1284 action->dest_tbl->fw_tbl.id = ft->id;
1285 action->dest_tbl->fw_tbl.dmn = dmn;
1286
1287 refcount_inc(&dmn->refcount);
1288
1289 return action;
1290 }
1291
1292 struct mlx5dr_action *
mlx5dr_action_create_flow_counter(u32 counter_id)1293 mlx5dr_action_create_flow_counter(u32 counter_id)
1294 {
1295 struct mlx5dr_action *action;
1296
1297 action = dr_action_create_generic(DR_ACTION_TYP_CTR);
1298 if (!action)
1299 return NULL;
1300
1301 action->ctr->ctr_id = counter_id;
1302
1303 return action;
1304 }
1305
mlx5dr_action_create_tag(u32 tag_value)1306 struct mlx5dr_action *mlx5dr_action_create_tag(u32 tag_value)
1307 {
1308 struct mlx5dr_action *action;
1309
1310 action = dr_action_create_generic(DR_ACTION_TYP_TAG);
1311 if (!action)
1312 return NULL;
1313
1314 action->flow_tag->flow_tag = tag_value & 0xffffff;
1315
1316 return action;
1317 }
1318
1319 struct mlx5dr_action *
mlx5dr_action_create_flow_sampler(struct mlx5dr_domain * dmn,u32 sampler_id)1320 mlx5dr_action_create_flow_sampler(struct mlx5dr_domain *dmn, u32 sampler_id)
1321 {
1322 struct mlx5dr_action *action;
1323 u64 icm_rx, icm_tx;
1324 int ret;
1325
1326 ret = mlx5dr_cmd_query_flow_sampler(dmn->mdev, sampler_id,
1327 &icm_rx, &icm_tx);
1328 if (ret)
1329 return NULL;
1330
1331 action = dr_action_create_generic(DR_ACTION_TYP_SAMPLER);
1332 if (!action)
1333 return NULL;
1334
1335 action->sampler->dmn = dmn;
1336 action->sampler->sampler_id = sampler_id;
1337 action->sampler->rx_icm_addr = icm_rx;
1338 action->sampler->tx_icm_addr = icm_tx;
1339
1340 refcount_inc(&dmn->refcount);
1341 return action;
1342 }
1343
1344 static int
dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type,struct mlx5dr_domain * dmn,u8 reformat_param_0,u8 reformat_param_1,size_t data_sz,void * data)1345 dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type,
1346 struct mlx5dr_domain *dmn,
1347 u8 reformat_param_0,
1348 u8 reformat_param_1,
1349 size_t data_sz,
1350 void *data)
1351 {
1352 if (reformat_type == DR_ACTION_TYP_INSERT_HDR) {
1353 if ((!data && data_sz) || (data && !data_sz) ||
1354 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_insert_size) < data_sz ||
1355 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_insert_offset) < reformat_param_1) {
1356 mlx5dr_dbg(dmn, "Invalid reformat parameters for INSERT_HDR\n");
1357 goto out_err;
1358 }
1359 } else if (reformat_type == DR_ACTION_TYP_REMOVE_HDR) {
1360 if (data ||
1361 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_remove_size) < data_sz ||
1362 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_remove_offset) < reformat_param_1) {
1363 mlx5dr_dbg(dmn, "Invalid reformat parameters for REMOVE_HDR\n");
1364 goto out_err;
1365 }
1366 } else if (reformat_param_0 || reformat_param_1 ||
1367 reformat_type > DR_ACTION_TYP_REMOVE_HDR) {
1368 mlx5dr_dbg(dmn, "Invalid reformat parameters\n");
1369 goto out_err;
1370 }
1371
1372 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB)
1373 return 0;
1374
1375 if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX) {
1376 if (reformat_type != DR_ACTION_TYP_TNL_L2_TO_L2 &&
1377 reformat_type != DR_ACTION_TYP_TNL_L3_TO_L2) {
1378 mlx5dr_dbg(dmn, "Action reformat type not support on RX domain\n");
1379 goto out_err;
1380 }
1381 } else if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_TX) {
1382 if (reformat_type != DR_ACTION_TYP_L2_TO_TNL_L2 &&
1383 reformat_type != DR_ACTION_TYP_L2_TO_TNL_L3) {
1384 mlx5dr_dbg(dmn, "Action reformat type not support on TX domain\n");
1385 goto out_err;
1386 }
1387 }
1388
1389 return 0;
1390
1391 out_err:
1392 return -EINVAL;
1393 }
1394
1395 static int
dr_action_create_reformat_action(struct mlx5dr_domain * dmn,u8 reformat_param_0,u8 reformat_param_1,size_t data_sz,void * data,struct mlx5dr_action * action)1396 dr_action_create_reformat_action(struct mlx5dr_domain *dmn,
1397 u8 reformat_param_0, u8 reformat_param_1,
1398 size_t data_sz, void *data,
1399 struct mlx5dr_action *action)
1400 {
1401 u32 reformat_id;
1402 int ret;
1403
1404 switch (action->action_type) {
1405 case DR_ACTION_TYP_L2_TO_TNL_L2:
1406 case DR_ACTION_TYP_L2_TO_TNL_L3:
1407 {
1408 enum mlx5_reformat_ctx_type rt;
1409
1410 if (action->action_type == DR_ACTION_TYP_L2_TO_TNL_L2)
1411 rt = MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL;
1412 else
1413 rt = MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
1414
1415 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, rt, 0, 0,
1416 data_sz, data,
1417 &reformat_id);
1418 if (ret)
1419 return ret;
1420
1421 action->reformat->id = reformat_id;
1422 action->reformat->size = data_sz;
1423 return 0;
1424 }
1425 case DR_ACTION_TYP_TNL_L2_TO_L2:
1426 {
1427 return 0;
1428 }
1429 case DR_ACTION_TYP_TNL_L3_TO_L2:
1430 {
1431 u8 *hw_actions;
1432
1433 hw_actions = kzalloc(DR_ACTION_CACHE_LINE_SIZE, GFP_KERNEL);
1434 if (!hw_actions)
1435 return -ENOMEM;
1436
1437 ret = mlx5dr_ste_set_action_decap_l3_list(dmn->ste_ctx,
1438 data, data_sz,
1439 hw_actions,
1440 DR_ACTION_CACHE_LINE_SIZE,
1441 &action->rewrite->num_of_actions);
1442 if (ret) {
1443 mlx5dr_dbg(dmn, "Failed creating decap l3 action list\n");
1444 kfree(hw_actions);
1445 return ret;
1446 }
1447
1448 action->rewrite->data = hw_actions;
1449 action->rewrite->dmn = dmn;
1450
1451 ret = mlx5dr_ste_alloc_modify_hdr(action);
1452 if (ret) {
1453 mlx5dr_dbg(dmn, "Failed preparing reformat data\n");
1454 kfree(hw_actions);
1455 return ret;
1456 }
1457 return 0;
1458 }
1459 case DR_ACTION_TYP_INSERT_HDR:
1460 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev,
1461 MLX5_REFORMAT_TYPE_INSERT_HDR,
1462 reformat_param_0,
1463 reformat_param_1,
1464 data_sz, data,
1465 &reformat_id);
1466 if (ret)
1467 return ret;
1468
1469 action->reformat->id = reformat_id;
1470 action->reformat->size = data_sz;
1471 action->reformat->param_0 = reformat_param_0;
1472 action->reformat->param_1 = reformat_param_1;
1473 return 0;
1474 case DR_ACTION_TYP_REMOVE_HDR:
1475 action->reformat->id = 0;
1476 action->reformat->size = data_sz;
1477 action->reformat->param_0 = reformat_param_0;
1478 action->reformat->param_1 = reformat_param_1;
1479 return 0;
1480 default:
1481 mlx5dr_info(dmn, "Reformat type is not supported %d\n", action->action_type);
1482 return -EINVAL;
1483 }
1484 }
1485
1486 #define CVLAN_ETHERTYPE 0x8100
1487 #define SVLAN_ETHERTYPE 0x88a8
1488
mlx5dr_action_create_pop_vlan(void)1489 struct mlx5dr_action *mlx5dr_action_create_pop_vlan(void)
1490 {
1491 return dr_action_create_generic(DR_ACTION_TYP_POP_VLAN);
1492 }
1493
mlx5dr_action_create_push_vlan(struct mlx5dr_domain * dmn,__be32 vlan_hdr)1494 struct mlx5dr_action *mlx5dr_action_create_push_vlan(struct mlx5dr_domain *dmn,
1495 __be32 vlan_hdr)
1496 {
1497 u32 vlan_hdr_h = ntohl(vlan_hdr);
1498 u16 ethertype = vlan_hdr_h >> 16;
1499 struct mlx5dr_action *action;
1500
1501 if (ethertype != SVLAN_ETHERTYPE && ethertype != CVLAN_ETHERTYPE) {
1502 mlx5dr_dbg(dmn, "Invalid vlan ethertype\n");
1503 return NULL;
1504 }
1505
1506 action = dr_action_create_generic(DR_ACTION_TYP_PUSH_VLAN);
1507 if (!action)
1508 return NULL;
1509
1510 action->push_vlan->vlan_hdr = vlan_hdr_h;
1511 return action;
1512 }
1513
1514 struct mlx5dr_action *
mlx5dr_action_create_packet_reformat(struct mlx5dr_domain * dmn,enum mlx5dr_action_reformat_type reformat_type,u8 reformat_param_0,u8 reformat_param_1,size_t data_sz,void * data)1515 mlx5dr_action_create_packet_reformat(struct mlx5dr_domain *dmn,
1516 enum mlx5dr_action_reformat_type reformat_type,
1517 u8 reformat_param_0,
1518 u8 reformat_param_1,
1519 size_t data_sz,
1520 void *data)
1521 {
1522 enum mlx5dr_action_type action_type;
1523 struct mlx5dr_action *action;
1524 int ret;
1525
1526 refcount_inc(&dmn->refcount);
1527
1528 /* General checks */
1529 ret = dr_action_reformat_to_action_type(reformat_type, &action_type);
1530 if (ret) {
1531 mlx5dr_dbg(dmn, "Invalid reformat_type provided\n");
1532 goto dec_ref;
1533 }
1534
1535 ret = dr_action_verify_reformat_params(action_type, dmn,
1536 reformat_param_0, reformat_param_1,
1537 data_sz, data);
1538 if (ret)
1539 goto dec_ref;
1540
1541 action = dr_action_create_generic(action_type);
1542 if (!action)
1543 goto dec_ref;
1544
1545 action->reformat->dmn = dmn;
1546
1547 ret = dr_action_create_reformat_action(dmn,
1548 reformat_param_0,
1549 reformat_param_1,
1550 data_sz,
1551 data,
1552 action);
1553 if (ret) {
1554 mlx5dr_dbg(dmn, "Failed creating reformat action %d\n", ret);
1555 goto free_action;
1556 }
1557
1558 return action;
1559
1560 free_action:
1561 kfree(action);
1562 dec_ref:
1563 refcount_dec(&dmn->refcount);
1564 return NULL;
1565 }
1566
1567 static int
dr_action_modify_sw_to_hw_add(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct mlx5dr_ste_action_modify_field ** ret_hw_info)1568 dr_action_modify_sw_to_hw_add(struct mlx5dr_domain *dmn,
1569 __be64 *sw_action,
1570 __be64 *hw_action,
1571 const struct mlx5dr_ste_action_modify_field **ret_hw_info)
1572 {
1573 const struct mlx5dr_ste_action_modify_field *hw_action_info;
1574 u8 max_length;
1575 u16 sw_field;
1576 u32 data;
1577
1578 /* Get SW modify action data */
1579 sw_field = MLX5_GET(set_action_in, sw_action, field);
1580 data = MLX5_GET(set_action_in, sw_action, data);
1581
1582 /* Convert SW data to HW modify action format */
1583 hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field);
1584 if (!hw_action_info) {
1585 mlx5dr_dbg(dmn, "Modify add action invalid field given\n");
1586 return -EINVAL;
1587 }
1588
1589 max_length = hw_action_info->end - hw_action_info->start + 1;
1590
1591 mlx5dr_ste_set_action_add(dmn->ste_ctx,
1592 hw_action,
1593 hw_action_info->hw_field,
1594 hw_action_info->start,
1595 max_length,
1596 data);
1597
1598 *ret_hw_info = hw_action_info;
1599
1600 return 0;
1601 }
1602
1603 static int
dr_action_modify_sw_to_hw_set(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct mlx5dr_ste_action_modify_field ** ret_hw_info)1604 dr_action_modify_sw_to_hw_set(struct mlx5dr_domain *dmn,
1605 __be64 *sw_action,
1606 __be64 *hw_action,
1607 const struct mlx5dr_ste_action_modify_field **ret_hw_info)
1608 {
1609 const struct mlx5dr_ste_action_modify_field *hw_action_info;
1610 u8 offset, length, max_length;
1611 u16 sw_field;
1612 u32 data;
1613
1614 /* Get SW modify action data */
1615 length = MLX5_GET(set_action_in, sw_action, length);
1616 offset = MLX5_GET(set_action_in, sw_action, offset);
1617 sw_field = MLX5_GET(set_action_in, sw_action, field);
1618 data = MLX5_GET(set_action_in, sw_action, data);
1619
1620 /* Convert SW data to HW modify action format */
1621 hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field);
1622 if (!hw_action_info) {
1623 mlx5dr_dbg(dmn, "Modify set action invalid field given\n");
1624 return -EINVAL;
1625 }
1626
1627 /* PRM defines that length zero specific length of 32bits */
1628 length = length ? length : 32;
1629
1630 max_length = hw_action_info->end - hw_action_info->start + 1;
1631
1632 if (length + offset > max_length) {
1633 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n");
1634 return -EINVAL;
1635 }
1636
1637 mlx5dr_ste_set_action_set(dmn->ste_ctx,
1638 hw_action,
1639 hw_action_info->hw_field,
1640 hw_action_info->start + offset,
1641 length,
1642 data);
1643
1644 *ret_hw_info = hw_action_info;
1645
1646 return 0;
1647 }
1648
1649 static int
dr_action_modify_sw_to_hw_copy(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct mlx5dr_ste_action_modify_field ** ret_dst_hw_info,const struct mlx5dr_ste_action_modify_field ** ret_src_hw_info)1650 dr_action_modify_sw_to_hw_copy(struct mlx5dr_domain *dmn,
1651 __be64 *sw_action,
1652 __be64 *hw_action,
1653 const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info,
1654 const struct mlx5dr_ste_action_modify_field **ret_src_hw_info)
1655 {
1656 u8 src_offset, dst_offset, src_max_length, dst_max_length, length;
1657 const struct mlx5dr_ste_action_modify_field *hw_dst_action_info;
1658 const struct mlx5dr_ste_action_modify_field *hw_src_action_info;
1659 u16 src_field, dst_field;
1660
1661 /* Get SW modify action data */
1662 src_field = MLX5_GET(copy_action_in, sw_action, src_field);
1663 dst_field = MLX5_GET(copy_action_in, sw_action, dst_field);
1664 src_offset = MLX5_GET(copy_action_in, sw_action, src_offset);
1665 dst_offset = MLX5_GET(copy_action_in, sw_action, dst_offset);
1666 length = MLX5_GET(copy_action_in, sw_action, length);
1667
1668 /* Convert SW data to HW modify action format */
1669 hw_src_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, src_field);
1670 hw_dst_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, dst_field);
1671 if (!hw_src_action_info || !hw_dst_action_info) {
1672 mlx5dr_dbg(dmn, "Modify copy action invalid field given\n");
1673 return -EINVAL;
1674 }
1675
1676 /* PRM defines that length zero specific length of 32bits */
1677 length = length ? length : 32;
1678
1679 src_max_length = hw_src_action_info->end -
1680 hw_src_action_info->start + 1;
1681 dst_max_length = hw_dst_action_info->end -
1682 hw_dst_action_info->start + 1;
1683
1684 if (length + src_offset > src_max_length ||
1685 length + dst_offset > dst_max_length) {
1686 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n");
1687 return -EINVAL;
1688 }
1689
1690 mlx5dr_ste_set_action_copy(dmn->ste_ctx,
1691 hw_action,
1692 hw_dst_action_info->hw_field,
1693 hw_dst_action_info->start + dst_offset,
1694 length,
1695 hw_src_action_info->hw_field,
1696 hw_src_action_info->start + src_offset);
1697
1698 *ret_dst_hw_info = hw_dst_action_info;
1699 *ret_src_hw_info = hw_src_action_info;
1700
1701 return 0;
1702 }
1703
1704 static int
dr_action_modify_sw_to_hw(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct mlx5dr_ste_action_modify_field ** ret_dst_hw_info,const struct mlx5dr_ste_action_modify_field ** ret_src_hw_info)1705 dr_action_modify_sw_to_hw(struct mlx5dr_domain *dmn,
1706 __be64 *sw_action,
1707 __be64 *hw_action,
1708 const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info,
1709 const struct mlx5dr_ste_action_modify_field **ret_src_hw_info)
1710 {
1711 u8 action;
1712 int ret;
1713
1714 *hw_action = 0;
1715 *ret_src_hw_info = NULL;
1716
1717 /* Get SW modify action type */
1718 action = MLX5_GET(set_action_in, sw_action, action_type);
1719
1720 switch (action) {
1721 case MLX5_ACTION_TYPE_SET:
1722 ret = dr_action_modify_sw_to_hw_set(dmn, sw_action,
1723 hw_action,
1724 ret_dst_hw_info);
1725 break;
1726
1727 case MLX5_ACTION_TYPE_ADD:
1728 ret = dr_action_modify_sw_to_hw_add(dmn, sw_action,
1729 hw_action,
1730 ret_dst_hw_info);
1731 break;
1732
1733 case MLX5_ACTION_TYPE_COPY:
1734 ret = dr_action_modify_sw_to_hw_copy(dmn, sw_action,
1735 hw_action,
1736 ret_dst_hw_info,
1737 ret_src_hw_info);
1738 break;
1739
1740 default:
1741 mlx5dr_info(dmn, "Unsupported action_type for modify action\n");
1742 ret = -EOPNOTSUPP;
1743 }
1744
1745 return ret;
1746 }
1747
1748 static int
dr_action_modify_check_set_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1749 dr_action_modify_check_set_field_limitation(struct mlx5dr_action *action,
1750 const __be64 *sw_action)
1751 {
1752 u16 sw_field = MLX5_GET(set_action_in, sw_action, field);
1753 struct mlx5dr_domain *dmn = action->rewrite->dmn;
1754
1755 if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_A) {
1756 action->rewrite->allow_rx = 0;
1757 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) {
1758 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n",
1759 sw_field);
1760 return -EINVAL;
1761 }
1762 } else if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_B) {
1763 action->rewrite->allow_tx = 0;
1764 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) {
1765 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n",
1766 sw_field);
1767 return -EINVAL;
1768 }
1769 }
1770
1771 if (!action->rewrite->allow_rx && !action->rewrite->allow_tx) {
1772 mlx5dr_dbg(dmn, "Modify SET actions not supported on both RX and TX\n");
1773 return -EINVAL;
1774 }
1775
1776 return 0;
1777 }
1778
1779 static int
dr_action_modify_check_add_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1780 dr_action_modify_check_add_field_limitation(struct mlx5dr_action *action,
1781 const __be64 *sw_action)
1782 {
1783 u16 sw_field = MLX5_GET(set_action_in, sw_action, field);
1784 struct mlx5dr_domain *dmn = action->rewrite->dmn;
1785
1786 if (sw_field != MLX5_ACTION_IN_FIELD_OUT_IP_TTL &&
1787 sw_field != MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT &&
1788 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM &&
1789 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM) {
1790 mlx5dr_dbg(dmn, "Unsupported field %d for add action\n",
1791 sw_field);
1792 return -EINVAL;
1793 }
1794
1795 return 0;
1796 }
1797
1798 static int
dr_action_modify_check_copy_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1799 dr_action_modify_check_copy_field_limitation(struct mlx5dr_action *action,
1800 const __be64 *sw_action)
1801 {
1802 struct mlx5dr_domain *dmn = action->rewrite->dmn;
1803 u16 sw_fields[2];
1804 int i;
1805
1806 sw_fields[0] = MLX5_GET(copy_action_in, sw_action, src_field);
1807 sw_fields[1] = MLX5_GET(copy_action_in, sw_action, dst_field);
1808
1809 for (i = 0; i < 2; i++) {
1810 if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_A) {
1811 action->rewrite->allow_rx = 0;
1812 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) {
1813 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n",
1814 sw_fields[i]);
1815 return -EINVAL;
1816 }
1817 } else if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_B) {
1818 action->rewrite->allow_tx = 0;
1819 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) {
1820 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n",
1821 sw_fields[i]);
1822 return -EINVAL;
1823 }
1824 }
1825 }
1826
1827 if (!action->rewrite->allow_rx && !action->rewrite->allow_tx) {
1828 mlx5dr_dbg(dmn, "Modify copy actions not supported on both RX and TX\n");
1829 return -EINVAL;
1830 }
1831
1832 return 0;
1833 }
1834
1835 static int
dr_action_modify_check_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1836 dr_action_modify_check_field_limitation(struct mlx5dr_action *action,
1837 const __be64 *sw_action)
1838 {
1839 struct mlx5dr_domain *dmn = action->rewrite->dmn;
1840 u8 action_type;
1841 int ret;
1842
1843 action_type = MLX5_GET(set_action_in, sw_action, action_type);
1844
1845 switch (action_type) {
1846 case MLX5_ACTION_TYPE_SET:
1847 ret = dr_action_modify_check_set_field_limitation(action,
1848 sw_action);
1849 break;
1850
1851 case MLX5_ACTION_TYPE_ADD:
1852 ret = dr_action_modify_check_add_field_limitation(action,
1853 sw_action);
1854 break;
1855
1856 case MLX5_ACTION_TYPE_COPY:
1857 ret = dr_action_modify_check_copy_field_limitation(action,
1858 sw_action);
1859 break;
1860
1861 default:
1862 mlx5dr_info(dmn, "Unsupported action %d modify action\n",
1863 action_type);
1864 ret = -EOPNOTSUPP;
1865 }
1866
1867 return ret;
1868 }
1869
1870 static bool
dr_action_modify_check_is_ttl_modify(const void * sw_action)1871 dr_action_modify_check_is_ttl_modify(const void *sw_action)
1872 {
1873 u16 sw_field = MLX5_GET(set_action_in, sw_action, field);
1874
1875 return sw_field == MLX5_ACTION_IN_FIELD_OUT_IP_TTL;
1876 }
1877
dr_actions_convert_modify_header(struct mlx5dr_action * action,u32 max_hw_actions,u32 num_sw_actions,__be64 sw_actions[],__be64 hw_actions[],u32 * num_hw_actions,bool * modify_ttl)1878 static int dr_actions_convert_modify_header(struct mlx5dr_action *action,
1879 u32 max_hw_actions,
1880 u32 num_sw_actions,
1881 __be64 sw_actions[],
1882 __be64 hw_actions[],
1883 u32 *num_hw_actions,
1884 bool *modify_ttl)
1885 {
1886 const struct mlx5dr_ste_action_modify_field *hw_dst_action_info;
1887 const struct mlx5dr_ste_action_modify_field *hw_src_action_info;
1888 struct mlx5dr_domain *dmn = action->rewrite->dmn;
1889 __be64 *modify_ttl_sw_action = NULL;
1890 int ret, i, hw_idx = 0;
1891 __be64 *sw_action;
1892 __be64 hw_action;
1893 u16 hw_field = 0;
1894 u32 l3_type = 0;
1895 u32 l4_type = 0;
1896
1897 *modify_ttl = false;
1898
1899 action->rewrite->allow_rx = 1;
1900 action->rewrite->allow_tx = 1;
1901
1902 for (i = 0; i < num_sw_actions || modify_ttl_sw_action; i++) {
1903 /* modify TTL is handled separately, as a last action */
1904 if (i == num_sw_actions) {
1905 sw_action = modify_ttl_sw_action;
1906 modify_ttl_sw_action = NULL;
1907 } else {
1908 sw_action = &sw_actions[i];
1909 }
1910
1911 ret = dr_action_modify_check_field_limitation(action,
1912 sw_action);
1913 if (ret)
1914 return ret;
1915
1916 if (!(*modify_ttl) &&
1917 dr_action_modify_check_is_ttl_modify(sw_action)) {
1918 modify_ttl_sw_action = sw_action;
1919 *modify_ttl = true;
1920 continue;
1921 }
1922
1923 /* Convert SW action to HW action */
1924 ret = dr_action_modify_sw_to_hw(dmn,
1925 sw_action,
1926 &hw_action,
1927 &hw_dst_action_info,
1928 &hw_src_action_info);
1929 if (ret)
1930 return ret;
1931
1932 /* Due to a HW limitation we cannot modify 2 different L3 types */
1933 if (l3_type && hw_dst_action_info->l3_type &&
1934 hw_dst_action_info->l3_type != l3_type) {
1935 mlx5dr_dbg(dmn, "Action list can't support two different L3 types\n");
1936 return -EINVAL;
1937 }
1938 if (hw_dst_action_info->l3_type)
1939 l3_type = hw_dst_action_info->l3_type;
1940
1941 /* Due to a HW limitation we cannot modify two different L4 types */
1942 if (l4_type && hw_dst_action_info->l4_type &&
1943 hw_dst_action_info->l4_type != l4_type) {
1944 mlx5dr_dbg(dmn, "Action list can't support two different L4 types\n");
1945 return -EINVAL;
1946 }
1947 if (hw_dst_action_info->l4_type)
1948 l4_type = hw_dst_action_info->l4_type;
1949
1950 /* HW reads and executes two actions at once this means we
1951 * need to create a gap if two actions access the same field
1952 */
1953 if ((hw_idx % 2) && (hw_field == hw_dst_action_info->hw_field ||
1954 (hw_src_action_info &&
1955 hw_field == hw_src_action_info->hw_field))) {
1956 /* Check if after gap insertion the total number of HW
1957 * modify actions doesn't exceeds the limit
1958 */
1959 hw_idx++;
1960 if (hw_idx >= max_hw_actions) {
1961 mlx5dr_dbg(dmn, "Modify header action number exceeds HW limit\n");
1962 return -EINVAL;
1963 }
1964 }
1965 hw_field = hw_dst_action_info->hw_field;
1966
1967 hw_actions[hw_idx] = hw_action;
1968 hw_idx++;
1969 }
1970
1971 /* if the resulting HW actions list is empty, add NOP action */
1972 if (!hw_idx)
1973 hw_idx++;
1974
1975 *num_hw_actions = hw_idx;
1976
1977 return 0;
1978 }
1979
dr_action_create_modify_action(struct mlx5dr_domain * dmn,size_t actions_sz,__be64 actions[],struct mlx5dr_action * action)1980 static int dr_action_create_modify_action(struct mlx5dr_domain *dmn,
1981 size_t actions_sz,
1982 __be64 actions[],
1983 struct mlx5dr_action *action)
1984 {
1985 u32 max_hw_actions;
1986 u32 num_hw_actions;
1987 u32 num_sw_actions;
1988 __be64 *hw_actions;
1989 bool modify_ttl;
1990 int ret;
1991
1992 num_sw_actions = actions_sz / DR_MODIFY_ACTION_SIZE;
1993 max_hw_actions = mlx5dr_icm_pool_chunk_size_to_entries(DR_CHUNK_SIZE_16);
1994
1995 if (num_sw_actions > max_hw_actions) {
1996 mlx5dr_dbg(dmn, "Max number of actions %d exceeds limit %d\n",
1997 num_sw_actions, max_hw_actions);
1998 return -EINVAL;
1999 }
2000
2001 hw_actions = kcalloc(1, max_hw_actions * DR_MODIFY_ACTION_SIZE, GFP_KERNEL);
2002 if (!hw_actions)
2003 return -ENOMEM;
2004
2005 ret = dr_actions_convert_modify_header(action,
2006 max_hw_actions,
2007 num_sw_actions,
2008 actions,
2009 hw_actions,
2010 &num_hw_actions,
2011 &modify_ttl);
2012 if (ret)
2013 goto free_hw_actions;
2014
2015 action->rewrite->modify_ttl = modify_ttl;
2016 action->rewrite->data = (u8 *)hw_actions;
2017 action->rewrite->num_of_actions = num_hw_actions;
2018
2019 if (num_hw_actions == 1 &&
2020 dmn->info.caps.sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX) {
2021 action->rewrite->single_action_opt = true;
2022 } else {
2023 action->rewrite->single_action_opt = false;
2024 ret = mlx5dr_ste_alloc_modify_hdr(action);
2025 if (ret)
2026 goto free_hw_actions;
2027 }
2028
2029 return 0;
2030
2031 free_hw_actions:
2032 kfree(hw_actions);
2033 return ret;
2034 }
2035
2036 struct mlx5dr_action *
mlx5dr_action_create_modify_header(struct mlx5dr_domain * dmn,u32 flags,size_t actions_sz,__be64 actions[])2037 mlx5dr_action_create_modify_header(struct mlx5dr_domain *dmn,
2038 u32 flags,
2039 size_t actions_sz,
2040 __be64 actions[])
2041 {
2042 struct mlx5dr_action *action;
2043 int ret = 0;
2044
2045 refcount_inc(&dmn->refcount);
2046
2047 if (actions_sz % DR_MODIFY_ACTION_SIZE) {
2048 mlx5dr_dbg(dmn, "Invalid modify actions size provided\n");
2049 goto dec_ref;
2050 }
2051
2052 action = dr_action_create_generic(DR_ACTION_TYP_MODIFY_HDR);
2053 if (!action)
2054 goto dec_ref;
2055
2056 action->rewrite->dmn = dmn;
2057
2058 ret = dr_action_create_modify_action(dmn,
2059 actions_sz,
2060 actions,
2061 action);
2062 if (ret) {
2063 mlx5dr_dbg(dmn, "Failed creating modify header action %d\n", ret);
2064 goto free_action;
2065 }
2066
2067 return action;
2068
2069 free_action:
2070 kfree(action);
2071 dec_ref:
2072 refcount_dec(&dmn->refcount);
2073 return NULL;
2074 }
2075
2076 struct mlx5dr_action *
mlx5dr_action_create_dest_vport(struct mlx5dr_domain * dmn,u16 vport,u8 vhca_id_valid,u16 vhca_id)2077 mlx5dr_action_create_dest_vport(struct mlx5dr_domain *dmn,
2078 u16 vport, u8 vhca_id_valid,
2079 u16 vhca_id)
2080 {
2081 struct mlx5dr_cmd_vport_cap *vport_cap;
2082 struct mlx5dr_domain *vport_dmn;
2083 struct mlx5dr_action *action;
2084 u8 peer_vport;
2085
2086 peer_vport = vhca_id_valid && mlx5_core_is_pf(dmn->mdev) &&
2087 (vhca_id != dmn->info.caps.gvmi);
2088 vport_dmn = peer_vport ? xa_load(&dmn->peer_dmn_xa, vhca_id) : dmn;
2089 if (!vport_dmn) {
2090 mlx5dr_dbg(dmn, "No peer vport domain for given vhca_id\n");
2091 return NULL;
2092 }
2093
2094 if (vport_dmn->type != MLX5DR_DOMAIN_TYPE_FDB) {
2095 mlx5dr_dbg(dmn, "Domain doesn't support vport actions\n");
2096 return NULL;
2097 }
2098
2099 vport_cap = mlx5dr_domain_get_vport_cap(vport_dmn, vport);
2100 if (!vport_cap) {
2101 mlx5dr_err(dmn,
2102 "Failed to get vport 0x%x caps - vport is disabled or invalid\n",
2103 vport);
2104 return NULL;
2105 }
2106
2107 action = dr_action_create_generic(DR_ACTION_TYP_VPORT);
2108 if (!action)
2109 return NULL;
2110
2111 action->vport->dmn = vport_dmn;
2112 action->vport->caps = vport_cap;
2113
2114 return action;
2115 }
2116
2117 struct mlx5dr_action *
mlx5dr_action_create_aso(struct mlx5dr_domain * dmn,u32 obj_id,u8 dest_reg_id,u8 aso_type,u8 init_color,u8 meter_id)2118 mlx5dr_action_create_aso(struct mlx5dr_domain *dmn, u32 obj_id,
2119 u8 dest_reg_id, u8 aso_type,
2120 u8 init_color, u8 meter_id)
2121 {
2122 struct mlx5dr_action *action;
2123
2124 if (aso_type != MLX5_EXE_ASO_FLOW_METER)
2125 return NULL;
2126
2127 if (init_color > MLX5_FLOW_METER_COLOR_UNDEFINED)
2128 return NULL;
2129
2130 action = dr_action_create_generic(DR_ACTION_TYP_ASO_FLOW_METER);
2131 if (!action)
2132 return NULL;
2133
2134 action->aso->obj_id = obj_id;
2135 action->aso->offset = meter_id;
2136 action->aso->dest_reg_id = dest_reg_id;
2137 action->aso->init_color = init_color;
2138 action->aso->dmn = dmn;
2139
2140 refcount_inc(&dmn->refcount);
2141
2142 return action;
2143 }
2144
mlx5dr_action_get_pkt_reformat_id(struct mlx5dr_action * action)2145 u32 mlx5dr_action_get_pkt_reformat_id(struct mlx5dr_action *action)
2146 {
2147 return action->reformat->id;
2148 }
2149
mlx5dr_action_destroy(struct mlx5dr_action * action)2150 int mlx5dr_action_destroy(struct mlx5dr_action *action)
2151 {
2152 if (WARN_ON_ONCE(refcount_read(&action->refcount) > 1))
2153 return -EBUSY;
2154
2155 switch (action->action_type) {
2156 case DR_ACTION_TYP_FT:
2157 if (action->dest_tbl->is_fw_tbl)
2158 refcount_dec(&action->dest_tbl->fw_tbl.dmn->refcount);
2159 else
2160 refcount_dec(&action->dest_tbl->tbl->refcount);
2161
2162 if (action->dest_tbl->is_fw_tbl &&
2163 action->dest_tbl->fw_tbl.num_of_ref_actions) {
2164 struct mlx5dr_action **ref_actions;
2165 int i;
2166
2167 ref_actions = action->dest_tbl->fw_tbl.ref_actions;
2168 for (i = 0; i < action->dest_tbl->fw_tbl.num_of_ref_actions; i++)
2169 refcount_dec(&ref_actions[i]->refcount);
2170
2171 kfree(ref_actions);
2172
2173 mlx5dr_fw_destroy_md_tbl(action->dest_tbl->fw_tbl.dmn,
2174 action->dest_tbl->fw_tbl.id,
2175 action->dest_tbl->fw_tbl.group_id);
2176 }
2177 break;
2178 case DR_ACTION_TYP_TNL_L2_TO_L2:
2179 case DR_ACTION_TYP_REMOVE_HDR:
2180 refcount_dec(&action->reformat->dmn->refcount);
2181 break;
2182 case DR_ACTION_TYP_TNL_L3_TO_L2:
2183 mlx5dr_ste_free_modify_hdr(action);
2184 kfree(action->rewrite->data);
2185 refcount_dec(&action->rewrite->dmn->refcount);
2186 break;
2187 case DR_ACTION_TYP_L2_TO_TNL_L2:
2188 case DR_ACTION_TYP_L2_TO_TNL_L3:
2189 case DR_ACTION_TYP_INSERT_HDR:
2190 mlx5dr_cmd_destroy_reformat_ctx((action->reformat->dmn)->mdev,
2191 action->reformat->id);
2192 refcount_dec(&action->reformat->dmn->refcount);
2193 break;
2194 case DR_ACTION_TYP_MODIFY_HDR:
2195 if (!action->rewrite->single_action_opt)
2196 mlx5dr_ste_free_modify_hdr(action);
2197 kfree(action->rewrite->data);
2198 refcount_dec(&action->rewrite->dmn->refcount);
2199 break;
2200 case DR_ACTION_TYP_SAMPLER:
2201 refcount_dec(&action->sampler->dmn->refcount);
2202 break;
2203 case DR_ACTION_TYP_ASO_FLOW_METER:
2204 refcount_dec(&action->aso->dmn->refcount);
2205 break;
2206 case DR_ACTION_TYP_RANGE:
2207 dr_action_destroy_range_definer(action);
2208 mlx5dr_action_destroy(action->range->miss_tbl_action);
2209 mlx5dr_action_destroy(action->range->hit_tbl_action);
2210 break;
2211 default:
2212 break;
2213 }
2214
2215 kfree(action);
2216 return 0;
2217 }
2218