1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
52 #endif
53 #include <linux/version.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
56 #include "lib/eq.h"
57 #include "fs_core.h"
58 #include "lib/mpfs.h"
59 #include "eswitch.h"
60 #include "devlink.h"
61 #include "fw_reset.h"
62 #include "lib/mlx5.h"
63 #include "lib/tout.h"
64 #include "fpga/core.h"
65 #include "en_accel/ipsec.h"
66 #include "lib/clock.h"
67 #include "lib/vxlan.h"
68 #include "lib/geneve.h"
69 #include "lib/devcom.h"
70 #include "lib/pci_vsc.h"
71 #include "diag/fw_tracer.h"
72 #include "ecpf.h"
73 #include "lib/hv_vhca.h"
74 #include "diag/rsc_dump.h"
75 #include "sf/vhca_event.h"
76 #include "sf/dev/dev.h"
77 #include "sf/sf.h"
78 #include "mlx5_irq.h"
79
80 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
81 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
82 MODULE_LICENSE("Dual BSD/GPL");
83
84 unsigned int mlx5_core_debug_mask;
85 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
86 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
87
88 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
89 module_param_named(prof_sel, prof_sel, uint, 0444);
90 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
91
92 static u32 sw_owner_id[4];
93 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1)
94 static DEFINE_IDA(sw_vhca_ida);
95
96 enum {
97 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
98 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
99 };
100
101 #define LOG_MAX_SUPPORTED_QPS 0xff
102
103 static struct mlx5_profile profile[] = {
104 [0] = {
105 .mask = 0,
106 },
107 [1] = {
108 .mask = MLX5_PROF_MASK_QP_SIZE,
109 .log_max_qp = 12,
110 },
111 [2] = {
112 .mask = MLX5_PROF_MASK_QP_SIZE |
113 MLX5_PROF_MASK_MR_CACHE,
114 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
115 .mr_cache[0] = {
116 .size = 500,
117 .limit = 250
118 },
119 .mr_cache[1] = {
120 .size = 500,
121 .limit = 250
122 },
123 .mr_cache[2] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[3] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[4] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[5] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[6] = {
140 .size = 500,
141 .limit = 250
142 },
143 .mr_cache[7] = {
144 .size = 500,
145 .limit = 250
146 },
147 .mr_cache[8] = {
148 .size = 500,
149 .limit = 250
150 },
151 .mr_cache[9] = {
152 .size = 500,
153 .limit = 250
154 },
155 .mr_cache[10] = {
156 .size = 500,
157 .limit = 250
158 },
159 .mr_cache[11] = {
160 .size = 500,
161 .limit = 250
162 },
163 .mr_cache[12] = {
164 .size = 64,
165 .limit = 32
166 },
167 .mr_cache[13] = {
168 .size = 32,
169 .limit = 16
170 },
171 .mr_cache[14] = {
172 .size = 16,
173 .limit = 8
174 },
175 .mr_cache[15] = {
176 .size = 8,
177 .limit = 4
178 },
179 },
180 };
181
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili)182 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
183 u32 warn_time_mili)
184 {
185 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
186 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
187 u32 fw_initializing;
188 int err = 0;
189
190 do {
191 fw_initializing = ioread32be(&dev->iseg->initializing);
192 if (!(fw_initializing >> 31))
193 break;
194 if (time_after(jiffies, end) ||
195 test_and_clear_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) {
196 err = -EBUSY;
197 break;
198 }
199 if (warn_time_mili && time_after(jiffies, warn)) {
200 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds (0x%x)\n",
201 jiffies_to_msecs(end - warn) / 1000, fw_initializing);
202 warn = jiffies + msecs_to_jiffies(warn_time_mili);
203 }
204 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
205 } while (true);
206
207 return err;
208 }
209
mlx5_set_driver_version(struct mlx5_core_dev * dev)210 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
211 {
212 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
213 driver_version);
214 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
215 int remaining_size = driver_ver_sz;
216 char *string;
217
218 if (!MLX5_CAP_GEN(dev, driver_version))
219 return;
220
221 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
222
223 strncpy(string, "Linux", remaining_size);
224
225 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
226 strncat(string, ",", remaining_size);
227
228 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
229 strncat(string, KBUILD_MODNAME, remaining_size);
230
231 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
232 strncat(string, ",", remaining_size);
233
234 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
235
236 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
237 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
238 LINUX_VERSION_SUBLEVEL);
239
240 /*Send the command*/
241 MLX5_SET(set_driver_version_in, in, opcode,
242 MLX5_CMD_OP_SET_DRIVER_VERSION);
243
244 mlx5_cmd_exec_in(dev, set_driver_version, in);
245 }
246
set_dma_caps(struct pci_dev * pdev)247 static int set_dma_caps(struct pci_dev *pdev)
248 {
249 int err;
250
251 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
252 if (err) {
253 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
254 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
255 if (err) {
256 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
257 return err;
258 }
259 }
260
261 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
262 return err;
263 }
264
mlx5_pci_enable_device(struct mlx5_core_dev * dev)265 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
266 {
267 struct pci_dev *pdev = dev->pdev;
268 int err = 0;
269
270 mutex_lock(&dev->pci_status_mutex);
271 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
272 err = pci_enable_device(pdev);
273 if (!err)
274 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
275 }
276 mutex_unlock(&dev->pci_status_mutex);
277
278 return err;
279 }
280
mlx5_pci_disable_device(struct mlx5_core_dev * dev)281 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
282 {
283 struct pci_dev *pdev = dev->pdev;
284
285 mutex_lock(&dev->pci_status_mutex);
286 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
287 pci_disable_device(pdev);
288 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
289 }
290 mutex_unlock(&dev->pci_status_mutex);
291 }
292
request_bar(struct pci_dev * pdev)293 static int request_bar(struct pci_dev *pdev)
294 {
295 int err = 0;
296
297 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
298 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
299 return -ENODEV;
300 }
301
302 err = pci_request_regions(pdev, KBUILD_MODNAME);
303 if (err)
304 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
305
306 return err;
307 }
308
release_bar(struct pci_dev * pdev)309 static void release_bar(struct pci_dev *pdev)
310 {
311 pci_release_regions(pdev);
312 }
313
314 struct mlx5_reg_host_endianness {
315 u8 he;
316 u8 rsvd[15];
317 };
318
319 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
320
321 enum {
322 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
323 MLX5_DEV_CAP_FLAG_DCT,
324 };
325
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)326 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
327 {
328 switch (size) {
329 case 128:
330 return 0;
331 case 256:
332 return 1;
333 case 512:
334 return 2;
335 case 1024:
336 return 3;
337 case 2048:
338 return 4;
339 case 4096:
340 return 5;
341 default:
342 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
343 return 0;
344 }
345 }
346
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)347 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
348 enum mlx5_cap_type cap_type,
349 enum mlx5_cap_mode cap_mode)
350 {
351 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
352 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
353 void *out, *hca_caps;
354 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
355 int err;
356
357 memset(in, 0, sizeof(in));
358 out = kzalloc(out_sz, GFP_KERNEL);
359 if (!out)
360 return -ENOMEM;
361
362 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
363 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
364 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
365 if (err) {
366 mlx5_core_warn(dev,
367 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
368 cap_type, cap_mode, err);
369 goto query_ex;
370 }
371
372 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
373
374 switch (cap_mode) {
375 case HCA_CAP_OPMOD_GET_MAX:
376 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
377 MLX5_UN_SZ_BYTES(hca_cap_union));
378 break;
379 case HCA_CAP_OPMOD_GET_CUR:
380 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
381 MLX5_UN_SZ_BYTES(hca_cap_union));
382 break;
383 default:
384 mlx5_core_warn(dev,
385 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
386 cap_type, cap_mode);
387 err = -EINVAL;
388 break;
389 }
390 query_ex:
391 kfree(out);
392 return err;
393 }
394
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)395 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
396 {
397 int ret;
398
399 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
400 if (ret)
401 return ret;
402 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
403 }
404
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)405 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
406 {
407 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
408 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
409 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
410 }
411
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)412 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
413 {
414 void *set_hca_cap;
415 int req_endianness;
416 int err;
417
418 if (!MLX5_CAP_GEN(dev, atomic))
419 return 0;
420
421 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
422 if (err)
423 return err;
424
425 req_endianness =
426 MLX5_CAP_ATOMIC(dev,
427 supported_atomic_req_8B_endianness_mode_1);
428
429 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
430 return 0;
431
432 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
433
434 /* Set requestor to host endianness */
435 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
436 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
437
438 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
439 }
440
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)441 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
442 {
443 void *set_hca_cap;
444 bool do_set = false;
445 int err;
446
447 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
448 !MLX5_CAP_GEN(dev, pg))
449 return 0;
450
451 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
452 if (err)
453 return err;
454
455 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
456 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
457 MLX5_ST_SZ_BYTES(odp_cap));
458
459 #define ODP_CAP_SET_MAX(dev, field) \
460 do { \
461 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
462 if (_res) { \
463 do_set = true; \
464 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
465 } \
466 } while (0)
467
468 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
469 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
470 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
471 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
472 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
473 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
474 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
475 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
476 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
477 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
478 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
479 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
480 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
481 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
482
483 if (!do_set)
484 return 0;
485
486 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
487 }
488
max_uc_list_get_devlink_param(struct mlx5_core_dev * dev)489 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
490 {
491 struct devlink *devlink = priv_to_devlink(dev);
492 union devlink_param_value val;
493 int err;
494
495 err = devlink_param_driverinit_value_get(devlink,
496 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
497 &val);
498 if (!err)
499 return val.vu32;
500 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
501 return err;
502 }
503
mlx5_is_roce_on(struct mlx5_core_dev * dev)504 bool mlx5_is_roce_on(struct mlx5_core_dev *dev)
505 {
506 struct devlink *devlink = priv_to_devlink(dev);
507 union devlink_param_value val;
508 int err;
509
510 err = devlink_param_driverinit_value_get(devlink,
511 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
512 &val);
513
514 if (!err)
515 return val.vbool;
516
517 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
518 return MLX5_CAP_GEN(dev, roce);
519 }
520 EXPORT_SYMBOL(mlx5_is_roce_on);
521
handle_hca_cap_2(struct mlx5_core_dev * dev,void * set_ctx)522 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx)
523 {
524 void *set_hca_cap;
525 int err;
526
527 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2))
528 return 0;
529
530 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2);
531 if (err)
532 return err;
533
534 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) ||
535 !(dev->priv.sw_vhca_id > 0))
536 return 0;
537
538 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
539 capability);
540 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur,
541 MLX5_ST_SZ_BYTES(cmd_hca_cap_2));
542 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1);
543
544 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2);
545 }
546
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)547 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
548 {
549 struct mlx5_profile *prof = &dev->profile;
550 void *set_hca_cap;
551 int max_uc_list;
552 int err;
553
554 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
555 if (err)
556 return err;
557
558 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
559 capability);
560 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
561 MLX5_ST_SZ_BYTES(cmd_hca_cap));
562
563 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
564 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
565 128);
566 /* we limit the size of the pkey table to 128 entries for now */
567 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
568 to_fw_pkey_sz(dev, 128));
569
570 /* Check log_max_qp from HCA caps to set in current profile */
571 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
572 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp));
573 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
574 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
575 prof->log_max_qp,
576 MLX5_CAP_GEN_MAX(dev, log_max_qp));
577 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
578 }
579 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
580 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
581 prof->log_max_qp);
582
583 /* disable cmdif checksum */
584 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
585
586 /* Enable 4K UAR only when HCA supports it and page size is bigger
587 * than 4K.
588 */
589 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
590 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
591
592 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
593
594 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
595 MLX5_SET(cmd_hca_cap,
596 set_hca_cap,
597 cache_line_128byte,
598 cache_line_size() >= 128 ? 1 : 0);
599
600 if (MLX5_CAP_GEN_MAX(dev, dct))
601 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
602
603 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
604 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
605
606 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
607 MLX5_SET(cmd_hca_cap,
608 set_hca_cap,
609 num_vhca_ports,
610 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
611
612 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
613 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
614
615 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
616 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
617
618 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
619
620 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
621 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
622 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
623
624 if (MLX5_CAP_GEN(dev, roce_rw_supported))
625 MLX5_SET(cmd_hca_cap, set_hca_cap, roce,
626 mlx5_is_roce_on(dev));
627
628 max_uc_list = max_uc_list_get_devlink_param(dev);
629 if (max_uc_list > 0)
630 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
631 ilog2(max_uc_list));
632
633 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
634 }
635
636 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
637 * boot process.
638 * In case RoCE cap is writable in FW and user/devlink requested to change the
639 * cap, we are yet to query the final state of the above cap.
640 * Hence, the need for this function.
641 *
642 * Returns
643 * True:
644 * 1) RoCE cap is read only in FW and already disabled
645 * OR:
646 * 2) RoCE cap is writable in FW and user/devlink requested it off.
647 *
648 * In any other case, return False.
649 */
is_roce_fw_disabled(struct mlx5_core_dev * dev)650 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
651 {
652 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) ||
653 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
654 }
655
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)656 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
657 {
658 void *set_hca_cap;
659 int err;
660
661 if (is_roce_fw_disabled(dev))
662 return 0;
663
664 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
665 if (err)
666 return err;
667
668 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
669 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
670 return 0;
671
672 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
673 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
674 MLX5_ST_SZ_BYTES(roce_cap));
675 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
676
677 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
678 return err;
679 }
680
set_hca_cap(struct mlx5_core_dev * dev)681 static int set_hca_cap(struct mlx5_core_dev *dev)
682 {
683 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
684 void *set_ctx;
685 int err;
686
687 set_ctx = kzalloc(set_sz, GFP_KERNEL);
688 if (!set_ctx)
689 return -ENOMEM;
690
691 err = handle_hca_cap(dev, set_ctx);
692 if (err) {
693 mlx5_core_err(dev, "handle_hca_cap failed\n");
694 goto out;
695 }
696
697 memset(set_ctx, 0, set_sz);
698 err = handle_hca_cap_atomic(dev, set_ctx);
699 if (err) {
700 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
701 goto out;
702 }
703
704 memset(set_ctx, 0, set_sz);
705 err = handle_hca_cap_odp(dev, set_ctx);
706 if (err) {
707 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
708 goto out;
709 }
710
711 memset(set_ctx, 0, set_sz);
712 err = handle_hca_cap_roce(dev, set_ctx);
713 if (err) {
714 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
715 goto out;
716 }
717
718 memset(set_ctx, 0, set_sz);
719 err = handle_hca_cap_2(dev, set_ctx);
720 if (err) {
721 mlx5_core_err(dev, "handle_hca_cap_2 failed\n");
722 goto out;
723 }
724
725 out:
726 kfree(set_ctx);
727 return err;
728 }
729
set_hca_ctrl(struct mlx5_core_dev * dev)730 static int set_hca_ctrl(struct mlx5_core_dev *dev)
731 {
732 struct mlx5_reg_host_endianness he_in;
733 struct mlx5_reg_host_endianness he_out;
734 int err;
735
736 if (!mlx5_core_is_pf(dev))
737 return 0;
738
739 memset(&he_in, 0, sizeof(he_in));
740 he_in.he = MLX5_SET_HOST_ENDIANNESS;
741 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
742 &he_out, sizeof(he_out),
743 MLX5_REG_HOST_ENDIANNESS, 0, 1);
744 return err;
745 }
746
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)747 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
748 {
749 int ret = 0;
750
751 /* Disable local_lb by default */
752 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
753 ret = mlx5_nic_vport_update_local_lb(dev, false);
754
755 return ret;
756 }
757
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)758 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
759 {
760 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
761
762 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
763 MLX5_SET(enable_hca_in, in, function_id, func_id);
764 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
765 dev->caps.embedded_cpu);
766 return mlx5_cmd_exec_in(dev, enable_hca, in);
767 }
768
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)769 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
770 {
771 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
772
773 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
774 MLX5_SET(disable_hca_in, in, function_id, func_id);
775 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
776 dev->caps.embedded_cpu);
777 return mlx5_cmd_exec_in(dev, disable_hca, in);
778 }
779
mlx5_core_set_issi(struct mlx5_core_dev * dev)780 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
781 {
782 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
783 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
784 u32 sup_issi;
785 int err;
786
787 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
788 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
789 if (err) {
790 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome);
791 u8 status = MLX5_GET(query_issi_out, query_out, status);
792
793 if (!status || syndrome == MLX5_DRIVER_SYND) {
794 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
795 err, status, syndrome);
796 return err;
797 }
798
799 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
800 dev->issi = 0;
801 return 0;
802 }
803
804 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
805
806 if (sup_issi & (1 << 1)) {
807 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
808
809 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
810 MLX5_SET(set_issi_in, set_in, current_issi, 1);
811 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
812 if (err) {
813 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
814 err);
815 return err;
816 }
817
818 dev->issi = 1;
819
820 return 0;
821 } else if (sup_issi & (1 << 0) || !sup_issi) {
822 return 0;
823 }
824
825 return -EOPNOTSUPP;
826 }
827
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)828 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
829 const struct pci_device_id *id)
830 {
831 int err = 0;
832
833 mutex_init(&dev->pci_status_mutex);
834 pci_set_drvdata(dev->pdev, dev);
835
836 dev->bar_addr = pci_resource_start(pdev, 0);
837
838 err = mlx5_pci_enable_device(dev);
839 if (err) {
840 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
841 return err;
842 }
843
844 err = request_bar(pdev);
845 if (err) {
846 mlx5_core_err(dev, "error requesting BARs, aborting\n");
847 goto err_disable;
848 }
849
850 pci_set_master(pdev);
851
852 err = set_dma_caps(pdev);
853 if (err) {
854 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
855 goto err_clr_master;
856 }
857
858 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
859 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
860 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
861 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
862
863 dev->iseg_base = dev->bar_addr;
864 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
865 if (!dev->iseg) {
866 err = -ENOMEM;
867 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
868 goto err_clr_master;
869 }
870
871 mlx5_pci_vsc_init(dev);
872 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
873 return 0;
874
875 err_clr_master:
876 pci_clear_master(dev->pdev);
877 release_bar(dev->pdev);
878 err_disable:
879 mlx5_pci_disable_device(dev);
880 return err;
881 }
882
mlx5_pci_close(struct mlx5_core_dev * dev)883 static void mlx5_pci_close(struct mlx5_core_dev *dev)
884 {
885 /* health work might still be active, and it needs pci bar in
886 * order to know the NIC state. Therefore, drain the health WQ
887 * before removing the pci bars
888 */
889 mlx5_drain_health_wq(dev);
890 iounmap(dev->iseg);
891 pci_clear_master(dev->pdev);
892 release_bar(dev->pdev);
893 mlx5_pci_disable_device(dev);
894 }
895
mlx5_init_once(struct mlx5_core_dev * dev)896 static int mlx5_init_once(struct mlx5_core_dev *dev)
897 {
898 int err;
899
900 dev->priv.devcom = mlx5_devcom_register_device(dev);
901 if (IS_ERR(dev->priv.devcom))
902 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
903 dev->priv.devcom);
904
905 err = mlx5_query_board_id(dev);
906 if (err) {
907 mlx5_core_err(dev, "query board id failed\n");
908 goto err_devcom;
909 }
910
911 err = mlx5_irq_table_init(dev);
912 if (err) {
913 mlx5_core_err(dev, "failed to initialize irq table\n");
914 goto err_devcom;
915 }
916
917 err = mlx5_eq_table_init(dev);
918 if (err) {
919 mlx5_core_err(dev, "failed to initialize eq\n");
920 goto err_irq_cleanup;
921 }
922
923 err = mlx5_events_init(dev);
924 if (err) {
925 mlx5_core_err(dev, "failed to initialize events\n");
926 goto err_eq_cleanup;
927 }
928
929 err = mlx5_fw_reset_init(dev);
930 if (err) {
931 mlx5_core_err(dev, "failed to initialize fw reset events\n");
932 goto err_events_cleanup;
933 }
934
935 mlx5_cq_debugfs_init(dev);
936
937 mlx5_init_reserved_gids(dev);
938
939 mlx5_init_clock(dev);
940
941 dev->vxlan = mlx5_vxlan_create(dev);
942 dev->geneve = mlx5_geneve_create(dev);
943
944 err = mlx5_init_rl_table(dev);
945 if (err) {
946 mlx5_core_err(dev, "Failed to init rate limiting\n");
947 goto err_tables_cleanup;
948 }
949
950 err = mlx5_mpfs_init(dev);
951 if (err) {
952 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
953 goto err_rl_cleanup;
954 }
955
956 err = mlx5_sriov_init(dev);
957 if (err) {
958 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
959 goto err_mpfs_cleanup;
960 }
961
962 err = mlx5_eswitch_init(dev);
963 if (err) {
964 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
965 goto err_sriov_cleanup;
966 }
967
968 err = mlx5_fpga_init(dev);
969 if (err) {
970 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
971 goto err_eswitch_cleanup;
972 }
973
974 err = mlx5_vhca_event_init(dev);
975 if (err) {
976 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
977 goto err_fpga_cleanup;
978 }
979
980 err = mlx5_sf_hw_table_init(dev);
981 if (err) {
982 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
983 goto err_sf_hw_table_cleanup;
984 }
985
986 err = mlx5_sf_table_init(dev);
987 if (err) {
988 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
989 goto err_sf_table_cleanup;
990 }
991
992 err = mlx5_fs_core_alloc(dev);
993 if (err) {
994 mlx5_core_err(dev, "Failed to alloc flow steering\n");
995 goto err_fs;
996 }
997
998 dev->dm = mlx5_dm_create(dev);
999 if (IS_ERR(dev->dm))
1000 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
1001
1002 dev->tracer = mlx5_fw_tracer_create(dev);
1003 dev->hv_vhca = mlx5_hv_vhca_create(dev);
1004 dev->rsc_dump = mlx5_rsc_dump_create(dev);
1005
1006 return 0;
1007
1008 err_fs:
1009 mlx5_sf_table_cleanup(dev);
1010 err_sf_table_cleanup:
1011 mlx5_sf_hw_table_cleanup(dev);
1012 err_sf_hw_table_cleanup:
1013 mlx5_vhca_event_cleanup(dev);
1014 err_fpga_cleanup:
1015 mlx5_fpga_cleanup(dev);
1016 err_eswitch_cleanup:
1017 mlx5_eswitch_cleanup(dev->priv.eswitch);
1018 err_sriov_cleanup:
1019 mlx5_sriov_cleanup(dev);
1020 err_mpfs_cleanup:
1021 mlx5_mpfs_cleanup(dev);
1022 err_rl_cleanup:
1023 mlx5_cleanup_rl_table(dev);
1024 err_tables_cleanup:
1025 mlx5_geneve_destroy(dev->geneve);
1026 mlx5_vxlan_destroy(dev->vxlan);
1027 mlx5_cq_debugfs_cleanup(dev);
1028 mlx5_fw_reset_cleanup(dev);
1029 err_events_cleanup:
1030 mlx5_events_cleanup(dev);
1031 err_eq_cleanup:
1032 mlx5_eq_table_cleanup(dev);
1033 err_irq_cleanup:
1034 mlx5_irq_table_cleanup(dev);
1035 err_devcom:
1036 mlx5_devcom_unregister_device(dev->priv.devcom);
1037
1038 return err;
1039 }
1040
mlx5_cleanup_once(struct mlx5_core_dev * dev)1041 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1042 {
1043 mlx5_rsc_dump_destroy(dev);
1044 mlx5_hv_vhca_destroy(dev->hv_vhca);
1045 mlx5_fw_tracer_destroy(dev->tracer);
1046 mlx5_dm_cleanup(dev);
1047 mlx5_fs_core_free(dev);
1048 mlx5_sf_table_cleanup(dev);
1049 mlx5_sf_hw_table_cleanup(dev);
1050 mlx5_vhca_event_cleanup(dev);
1051 mlx5_fpga_cleanup(dev);
1052 mlx5_eswitch_cleanup(dev->priv.eswitch);
1053 mlx5_sriov_cleanup(dev);
1054 mlx5_mpfs_cleanup(dev);
1055 mlx5_cleanup_rl_table(dev);
1056 mlx5_geneve_destroy(dev->geneve);
1057 mlx5_vxlan_destroy(dev->vxlan);
1058 mlx5_cleanup_clock(dev);
1059 mlx5_cleanup_reserved_gids(dev);
1060 mlx5_cq_debugfs_cleanup(dev);
1061 mlx5_fw_reset_cleanup(dev);
1062 mlx5_events_cleanup(dev);
1063 mlx5_eq_table_cleanup(dev);
1064 mlx5_irq_table_cleanup(dev);
1065 mlx5_devcom_unregister_device(dev->priv.devcom);
1066 }
1067
mlx5_function_setup(struct mlx5_core_dev * dev,u64 timeout)1068 static int mlx5_function_setup(struct mlx5_core_dev *dev, u64 timeout)
1069 {
1070 int err;
1071
1072 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1073 fw_rev_min(dev), fw_rev_sub(dev));
1074
1075 /* Only PFs hold the relevant PCIe information for this query */
1076 if (mlx5_core_is_pf(dev))
1077 pcie_print_link_status(dev->pdev);
1078
1079 /* wait for firmware to accept initialization segments configurations
1080 */
1081 err = wait_fw_init(dev, timeout,
1082 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL));
1083 if (err) {
1084 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n",
1085 timeout);
1086 return err;
1087 }
1088
1089 err = mlx5_cmd_init(dev);
1090 if (err) {
1091 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1092 return err;
1093 }
1094
1095 mlx5_tout_query_iseg(dev);
1096
1097 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0);
1098 if (err) {
1099 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n",
1100 mlx5_tout_ms(dev, FW_INIT));
1101 goto err_cmd_cleanup;
1102 }
1103
1104 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1105
1106 err = mlx5_core_enable_hca(dev, 0);
1107 if (err) {
1108 mlx5_core_err(dev, "enable hca failed\n");
1109 goto err_cmd_cleanup;
1110 }
1111
1112 err = mlx5_core_set_issi(dev);
1113 if (err) {
1114 mlx5_core_err(dev, "failed to set issi\n");
1115 goto err_disable_hca;
1116 }
1117
1118 err = mlx5_satisfy_startup_pages(dev, 1);
1119 if (err) {
1120 mlx5_core_err(dev, "failed to allocate boot pages\n");
1121 goto err_disable_hca;
1122 }
1123
1124 err = mlx5_tout_query_dtor(dev);
1125 if (err) {
1126 mlx5_core_err(dev, "failed to read dtor\n");
1127 goto reclaim_boot_pages;
1128 }
1129
1130 err = set_hca_ctrl(dev);
1131 if (err) {
1132 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1133 goto reclaim_boot_pages;
1134 }
1135
1136 err = set_hca_cap(dev);
1137 if (err) {
1138 mlx5_core_err(dev, "set_hca_cap failed\n");
1139 goto reclaim_boot_pages;
1140 }
1141
1142 err = mlx5_satisfy_startup_pages(dev, 0);
1143 if (err) {
1144 mlx5_core_err(dev, "failed to allocate init pages\n");
1145 goto reclaim_boot_pages;
1146 }
1147
1148 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1149 if (err) {
1150 mlx5_core_err(dev, "init hca failed\n");
1151 goto reclaim_boot_pages;
1152 }
1153
1154 mlx5_set_driver_version(dev);
1155
1156 err = mlx5_query_hca_caps(dev);
1157 if (err) {
1158 mlx5_core_err(dev, "query hca failed\n");
1159 goto reclaim_boot_pages;
1160 }
1161
1162 mlx5_start_health_poll(dev);
1163
1164 return 0;
1165
1166 reclaim_boot_pages:
1167 mlx5_reclaim_startup_pages(dev);
1168 err_disable_hca:
1169 mlx5_core_disable_hca(dev, 0);
1170 err_cmd_cleanup:
1171 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1172 mlx5_cmd_cleanup(dev);
1173
1174 return err;
1175 }
1176
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1177 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1178 {
1179 int err;
1180
1181 mlx5_stop_health_poll(dev, boot);
1182 err = mlx5_cmd_teardown_hca(dev);
1183 if (err) {
1184 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1185 return err;
1186 }
1187 mlx5_reclaim_startup_pages(dev);
1188 mlx5_core_disable_hca(dev, 0);
1189 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1190 mlx5_cmd_cleanup(dev);
1191
1192 return 0;
1193 }
1194
mlx5_load(struct mlx5_core_dev * dev)1195 static int mlx5_load(struct mlx5_core_dev *dev)
1196 {
1197 int err;
1198
1199 dev->priv.uar = mlx5_get_uars_page(dev);
1200 if (IS_ERR(dev->priv.uar)) {
1201 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1202 err = PTR_ERR(dev->priv.uar);
1203 return err;
1204 }
1205
1206 mlx5_events_start(dev);
1207 mlx5_pagealloc_start(dev);
1208
1209 err = mlx5_irq_table_create(dev);
1210 if (err) {
1211 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1212 goto err_irq_table;
1213 }
1214
1215 err = mlx5_eq_table_create(dev);
1216 if (err) {
1217 mlx5_core_err(dev, "Failed to create EQs\n");
1218 goto err_eq_table;
1219 }
1220
1221 err = mlx5_fw_tracer_init(dev->tracer);
1222 if (err) {
1223 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1224 mlx5_fw_tracer_destroy(dev->tracer);
1225 dev->tracer = NULL;
1226 }
1227
1228 mlx5_fw_reset_events_start(dev);
1229 mlx5_hv_vhca_init(dev->hv_vhca);
1230
1231 err = mlx5_rsc_dump_init(dev);
1232 if (err) {
1233 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1234 mlx5_rsc_dump_destroy(dev);
1235 dev->rsc_dump = NULL;
1236 }
1237
1238 err = mlx5_fpga_device_start(dev);
1239 if (err) {
1240 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1241 goto err_fpga_start;
1242 }
1243
1244 err = mlx5_fs_core_init(dev);
1245 if (err) {
1246 mlx5_core_err(dev, "Failed to init flow steering\n");
1247 goto err_fs;
1248 }
1249
1250 err = mlx5_core_set_hca_defaults(dev);
1251 if (err) {
1252 mlx5_core_err(dev, "Failed to set hca defaults\n");
1253 goto err_set_hca;
1254 }
1255
1256 mlx5_vhca_event_start(dev);
1257
1258 err = mlx5_sf_hw_table_create(dev);
1259 if (err) {
1260 mlx5_core_err(dev, "sf table create failed %d\n", err);
1261 goto err_vhca;
1262 }
1263
1264 err = mlx5_ec_init(dev);
1265 if (err) {
1266 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1267 goto err_ec;
1268 }
1269
1270 mlx5_lag_add_mdev(dev);
1271 err = mlx5_sriov_attach(dev);
1272 if (err) {
1273 mlx5_core_err(dev, "sriov init failed %d\n", err);
1274 goto err_sriov;
1275 }
1276
1277 mlx5_sf_dev_table_create(dev);
1278
1279 return 0;
1280
1281 err_sriov:
1282 mlx5_lag_remove_mdev(dev);
1283 mlx5_ec_cleanup(dev);
1284 err_ec:
1285 mlx5_sf_hw_table_destroy(dev);
1286 err_vhca:
1287 mlx5_vhca_event_stop(dev);
1288 err_set_hca:
1289 mlx5_fs_core_cleanup(dev);
1290 err_fs:
1291 mlx5_fpga_device_stop(dev);
1292 err_fpga_start:
1293 mlx5_rsc_dump_cleanup(dev);
1294 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1295 mlx5_fw_reset_events_stop(dev);
1296 mlx5_fw_tracer_cleanup(dev->tracer);
1297 mlx5_eq_table_destroy(dev);
1298 err_eq_table:
1299 mlx5_irq_table_destroy(dev);
1300 err_irq_table:
1301 mlx5_pagealloc_stop(dev);
1302 mlx5_events_stop(dev);
1303 mlx5_put_uars_page(dev, dev->priv.uar);
1304 return err;
1305 }
1306
mlx5_unload(struct mlx5_core_dev * dev)1307 static void mlx5_unload(struct mlx5_core_dev *dev)
1308 {
1309 mlx5_sf_dev_table_destroy(dev);
1310 mlx5_sriov_detach(dev);
1311 mlx5_lag_remove_mdev(dev);
1312 mlx5_ec_cleanup(dev);
1313 mlx5_sf_hw_table_destroy(dev);
1314 mlx5_vhca_event_stop(dev);
1315 mlx5_fs_core_cleanup(dev);
1316 mlx5_fpga_device_stop(dev);
1317 mlx5_rsc_dump_cleanup(dev);
1318 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1319 mlx5_fw_reset_events_stop(dev);
1320 mlx5_fw_tracer_cleanup(dev->tracer);
1321 mlx5_eq_table_destroy(dev);
1322 mlx5_irq_table_destroy(dev);
1323 mlx5_pagealloc_stop(dev);
1324 mlx5_events_stop(dev);
1325 mlx5_put_uars_page(dev, dev->priv.uar);
1326 }
1327
mlx5_init_one(struct mlx5_core_dev * dev)1328 int mlx5_init_one(struct mlx5_core_dev *dev)
1329 {
1330 int err = 0;
1331
1332 mutex_lock(&dev->intf_state_mutex);
1333 dev->state = MLX5_DEVICE_STATE_UP;
1334
1335 err = mlx5_function_setup(dev, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1336 if (err)
1337 goto err_function;
1338
1339 err = mlx5_init_once(dev);
1340 if (err) {
1341 mlx5_core_err(dev, "sw objs init failed\n");
1342 goto function_teardown;
1343 }
1344
1345 err = mlx5_load(dev);
1346 if (err)
1347 goto err_load;
1348
1349 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1350
1351 err = mlx5_devlink_register(priv_to_devlink(dev));
1352 if (err)
1353 goto err_devlink_reg;
1354
1355 err = mlx5_register_device(dev);
1356 if (err)
1357 goto err_register;
1358
1359 mutex_unlock(&dev->intf_state_mutex);
1360 return 0;
1361
1362 err_register:
1363 mlx5_devlink_unregister(priv_to_devlink(dev));
1364 err_devlink_reg:
1365 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1366 mlx5_unload(dev);
1367 err_load:
1368 mlx5_cleanup_once(dev);
1369 function_teardown:
1370 mlx5_function_teardown(dev, true);
1371 err_function:
1372 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1373 mutex_unlock(&dev->intf_state_mutex);
1374 return err;
1375 }
1376
mlx5_uninit_one(struct mlx5_core_dev * dev)1377 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1378 {
1379 mutex_lock(&dev->intf_state_mutex);
1380
1381 mlx5_unregister_device(dev);
1382 mlx5_devlink_unregister(priv_to_devlink(dev));
1383
1384 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1385 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1386 __func__);
1387 mlx5_cleanup_once(dev);
1388 goto out;
1389 }
1390
1391 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1392 mlx5_unload(dev);
1393 mlx5_cleanup_once(dev);
1394 mlx5_function_teardown(dev, true);
1395 out:
1396 mutex_unlock(&dev->intf_state_mutex);
1397 }
1398
mlx5_load_one(struct mlx5_core_dev * dev,bool recovery)1399 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery)
1400 {
1401 int err = 0;
1402 u64 timeout;
1403
1404 mutex_lock(&dev->intf_state_mutex);
1405 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1406 mlx5_core_warn(dev, "interface is up, NOP\n");
1407 goto out;
1408 }
1409 /* remove any previous indication of internal error */
1410 dev->state = MLX5_DEVICE_STATE_UP;
1411
1412 if (recovery)
1413 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT);
1414 else
1415 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT);
1416 err = mlx5_function_setup(dev, timeout);
1417 if (err)
1418 goto err_function;
1419
1420 err = mlx5_load(dev);
1421 if (err)
1422 goto err_load;
1423
1424 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1425
1426 err = mlx5_attach_device(dev);
1427 if (err)
1428 goto err_attach;
1429
1430 mutex_unlock(&dev->intf_state_mutex);
1431 return 0;
1432
1433 err_attach:
1434 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1435 mlx5_unload(dev);
1436 err_load:
1437 mlx5_function_teardown(dev, false);
1438 err_function:
1439 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1440 out:
1441 mutex_unlock(&dev->intf_state_mutex);
1442 return err;
1443 }
1444
mlx5_unload_one(struct mlx5_core_dev * dev)1445 void mlx5_unload_one(struct mlx5_core_dev *dev)
1446 {
1447 mutex_lock(&dev->intf_state_mutex);
1448
1449 mlx5_detach_device(dev);
1450
1451 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1452 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1453 __func__);
1454 goto out;
1455 }
1456
1457 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1458 mlx5_unload(dev);
1459 mlx5_function_teardown(dev, false);
1460 out:
1461 mutex_unlock(&dev->intf_state_mutex);
1462 }
1463
1464 static const int types[] = {
1465 MLX5_CAP_GENERAL,
1466 MLX5_CAP_GENERAL_2,
1467 MLX5_CAP_ETHERNET_OFFLOADS,
1468 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1469 MLX5_CAP_ODP,
1470 MLX5_CAP_ATOMIC,
1471 MLX5_CAP_ROCE,
1472 MLX5_CAP_IPOIB_OFFLOADS,
1473 MLX5_CAP_FLOW_TABLE,
1474 MLX5_CAP_ESWITCH_FLOW_TABLE,
1475 MLX5_CAP_ESWITCH,
1476 MLX5_CAP_VECTOR_CALC,
1477 MLX5_CAP_QOS,
1478 MLX5_CAP_DEBUG,
1479 MLX5_CAP_DEV_MEM,
1480 MLX5_CAP_DEV_EVENT,
1481 MLX5_CAP_TLS,
1482 MLX5_CAP_VDPA_EMULATION,
1483 MLX5_CAP_IPSEC,
1484 MLX5_CAP_PORT_SELECTION,
1485 MLX5_CAP_DEV_SHAMPO,
1486 };
1487
mlx5_hca_caps_free(struct mlx5_core_dev * dev)1488 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1489 {
1490 int type;
1491 int i;
1492
1493 for (i = 0; i < ARRAY_SIZE(types); i++) {
1494 type = types[i];
1495 kfree(dev->caps.hca[type]);
1496 }
1497 }
1498
mlx5_hca_caps_alloc(struct mlx5_core_dev * dev)1499 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1500 {
1501 struct mlx5_hca_cap *cap;
1502 int type;
1503 int i;
1504
1505 for (i = 0; i < ARRAY_SIZE(types); i++) {
1506 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1507 if (!cap)
1508 goto err;
1509 type = types[i];
1510 dev->caps.hca[type] = cap;
1511 }
1512
1513 return 0;
1514
1515 err:
1516 mlx5_hca_caps_free(dev);
1517 return -ENOMEM;
1518 }
1519
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1520 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1521 {
1522 struct mlx5_priv *priv = &dev->priv;
1523 int err;
1524
1525 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1526 INIT_LIST_HEAD(&priv->ctx_list);
1527 spin_lock_init(&priv->ctx_lock);
1528 lockdep_register_key(&dev->lock_key);
1529 mutex_init(&dev->intf_state_mutex);
1530 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key);
1531
1532 mutex_init(&priv->bfregs.reg_head.lock);
1533 mutex_init(&priv->bfregs.wc_head.lock);
1534 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1535 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1536
1537 mutex_init(&priv->alloc_mutex);
1538 mutex_init(&priv->pgdir_mutex);
1539 INIT_LIST_HEAD(&priv->pgdir_list);
1540
1541 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1542 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device),
1543 mlx5_debugfs_root);
1544 INIT_LIST_HEAD(&priv->traps);
1545
1546 err = mlx5_tout_init(dev);
1547 if (err) {
1548 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1549 goto err_timeout_init;
1550 }
1551
1552 err = mlx5_health_init(dev);
1553 if (err)
1554 goto err_health_init;
1555
1556 err = mlx5_pagealloc_init(dev);
1557 if (err)
1558 goto err_pagealloc_init;
1559
1560 err = mlx5_adev_init(dev);
1561 if (err)
1562 goto err_adev_init;
1563
1564 err = mlx5_hca_caps_alloc(dev);
1565 if (err)
1566 goto err_hca_caps;
1567
1568 /* The conjunction of sw_vhca_id with sw_owner_id will be a global
1569 * unique id per function which uses mlx5_core.
1570 * Those values are supplied to FW as part of the init HCA command to
1571 * be used by both driver and FW when it's applicable.
1572 */
1573 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1,
1574 MAX_SW_VHCA_ID,
1575 GFP_KERNEL);
1576 if (dev->priv.sw_vhca_id < 0)
1577 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n",
1578 dev->priv.sw_vhca_id);
1579
1580 return 0;
1581
1582 err_hca_caps:
1583 mlx5_adev_cleanup(dev);
1584 err_adev_init:
1585 mlx5_pagealloc_cleanup(dev);
1586 err_pagealloc_init:
1587 mlx5_health_cleanup(dev);
1588 err_health_init:
1589 mlx5_tout_cleanup(dev);
1590 err_timeout_init:
1591 debugfs_remove(dev->priv.dbg.dbg_root);
1592 mutex_destroy(&priv->pgdir_mutex);
1593 mutex_destroy(&priv->alloc_mutex);
1594 mutex_destroy(&priv->bfregs.wc_head.lock);
1595 mutex_destroy(&priv->bfregs.reg_head.lock);
1596 mutex_destroy(&dev->intf_state_mutex);
1597 lockdep_unregister_key(&dev->lock_key);
1598 return err;
1599 }
1600
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1601 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1602 {
1603 struct mlx5_priv *priv = &dev->priv;
1604
1605 if (priv->sw_vhca_id > 0)
1606 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id);
1607
1608 mlx5_hca_caps_free(dev);
1609 mlx5_adev_cleanup(dev);
1610 mlx5_pagealloc_cleanup(dev);
1611 mlx5_health_cleanup(dev);
1612 mlx5_tout_cleanup(dev);
1613 debugfs_remove_recursive(dev->priv.dbg.dbg_root);
1614 mutex_destroy(&priv->pgdir_mutex);
1615 mutex_destroy(&priv->alloc_mutex);
1616 mutex_destroy(&priv->bfregs.wc_head.lock);
1617 mutex_destroy(&priv->bfregs.reg_head.lock);
1618 mutex_destroy(&dev->intf_state_mutex);
1619 lockdep_unregister_key(&dev->lock_key);
1620 }
1621
probe_one(struct pci_dev * pdev,const struct pci_device_id * id)1622 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1623 {
1624 struct mlx5_core_dev *dev;
1625 struct devlink *devlink;
1626 int err;
1627
1628 devlink = mlx5_devlink_alloc(&pdev->dev);
1629 if (!devlink) {
1630 dev_err(&pdev->dev, "devlink alloc failed\n");
1631 return -ENOMEM;
1632 }
1633
1634 dev = devlink_priv(devlink);
1635 dev->device = &pdev->dev;
1636 dev->pdev = pdev;
1637
1638 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1639 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1640
1641 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1642 if (dev->priv.adev_idx < 0) {
1643 err = dev->priv.adev_idx;
1644 goto adev_init_err;
1645 }
1646
1647 err = mlx5_mdev_init(dev, prof_sel);
1648 if (err)
1649 goto mdev_init_err;
1650
1651 err = mlx5_pci_init(dev, pdev, id);
1652 if (err) {
1653 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1654 err);
1655 goto pci_init_err;
1656 }
1657
1658 err = mlx5_init_one(dev);
1659 if (err) {
1660 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1661 err);
1662 goto err_init_one;
1663 }
1664
1665 err = mlx5_crdump_enable(dev);
1666 if (err)
1667 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1668
1669 pci_save_state(pdev);
1670 devlink_register(devlink);
1671 return 0;
1672
1673 err_init_one:
1674 mlx5_pci_close(dev);
1675 pci_init_err:
1676 mlx5_mdev_uninit(dev);
1677 mdev_init_err:
1678 mlx5_adev_idx_free(dev->priv.adev_idx);
1679 adev_init_err:
1680 mlx5_devlink_free(devlink);
1681
1682 return err;
1683 }
1684
remove_one(struct pci_dev * pdev)1685 static void remove_one(struct pci_dev *pdev)
1686 {
1687 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1688 struct devlink *devlink = priv_to_devlink(dev);
1689
1690 /* mlx5_drain_fw_reset() is using devlink APIs. Hence, we must drain
1691 * fw_reset before unregistering the devlink.
1692 */
1693 mlx5_drain_fw_reset(dev);
1694 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
1695 devlink_unregister(devlink);
1696 mlx5_sriov_disable(pdev);
1697 mlx5_crdump_disable(dev);
1698 mlx5_drain_health_wq(dev);
1699 mlx5_uninit_one(dev);
1700 mlx5_pci_close(dev);
1701 mlx5_mdev_uninit(dev);
1702 mlx5_adev_idx_free(dev->priv.adev_idx);
1703 mlx5_devlink_free(devlink);
1704 }
1705
1706 #define mlx5_pci_trace(dev, fmt, ...) ({ \
1707 struct mlx5_core_dev *__dev = (dev); \
1708 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
1709 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
1710 __dev->pci_status, ##__VA_ARGS__); \
1711 })
1712
result2str(enum pci_ers_result result)1713 static const char *result2str(enum pci_ers_result result)
1714 {
1715 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
1716 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
1717 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
1718 "unknown";
1719 }
1720
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)1721 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1722 pci_channel_state_t state)
1723 {
1724 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1725 enum pci_ers_result res;
1726
1727 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
1728
1729 mlx5_enter_error_state(dev, false);
1730 mlx5_error_sw_reset(dev);
1731 mlx5_unload_one(dev);
1732 mlx5_drain_health_wq(dev);
1733 mlx5_pci_disable_device(dev);
1734
1735 res = state == pci_channel_io_perm_failure ?
1736 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1737
1738 mlx5_pci_trace(dev, "Exit, result = %d, %s\n", res, result2str(res));
1739 return res;
1740 }
1741
1742 /* wait for the device to show vital signs by waiting
1743 * for the health counter to start counting.
1744 */
wait_vital(struct pci_dev * pdev)1745 static int wait_vital(struct pci_dev *pdev)
1746 {
1747 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1748 struct mlx5_core_health *health = &dev->priv.health;
1749 const int niter = 100;
1750 u32 last_count = 0;
1751 u32 count;
1752 int i;
1753
1754 for (i = 0; i < niter; i++) {
1755 count = ioread32be(health->health_counter);
1756 if (count && count != 0xffffffff) {
1757 if (last_count && last_count != count) {
1758 mlx5_core_info(dev,
1759 "wait vital counter value 0x%x after %d iterations\n",
1760 count, i);
1761 return 0;
1762 }
1763 last_count = count;
1764 }
1765 msleep(50);
1766 }
1767
1768 return -ETIMEDOUT;
1769 }
1770
mlx5_pci_slot_reset(struct pci_dev * pdev)1771 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1772 {
1773 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
1774 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1775 int err;
1776
1777 mlx5_pci_trace(dev, "Enter\n");
1778
1779 err = mlx5_pci_enable_device(dev);
1780 if (err) {
1781 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1782 __func__, err);
1783 goto out;
1784 }
1785
1786 pci_set_master(pdev);
1787 pci_restore_state(pdev);
1788 pci_save_state(pdev);
1789
1790 err = wait_vital(pdev);
1791 if (err) {
1792 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
1793 __func__, err);
1794 goto out;
1795 }
1796
1797 res = PCI_ERS_RESULT_RECOVERED;
1798 out:
1799 mlx5_pci_trace(dev, "Exit, err = %d, result = %d, %s\n", err, res, result2str(res));
1800 return res;
1801 }
1802
mlx5_pci_resume(struct pci_dev * pdev)1803 static void mlx5_pci_resume(struct pci_dev *pdev)
1804 {
1805 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1806 int err;
1807
1808 mlx5_pci_trace(dev, "Enter, loading driver..\n");
1809
1810 err = mlx5_load_one(dev, false);
1811
1812 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
1813 !err ? "recovered" : "Failed");
1814 }
1815
1816 static const struct pci_error_handlers mlx5_err_handler = {
1817 .error_detected = mlx5_pci_err_detected,
1818 .slot_reset = mlx5_pci_slot_reset,
1819 .resume = mlx5_pci_resume
1820 };
1821
mlx5_try_fast_unload(struct mlx5_core_dev * dev)1822 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1823 {
1824 bool fast_teardown = false, force_teardown = false;
1825 int ret = 1;
1826
1827 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1828 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1829
1830 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1831 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1832
1833 if (!fast_teardown && !force_teardown)
1834 return -EOPNOTSUPP;
1835
1836 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1837 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1838 return -EAGAIN;
1839 }
1840
1841 /* Panic tear down fw command will stop the PCI bus communication
1842 * with the HCA, so the health poll is no longer needed.
1843 */
1844 mlx5_drain_health_wq(dev);
1845 mlx5_stop_health_poll(dev, false);
1846
1847 ret = mlx5_cmd_fast_teardown_hca(dev);
1848 if (!ret)
1849 goto succeed;
1850
1851 ret = mlx5_cmd_force_teardown_hca(dev);
1852 if (!ret)
1853 goto succeed;
1854
1855 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1856 mlx5_start_health_poll(dev);
1857 return ret;
1858
1859 succeed:
1860 mlx5_enter_error_state(dev, true);
1861
1862 /* Some platforms requiring freeing the IRQ's in the shutdown
1863 * flow. If they aren't freed they can't be allocated after
1864 * kexec. There is no need to cleanup the mlx5_core software
1865 * contexts.
1866 */
1867 mlx5_core_eq_free_irqs(dev);
1868
1869 return 0;
1870 }
1871
shutdown(struct pci_dev * pdev)1872 static void shutdown(struct pci_dev *pdev)
1873 {
1874 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1875 int err;
1876
1877 mlx5_core_info(dev, "Shutdown was called\n");
1878 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
1879 err = mlx5_try_fast_unload(dev);
1880 if (err)
1881 mlx5_unload_one(dev);
1882 mlx5_pci_disable_device(dev);
1883 }
1884
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)1885 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1886 {
1887 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1888
1889 mlx5_unload_one(dev);
1890
1891 return 0;
1892 }
1893
mlx5_resume(struct pci_dev * pdev)1894 static int mlx5_resume(struct pci_dev *pdev)
1895 {
1896 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1897
1898 return mlx5_load_one(dev, false);
1899 }
1900
1901 static const struct pci_device_id mlx5_core_pci_table[] = {
1902 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1903 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1904 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1905 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1906 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1907 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1908 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1909 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1910 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1911 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1912 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1913 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1914 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1915 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1916 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1917 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1918 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
1919 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1920 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1921 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1922 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
1923 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
1924 { 0, }
1925 };
1926
1927 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1928
mlx5_disable_device(struct mlx5_core_dev * dev)1929 void mlx5_disable_device(struct mlx5_core_dev *dev)
1930 {
1931 mlx5_error_sw_reset(dev);
1932 mlx5_unload_one(dev);
1933 }
1934
mlx5_recover_device(struct mlx5_core_dev * dev)1935 int mlx5_recover_device(struct mlx5_core_dev *dev)
1936 {
1937 if (!mlx5_core_is_sf(dev)) {
1938 mlx5_pci_disable_device(dev);
1939 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
1940 return -EIO;
1941 }
1942
1943 return mlx5_load_one(dev, true);
1944 }
1945
1946 static struct pci_driver mlx5_core_driver = {
1947 .name = KBUILD_MODNAME,
1948 .id_table = mlx5_core_pci_table,
1949 .probe = probe_one,
1950 .remove = remove_one,
1951 .suspend = mlx5_suspend,
1952 .resume = mlx5_resume,
1953 .shutdown = shutdown,
1954 .err_handler = &mlx5_err_handler,
1955 .sriov_configure = mlx5_core_sriov_configure,
1956 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
1957 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
1958 };
1959
1960 /**
1961 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if
1962 * mlx5_core is its driver.
1963 * @pdev: The associated PCI device.
1964 *
1965 * Upon return the interface state lock stay held to let caller uses it safely.
1966 * Caller must ensure to use the returned mlx5 device for a narrow window
1967 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over.
1968 *
1969 * Return: Pointer to the associated mlx5_core_dev or NULL.
1970 */
mlx5_vf_get_core_dev(struct pci_dev * pdev)1971 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev)
1972 {
1973 struct mlx5_core_dev *mdev;
1974
1975 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver);
1976 if (IS_ERR(mdev))
1977 return NULL;
1978
1979 mutex_lock(&mdev->intf_state_mutex);
1980 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) {
1981 mutex_unlock(&mdev->intf_state_mutex);
1982 return NULL;
1983 }
1984
1985 return mdev;
1986 }
1987 EXPORT_SYMBOL(mlx5_vf_get_core_dev);
1988
1989 /**
1990 * mlx5_vf_put_core_dev - Put the mlx5 core device back.
1991 * @mdev: The mlx5 core device.
1992 *
1993 * Upon return the interface state lock is unlocked and caller should not
1994 * access the mdev any more.
1995 */
mlx5_vf_put_core_dev(struct mlx5_core_dev * mdev)1996 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev)
1997 {
1998 mutex_unlock(&mdev->intf_state_mutex);
1999 }
2000 EXPORT_SYMBOL(mlx5_vf_put_core_dev);
2001
mlx5_core_verify_params(void)2002 static void mlx5_core_verify_params(void)
2003 {
2004 if (prof_sel >= ARRAY_SIZE(profile)) {
2005 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
2006 prof_sel,
2007 ARRAY_SIZE(profile) - 1,
2008 MLX5_DEFAULT_PROF);
2009 prof_sel = MLX5_DEFAULT_PROF;
2010 }
2011 }
2012
init(void)2013 static int __init init(void)
2014 {
2015 int err;
2016
2017 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
2018 "mlx5_core name not in sync with kernel module name");
2019
2020 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
2021
2022 mlx5_core_verify_params();
2023 mlx5_register_debugfs();
2024
2025 err = pci_register_driver(&mlx5_core_driver);
2026 if (err)
2027 goto err_debug;
2028
2029 err = mlx5_sf_driver_register();
2030 if (err)
2031 goto err_sf;
2032
2033 err = mlx5e_init();
2034 if (err)
2035 goto err_en;
2036
2037 return 0;
2038
2039 err_en:
2040 mlx5_sf_driver_unregister();
2041 err_sf:
2042 pci_unregister_driver(&mlx5_core_driver);
2043 err_debug:
2044 mlx5_unregister_debugfs();
2045 return err;
2046 }
2047
cleanup(void)2048 static void __exit cleanup(void)
2049 {
2050 mlx5e_cleanup();
2051 mlx5_sf_driver_unregister();
2052 pci_unregister_driver(&mlx5_core_driver);
2053 mlx5_unregister_debugfs();
2054 }
2055
2056 module_init(init);
2057 module_exit(cleanup);
2058