1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2020, Mellanox Technologies inc. All rights reserved. */
3
4 #include "fw_reset.h"
5 #include "diag/fw_tracer.h"
6 #include "lib/tout.h"
7
8 enum {
9 MLX5_FW_RESET_FLAGS_RESET_REQUESTED,
10 MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
11 MLX5_FW_RESET_FLAGS_PENDING_COMP,
12 MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS,
13 MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED
14 };
15
16 struct mlx5_fw_reset {
17 struct mlx5_core_dev *dev;
18 struct mlx5_nb nb;
19 struct workqueue_struct *wq;
20 struct work_struct fw_live_patch_work;
21 struct work_struct reset_request_work;
22 struct work_struct reset_reload_work;
23 struct work_struct reset_now_work;
24 struct work_struct reset_abort_work;
25 unsigned long reset_flags;
26 struct timer_list timer;
27 struct completion done;
28 int ret;
29 };
30
mlx5_fw_reset_enable_remote_dev_reset_set(struct mlx5_core_dev * dev,bool enable)31 void mlx5_fw_reset_enable_remote_dev_reset_set(struct mlx5_core_dev *dev, bool enable)
32 {
33 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
34
35 if (enable)
36 clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
37 else
38 set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
39 }
40
mlx5_fw_reset_enable_remote_dev_reset_get(struct mlx5_core_dev * dev)41 bool mlx5_fw_reset_enable_remote_dev_reset_get(struct mlx5_core_dev *dev)
42 {
43 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
44
45 return !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
46 }
47
mlx5_reg_mfrl_set(struct mlx5_core_dev * dev,u8 reset_level,u8 reset_type_sel,u8 sync_resp,bool sync_start)48 static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level,
49 u8 reset_type_sel, u8 sync_resp, bool sync_start)
50 {
51 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
52 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
53
54 MLX5_SET(mfrl_reg, in, reset_level, reset_level);
55 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
56 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp);
57 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start);
58
59 return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1);
60 }
61
mlx5_reg_mfrl_query(struct mlx5_core_dev * dev,u8 * reset_level,u8 * reset_type,u8 * reset_state)62 static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level,
63 u8 *reset_type, u8 *reset_state)
64 {
65 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
66 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
67 int err;
68
69 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0);
70 if (err)
71 return err;
72
73 if (reset_level)
74 *reset_level = MLX5_GET(mfrl_reg, out, reset_level);
75 if (reset_type)
76 *reset_type = MLX5_GET(mfrl_reg, out, reset_type);
77 if (reset_state)
78 *reset_state = MLX5_GET(mfrl_reg, out, reset_state);
79
80 return 0;
81 }
82
mlx5_fw_reset_query(struct mlx5_core_dev * dev,u8 * reset_level,u8 * reset_type)83 int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type)
84 {
85 return mlx5_reg_mfrl_query(dev, reset_level, reset_type, NULL);
86 }
87
mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev * dev,struct netlink_ext_ack * extack)88 static int mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev *dev,
89 struct netlink_ext_ack *extack)
90 {
91 u8 reset_state;
92
93 if (mlx5_reg_mfrl_query(dev, NULL, NULL, &reset_state))
94 goto out;
95
96 switch (reset_state) {
97 case MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION:
98 case MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS:
99 NL_SET_ERR_MSG_MOD(extack, "Sync reset was already triggered");
100 return -EBUSY;
101 case MLX5_MFRL_REG_RESET_STATE_TIMEOUT:
102 NL_SET_ERR_MSG_MOD(extack, "Sync reset got timeout");
103 return -ETIMEDOUT;
104 case MLX5_MFRL_REG_RESET_STATE_NACK:
105 NL_SET_ERR_MSG_MOD(extack, "One of the hosts disabled reset");
106 return -EPERM;
107 }
108
109 out:
110 NL_SET_ERR_MSG_MOD(extack, "Sync reset failed");
111 return -EIO;
112 }
113
mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev * dev,u8 reset_type_sel,struct netlink_ext_ack * extack)114 int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *dev, u8 reset_type_sel,
115 struct netlink_ext_ack *extack)
116 {
117 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
118 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
119 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
120 int err;
121
122 set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
123
124 MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3);
125 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
126 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, 1);
127 err = mlx5_access_reg(dev, in, sizeof(in), out, sizeof(out),
128 MLX5_REG_MFRL, 0, 1, false);
129 if (!err)
130 return 0;
131
132 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
133 if (err == -EREMOTEIO && MLX5_CAP_MCAM_FEATURE(dev, reset_state))
134 return mlx5_fw_reset_get_reset_state_err(dev, extack);
135
136 NL_SET_ERR_MSG_MOD(extack, "Sync reset command failed");
137 return mlx5_cmd_check(dev, err, in, out);
138 }
139
mlx5_fw_reset_set_live_patch(struct mlx5_core_dev * dev)140 int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev)
141 {
142 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false);
143 }
144
mlx5_fw_reset_complete_reload(struct mlx5_core_dev * dev)145 static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev)
146 {
147 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
148
149 /* if this is the driver that initiated the fw reset, devlink completed the reload */
150 if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) {
151 complete(&fw_reset->done);
152 } else {
153 mlx5_unload_one(dev);
154 if (mlx5_health_wait_pci_up(dev))
155 mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
156 else
157 mlx5_load_one(dev, false);
158 devlink_remote_reload_actions_performed(priv_to_devlink(dev), 0,
159 BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
160 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));
161 }
162 }
163
mlx5_stop_sync_reset_poll(struct mlx5_core_dev * dev)164 static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev)
165 {
166 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
167
168 del_timer_sync(&fw_reset->timer);
169 }
170
mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev * dev,bool poll_health)171 static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health)
172 {
173 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
174
175 if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
176 mlx5_core_warn(dev, "Reset request was already cleared\n");
177 return -EALREADY;
178 }
179
180 mlx5_stop_sync_reset_poll(dev);
181 if (poll_health)
182 mlx5_start_health_poll(dev);
183 return 0;
184 }
185
mlx5_sync_reset_reload_work(struct work_struct * work)186 static void mlx5_sync_reset_reload_work(struct work_struct *work)
187 {
188 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
189 reset_reload_work);
190 struct mlx5_core_dev *dev = fw_reset->dev;
191
192 mlx5_sync_reset_clear_reset_requested(dev, false);
193 mlx5_enter_error_state(dev, true);
194 mlx5_fw_reset_complete_reload(dev);
195 }
196
197 #define MLX5_RESET_POLL_INTERVAL (HZ / 10)
poll_sync_reset(struct timer_list * t)198 static void poll_sync_reset(struct timer_list *t)
199 {
200 struct mlx5_fw_reset *fw_reset = from_timer(fw_reset, t, timer);
201 struct mlx5_core_dev *dev = fw_reset->dev;
202 u32 fatal_error;
203
204 if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))
205 return;
206
207 fatal_error = mlx5_health_check_fatal_sensors(dev);
208
209 if (fatal_error) {
210 mlx5_core_warn(dev, "Got Device Reset\n");
211 if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
212 queue_work(fw_reset->wq, &fw_reset->reset_reload_work);
213 else
214 mlx5_core_err(dev, "Device is being removed, Drop new reset work\n");
215 return;
216 }
217
218 mod_timer(&fw_reset->timer, round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL));
219 }
220
mlx5_start_sync_reset_poll(struct mlx5_core_dev * dev)221 static void mlx5_start_sync_reset_poll(struct mlx5_core_dev *dev)
222 {
223 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
224
225 timer_setup(&fw_reset->timer, poll_sync_reset, 0);
226 fw_reset->timer.expires = round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL);
227 add_timer(&fw_reset->timer);
228 }
229
mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev * dev)230 static int mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev *dev)
231 {
232 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 1, false);
233 }
234
mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev * dev)235 static int mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev *dev)
236 {
237 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false);
238 }
239
mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev * dev)240 static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev)
241 {
242 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
243
244 if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
245 mlx5_core_warn(dev, "Reset request was already set\n");
246 return -EALREADY;
247 }
248 mlx5_stop_health_poll(dev, true);
249 mlx5_start_sync_reset_poll(dev);
250 return 0;
251 }
252
mlx5_fw_live_patch_event(struct work_struct * work)253 static void mlx5_fw_live_patch_event(struct work_struct *work)
254 {
255 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
256 fw_live_patch_work);
257 struct mlx5_core_dev *dev = fw_reset->dev;
258
259 mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev),
260 fw_rev_min(dev), fw_rev_sub(dev));
261
262 if (mlx5_fw_tracer_reload(dev->tracer))
263 mlx5_core_err(dev, "Failed to reload FW tracer\n");
264 }
265
mlx5_sync_reset_request_event(struct work_struct * work)266 static void mlx5_sync_reset_request_event(struct work_struct *work)
267 {
268 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
269 reset_request_work);
270 struct mlx5_core_dev *dev = fw_reset->dev;
271 int err;
272
273 if (test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags)) {
274 err = mlx5_fw_reset_set_reset_sync_nack(dev);
275 mlx5_core_warn(dev, "PCI Sync FW Update Reset Nack %s",
276 err ? "Failed" : "Sent");
277 return;
278 }
279 if (mlx5_sync_reset_set_reset_requested(dev))
280 return;
281
282 err = mlx5_fw_reset_set_reset_sync_ack(dev);
283 if (err)
284 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err);
285 else
286 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack. Device reset is expected.\n");
287 }
288
mlx5_pci_link_toggle(struct mlx5_core_dev * dev)289 static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev)
290 {
291 struct pci_bus *bridge_bus = dev->pdev->bus;
292 struct pci_dev *bridge = bridge_bus->self;
293 u16 reg16, dev_id, sdev_id;
294 unsigned long timeout;
295 struct pci_dev *sdev;
296 int cap, err;
297 u32 reg32;
298
299 /* Check that all functions under the pci bridge are PFs of
300 * this device otherwise fail this function.
301 */
302 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
303 if (err)
304 return err;
305 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
306 err = pci_read_config_word(sdev, PCI_DEVICE_ID, &sdev_id);
307 if (err)
308 return err;
309 if (sdev_id != dev_id)
310 return -EPERM;
311 }
312
313 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
314 if (!cap)
315 return -EOPNOTSUPP;
316
317 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
318 pci_save_state(sdev);
319 pci_cfg_access_lock(sdev);
320 }
321 /* PCI link toggle */
322 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKCTL, ®16);
323 if (err)
324 return err;
325 reg16 |= PCI_EXP_LNKCTL_LD;
326 err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16);
327 if (err)
328 return err;
329 msleep(500);
330 reg16 &= ~PCI_EXP_LNKCTL_LD;
331 err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16);
332 if (err)
333 return err;
334
335 /* Check link */
336 err = pci_read_config_dword(bridge, cap + PCI_EXP_LNKCAP, ®32);
337 if (err)
338 return err;
339 if (!(reg32 & PCI_EXP_LNKCAP_DLLLARC)) {
340 mlx5_core_warn(dev, "No PCI link reporting capability (0x%08x)\n", reg32);
341 msleep(1000);
342 goto restore;
343 }
344
345 timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, PCI_TOGGLE));
346 do {
347 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKSTA, ®16);
348 if (err)
349 return err;
350 if (reg16 & PCI_EXP_LNKSTA_DLLLA)
351 break;
352 msleep(20);
353 } while (!time_after(jiffies, timeout));
354
355 if (reg16 & PCI_EXP_LNKSTA_DLLLA) {
356 mlx5_core_info(dev, "PCI Link up\n");
357 } else {
358 mlx5_core_err(dev, "PCI link not ready (0x%04x) after %llu ms\n",
359 reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
360 err = -ETIMEDOUT;
361 }
362
363 do {
364 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, ®16);
365 if (err)
366 return err;
367 if (reg16 == dev_id)
368 break;
369 msleep(20);
370 } while (!time_after(jiffies, timeout));
371
372 if (reg16 == dev_id) {
373 mlx5_core_info(dev, "Firmware responds to PCI config cycles again\n");
374 } else {
375 mlx5_core_err(dev, "Firmware is not responsive (0x%04x) after %llu ms\n",
376 reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
377 err = -ETIMEDOUT;
378 }
379
380 restore:
381 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
382 pci_cfg_access_unlock(sdev);
383 pci_restore_state(sdev);
384 }
385
386 return err;
387 }
388
mlx5_sync_reset_now_event(struct work_struct * work)389 static void mlx5_sync_reset_now_event(struct work_struct *work)
390 {
391 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
392 reset_now_work);
393 struct mlx5_core_dev *dev = fw_reset->dev;
394 int err;
395
396 if (mlx5_sync_reset_clear_reset_requested(dev, false))
397 return;
398
399 mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n");
400
401 err = mlx5_cmd_fast_teardown_hca(dev);
402 if (err) {
403 mlx5_core_warn(dev, "Fast teardown failed, no reset done, err %d\n", err);
404 goto done;
405 }
406
407 err = mlx5_pci_link_toggle(dev);
408 if (err) {
409 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, no reset done, err %d\n", err);
410 set_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags);
411 }
412
413 mlx5_enter_error_state(dev, true);
414 done:
415 fw_reset->ret = err;
416 mlx5_fw_reset_complete_reload(dev);
417 }
418
mlx5_sync_reset_abort_event(struct work_struct * work)419 static void mlx5_sync_reset_abort_event(struct work_struct *work)
420 {
421 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
422 reset_abort_work);
423 struct mlx5_core_dev *dev = fw_reset->dev;
424
425 if (mlx5_sync_reset_clear_reset_requested(dev, true))
426 return;
427 mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n");
428 }
429
mlx5_sync_reset_events_handle(struct mlx5_fw_reset * fw_reset,struct mlx5_eqe * eqe)430 static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe)
431 {
432 struct mlx5_eqe_sync_fw_update *sync_fw_update_eqe;
433 u8 sync_event_rst_type;
434
435 sync_fw_update_eqe = &eqe->data.sync_fw_update;
436 sync_event_rst_type = sync_fw_update_eqe->sync_rst_state & SYNC_RST_STATE_MASK;
437 switch (sync_event_rst_type) {
438 case MLX5_SYNC_RST_STATE_RESET_REQUEST:
439 queue_work(fw_reset->wq, &fw_reset->reset_request_work);
440 break;
441 case MLX5_SYNC_RST_STATE_RESET_NOW:
442 queue_work(fw_reset->wq, &fw_reset->reset_now_work);
443 break;
444 case MLX5_SYNC_RST_STATE_RESET_ABORT:
445 queue_work(fw_reset->wq, &fw_reset->reset_abort_work);
446 break;
447 }
448 }
449
fw_reset_event_notifier(struct notifier_block * nb,unsigned long action,void * data)450 static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long action, void *data)
451 {
452 struct mlx5_fw_reset *fw_reset = mlx5_nb_cof(nb, struct mlx5_fw_reset, nb);
453 struct mlx5_eqe *eqe = data;
454
455 if (test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
456 return NOTIFY_DONE;
457
458 switch (eqe->sub_type) {
459 case MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT:
460 queue_work(fw_reset->wq, &fw_reset->fw_live_patch_work);
461 break;
462 case MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT:
463 mlx5_sync_reset_events_handle(fw_reset, eqe);
464 break;
465 default:
466 return NOTIFY_DONE;
467 }
468
469 return NOTIFY_OK;
470 }
471
mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev * dev)472 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev)
473 {
474 unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE);
475 unsigned long timeout = msecs_to_jiffies(pci_sync_update_timeout);
476 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
477 int err;
478
479 if (!wait_for_completion_timeout(&fw_reset->done, timeout)) {
480 mlx5_core_warn(dev, "FW sync reset timeout after %lu seconds\n",
481 pci_sync_update_timeout / 1000);
482 err = -ETIMEDOUT;
483 goto out;
484 }
485 err = fw_reset->ret;
486 if (test_and_clear_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags)) {
487 mlx5_unload_one_devl_locked(dev);
488 mlx5_load_one_devl_locked(dev, false);
489 }
490 out:
491 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
492 return err;
493 }
494
mlx5_fw_reset_events_start(struct mlx5_core_dev * dev)495 void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev)
496 {
497 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
498
499 MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT);
500 mlx5_eq_notifier_register(dev, &fw_reset->nb);
501 }
502
mlx5_fw_reset_events_stop(struct mlx5_core_dev * dev)503 void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev)
504 {
505 mlx5_eq_notifier_unregister(dev, &dev->priv.fw_reset->nb);
506 }
507
mlx5_drain_fw_reset(struct mlx5_core_dev * dev)508 void mlx5_drain_fw_reset(struct mlx5_core_dev *dev)
509 {
510 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
511
512 set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags);
513 cancel_work_sync(&fw_reset->fw_live_patch_work);
514 cancel_work_sync(&fw_reset->reset_request_work);
515 cancel_work_sync(&fw_reset->reset_reload_work);
516 cancel_work_sync(&fw_reset->reset_now_work);
517 cancel_work_sync(&fw_reset->reset_abort_work);
518 }
519
mlx5_fw_reset_init(struct mlx5_core_dev * dev)520 int mlx5_fw_reset_init(struct mlx5_core_dev *dev)
521 {
522 struct mlx5_fw_reset *fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL);
523
524 if (!fw_reset)
525 return -ENOMEM;
526 fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events");
527 if (!fw_reset->wq) {
528 kfree(fw_reset);
529 return -ENOMEM;
530 }
531
532 fw_reset->dev = dev;
533 dev->priv.fw_reset = fw_reset;
534
535 INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event);
536 INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event);
537 INIT_WORK(&fw_reset->reset_reload_work, mlx5_sync_reset_reload_work);
538 INIT_WORK(&fw_reset->reset_now_work, mlx5_sync_reset_now_event);
539 INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event);
540
541 init_completion(&fw_reset->done);
542 return 0;
543 }
544
mlx5_fw_reset_cleanup(struct mlx5_core_dev * dev)545 void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev)
546 {
547 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
548
549 destroy_workqueue(fw_reset->wq);
550 kfree(dev->priv.fw_reset);
551 }
552