1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2019 Mellanox Technologies */
3
4 #include <devlink.h>
5
6 #include "mlx5_core.h"
7 #include "fw_reset.h"
8 #include "fs_core.h"
9 #include "eswitch.h"
10 #include "esw/qos.h"
11 #include "sf/dev/dev.h"
12 #include "sf/sf.h"
13
mlx5_devlink_flash_update(struct devlink * devlink,struct devlink_flash_update_params * params,struct netlink_ext_ack * extack)14 static int mlx5_devlink_flash_update(struct devlink *devlink,
15 struct devlink_flash_update_params *params,
16 struct netlink_ext_ack *extack)
17 {
18 struct mlx5_core_dev *dev = devlink_priv(devlink);
19
20 return mlx5_firmware_flash(dev, params->fw, extack);
21 }
22
mlx5_fw_ver_major(u32 version)23 static u8 mlx5_fw_ver_major(u32 version)
24 {
25 return (version >> 24) & 0xff;
26 }
27
mlx5_fw_ver_minor(u32 version)28 static u8 mlx5_fw_ver_minor(u32 version)
29 {
30 return (version >> 16) & 0xff;
31 }
32
mlx5_fw_ver_subminor(u32 version)33 static u16 mlx5_fw_ver_subminor(u32 version)
34 {
35 return version & 0xffff;
36 }
37
38 #define DEVLINK_FW_STRING_LEN 32
39
40 static int
mlx5_devlink_info_get(struct devlink * devlink,struct devlink_info_req * req,struct netlink_ext_ack * extack)41 mlx5_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
42 struct netlink_ext_ack *extack)
43 {
44 struct mlx5_core_dev *dev = devlink_priv(devlink);
45 char version_str[DEVLINK_FW_STRING_LEN];
46 u32 running_fw, stored_fw;
47 int err;
48
49 err = devlink_info_version_fixed_put(req, "fw.psid", dev->board_id);
50 if (err)
51 return err;
52
53 err = mlx5_fw_version_query(dev, &running_fw, &stored_fw);
54 if (err)
55 return err;
56
57 snprintf(version_str, sizeof(version_str), "%d.%d.%04d",
58 mlx5_fw_ver_major(running_fw), mlx5_fw_ver_minor(running_fw),
59 mlx5_fw_ver_subminor(running_fw));
60 err = devlink_info_version_running_put(req, "fw.version", version_str);
61 if (err)
62 return err;
63 err = devlink_info_version_running_put(req,
64 DEVLINK_INFO_VERSION_GENERIC_FW,
65 version_str);
66 if (err)
67 return err;
68
69 /* no pending version, return running (stored) version */
70 if (stored_fw == 0)
71 stored_fw = running_fw;
72
73 snprintf(version_str, sizeof(version_str), "%d.%d.%04d",
74 mlx5_fw_ver_major(stored_fw), mlx5_fw_ver_minor(stored_fw),
75 mlx5_fw_ver_subminor(stored_fw));
76 err = devlink_info_version_stored_put(req, "fw.version", version_str);
77 if (err)
78 return err;
79 return devlink_info_version_stored_put(req,
80 DEVLINK_INFO_VERSION_GENERIC_FW,
81 version_str);
82 }
83
mlx5_devlink_reload_fw_activate(struct devlink * devlink,struct netlink_ext_ack * extack)84 static int mlx5_devlink_reload_fw_activate(struct devlink *devlink, struct netlink_ext_ack *extack)
85 {
86 struct mlx5_core_dev *dev = devlink_priv(devlink);
87 u8 reset_level, reset_type, net_port_alive;
88 int err;
89
90 err = mlx5_fw_reset_query(dev, &reset_level, &reset_type);
91 if (err)
92 return err;
93 if (!(reset_level & MLX5_MFRL_REG_RESET_LEVEL3)) {
94 NL_SET_ERR_MSG_MOD(extack, "FW activate requires reboot");
95 return -EINVAL;
96 }
97
98 net_port_alive = !!(reset_type & MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE);
99 err = mlx5_fw_reset_set_reset_sync(dev, net_port_alive, extack);
100 if (err)
101 return err;
102
103 err = mlx5_fw_reset_wait_reset_done(dev);
104 if (err)
105 return err;
106
107 mlx5_unload_one_devl_locked(dev, true);
108 err = mlx5_health_wait_pci_up(dev);
109 if (err)
110 NL_SET_ERR_MSG_MOD(extack, "FW activate aborted, PCI reads fail after reset");
111
112 return err;
113 }
114
mlx5_devlink_trigger_fw_live_patch(struct devlink * devlink,struct netlink_ext_ack * extack)115 static int mlx5_devlink_trigger_fw_live_patch(struct devlink *devlink,
116 struct netlink_ext_ack *extack)
117 {
118 struct mlx5_core_dev *dev = devlink_priv(devlink);
119 u8 reset_level;
120 int err;
121
122 err = mlx5_fw_reset_query(dev, &reset_level, NULL);
123 if (err)
124 return err;
125 if (!(reset_level & MLX5_MFRL_REG_RESET_LEVEL0)) {
126 NL_SET_ERR_MSG_MOD(extack,
127 "FW upgrade to the stored FW can't be done by FW live patching");
128 return -EINVAL;
129 }
130
131 return mlx5_fw_reset_set_live_patch(dev);
132 }
133
mlx5_devlink_reload_down(struct devlink * devlink,bool netns_change,enum devlink_reload_action action,enum devlink_reload_limit limit,struct netlink_ext_ack * extack)134 static int mlx5_devlink_reload_down(struct devlink *devlink, bool netns_change,
135 enum devlink_reload_action action,
136 enum devlink_reload_limit limit,
137 struct netlink_ext_ack *extack)
138 {
139 struct mlx5_core_dev *dev = devlink_priv(devlink);
140 struct pci_dev *pdev = dev->pdev;
141 bool sf_dev_allocated;
142 int ret = 0;
143
144 if (mlx5_dev_is_lightweight(dev)) {
145 if (action != DEVLINK_RELOAD_ACTION_DRIVER_REINIT)
146 return -EOPNOTSUPP;
147 mlx5_unload_one_light(dev);
148 return 0;
149 }
150
151 sf_dev_allocated = mlx5_sf_dev_allocated(dev);
152 if (sf_dev_allocated) {
153 /* Reload results in deleting SF device which further results in
154 * unregistering devlink instance while holding devlink_mutext.
155 * Hence, do not support reload.
156 */
157 NL_SET_ERR_MSG_MOD(extack, "reload is unsupported when SFs are allocated");
158 return -EOPNOTSUPP;
159 }
160
161 if (mlx5_lag_is_active(dev)) {
162 NL_SET_ERR_MSG_MOD(extack, "reload is unsupported in Lag mode");
163 return -EOPNOTSUPP;
164 }
165
166 if (mlx5_core_is_mp_slave(dev)) {
167 NL_SET_ERR_MSG_MOD(extack, "reload is unsupported for multi port slave");
168 return -EOPNOTSUPP;
169 }
170
171 if (mlx5_core_is_pf(dev) && pci_num_vf(pdev))
172 NL_SET_ERR_MSG_MOD(extack, "reload while VFs are present is unfavorable");
173
174 switch (action) {
175 case DEVLINK_RELOAD_ACTION_DRIVER_REINIT:
176 mlx5_unload_one_devl_locked(dev, false);
177 break;
178 case DEVLINK_RELOAD_ACTION_FW_ACTIVATE:
179 if (limit == DEVLINK_RELOAD_LIMIT_NO_RESET)
180 ret = mlx5_devlink_trigger_fw_live_patch(devlink, extack);
181 else
182 ret = mlx5_devlink_reload_fw_activate(devlink, extack);
183 break;
184 default:
185 /* Unsupported action should not get to this function */
186 WARN_ON(1);
187 ret = -EOPNOTSUPP;
188 }
189
190 return ret;
191 }
192
mlx5_devlink_reload_up(struct devlink * devlink,enum devlink_reload_action action,enum devlink_reload_limit limit,u32 * actions_performed,struct netlink_ext_ack * extack)193 static int mlx5_devlink_reload_up(struct devlink *devlink, enum devlink_reload_action action,
194 enum devlink_reload_limit limit, u32 *actions_performed,
195 struct netlink_ext_ack *extack)
196 {
197 struct mlx5_core_dev *dev = devlink_priv(devlink);
198 int ret = 0;
199
200 *actions_performed = BIT(action);
201 switch (action) {
202 case DEVLINK_RELOAD_ACTION_DRIVER_REINIT:
203 if (mlx5_dev_is_lightweight(dev)) {
204 mlx5_fw_reporters_create(dev);
205 return mlx5_init_one_devl_locked(dev);
206 }
207 ret = mlx5_load_one_devl_locked(dev, false);
208 break;
209 case DEVLINK_RELOAD_ACTION_FW_ACTIVATE:
210 if (limit == DEVLINK_RELOAD_LIMIT_NO_RESET)
211 break;
212 /* On fw_activate action, also driver is reloaded and reinit performed */
213 *actions_performed |= BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT);
214 ret = mlx5_load_one_devl_locked(dev, true);
215 if (ret)
216 return ret;
217 ret = mlx5_fw_reset_verify_fw_complete(dev, extack);
218 break;
219 default:
220 /* Unsupported action should not get to this function */
221 WARN_ON(1);
222 ret = -EOPNOTSUPP;
223 }
224
225 return ret;
226 }
227
mlx5_find_trap_by_id(struct mlx5_core_dev * dev,int trap_id)228 static struct mlx5_devlink_trap *mlx5_find_trap_by_id(struct mlx5_core_dev *dev, int trap_id)
229 {
230 struct mlx5_devlink_trap *dl_trap;
231
232 list_for_each_entry(dl_trap, &dev->priv.traps, list)
233 if (dl_trap->trap.id == trap_id)
234 return dl_trap;
235
236 return NULL;
237 }
238
mlx5_devlink_trap_init(struct devlink * devlink,const struct devlink_trap * trap,void * trap_ctx)239 static int mlx5_devlink_trap_init(struct devlink *devlink, const struct devlink_trap *trap,
240 void *trap_ctx)
241 {
242 struct mlx5_core_dev *dev = devlink_priv(devlink);
243 struct mlx5_devlink_trap *dl_trap;
244
245 dl_trap = kzalloc(sizeof(*dl_trap), GFP_KERNEL);
246 if (!dl_trap)
247 return -ENOMEM;
248
249 dl_trap->trap.id = trap->id;
250 dl_trap->trap.action = DEVLINK_TRAP_ACTION_DROP;
251 dl_trap->item = trap_ctx;
252
253 if (mlx5_find_trap_by_id(dev, trap->id)) {
254 kfree(dl_trap);
255 mlx5_core_err(dev, "Devlink trap: Trap 0x%x already found", trap->id);
256 return -EEXIST;
257 }
258
259 list_add_tail(&dl_trap->list, &dev->priv.traps);
260 return 0;
261 }
262
mlx5_devlink_trap_fini(struct devlink * devlink,const struct devlink_trap * trap,void * trap_ctx)263 static void mlx5_devlink_trap_fini(struct devlink *devlink, const struct devlink_trap *trap,
264 void *trap_ctx)
265 {
266 struct mlx5_core_dev *dev = devlink_priv(devlink);
267 struct mlx5_devlink_trap *dl_trap;
268
269 dl_trap = mlx5_find_trap_by_id(dev, trap->id);
270 if (!dl_trap) {
271 mlx5_core_err(dev, "Devlink trap: Missing trap id 0x%x", trap->id);
272 return;
273 }
274 list_del(&dl_trap->list);
275 kfree(dl_trap);
276 }
277
mlx5_devlink_trap_action_set(struct devlink * devlink,const struct devlink_trap * trap,enum devlink_trap_action action,struct netlink_ext_ack * extack)278 static int mlx5_devlink_trap_action_set(struct devlink *devlink,
279 const struct devlink_trap *trap,
280 enum devlink_trap_action action,
281 struct netlink_ext_ack *extack)
282 {
283 struct mlx5_core_dev *dev = devlink_priv(devlink);
284 struct mlx5_devlink_trap_event_ctx trap_event_ctx;
285 enum devlink_trap_action action_orig;
286 struct mlx5_devlink_trap *dl_trap;
287 int err;
288
289 if (is_mdev_switchdev_mode(dev)) {
290 NL_SET_ERR_MSG_MOD(extack, "Devlink traps can't be set in switchdev mode");
291 return -EOPNOTSUPP;
292 }
293
294 dl_trap = mlx5_find_trap_by_id(dev, trap->id);
295 if (!dl_trap) {
296 mlx5_core_err(dev, "Devlink trap: Set action on invalid trap id 0x%x", trap->id);
297 return -EINVAL;
298 }
299
300 if (action != DEVLINK_TRAP_ACTION_DROP && action != DEVLINK_TRAP_ACTION_TRAP)
301 return -EOPNOTSUPP;
302
303 if (action == dl_trap->trap.action)
304 return 0;
305
306 action_orig = dl_trap->trap.action;
307 dl_trap->trap.action = action;
308 trap_event_ctx.trap = &dl_trap->trap;
309 trap_event_ctx.err = 0;
310 err = mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_TYPE_TRAP,
311 &trap_event_ctx);
312 if (err == NOTIFY_BAD)
313 dl_trap->trap.action = action_orig;
314
315 return trap_event_ctx.err;
316 }
317
318 static const struct devlink_ops mlx5_devlink_ops = {
319 #ifdef CONFIG_MLX5_ESWITCH
320 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
321 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
322 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
323 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
324 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
325 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
326 .rate_leaf_tx_share_set = mlx5_esw_devlink_rate_leaf_tx_share_set,
327 .rate_leaf_tx_max_set = mlx5_esw_devlink_rate_leaf_tx_max_set,
328 .rate_node_tx_share_set = mlx5_esw_devlink_rate_node_tx_share_set,
329 .rate_node_tx_max_set = mlx5_esw_devlink_rate_node_tx_max_set,
330 .rate_node_new = mlx5_esw_devlink_rate_node_new,
331 .rate_node_del = mlx5_esw_devlink_rate_node_del,
332 .rate_leaf_parent_set = mlx5_esw_devlink_rate_parent_set,
333 #endif
334 #ifdef CONFIG_MLX5_SF_MANAGER
335 .port_new = mlx5_devlink_sf_port_new,
336 #endif
337 .flash_update = mlx5_devlink_flash_update,
338 .info_get = mlx5_devlink_info_get,
339 .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
340 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE),
341 .reload_limits = BIT(DEVLINK_RELOAD_LIMIT_NO_RESET),
342 .reload_down = mlx5_devlink_reload_down,
343 .reload_up = mlx5_devlink_reload_up,
344 .trap_init = mlx5_devlink_trap_init,
345 .trap_fini = mlx5_devlink_trap_fini,
346 .trap_action_set = mlx5_devlink_trap_action_set,
347 };
348
mlx5_devlink_trap_report(struct mlx5_core_dev * dev,int trap_id,struct sk_buff * skb,struct devlink_port * dl_port)349 void mlx5_devlink_trap_report(struct mlx5_core_dev *dev, int trap_id, struct sk_buff *skb,
350 struct devlink_port *dl_port)
351 {
352 struct devlink *devlink = priv_to_devlink(dev);
353 struct mlx5_devlink_trap *dl_trap;
354
355 dl_trap = mlx5_find_trap_by_id(dev, trap_id);
356 if (!dl_trap) {
357 mlx5_core_err(dev, "Devlink trap: Report on invalid trap id 0x%x", trap_id);
358 return;
359 }
360
361 if (dl_trap->trap.action != DEVLINK_TRAP_ACTION_TRAP) {
362 mlx5_core_dbg(dev, "Devlink trap: Trap id %d has action %d", trap_id,
363 dl_trap->trap.action);
364 return;
365 }
366 devlink_trap_report(devlink, skb, dl_trap->item, dl_port, NULL);
367 }
368
mlx5_devlink_trap_get_num_active(struct mlx5_core_dev * dev)369 int mlx5_devlink_trap_get_num_active(struct mlx5_core_dev *dev)
370 {
371 struct mlx5_devlink_trap *dl_trap;
372 int count = 0;
373
374 list_for_each_entry(dl_trap, &dev->priv.traps, list)
375 if (dl_trap->trap.action == DEVLINK_TRAP_ACTION_TRAP)
376 count++;
377
378 return count;
379 }
380
mlx5_devlink_traps_get_action(struct mlx5_core_dev * dev,int trap_id,enum devlink_trap_action * action)381 int mlx5_devlink_traps_get_action(struct mlx5_core_dev *dev, int trap_id,
382 enum devlink_trap_action *action)
383 {
384 struct mlx5_devlink_trap *dl_trap;
385
386 dl_trap = mlx5_find_trap_by_id(dev, trap_id);
387 if (!dl_trap) {
388 mlx5_core_err(dev, "Devlink trap: Get action on invalid trap id 0x%x",
389 trap_id);
390 return -EINVAL;
391 }
392
393 *action = dl_trap->trap.action;
394 return 0;
395 }
396
mlx5_devlink_alloc(struct device * dev)397 struct devlink *mlx5_devlink_alloc(struct device *dev)
398 {
399 return devlink_alloc(&mlx5_devlink_ops, sizeof(struct mlx5_core_dev),
400 dev);
401 }
402
mlx5_devlink_free(struct devlink * devlink)403 void mlx5_devlink_free(struct devlink *devlink)
404 {
405 devlink_free(devlink);
406 }
407
mlx5_devlink_enable_roce_validate(struct devlink * devlink,u32 id,union devlink_param_value val,struct netlink_ext_ack * extack)408 static int mlx5_devlink_enable_roce_validate(struct devlink *devlink, u32 id,
409 union devlink_param_value val,
410 struct netlink_ext_ack *extack)
411 {
412 struct mlx5_core_dev *dev = devlink_priv(devlink);
413 bool new_state = val.vbool;
414
415 if (new_state && !MLX5_CAP_GEN(dev, roce) &&
416 !(MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))) {
417 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support RoCE");
418 return -EOPNOTSUPP;
419 }
420 if (mlx5_core_is_mp_slave(dev) || mlx5_lag_is_active(dev)) {
421 NL_SET_ERR_MSG_MOD(extack, "Multi port slave/Lag device can't configure RoCE");
422 return -EOPNOTSUPP;
423 }
424
425 return 0;
426 }
427
428 #ifdef CONFIG_MLX5_ESWITCH
mlx5_devlink_large_group_num_validate(struct devlink * devlink,u32 id,union devlink_param_value val,struct netlink_ext_ack * extack)429 static int mlx5_devlink_large_group_num_validate(struct devlink *devlink, u32 id,
430 union devlink_param_value val,
431 struct netlink_ext_ack *extack)
432 {
433 int group_num = val.vu32;
434
435 if (group_num < 1 || group_num > 1024) {
436 NL_SET_ERR_MSG_MOD(extack,
437 "Unsupported group number, supported range is 1-1024");
438 return -EOPNOTSUPP;
439 }
440
441 return 0;
442 }
443 #endif
444
mlx5_devlink_eq_depth_validate(struct devlink * devlink,u32 id,union devlink_param_value val,struct netlink_ext_ack * extack)445 static int mlx5_devlink_eq_depth_validate(struct devlink *devlink, u32 id,
446 union devlink_param_value val,
447 struct netlink_ext_ack *extack)
448 {
449 return (val.vu32 >= 64 && val.vu32 <= 4096) ? 0 : -EINVAL;
450 }
451
452 static int
mlx5_devlink_hairpin_num_queues_validate(struct devlink * devlink,u32 id,union devlink_param_value val,struct netlink_ext_ack * extack)453 mlx5_devlink_hairpin_num_queues_validate(struct devlink *devlink, u32 id,
454 union devlink_param_value val,
455 struct netlink_ext_ack *extack)
456 {
457 return val.vu32 ? 0 : -EINVAL;
458 }
459
460 static int
mlx5_devlink_hairpin_queue_size_validate(struct devlink * devlink,u32 id,union devlink_param_value val,struct netlink_ext_ack * extack)461 mlx5_devlink_hairpin_queue_size_validate(struct devlink *devlink, u32 id,
462 union devlink_param_value val,
463 struct netlink_ext_ack *extack)
464 {
465 struct mlx5_core_dev *dev = devlink_priv(devlink);
466 u32 val32 = val.vu32;
467
468 if (!is_power_of_2(val32)) {
469 NL_SET_ERR_MSG_MOD(extack, "Value is not power of two");
470 return -EINVAL;
471 }
472
473 if (val32 > BIT(MLX5_CAP_GEN(dev, log_max_hairpin_num_packets))) {
474 NL_SET_ERR_MSG_FMT_MOD(
475 extack, "Maximum hairpin queue size is %lu",
476 BIT(MLX5_CAP_GEN(dev, log_max_hairpin_num_packets)));
477 return -EINVAL;
478 }
479
480 return 0;
481 }
482
mlx5_devlink_hairpin_params_init_values(struct devlink * devlink)483 static void mlx5_devlink_hairpin_params_init_values(struct devlink *devlink)
484 {
485 struct mlx5_core_dev *dev = devlink_priv(devlink);
486 union devlink_param_value value;
487 u32 link_speed = 0;
488 u64 link_speed64;
489
490 /* set hairpin pair per each 50Gbs share of the link */
491 mlx5_port_max_linkspeed(dev, &link_speed);
492 link_speed = max_t(u32, link_speed, 50000);
493 link_speed64 = link_speed;
494 do_div(link_speed64, 50000);
495
496 value.vu32 = link_speed64;
497 devl_param_driverinit_value_set(
498 devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES, value);
499
500 value.vu32 =
501 BIT(min_t(u32, 16 - MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(dev),
502 MLX5_CAP_GEN(dev, log_max_hairpin_num_packets)));
503 devl_param_driverinit_value_set(
504 devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE, value);
505 }
506
507 static const struct devlink_param mlx5_devlink_params[] = {
508 DEVLINK_PARAM_GENERIC(ENABLE_ROCE, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
509 NULL, NULL, mlx5_devlink_enable_roce_validate),
510 #ifdef CONFIG_MLX5_ESWITCH
511 DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_ESW_LARGE_GROUP_NUM,
512 "fdb_large_groups", DEVLINK_PARAM_TYPE_U32,
513 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
514 NULL, NULL,
515 mlx5_devlink_large_group_num_validate),
516 #endif
517 DEVLINK_PARAM_GENERIC(IO_EQ_SIZE, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
518 NULL, NULL, mlx5_devlink_eq_depth_validate),
519 DEVLINK_PARAM_GENERIC(EVENT_EQ_SIZE, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
520 NULL, NULL, mlx5_devlink_eq_depth_validate),
521 };
522
mlx5_devlink_set_params_init_values(struct devlink * devlink)523 static void mlx5_devlink_set_params_init_values(struct devlink *devlink)
524 {
525 struct mlx5_core_dev *dev = devlink_priv(devlink);
526 union devlink_param_value value;
527
528 value.vbool = MLX5_CAP_GEN(dev, roce) && !mlx5_dev_is_lightweight(dev);
529 devl_param_driverinit_value_set(devlink,
530 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
531 value);
532
533 #ifdef CONFIG_MLX5_ESWITCH
534 value.vu32 = ESW_OFFLOADS_DEFAULT_NUM_GROUPS;
535 devl_param_driverinit_value_set(devlink,
536 MLX5_DEVLINK_PARAM_ID_ESW_LARGE_GROUP_NUM,
537 value);
538 #endif
539
540 value.vu32 = MLX5_COMP_EQ_SIZE;
541 devl_param_driverinit_value_set(devlink,
542 DEVLINK_PARAM_GENERIC_ID_IO_EQ_SIZE,
543 value);
544
545 value.vu32 = MLX5_NUM_ASYNC_EQE;
546 devl_param_driverinit_value_set(devlink,
547 DEVLINK_PARAM_GENERIC_ID_EVENT_EQ_SIZE,
548 value);
549 }
550
551 static const struct devlink_param mlx5_devlink_eth_params[] = {
552 DEVLINK_PARAM_GENERIC(ENABLE_ETH, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
553 NULL, NULL, NULL),
554 DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES,
555 "hairpin_num_queues", DEVLINK_PARAM_TYPE_U32,
556 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), NULL, NULL,
557 mlx5_devlink_hairpin_num_queues_validate),
558 DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE,
559 "hairpin_queue_size", DEVLINK_PARAM_TYPE_U32,
560 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), NULL, NULL,
561 mlx5_devlink_hairpin_queue_size_validate),
562 };
563
mlx5_devlink_eth_params_register(struct devlink * devlink)564 static int mlx5_devlink_eth_params_register(struct devlink *devlink)
565 {
566 struct mlx5_core_dev *dev = devlink_priv(devlink);
567 union devlink_param_value value;
568 int err;
569
570 if (!mlx5_eth_supported(dev))
571 return 0;
572
573 err = devl_params_register(devlink, mlx5_devlink_eth_params,
574 ARRAY_SIZE(mlx5_devlink_eth_params));
575 if (err)
576 return err;
577
578 value.vbool = !mlx5_dev_is_lightweight(dev);
579 devl_param_driverinit_value_set(devlink,
580 DEVLINK_PARAM_GENERIC_ID_ENABLE_ETH,
581 value);
582
583 mlx5_devlink_hairpin_params_init_values(devlink);
584
585 return 0;
586 }
587
mlx5_devlink_eth_params_unregister(struct devlink * devlink)588 static void mlx5_devlink_eth_params_unregister(struct devlink *devlink)
589 {
590 struct mlx5_core_dev *dev = devlink_priv(devlink);
591
592 if (!mlx5_eth_supported(dev))
593 return;
594
595 devl_params_unregister(devlink, mlx5_devlink_eth_params,
596 ARRAY_SIZE(mlx5_devlink_eth_params));
597 }
598
mlx5_devlink_enable_rdma_validate(struct devlink * devlink,u32 id,union devlink_param_value val,struct netlink_ext_ack * extack)599 static int mlx5_devlink_enable_rdma_validate(struct devlink *devlink, u32 id,
600 union devlink_param_value val,
601 struct netlink_ext_ack *extack)
602 {
603 struct mlx5_core_dev *dev = devlink_priv(devlink);
604 bool new_state = val.vbool;
605
606 if (new_state && !mlx5_rdma_supported(dev))
607 return -EOPNOTSUPP;
608 return 0;
609 }
610
611 static const struct devlink_param mlx5_devlink_rdma_params[] = {
612 DEVLINK_PARAM_GENERIC(ENABLE_RDMA, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
613 NULL, NULL, mlx5_devlink_enable_rdma_validate),
614 };
615
mlx5_devlink_rdma_params_register(struct devlink * devlink)616 static int mlx5_devlink_rdma_params_register(struct devlink *devlink)
617 {
618 struct mlx5_core_dev *dev = devlink_priv(devlink);
619 union devlink_param_value value;
620 int err;
621
622 if (!IS_ENABLED(CONFIG_MLX5_INFINIBAND))
623 return 0;
624
625 err = devl_params_register(devlink, mlx5_devlink_rdma_params,
626 ARRAY_SIZE(mlx5_devlink_rdma_params));
627 if (err)
628 return err;
629
630 value.vbool = !mlx5_dev_is_lightweight(dev);
631 devl_param_driverinit_value_set(devlink,
632 DEVLINK_PARAM_GENERIC_ID_ENABLE_RDMA,
633 value);
634 return 0;
635 }
636
mlx5_devlink_rdma_params_unregister(struct devlink * devlink)637 static void mlx5_devlink_rdma_params_unregister(struct devlink *devlink)
638 {
639 if (!IS_ENABLED(CONFIG_MLX5_INFINIBAND))
640 return;
641
642 devl_params_unregister(devlink, mlx5_devlink_rdma_params,
643 ARRAY_SIZE(mlx5_devlink_rdma_params));
644 }
645
646 static const struct devlink_param mlx5_devlink_vnet_params[] = {
647 DEVLINK_PARAM_GENERIC(ENABLE_VNET, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
648 NULL, NULL, NULL),
649 };
650
mlx5_devlink_vnet_params_register(struct devlink * devlink)651 static int mlx5_devlink_vnet_params_register(struct devlink *devlink)
652 {
653 struct mlx5_core_dev *dev = devlink_priv(devlink);
654 union devlink_param_value value;
655 int err;
656
657 if (!mlx5_vnet_supported(dev))
658 return 0;
659
660 err = devl_params_register(devlink, mlx5_devlink_vnet_params,
661 ARRAY_SIZE(mlx5_devlink_vnet_params));
662 if (err)
663 return err;
664
665 value.vbool = !mlx5_dev_is_lightweight(dev);
666 devl_param_driverinit_value_set(devlink,
667 DEVLINK_PARAM_GENERIC_ID_ENABLE_VNET,
668 value);
669 return 0;
670 }
671
mlx5_devlink_vnet_params_unregister(struct devlink * devlink)672 static void mlx5_devlink_vnet_params_unregister(struct devlink *devlink)
673 {
674 struct mlx5_core_dev *dev = devlink_priv(devlink);
675
676 if (!mlx5_vnet_supported(dev))
677 return;
678
679 devl_params_unregister(devlink, mlx5_devlink_vnet_params,
680 ARRAY_SIZE(mlx5_devlink_vnet_params));
681 }
682
mlx5_devlink_auxdev_params_register(struct devlink * devlink)683 static int mlx5_devlink_auxdev_params_register(struct devlink *devlink)
684 {
685 int err;
686
687 err = mlx5_devlink_eth_params_register(devlink);
688 if (err)
689 return err;
690
691 err = mlx5_devlink_rdma_params_register(devlink);
692 if (err)
693 goto rdma_err;
694
695 err = mlx5_devlink_vnet_params_register(devlink);
696 if (err)
697 goto vnet_err;
698 return 0;
699
700 vnet_err:
701 mlx5_devlink_rdma_params_unregister(devlink);
702 rdma_err:
703 mlx5_devlink_eth_params_unregister(devlink);
704 return err;
705 }
706
mlx5_devlink_auxdev_params_unregister(struct devlink * devlink)707 static void mlx5_devlink_auxdev_params_unregister(struct devlink *devlink)
708 {
709 mlx5_devlink_vnet_params_unregister(devlink);
710 mlx5_devlink_rdma_params_unregister(devlink);
711 mlx5_devlink_eth_params_unregister(devlink);
712 }
713
mlx5_devlink_max_uc_list_validate(struct devlink * devlink,u32 id,union devlink_param_value val,struct netlink_ext_ack * extack)714 static int mlx5_devlink_max_uc_list_validate(struct devlink *devlink, u32 id,
715 union devlink_param_value val,
716 struct netlink_ext_ack *extack)
717 {
718 struct mlx5_core_dev *dev = devlink_priv(devlink);
719
720 if (val.vu32 == 0) {
721 NL_SET_ERR_MSG_MOD(extack, "max_macs value must be greater than 0");
722 return -EINVAL;
723 }
724
725 if (!is_power_of_2(val.vu32)) {
726 NL_SET_ERR_MSG_MOD(extack, "Only power of 2 values are supported for max_macs");
727 return -EINVAL;
728 }
729
730 if (ilog2(val.vu32) >
731 MLX5_CAP_GEN_MAX(dev, log_max_current_uc_list)) {
732 NL_SET_ERR_MSG_MOD(extack, "max_macs value is out of the supported range");
733 return -EINVAL;
734 }
735
736 return 0;
737 }
738
739 static const struct devlink_param mlx5_devlink_max_uc_list_params[] = {
740 DEVLINK_PARAM_GENERIC(MAX_MACS, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
741 NULL, NULL, mlx5_devlink_max_uc_list_validate),
742 };
743
mlx5_devlink_max_uc_list_params_register(struct devlink * devlink)744 static int mlx5_devlink_max_uc_list_params_register(struct devlink *devlink)
745 {
746 struct mlx5_core_dev *dev = devlink_priv(devlink);
747 union devlink_param_value value;
748 int err;
749
750 if (!MLX5_CAP_GEN_MAX(dev, log_max_current_uc_list_wr_supported))
751 return 0;
752
753 err = devl_params_register(devlink, mlx5_devlink_max_uc_list_params,
754 ARRAY_SIZE(mlx5_devlink_max_uc_list_params));
755 if (err)
756 return err;
757
758 value.vu32 = 1 << MLX5_CAP_GEN(dev, log_max_current_uc_list);
759 devl_param_driverinit_value_set(devlink,
760 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
761 value);
762 return 0;
763 }
764
765 static void
mlx5_devlink_max_uc_list_params_unregister(struct devlink * devlink)766 mlx5_devlink_max_uc_list_params_unregister(struct devlink *devlink)
767 {
768 struct mlx5_core_dev *dev = devlink_priv(devlink);
769
770 if (!MLX5_CAP_GEN_MAX(dev, log_max_current_uc_list_wr_supported))
771 return;
772
773 devl_params_unregister(devlink, mlx5_devlink_max_uc_list_params,
774 ARRAY_SIZE(mlx5_devlink_max_uc_list_params));
775 }
776
777 #define MLX5_TRAP_DROP(_id, _group_id) \
778 DEVLINK_TRAP_GENERIC(DROP, DROP, _id, \
779 DEVLINK_TRAP_GROUP_GENERIC_ID_##_group_id, \
780 DEVLINK_TRAP_METADATA_TYPE_F_IN_PORT)
781
782 static const struct devlink_trap mlx5_traps_arr[] = {
783 MLX5_TRAP_DROP(INGRESS_VLAN_FILTER, L2_DROPS),
784 MLX5_TRAP_DROP(DMAC_FILTER, L2_DROPS),
785 };
786
787 static const struct devlink_trap_group mlx5_trap_groups_arr[] = {
788 DEVLINK_TRAP_GROUP_GENERIC(L2_DROPS, 0),
789 };
790
mlx5_devlink_traps_register(struct devlink * devlink)791 int mlx5_devlink_traps_register(struct devlink *devlink)
792 {
793 struct mlx5_core_dev *core_dev = devlink_priv(devlink);
794 int err;
795
796 err = devl_trap_groups_register(devlink, mlx5_trap_groups_arr,
797 ARRAY_SIZE(mlx5_trap_groups_arr));
798 if (err)
799 return err;
800
801 err = devl_traps_register(devlink, mlx5_traps_arr, ARRAY_SIZE(mlx5_traps_arr),
802 &core_dev->priv);
803 if (err)
804 goto err_trap_group;
805 return 0;
806
807 err_trap_group:
808 devl_trap_groups_unregister(devlink, mlx5_trap_groups_arr,
809 ARRAY_SIZE(mlx5_trap_groups_arr));
810 return err;
811 }
812
mlx5_devlink_traps_unregister(struct devlink * devlink)813 void mlx5_devlink_traps_unregister(struct devlink *devlink)
814 {
815 devl_traps_unregister(devlink, mlx5_traps_arr, ARRAY_SIZE(mlx5_traps_arr));
816 devl_trap_groups_unregister(devlink, mlx5_trap_groups_arr,
817 ARRAY_SIZE(mlx5_trap_groups_arr));
818 }
819
mlx5_devlink_params_register(struct devlink * devlink)820 int mlx5_devlink_params_register(struct devlink *devlink)
821 {
822 int err;
823
824 /* Here only the driver init params should be registered.
825 * Runtime params should be registered by the code which
826 * behaviour they configure.
827 */
828
829 err = devl_params_register(devlink, mlx5_devlink_params,
830 ARRAY_SIZE(mlx5_devlink_params));
831 if (err)
832 return err;
833
834 mlx5_devlink_set_params_init_values(devlink);
835
836 err = mlx5_devlink_auxdev_params_register(devlink);
837 if (err)
838 goto auxdev_reg_err;
839
840 err = mlx5_devlink_max_uc_list_params_register(devlink);
841 if (err)
842 goto max_uc_list_err;
843
844 return 0;
845
846 max_uc_list_err:
847 mlx5_devlink_auxdev_params_unregister(devlink);
848 auxdev_reg_err:
849 devl_params_unregister(devlink, mlx5_devlink_params,
850 ARRAY_SIZE(mlx5_devlink_params));
851 return err;
852 }
853
mlx5_devlink_params_unregister(struct devlink * devlink)854 void mlx5_devlink_params_unregister(struct devlink *devlink)
855 {
856 mlx5_devlink_max_uc_list_params_unregister(devlink);
857 mlx5_devlink_auxdev_params_unregister(devlink);
858 devl_params_unregister(devlink, mlx5_devlink_params,
859 ARRAY_SIZE(mlx5_devlink_params));
860 }
861